LMZ31710RVQR - Texas Instruments - Datasheet.Directory

LMZ31710

PWRGD

SENSE+

VOUT

PVIN

VIN

INH/UVLO

RT/CLK

VADJ

SS/TR

STSEL

AGND PGND

SET

OUT

SYNC_OUT

ISHARE

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Folder

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Now

Technical

Documents

Tools &

Software

Support &

Community

Reference

Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMZ31710

SNVS987C –JULY 2013–REVISED APRIL 2018

LMZ31710 10-A Power Module With 2.95-V to 17-V Input and Current Sharing

in QFN Package

1 Features

1• Complete Integrated Power Solution

– Small Footprint, Low-Profile Design

– Pin Compatible with LMZ31707 and

LMZ31704

– 10 mm × 10 mm × 4.3 mm Package

• Efficiencies Up to 95%

• Eco-Mode™ and Light Load Efficiency (LLE)

• Wide-Output Voltage Adjust

0.6 V to 5.5 V, With 1% Reference Accuracy

• Supports Parallel Operation for Higher Current

• Optional Split Power Rail Allows

Input Voltage Down to 2.95 V

• Adjustable Switching Frequency

(200 kHz to 1.2 MHz)

• Synchronizes to an External Clock

• Provides 180° Out-of-Phase Clock Signal

• Adjustable Slow Start

• Output Voltage Sequencing and Tracking

• Power-Good Output

• Programmable Undervoltage Lockout (UVLO)

• Overcurrent and Overtemperature Protection

• Prebias Output Start-up

• Operating Temperature Range: –40°C to +85°C

• Enhanced Thermal Performance: 13.3°C/W

• Meets EN55022 Class B Emissions

- Integrated Shielded Inductor

• Create a Custom Design using the LMZ31710

with the WEBENCH® Power Designer

2 Applications

• Broadband and Communications Infrastructure

• Automated Test and Medical Equipment

• Compact PCI / PCI Express / PXI Express

• DSP and FPGA Point-of-Load Applications

3 Description

The LMZ31710 power module is an easy-to-use

integrated power solution that combines a 10-A

DC/DC converter with power MOSFETs, a shielded

inductor, and passives into a low-profile QFN

package. This total power solution allows as few as

three external components and eliminates the loop

compensation and magnetics part selection process.

The 10 × 10 × 4.3 mm QFN package is easy to

solder onto a printed circuit board and allows a

compact point-of-load design. The device achieves

greater than 95% efficiency and excellent power

dissipation capability with a thermal impedance of

13.3°C/W. The LMZ31710 offers the flexibility and the

feature set of a discrete point-of-load design and is

ideal for powering a wide range of ICs and systems.

Advanced packaging technology affords a robust and

reliable power solution compatible with standard QFN

mounting and testing techniques.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LMZ31710 RVQ (42) 10.00 mm × 10.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Application

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics.......................................... 6

6.6 Typical Characteristics (PVIN = VIN = 12 V) .............. 8

6.7 Typical Characteristics (PVIN = VIN = 5 V) ............... 9

6.8 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V) ... 10

7 Detailed Description............................................ 11

7.1 Overview................................................................. 11

7.2 Functional Block Diagram....................................... 11

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 25

8 Application and Implementation ........................ 26

8.1 Application Information............................................ 26

8.2 Typical Application.................................................. 26

8.3 Additional Application Schematics.......................... 27

9 Power Supply Recommendations...................... 28

10 Layout................................................................... 29

10.1 Layout Considerations .......................................... 29

10.2 Layout Examples................................................... 29

11 Device and Documentation Support................. 31

11.1 Device Support...................................................... 31

11.2 Documentation Support ........................................ 31

11.3 Receiving Notification of Documentation Updates 31

11.4 Community Resources.......................................... 31

11.5 Trademarks........................................................... 32

11.6 Electrostatic Discharge Caution............................ 32

11.7 Glossary................................................................ 32

12 Mechanical, Packaging, and Orderable

Information........................................................... 32

12.1 Tape and Reel Information ................................... 32

4 Revision History

Changes from Revision B (June 2017) to Revision C Page

• Added WEBENCH® design links for the LMZ31710 ............................................................................................................. 1

• Increased the peak reflow temperature and maximum number of reflows to JEDEC specifications for improved

manufacturability..................................................................................................................................................................... 5

Changes from Revision A (July 2013) to Revision B Page

• Changed Device Information and Pin Configuration and Functions sections, ESD Rating table, Feature Description,

Device Functional Modes,Application and Implementation,Power Supply Recommendations,Layout,Device and

Documentation Support , and Mechanical, Packaging, and Orderable Information sections................................................ 1

• Added peak reflow and maximum number of reflows information ........................................................................................ 5

11 12 13 14 15 16 17 18 19 20 21

3233343536373839

INH/UVLO

PWRGD

OCP_SEL

DNC

RT/CLK

VIN

SS/TR

STSEL

ISHARE

ILIM

SYNC_OUT

PVIN

SENSE+

VADJ

AGND

PVIN

PGND

VOUT

PGND

VOUT

PGND

DNC

PGND

DNC

PVIN

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5 Pin Configuration and Functions

RVQ Package

42-Pin B3QFN

(Top View)

Pin Functions

PIN TYPE DESCRIPTION

NAME NO.

AGND 2-Zero volt reference for the analog control circuit. These pins are not connected together internal to the

device and must be connected to one another using an AGND plane of the PCB. These pins are

associated with the internal analog ground (AGND) of the device. Keep AGND seperate from PGND,

as a single connection is made internal to the device. See Layout.

PGND

-This is the return current path for the power stage of the device. Connect these pins to the load and to

the bypass capacitors associated with PVIN and VOUT. Keep PGND seperate from AGND, as a single

connection is made internal to the device.

VIN 3 I Input bias voltage pin. Supplies the control circuitry of the power converter. Connect this pin to the

input bias supply. Connect bypass capacitors between this pin and PGND.

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Pin Functions (continued)

PIN TYPE DESCRIPTION

NAME NO.

PVIN

IInput switching voltage. Supplies voltage to the power switches of the converter. Connect these pins to

the input supply. Connect bypass capacitors between these pins and PGND.

VOUT

OOutput voltage. These pins are connected to the internal output inductor. Connect these pins to the

output load and connect external bypass capacitors between these pins and PGND.

OPhase switch node. These pins must be connected to one another using a small copper island under

the device for thermal relief. Do not place any external component on these pins or tie them to a pin of

another function.

DNC 5-Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage.

These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.

ISHARE 25 O Current share pin. Connect this pin to other LMZ31710 device's ISHARE pin when paralleling multple

LMZ31710 devices. When unused, treat this pin as a Do Not Connect (DNC) and leave it isolated from

all other signals or ground.

OCP_SEL 4 I Over current protection select pin. Leave this pin open for hiccup mode operation. Connect this pin to

AGND for cycle-by-cycle operation. See Overcurrent Protection for more details.

ILIM 6 I Current limit pin. Leave this pin open for full current limit threshold. Connect this pin to AGND to reduce

the current limit threshold by appoximately 3 A.

SYNC_OU

T7 O Synchronization output pin. Provides a 180° out-of-phase clock signal.

PWRGD 8 O Power Good flag pin. This open drain output asserts low if the output voltage is more than

approximately ±6% out of regulation. A pull-up resistor is required.

RT/CLK 22 I This pin is connected to an internal frequency setting resistor which sets the default switching

frequency. An external resistor can be connected from this pin to AGND to increase the frequency.

This pin can also be used to synchronize to an external clock.

VADJ 26 I Connecting a resistor between this pin and AGND sets the output voltage.

SENSE+ 27 O Remote sense connection. This pin must be connected to VOUT at the load or at the device pins.

Connect this pin to VOUT at the load for improved regulation.

SS/TR 28 I Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise

time. A voltage applied to this pin allows for tracking and sequencing control.

STSEL 29 I Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave

this pin open to enable the TR feature.

INH/UVLO 30 I Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to

control the INH function. A resistor divider between this pin, AGND, and PVIN/VIN sets the UVLO

voltage.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) See the temperature derating curves in the Typical Characteristics section for thermal information.

(3) For soldering specifications, refer to the Soldering Requirements for BQFN Packages application note.

(4) Devices with a date code prior to week 14 2018 (1814) have a peak reflow case temperature of 240°C with a maximum of one reflow.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Input voltage VIN, PVIN –0.3 20 V

INH/UVLO, PWRGD, RT/CLK, SENSE+ –0.3 6 V

ILIM, VADJ, SS/TR, STSEL, SYNC_OUT, ISHARE, OCP_SEL –0.3 3 V

Output voltage PH –1.0 20 V

PH 10ns Transient –3.0 20 V

VOUT –0.3 10 V

Source current RT/CLK, INH/UVLO ±100 µA

PH current limit A

Sink current PH current limit A

PVIN current limit A

PWRGD –0.1 2 mA

Operating junction temperature –40 125(2) °C

Storage temperature, Tstg –65 150 °C

Peak Reflow Case Temperature(3) 245(4) °C

Maximum Number of Reflows Allowed(3) 3(4)

Mechanical shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted 1500 G

Mechanical vibration Mil-STD-883D, Method 2007.2, 20-2000Hz 20

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic

discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

Input switching voltage, PVIN 2.95 17 V

Input bias voltage, VIN 4.5 17 V

Output voltage, VOUT 0.6 5.5 V

Switching frequency, ƒSW 200 1200 kHz

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SNVS987C –JULY 2013–REVISED APRIL 2018

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 100 mm × 100 mm double-sided PCB with

2 oz. copper and natural convection cooling. Additional airflow reduces RθJA.

(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). TJ=ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TTis

the temperature of the top of the device.

(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). TJ=ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TBis

the temperature of the board 1 mm from the device.

6.4 Thermal Information

THERMAL METRIC(1) LMZ31710

UNITRVQ (B3QFN)

42 PINS

RθJA Junction-to-ambient thermal resistance(2) 13.3 °C/W

RθJB Junction-to-board thermal resistance(3) 1.6 °C/W

ψJT Junction-to-top characterization parameter(4) 5.3 °C/W

(1) See Light Load Efficiency (LLE) for more information for output voltages < 1.5 V.

(2) The minimum PVIN is 2.95 V or (VOUT + 0.7 V), whichever is greater. See Table 7 for more details.

(3) The maximum PVIN voltage is 17 V or (22 x VOUT), whichever is less. See Table 7 for more details.

(4) The maximum output voltage may be limited by the power dissipation. The maximum power dissipation of this device is 4.5 W.

(5) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal

adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.

6.5 Electrical Characteristics

Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 10 A,

CIN = 0.1 µF + 2 × 22 µF ceramic + 100 µF bulk, COUT = 4 × 47 µF ceramic (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IOUT Output current TA= 85°C, natural convection 0(1) 10 A

VIN Input bias voltage range Over output current range 4.5 17 V

PVIN Input switching voltage range Over output current range 2.95(2) 17(3) V

UVLO VIN undervoltage lockout VIN Increasing 4 4.5 V

VIN Decreasing 3.5 3.85

VOUT(adj) Output voltage adjust range Over output current range 0.6 5.5(4) V

VOUT

Set-point voltage tolerance TA= 25°C, IOUT = 0 A ±1%(5)

Temperature variation –40°C ≤TA≤+85°C, IOUT = 0 A ±0.2%

Line regulation Over input voltage range ±0.1%

Load regulation Over output current range ±0.2%

Total output voltage variation Includes set-point, line, load, and temperature variation ±1.5%(5)

ηEfficiency

PVIN = VIN = 12 V

IO= 5 A

VOUT = 5 V, fSW = 1 MHz 93%

VOUT = 3.3 V, fSW = 750 kHz 92%

VOUT = 2.5 V, fSW = 750 kHz 90%

VOUT = 1.8 V, fSW = 500 kHz 89%

VOUT = 1.2 V, fSW = 300 kHz 86%

VOUT = 0.9 V, fSW = 250 kHz 84%

VOUT = 0.6 V, fSW = 200 kHz 81%

PVIN = VIN = 5 V

IO= 5 A VOUT = 3.3 V, fSW = 750 kHz 94%

VOUT = 2.5 V, fSW = 750 kHz 93%

VOUT = 1.8 V, fSW = 500 kHz 92%

VOUT = 1.2 V, fSW = 300 kHz 89%

VOUT = 0.9 V, fSW = 250 kHz 87%

VOUT = 0.6 V, fSW = 200 kHz 83%

Output voltage ripple 20 MHz bandwith 14 mVP-P

ILIM Current limit threshold ILIM pin open 15 A

ILIM pin to AGND 12 A

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Electrical Characteristics (continued)

Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 10 A,

CIN = 0.1 µF + 2 × 22 µF ceramic + 100 µF bulk, COUT = 4 × 47 µF ceramic (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(6) Value when no voltage divider is present at the INH/UVLO pin. This pin has an internal pull-up. If it is left open, the device operates

when input power is applied. A small, low-leakage MOSFET is recommended for control. Do not tie this pin to VIN.

(7) A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An

additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1 µF ceramic capacitor directly across the

PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails,

place 4.7 µF of ceramic capacitance directly at the VIN pin. See Table 4 for more details.

(8) The amount of required output capacitance varies depending on the output voltage (see Table 3). The amount of required capacitance

must include at least 1 × 47 µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to

the load improves the response of the regulator to load transients. See Table 3 and Table 4 more details.

(9) The maximum output capacitance of 5000 µF includes the combination of both ceramic and non-ceramic capacitors. It may be

necessary to increase the slow-start time when turning on into the maximum capacitance. See the Slow Start (SS/TR) section for

information on adjusting the slow-start time.

Transient response 1 A/µs load step from

25 to 75% IOUT(max)

Recovery time 100 µs

VOUT over/undershoot 80 mV

VINH Inhibit threshold voltage Inhibit High Voltage 1.3 open(6) V

Inhibit Low Voltage –0.3 1.1

IINH INH Input current VINH < 1.1 V -1.15 μA

INH Hysteresis current VINH > 1.3 V -3.3 μA

II(stby) Input standby current INH pin to AGND 2 10 µA

Power

Good PWRGD Thresholds

VOUT rising Good 95%

Fault 108%

VOUT falling Fault 91%

Good 104%

PWRGD Low Voltage I(PWRGD) = 0.5 mA 0.3 V

ƒSW Switching frequency RRT = 169 kΩ400 500 600 kHz

ƒCLK Synchronization frequency

CLK Control

200 1200 kHz

VCLK-H CLK High-Level 2 5.5 V

VCLK-L CLK Low-Level 0.5 V

DCLK CLK Duty Cycle 20% 50% 80%

Thermal Shutdown Thermal shutdown 175 °C

Thermal shutdown hysteresis 10 °C

CIN External input capacitance Ceramic 44(7) µF

Non-ceramic 100(7)

COUT External output capacitance

VOUT = 0.6 V to 5.5 V Ceramic 47(8) 200 1500 µF

VOUT = 0.6 V to 5.5 V Non-ceramic 220(8) 5000(9)

Equivalent series resistance (ESR) 35 mΩ

0 2 4 6 8 10

Ambient Temperature (ƒC)

Output Current (A)

9R”9IVZ N+]

Vo = 2.5V, fsw = 750kHz

Vo = 3.3V, fsw = 750kHz

Vo = 5.0V, fsw = 1MHz

C001

Airflow = 0 LFM

0 2 4 6 8 10

Ambient Temperature (ƒC)

Output Current (A)

9R”9IVZ N+]

Vo = 2.5V, fsw = 750kHz

Vo = 3.3V, fsw = 750kHz

Vo = 5.0V, fsw = 1MHz

C001

Airflow = 200 LFM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 2 4 6 8 10

Power Dissipation (W)

Output Current (A)

Vo = 5.0V, fsw = 1MHz

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

C004

±120

±90

±60

±30

120

±40

±30

±20

±10

1000 10k 100k

Phase (ƒ)

Gain (dB)

Frequency (Hz)

Gain

Phase

C006

400k

100

0 1 2 3 4 5 6 7 8 9 10

Efficiency (%)

Output Current (A)

Vo = 5.0V, fsw = 1MHz

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

C001

0 2 4 6 8 10

Output Ripple Voltage (mV)

Output Current (A)

Vo = 5.0V, fsw = 1MHz

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

C004

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6.6 Typical Characteristics (PVIN = VIN = 12 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 1,Figure 2, and Figure 3. The temperature derating curves represent the conditions at which

internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices

soldered directly to a 100 mm × 100 mm double-sided PCB with 2 oz. copper. Applies to Figure 5 and Figure 6.

Figure 1. Efficiency vs Output Current Figure 2. Voltage Ripple vs Output Current

Figure 3. Power Dissipation vs Output Current Figure 4. VOUT= 1.8 V, IOUT= 10 A, COUT1= 200 Μf Ceramic,

FSW= 500 Khz

Figure 5. Safe Operating Area Figure 6. Safe Operating Area

0 2 4 6 8 10

Ambient Temperature (ƒC)

Output Current (A)

All Output Voltages

C001

Airflow = 0 LFM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 2 4 6 8 10

Power Dissipation (W)

Output Current (A)

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C004

±120

±90

±60

±30

120

±40

±30

±20

±10

1000 10k 100k

Phase (ƒ)

Gain (dB)

Frequency (Hz)

Gain

Phase

C006

400k

100

0 1 2 3 4 5 6 7 8 9 10

Efficiency (%)

Output Current (A)

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C001

0 2 4 6 8 10

Output Voltage Ripple (mV)

Output Current (A)

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C004

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6.7 Typical Characteristics (PVIN = VIN = 5 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 7,Figure 8, and Figure 9. The temperature derating curves represent the conditions at which

internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices

soldered directly to a 100 mm × 100 mm double-sided PCB with 2 oz. copper. Applies to Figure 11.

Figure 7. Efficiency vs Output Current Figure 8. Voltage Ripple vs Output Current

Figure 9. Power Dissipation vs Output Current Figure 10. VOUT= 1.8 V, IOUT= 10 A, COUT1= 200 Μf Ceramic,

FSW= 500 Khz

Figure 11. Safe Operating Area

0 2 4 6 8 10

Ambient Temperature (ƒC)

Output Current (A)

All Output Voltages

C001

Airflow = 0 LFM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 2 4 6 8 10

Power Dissipation (W)

Output Current (A)

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C004

±120

±90

±60

±30

120

±40

±30

±20

±10

1000 10k 100k

Phase (ƒ)

Gain (dB)

Frequency (Hz)

Gain

Phase

C006

400k

100

0 1 2 3 4 5 6 7 8 9 10

Efficiency (%)

Output Current (A)

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C001

0 2 4 6 8 10

Output Ripple Voltage (mV)

Output Current (A)

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C004

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6.8 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 12,Figure 13, and Figure 14. The temperature derating curves represent the conditions at

which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to

devices soldered directly to a 100 mm × 100 mm double-sided PCB with 2 oz. copper. Applies to Figure 16.

Figure 12. Efficiency vs Output Current Figure 13. Voltage Ripple vs Output Current

Figure 14. Power Dissipation vs Output Current Figure 15. VOUT= 1.8 V, IOUT= 10 A, COUT1= 200 Μf Ceramic,

FSW= 500 Khz

Figure 16. Safe Operating Area

PWRGD

VIN

PVIN

PGND

VOUT

RT/CLK

AGND

VADJ

INH/UVLO

STSEL

SS/TR

SENSE+

LMZ31710

PWRGD

Logic

VREF Comp Power

Stage

and

Control

Logic

Thermal

Shutdown

Logic

OCP

VIN

UVLO

Oscillator

with PLL

SYNC_OUT

ILIM

Current

ISHARE

OCP_SEL

LMZ31710

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7 Detailed Description

7.1 Overview

The LMZ31710 is a full-featured 2.95 V to 17 V input, 10-A, synchronous step down converter with PWM,

MOSFETs, inductor, and control circuitry integrated into a low-profile, overmolded package. This device enables

small designs by integrating all but the input and output capacitors, while still leaving the ability to adjust key

parameters to meet specific design requirements. The LMZ31710 provides a wide output voltage range of 0.6 V

to 5.5 V. In most applications, a single external resistor is used to adjust the output voltage. The switching

frequency is also adjustable by using an external resistor or a synchronization pulse to accommodate various

input/output voltage conditions and to optimize efficiency. The device provides accurate voltage regulation for a

variety of loads by using an internal voltage reference that is ±1% accurate over temperature. The INH/UVLO pin

can be pulled low to put the device in standby mode to reduce input quiescent current. The input under-voltage

lockout can be adjusted using a resistor divider on the IN/UVLO pin of the device. The device provides a power

good signal to indicate when the output is within ±5% of its nominal voltage. The ability to parallel the LMZ31710

allows it to be used in higher current applications. Thermal shutdown and current limit features protect the device

during an overload condition. Automatic pulse skip mode improves light-load efficiency. A 42-pin, QFN, package

that includes exposed bottom pads provides a thermally enhanced solution for space-constrained applications.

7.2 Functional Block Diagram

RSET VOUT

0.6

1.43

=)( (k)

( )- 1

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7.3 Feature Description

7.3.1 VIN and PVIN Input Voltage

The LMZ31710 allows for a variety of applications by using the VIN and PVIN pins together or separately. The

VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the

power converter system.

If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 17 V. If using the VIN

pin separately from the PVIN pin, the VIN pin must be greater than 4.5 V, and the PVIN pin can range from as

low as 2.95 V to 17 V. When operating from a split rail, it is recommended to supply VIN from 5 V to 12 V, for

best performance. A voltage divider connected to the INH/UVLO pin can adjust either input voltage UVLO

appropriately. See Programmable Undervoltage Lockout (UVLO) for more information.

7.3.2 3.3-V PVIN Operation

Applications operating from a PVIN of 3.3 V must provide at least 4.5 V for VIN. It is recommended to supply VIN

from 5 V to 12 V, for best performance. See application note, SNVA692 for help creating 5 V from 3.3 V using a

small, simple charge pump device.

7.3.3 Adjusting the Output Voltage (0.6 V to 5.5 V)

The VADJ control sets the output voltage of the LMZ31710. The output voltage adjustment range of the

LMZ31710 is from 0.6V to 5.5V. The adjustment method requires the addition of RSET, which sets the output

voltage, the connection of SENSE+ to VOUT, and in some cases RRT which sets the switching frequency. The

RSET resistor must be connected directly between the VADJ (pin 26) and AGND (pin 23). The SENSE+ pin (pin

27) must be connected to VOUT either at the load for improved regulation or at VOUT of the device. The RRT

resistor must be connected directly between the RT/CLK (pin 22) and AGND (pin 23). Table 1 gives the standard

external RSET resistor for a number of common bus voltages, along with the recommended RRT resistor for that

output voltage.

Table 1. Standard RSET Resistor Values for Common Output Voltages

RESISTORS OUTPUT VOLTAGE VOUT (V)

0.9 1.0 1.2 1.8 2.5 3.3 5.0

RSET (kΩ)2.87 2.15 1.43 0.715 0.453 0.316 0.196

RRT (kΩ)1000 1000 487 169 90.9 90.9 63.4

For other output voltages, the value of the required resistor can either be calculated using the following formula,

or simply selected from the range of values given in Table 2.

(1)

Table 2. Standard RSET Resistor Values

VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz) VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz)

0.6 open OPEN 200 3.1 0.348 90.9 750

0.7 8.66 OPEN 200 3.2 0.332 90.9 750

0.8 4.32 OPEN 200 3.3 0.316 90.9 750

0.9 2.87 1000 250 3.4 0.309 90.9 750

1.0 2.15 1000 250 3.5 0.294 90.9 750

1.1 1.74 1000 250 3.6 0.287 90.9 750

1.2 1.43 487 300 3.7 0.280 90.9 750

1.3 1.24 487 300 3.8 0.267 90.9 750

1.4 1.07 487 300 3.9 0.261 90.9 750

1.5 0.953 487 300 4.0 0.255 90.9 750

1.6 0.866 487 300 4.1 0.243 63.4 1000

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Table 2. Standard RSET Resistor Values (continued)

VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz) VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz)

1.7 0.787 487 300 4.2 0.237 63.4 1000

1.8 0.715 169 500 4.3 0.232 63.4 1000

1.9 0.665 169 500 4.4 0.226 63.4 1000

2.0 0.619 169 500 4.5 0.221 63.4 1000

2.1 0.576 169 500 4.6 0.215 63.4 1000

2.2 0.536 169 500 4.7 0.210 63.4 1000

2.3 0.511 169 500 4.8 0.205 63.4 1000

2.4 0.475 169 500 4.9 0.200 63.4 1000

2.5 0.453 90.9 750 5.0 0.196 63.4 1000

2.6 0.432 90.9 750 5.1 0.191 63.4 1000

2.7 0.412 90.9 750 5.2 0.187 63.4 1000

2.8 0.392 90.9 750 5.3 0.182 63.4 1000

2.9 0.374 90.9 750 5.4 0.178 63.4 1000

3.0 0.357 90.9 750 5.5 0.174 63.4 1000

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7.3.4 Capacitor Recommendations For the LMZ31710 Power Supply

7.3.4.1 Capacitor Technologies

7.3.4.1.1 Electrolytic, Polymer-Electrolytic Capacitors

When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.

Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature

is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge,

power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide

adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures

are above 0°C.

7.3.4.1.2 Ceramic Capacitors

The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.

Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the

regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient

response of the output.

7.3.4.1.3 Tantalum, Polymer-Tantalum Capacitors

Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is

less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many

other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and

small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended

for power applications.

7.3.4.2 Input Capacitor

The LMZ31710 requires a minimum input capacitance of 44 μF of ceramic type. An additional 100 µF of non-

ceramic capacitance is recommended for applications with transient load requirements. The voltage rating of

input capacitors must be greater than the maximum input voltage. At worst case, when operating at 50% duty

cycle and maximum load, the combined ripple current rating of the input capacitors must be at least 5 Arms.

Table 4 includes a preferred list of capacitors by vendor. It is also recommended to place a 0.1 µF ceramic

capacitor directly across the PVIN and PGND pins of the device. When operating with split VIN and PVIN rails,

place 4.7µF of ceramic capacitance directly at the VIN pin.

7.3.4.3 Output Capacitor

The required output capacitance is determined by the output voltage of the LMZ31710. See Table 3 for the

amount of required capacitance. The effects of temperature and capacitor voltage rating must be considered

when selecting capacitors to meet the minimum required capacitance. The required output capacitance can be

comprised of all ceramic capacitors, or a combination of ceramic and bulk capacitors. The required capacitance

must include at least one 47 µF ceramic. When adding additional non-ceramic bulk capacitors, low-ESR devices

like the ones recommended in Table 4 are required. The required capacitance above the minimum is determined

by actual transient deviation requirements. See Table 5 for typical transient response values for several output

voltage, input voltage and capacitance combinations. Table 4 includes a preferred list of capacitors by vendor.

(1) Minimum required must include at least one 47 µF ceramic capacitor.

Table 3. Required Output Capacitance

VOUT RANGE (V) MINIMUM REQUIRED COUT (µF)

MIN MAX

0.6 < 0.8 500 µF(1)

0.8 < 1.2 300 µF(1)

1.2 < 3.0 200 µF(1)

3.0 < 4.0 100 µF(1)

4.0 5.5 47 µF ceramic

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(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details

Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in this table.

(2) Maximum ESR at 100 kHz, 25°C.

Table 4. Recommended Input/Output Capacitors(1)

VENDOR SERIES PART NUMBER

CAPACITOR CHARACTERISTICS

WORKING

VOLTAGE

(V)

CAPACITANCE

(µF) ESR(2)

(mΩ)

Murata X5R GRM32ER61E226K 25 22 2

TDK X5R C3225X5R0J107M 6.3 100 2

TDK X5R C3225X5R0J476K 6.3 47 2

Murata X5R GRM32ER60J107M 6.3 100 2

Murata X5R GRM32ER60J476M 6.3 47 2

Panasonic EEH-ZA EEH-ZA1E101XP 25 100 30

Sanyo POSCAP 16TQC68M 16 68 50

Kemet T520 T520V107M010ASE025 10 100 25

Sanyo POSCAP 10TPE220ML 10 220 25

Sanyo POSCAP 6TPE100MI 6.3 100 25

Sanyo POSCAP 2R5TPE220M7 2.5 220 7

Kemet T530 T530D227M006ATE006 6.3 220 6

Kemet T530 T530D337M006ATE010 6.3 330 10

Sanyo POSCAP 2TPF330M6 2.0 330 6

Sanyo POSCAP 6TPE330MFL 6.3 330 15

7.3.5 Transient Response

Table 5. Output Voltage Transient Response

CIN1 = 3x 47 µF CERAMIC, CIN2 = 100 µF POLYMER-TANTALUM

VOUT (V) VIN (V) COUT1 Ceramic COUT2 BULK VOLTAGE DEVIATION (mV) RECOVERY TIME

(µs)

2.5 A LOAD STEP,

(1 A/µs) 5 A LOAD STEP,

(1 A/µs)

0.6 5 500 µF 220 µF 25 60 100

12 500 µF 220 µF 30 65 100

0.9 5300 µF 220 µF 40 85 100

300 µF 470 µF 35 70 110

12 300 µF 220 µF 45 90 100

300 µF 470 µF 35 75 110

1.2 5200 µF 220 µF 55 110 110

200 µF 470 µF 45 90 110

12 200 µF 220 µF 55 110 110

200 µF 470 µF 45 90 110

1.8 5200 µF 220 µF 70 140 130

200 µF 470 µF 60 120 140

12 200 µF 220 µF 70 145 140

200 µF 470 µF 55 120 150

3.3 5 100 µF 220 µF 115 230 200

12 100 µF 220 µF 120 240 200