TPS74901
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
COUT
CIN
CSS
VBIAS
CBIAS
VOUT
1V/div
1V/div
Time(1ms/div)
C =0 F
SS m
C =0.001 F
SS m
C =0.0047 F
SS m
VOUT
VEN
0V
1.2V
TPS749xx
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SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
3.0A Low Dropout Linear Regulator with Programmable Soft-Start
Check for Samples: TPS749xx
1FEATURES DESCRIPTION
2• VOUT Range: 0.8V to 3.6V The TPS749xx low-dropout (LDO) linear regulator
• Ultralow VIN Range: 0.8V to 5.5V provides an easy-to-use robust power management
• VBIAS Range: 2.7V to 5.5V solution for a wide variety of applications.
• Low Dropout: 120mV (typ) at 3.0A, VBIAS = 5V User-programmable soft-start minimizes stress on the
input power source by reducing capacitive inrush
• Power-Good (PG) Output Allows Supply current on start-up. The soft-start is monotonic and
Monitoring or Provides a Sequencing Signal well-suited for powering many different types of
for Other Supplies processors and ASICs. The enable input and
• 2% Accuracy Over Line/Load/Temperature power-good output allow easy sequencing with
• Programmable Soft-Start Provides Linear external regulators. This complete flexibility permits
the user to configure a solution that meets the
Voltage Startup sequencing requirements of FPGAs, DSPs, and other
• VBIAS Permits Low VIN Operation with Good applications with special start-up requirements.
Transient Response A precision reference and error amplifier deliver 2%
• Stable with Any Output Capacitor ≥2.2mFaccuracy over load, line, temperature, and process.
• Available in 5mm × 5mm × 1mm QFN and The device is stable with any type of capacitor
DDPAK-7 Packages ≥2.2mF, and the device is fully specified from –40°C
• Open-Drain Power-Good to +125°C. The TPS749xx is offered in a small (5mm
× 5mm) QFN package, yielding a highly compact total
• Active High Enable solution size. It is also available in a DDPAK-7.
APPLICATIONS blank
• FPGA Applications blank
• DSP Core and I/O Voltages blank
• Post-Regulation Applications blank
• Applications with Special Start-Up Time or
Sequencing Requirements blank
• Hot-Swap and Inrush Controls blank
Figure 1. Typical Application Circuit (Adjustable)
Figure 2. Turn-On Response
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS749xx
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TPS749xx yyy z XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable).(3)
YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Fixed output voltages from 0.8V to 3.3V are available; minimum order quantities may apply. Contact factory for details and availability.
(3) For fixed 0.8V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS(1)
At TJ= –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
PARAMETER TPS749xx UNIT
VIN, VBIAS Input voltage range –0.3 to +6 V
VEN Enable voltage range –0.3 to +6 V
VPG Power-good voltage range –0.3 to +6 V
IPG PG sink current 0 to +1.5 mA
VSS SS pin voltage range –0.3 to +6 V
VFB Feedback pin voltage range –0.3 to +6 V
VOUT Output voltage range –0.3 to VIN + 0.3 V
IOUT Maximum output current Internally limited
Output short-circuit duration Indefinite
PDISS Continuous total power dissipation See Thermal Information Table
TJOperating junction temperature range –40 to +125 °C
TSTG Storage junction temperature range –55 to +150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
2Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
TPS749xx
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SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
THERMAL INFORMATION TPS74901(2)
THERMAL METRIC(1) UNITS
RGW (20 PINS) KTW (7 PINS)
qJA Junction-to-ambient thermal resistance(3) 30.5 20.1
qJCtop Junction-to-case (top) thermal resistance(4) 27.6 2.1
qJB Junction-to-board thermal resistance(5) N/A N/A °C/W
yJT Junction-to-top characterization parameter(6) 0.37 4.2
yJB Junction-to-board characterization parameter(7) 10.6 6.1
qJCbot Junction-to-case (bottom) thermal resistance(8) 4.1 1.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) Thermal data for the RGW and KTW packages are derived by thermal simulations based on JEDEC-standard methodology as specified
in the JESD51 series. The following assumptions are used in the simulations:
(a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array.
-ii. KTW: The exposed pad is connected to the PCB ground layer through a 6x6 thermal via array.
(b) Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction
Temperature sections.
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
TPS749xx
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
At TJ= –40°C to +125°C, VEN = 1.1V, VIN = VOUT + 0.3V, CBIAS = 0.1mF, CIN = COUT = 10mF, CNR = 1nF, IOUT = 50mA, and
VBIAS = 5.0V, unless otherwise noted. Typical values are at TJ= +25°C. TPS74901
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VOUT + VDO 5.5 V
VBIAS Bias pin voltage range 2.7 5.5 V
VREF Internal reference (Adj.) TJ= +25°C 0.798 0.802 0.806 V
Output voltage range VIN = 5V, IOUT = 3.0V VREF 3.6 V
Accuracy VOUT + 2.2V ≤VBIAS ≤5.5V, –2 ±0.5 2 %
VOUT (RGW package)(1) 50mA ≤IOUT ≤3.0A
Accuracy VOUT + 2.4V ≤VBIAS ≤5.5V, –2 ±0.5 2 %
(KTW package)(1) 50mA ≤IOUT ≤3.0A
VOUT/VIN Line regulation VOUT (NOM) + 0.3 ≤VIN ≤5.5V 0.03 %/V
VOUT/IOUT Load regulation 50mA ≤IOUT ≤3.0A 0.09 %/A
IOUT = 3.0A,
VIN dropout voltage(2) 120 280 mV
VBIAS – VOUT (NOM) ≥3.25V(3)
VDO VBIAS dropout voltage(2) IOUT = 3.0A, VIN = VBIAS 1.31 1.75 V
VOUT = 80% × VOUT (NOM), RGW 3.9 4.6 5.5
Package
ICL Current limit A
VOUT = 80% × VOUT (NOM), KTW 3.8 4.6 5.5
Package
IBIAS Bias pin current 1 2 mA
Shutdown supply current
ISHDN VEN ≤0.4V 1 50 mA
(IGND)
IFB Feedback pin current –1 0.150 1 mA
1kHz, IOUT = 1.5A, 60
VIN = 1.8V, VOUT = 1.5V
Power-supply rejection dB
(VIN to VOUT)300kHz, IOUT = 1.5A, 30
VIN = 1.8V, VOUT = 1.5V
PSRR 1kHz, IOUT = 1.5A, 50
VIN = 1.8V, VOUT = 1.5V
Power-supply rejection dB
(VBIAS to VOUT)300kHz, IOUT = 1.5A, 30
VIN = 1.8V, VOUT = 1.5V
100Hz to 100kHz,
Noise Output noise voltage 25 × VOUT mVRMS
IOUT = 3.0A, CSS = 0.001mF
tSTR Minimum startup time RLOAD for IOUT = 1.0A, CSS = open 200 ms
ISS Soft-start charging current VSS = 0.4V 440 nA
VEN, HI Enable input high level 1.1 5.5 V
VEN, LO Enable input low level 0 0.4 V
VEN, HYS Enable pin hysteresis 50 mV
VEN, DG Enable pin deglitch time 20 ms
IEN Enable pin current VEN = 5V 0.1 1 mA
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 3 %VOUT
VPG, LO PG output low voltage IPG = 1mA (sinking), VOUT < VIT 0.3 V
IPG, LKG PG leakage current VPG = 5.25V, VOUT > VIT 0.1 1 mA
Operating junction
TJ–40 +125 °C
temperature Shutdown, temperature increasing +165
Thermal shutdown
TSD °C
temperature Reset, temperature decreasing +140
(1) Adjustable devices tested at 0.8V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25V is a test condition of this device and can be adjusted by referring to Figure 8 .
4Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
t (s) =
SS
V C
I
REF SS
SS
×0.8V C (F)
0.44 A
SS
m
×
=
Thermal
Limit
Soft-Start
Discharge
OUT VOUT
FB
PG
IN
BIAS
SS
EN Hysteresis
andDeglitch
Current
Limit
UVLO
0.44 Am
0.8V
Reference
0.9 ´VREF
GND
CSS
R1
R2
(1) where tSS(s) = soft-start time in seconds.
TPS749xx
www.ti.com
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
BLOCK DIAGRAM
Table 1. Standard 1% Resistor Values for Programming the Output Voltage(1)
R1(kΩ) R2(kΩ) VOUT (V)
Short Open 0.8
0.619 4.99 0.9
1.13 4.53 1.0
1.37 4.42 1.05
1.87 4.99 1.1
2.49 4.99 1.2
4.12 4.75 1.5
3.57 2.87 1.8
3.57 1.69 2.5
3.57 1.15 3.3
(1) VOUT = 0.8 × (1 + R1/R2)
Table 2. Standard Capacitor Values for Programming the Soft-Start Time(1)
CSS SOFT-START TIME
Open 0.1ms
270pF 0.5ms
560pF 1ms
2.7nF 5ms
5.6nF 10ms
0.01mF 18ms
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
IN
IN
IN
PG
BIAS
OUT
OUT
OUT
NC
FB
IN
EN 11
GND 12
NC 13
NC 14
SS 15
6
7
8
9
10
20
19
18
17
16
5
NC4
NC3
NC2
OUT1
OUT
GND
BIAS
IN
FB
SS
1 2 3 4 56
EN
7
TPS749xx
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
www.ti.com
PIN ASSIGNMENTS
RGW PACKAGE KTW PACKAGE
QFN-20 DDPAK-7
(TOP VIEW) (TOP VIEW)
PIN DESCRIPTIONS
NAME KTW (DDPAK) RGW (QFN) DESCRIPTION
IN 5 5–8 Unregulated input to the device.
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts
EN 7 11 the regulator into shutdown mode. This pin must not be left floating.
SS 1 15 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up
time. If this pin is left floating, the regulator output soft-start ramp time is
typically 100ms.
BIAS 6 10 Bias input voltage for error amplifier, reference, and internal control circuits.
Power-Good (PG) is an open-drain, active-high output that indicates the status
of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a
high-impedance state. When VOUT is below this threshold the pin is driven to a
PG N/A 9 low-impedance state. A pull-up resistor from 10kΩto 1MΩshould be connected
from this pin to a supply up to 5.5V. The supply can be higher than the input
voltage. Alternatively, the PG pin can be left floating if output monitoring is not
necessary.
This pin is the feedback connection to the center tap of an external resistor
FB 2 16 divider network that sets the output voltage. This pin must not be left floating.
OUT 3 1, 18–20 Regulated output voltage. A small capacitor (total typical capacitance ≥2.2mF,
ceramic) is needed from this pin to ground to assure stability.
No connection. This pin can be left floating or connected to GND to allow better
NC N/A 2–4, 13, 14, 17 thermal contact to the top-side plane.
GND 4 12 Ground
PAD/TAB Should be soldered to the ground plane for increased thermal performance.
6Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
0.20
0.15
0.10
0.05
0
-0.05
-0.01
-0.15
-0.20
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
ChangeinV (%)
OUT
V V-
IN OUT (V)
5.0
+125 C°
+25 C°
- °40 C
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5
ChangeinV (%)
OUT
V V-
BIAS OUT (V)
4.0
+125 C°+25 C°
- °40 C
0.5
0.4
03
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
01.0 1.50.5 2.0 2.5
ChangeinV (%)
OUT
I (A)
OUT
3.0
- °40 C
+125 C°
+25 C°
180
160
140
120
100
80
60
40
20
0
01.0 1.50.5 2.0 2.5
VDO IN OUT
(V -V )(mV)
I (A)
OUT
3.0
+125 C°
+25 C°
- °40 C
400
350
300
250
200
150
100
50
0
1.0 1.5
V (V -
DO IN OUT
V )(mV)
V V-
BIAS OUT (V)
4.5
+125 C°
+25 C°
- °40 C
2.0 2.5 3.0 3.5 4.0
I =3A
OUT
TPS749xx
www.ti.com
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
TYPICAL CHARACTERISTICS
At TJ= +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF,
unless otherwise noted.
VIN LINE REGULATION VBIAS LINE REGULATION
Figure 3. Figure 4.
LOAD REGULATION LOAD REGULATION
Figure 5. Figure 6.
VIN DROPOUT VOLTAGE vs VIN DROPOUT VOLTAGE vs
iOUT AND TEMPERATURE (TJ) VIN DROPOUT VOLTAGE vs IOUT AND TEMPERATURE (TJ)
Figure 7. Figure 8.
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
2200
2000
1800
1600
1400
1200
1000
800
600
01.0 1.50.5 2.0 2.5
VDO BIAS OUT
(V -V )(mV)
I (A)
OUT
3.0
+125 C°
+25 C°
- °40 C
200
180
160
140
120
100
80
60
40
20
0
01.51.00.5 2.0 2.5 3.0 3.5 4.0
V (mV)
DO IN OUT
(V V )-
V V-
BIAS OUT (V)
4.5
+125 C°
+25 C°
- °40 C
I =0.5A
OUT
90
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Power-SupplyRejectionRatio(dB)
Frequency(Hz)
10M
V =1.8V
IN
V =1.2V
OUT
V =5V
BIAS
C =1nF
SS
I =0.5A
OUT
I =0.1A
OUT I =1.5A
OUT
80
90
80
70
60
50
40
30
20
10
0
00.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Power-SupplyRejectionRatio(dB)
V V-
IN OUT (V)
2.25
1kHz
10kHz
500kHz
100kHz
VOUT =1.2V
IOUT =1.5A
CSS =1nF
1
0.1
0.01
100 1k 10k
OutputSpectralNoiseDensity(mV/Ö)Hz
Frequency(Hz)
100k
C =1nF
SS
C =0nF
SS
C =10nF
SS
I =100mA
OUT
V =1.2V
OUT
TPS749xx
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF,
unless otherwise noted.
VIN DROPOUT VOLTAGE vs VBIAS DROPOUT VOLTAGE vs
(VBIAS – VOUT) AND TEMPERATURE (TJ) IOUT AND TEMPERATURE (TJ)
Figure 9. Figure 10.
VBIAS PSRR vs FREQUENCY VIN PSRR vs FREQUENCY
Figure 11. Figure 12.
VIN PSRR vs (VIN – VOUT) NOISE SPECTRAL DENSITY
Figure 13. Figure 14.
8Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
I (mA)
BIAS
V (V)
BIAS
5.5
+125 C°
+25 C°
- °40 C
500
475
450
425
400
375
350
325
300
-50 -25 0 25 50 75 100
I (nA)
SS
JunctionTemperature( C)°
125
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V Low-LevelPGVoltage(V)
OL
02 4 6 8 10 12
PGCurrent(mA)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
1.0 2.0 2.51.5 3.0 3.5 4.0 4.5
CurrentLimit(A)
VBIAS OUT
-V (V)
5.0
+125 C°
- °40 C
+25 C°
V =0.8V
OUT
DrivecapabilityofoutputFETlimits
I whenV V isunder2.0V.
OUT BIAS OUT
-
TPS749xx
www.ti.com
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF,
unless otherwise noted.
BIAS PIN CURRENT vs BIAS PIN CURRENT vs
IOUT AND TEMPERATURE (TJ) VBIAS AND TEMPERATURE (TJ)
Figure 15. Figure 16.
SOFT-START CHARGING CURRENT (ISS) vs
TEMPERATURE (TJ) LOW-LEVEL PG VOLTAGE vs CURRENT
Figure 17. Figure 18.
CURRENT LIMIT vs (VBIAS – VOUT)
Figure 19.
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
100mV/div
100mV/div
1V/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
5.0V
1V/ sm
3.3V
C =1nF
SS
100mV/div
1V/div
Time(50 s/div)m
C =10 F(Ceramic)
OUT m
3.8V
1V/ sm
1.8V
C =1nF
SS
100mV/div
100mV/div
100mV/div
2A/div
Time(50 s/div)m
C =22 F(Ceramic)
OUT m
C =100 F(Ceramic)
OUT m
C =470 F(OSCON)
OUT m
50mA
3A
1A/ sm
C =1nF
SS
0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
1.2V
0V
1V/div
Time(20ms/div)
V (500mV/div)
PG
VOUT
V =V =V
IN BIAS EN
TPS749xx
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
At TJ= +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 1A, VEN = VIN = 1.8V, VOUT = 1.5V, CIN = 1mF, CBIAS = 4.7mF, and
COUT = 10mF, unless otherwise noted.
VBIAS LINE TRANSIENT VIN LINE TRANSIENT
Figure 20. Figure 21.
OUTPUT LOAD TRANSIENT RESPONSE TURN-ON RESPONSE
Figure 22. Figure 23.
POWER-UP/POWER-DOWN
Figure 24.
10 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
VOUT
COUT
10 Fm
TPS74901
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
CIN
1 Fm
CSS
VBIAS
CBIAS
1 Fm
V =0.8
OUT ´1+ R1
R2
)(
TPS749xx
www.ti.com
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
APPLICATION INFORMATION
The TPS749xx belongs to a family of low dropout INPUT, OUTPUT, AND BIAS CAPACITOR
regulators that feature soft-start capabilities. These REQUIREMENTS
regulators use a low current bias input to power all The device is designed to be stable for all available
internal control circuitry, allowing the NMOS pass types of and values of output capacitors ≥2.2mF. The
transistor to regulate very low input and output device is also stable with multiple capacitors in
voltages. parallel, which can be of any type or value.
The use of an NMOS-pass FET offers several critical The capacitance required on the IN and BIAS pin
advantages for many applications. Unlike a PMOS strongly depends on the input supply source
topology device, the output capacitor has little effect impedance. To counteract any inductance in the
on loop stability. This architecture allows the input, the minimum recommended capacitor for VINTPS749xx to be stable with any capacitor type of and VBIAS is 1mF. If VIN and VBIAS are connected to
value 2.2mF or greater. Transient response is also the same supply, the recommended minimum
superior to PMOS topologies, particularly for low VIN capacitor for VBIAS is 4.7mF. Good quality, low ESR
applications. capacitors should be used on the input; ceramic X5R
The TPS749xx features a programmable and X7R capacitors are preferred. These capacitors
voltage-controlled soft-start circuit that provides a should be placed as close the pins as possible for
smooth, monotonic start-up and limits startup inrush optimum performance.
currents that may be caused by large capacitive
loads. A power-good (PG) output is available to allow TRANSIENT RESPONSE
supply monitoring and sequencing of other supplies. The TPS749xx is designed to have excellent transient
An enable (EN) pin with hysteresis and deglitch response for most applications with a small amount of
allows slow-ramping signals to be used for output capacitance. In some cases, the transient
sequencing the device. The low VIN and VOUT response may be limited by the transient response of
capability allows for inexpensive, easy-to-design, and the input supply. This limitation is especially true in
efficient linear regulation between the multiple supply applications where the difference between the input
voltages often present in processor intensive and output is less than 300mV. In this case, adding
systems. additional input capacitance improves the transient
Figure 25 illustrates the typical application circuit for response much more than just adding additional
the TPS749xx adjustable output device. output capacitance would do. With a solid input
supply, adding additional output capacitance reduces
R1and R2can be calculated for any output voltage undershoot and overshoot during a transient event;
using the formula shown in Figure 25. Refer to refer to Figure 22 in the Typical Characteristics
Table 1 for sample resistor values of common output section. Because the TPS749xx is stable with output
voltages. In order to achieve the maximum accuracy capacitors as low as 2.2mF, many applications may
specifications, R2should be ≤4.99kΩ.need very little capacitance at the LDO output. For
these applications, local bypass capacitance for the
powered device may be sufficient to meet the
transient requirements of the application. This design
reduces the total solution cost by avoiding the need
to use expensive high-value capacitors at the LDO
output.
Figure 25. Typical Application Circuit for the
TPS749xx (Adjustable)
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN
VIN
V =3.3V 5%
BIAS ±
V =3.3V 5V
V =1.5V
I =1.5A
Efficiency=45%
IN
OUT
OUT
±
COUT
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN V =5V 5%
BIAS ±
V =1.8V
V =1.5V
I =1.5A
Efficiency=83%
IN
OUT
OUT
COUT
t =
SS
(V xC )
REF SS
ISS
t =
SSCL
(V xC )
OUT(NOM) OUT
ICL(MIN)
TPS749xx
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
www.ti.com
DROPOUT VOLTAGE
The TPS749xx offers very low dropout performance,
making it well-suited for high-current low VIN/low VOUT
applications. The low dropout of the TPS749xx allows
the device to be used in place of a DC/DC converter
and still achieve good efficiencies. This provides
designers with the power architecture for their
applications to achieve the smallest, simplest, and
lowest cost solution.
There are two different specifications for dropout
voltage with the TPS749xx. The first specification
(see Figure 26) is referred to as VIN Dropout and is
used when an external bias voltage is applied to
achieve low dropout. This specification assumes that
VBIAS is at least 3.25V(1) above VOUT, which is the Figure 27. Typical Application of the TPS749xx
case for VBIAS when powered by a 5.0V rail with 5% Without an Auxiliary Bias
tolerance and with VOUT = 1.5V. If VBIAS is
higher than VOUT + 3.25V, VIN dropout is less than
specified(1).PROGRAMMABLE SOFT-START
The TPS749xx features a programmable, monotonic,
voltage-controlled soft-start that is set with an
external capacitor (CSS). This feature is important for
many applications because it eliminates power-up
initialization problems when powering FPGAs, DSPs,
or other processors. The controlled voltage ramp of
the output also reduces peak inrush current during
start-up, minimizing start-up transient events to the
input power bus.
To achieve a linear and monotonic soft-start, the
TPS749xx error amplifier tracks the voltage ramp of
the external soft-start capacitor until the voltage
exceeds the internal reference. The soft-start ramp
time is dependent on the soft-start charging current
Figure 26. Typical Application of the TPS749xx (ISS), soft-start capacitance (CSS), and the internal
Using an Auxiliary Bias Rail reference voltage (VREF), and can be calculated using
Equation 1:
The second specification (shown in Figure 27) is
referred to as VBIAS Dropout and applied to
applications where IN and BIAS are tied together. (1)
This option allows the device to be used in If large output capacitors are used, the device current
applications where an auxiliary bias voltage is not limit (ICL) and the output capacitor may set the
available or low dropout is not required. Dropout is start-up time. In this case, the start-up time is given
limited by BIAS in these applications because VBIAS by Equation 2:
provides the gate drive to the pass FET; therefore,
VBIAS must be 1.75V above VOUT. Dropout is limited
by BIAS in these applications because VBIAS provides (2)
the gate drive to the pass FET; therefore, VBIAS must
be 1.75V above VOUT. Because of this usage, IN and where:
BIAS tied together easily consume huge power. Pay VOUT(NOM) is the nominal set output voltage,
attention not to exceed the power rating of the IC
package. COUT is the output capacitance, and
ICL(MIN) is the minimum current limit for the device.
In applications where monotonic startup is required,
the soft-start time given by Equation 1 should be set
to be greater than Equation 2.
(1) 3.25V is a test condition of this device and can be adjusted by
referring to Figure 8 .
12 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
V (
N RMS
mV )=25xV (V)
OUT
mVRMS
V
TPS74901
GND SS
OUT
FB
EN
IN
BIAS
VIN VOUT
R2
R1
CSS
CIN
C
VBIAS
CBIAS
R
COUT
TPS749xx
www.ti.com
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
The maximum recommended soft-start capacitor is OUTPUT NOISE
0.015mF. Larger soft-start capacitors can be used and The TPS749xx provides low output noise when a
will not damage the device; however, the soft-start soft-start capacitor is used. When the device reaches
capacitor discharge circuit may not be able to fully the end of the soft-start cycle, the soft-start capacitor
discharge the soft-start capacitor when enabled. serves as a filter for the internal reference. By using a
Soft-start capacitors larger than 0.015mF could be a 0.001mF soft-start capacitor, the output noise is
problem in applications where the user needs to reduced by half and is typically 30mVRMS for a 1.2V
rapidly pulse the enable pin and still requires the output (10Hz to 100kHz). Further increasing CSS has
device to soft-start from ground. CSS must be little effect on noise, Because most of the output
low-leakage; X7R, X5R, or C0G dielectric materials noise is generated by the internal reference, the
are preferred. Refer to Table 2 for suggested noise is a function of the set output voltage. The RMS
soft-start capacitor values. noise with a 0.001mF soft-start capacitor is given in
Equation 3.
SEQUENCING REQUIREMENTS
VIN, VBIAS, and VEN can be sequenced in any order (3)
without causing damage to the device. However, for
the soft-start function to work as intended, certain The low output noise of the TPS749xx makes it a
sequencing rules must be applied. Connecting EN to good choice for powering transceivers, PLLs, or other
IN is acceptable for most applications as long as VIN noise-sensitive circuitry.
is greater than 1.1V and the ramp rate of VIN and
VBIAS is faster than the set soft-start ramp rate. If the ENABLE/SHUTDOWN
ramp rate of the input sources is slower than the set The enable (EN) pin is active high and is compatible
soft-start time, the output tracks the slower supply with standard digital signaling levels. VEN below 0.4V
minus the dropout voltage until it reaches the set turns the regulator off, while VEN above 1.1V turns the
output voltage. If EN is connected to BIAS, the device regulator on. Unlike many regulators, the enable
will soft-start as programmed, provided that VIN is circuitry has hysteresis and deglitching for use with
present before VBIAS. If VBIAS and VEN are present relatively slowly ramping analog signals. This
before VIN is applied and the set soft-start time has configuration allows the TPS749xx to be enabled by
expired, then VOUT tracks VIN. If the soft-start time has connecting the output of another supply to the EN
not expired, the output tracks VIN until VOUT reaches pin. The enable circuitry typically has 50mV of
the value set by the charging soft-start capacitor. hysteresis and a deglitch circuit to help avoid on-off
Figure 28 shows the use of an RC-delay circuit to cycling because of small glitches in the VEN signal.
hold off VEN until VBIAS has ramped. This technique
can also be used to drive EN from VIN. An external The enable threshold is typically 0.8V and varies with
control signal can also be used to enable the device temperature and process variations. Temperature
after VIN and VBIAS are present. variation is approximately –1mV/°C; process variation
accounts for most of the rest of the variation to the
NOTE: When VBIAS and VEN are present and VIN is 0.4V and 1.1V limits. If precise turn-on timing is
not supplied, this device outputs approximately 50mArequired, a fast rise-time signal must be used to
of current from OUT. Although this condition will not enable the TPS749xx.
cause any damage to the device, the output current
may charge up the OUT node if total resistance If not used, EN can be connected to either IN or
between OUT and GND (including external feedback BIAS. If EN is connected to IN, it should be
resistors) is greater than 10kΩ.connected as close as possible to the largest
capacitance on the input to prevent voltage droops on
that line from triggering the enable circuit.
POWER-GOOD
The power-good (PG) pin is an open-drain output and
can be connected to any 5.5V or lower rail through an
external pull-up resistor. This pin requires at least
1.1V on VBIAS in order to have a valid output. The PG
output is high-impedance when VOUT is greater than
VIT + VHYS. If VOUT drops below VIT or if VBIAS drops
Figure 28. Soft-Start Delay Using an RC Circuit below 1.9V, the open-drain output turns on and pulls
on Enable the PG output low. The PG pin also asserts when the
device is disabled. The recommended operating
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
P =(V V )xI-
D IN OUTOUT
R =
qJA
(+125 C T )° - A
PD
TPS749xx
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
www.ti.com
condition of PG pin sink current is up to 1mA, so the LAYOUT RECOMMENDATIONS AND POWER
pull-up resistor for PG should be in the range of 10kΩDISSIPATION
to 1MΩ. PG is only provided on the QFN package. If An optimal layout can greatly improve transient
output voltage monitoring is not needed, the PG pin performance, PSRR, and noise. To minimize the
can be left floating. voltage droop on the input of the device during load
transients, the capacitance on IN and BIAS should be
INTERNAL CURRENT LIMIT connected as close as possible to the device. This
capacitance also minimizes the effects of parasitic
The TPS749xx features a factory-trimmed, accurate inductance and resistance of the input source and
current limit that is flat over temperature and supply can therefore improve stability. To achieve optimal
voltage. The current limit allows the device to supply transient performance and accuracy, the top side of
surges of up to 4A and maintain regulation. The R1in Figure 25 should be connected as close as
current limit responds in about 10ms to reduce the possible to the load. If BIAS is connected to IN it is
current during a short-circuit fault. recommended to connect BIAS as close to the sense
The internal current limit protection circuitry of the point of the input supply as possible. This connection
TPS749xx is designed to protect against overload minimizes the voltage droop on BIAS during transient
conditions. It is not intended to allow operation above conditions and can improve the turn-on response.
the rated current of the device. Continuously running Knowing the device power dissipation and proper
the TPS749xx above the rated current degrades sizing of the thermal plane that is connected to the
device reliability. tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation. Power dissipation of
THERMAL PROTECTION the device depends on input voltage and load
Thermal protection disables the output when the conditions and can be calculated using Equation 4:
junction temperature rises to approximately +160°C, (4)
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the Power dissipation can be minimized and greater
output circuitry is enabled. Depending on power efficiency can be achieved by using the lowest
dissipation, thermal resistance, and ambient possible input voltage necessary to achieve the
temperature the thermal protection circuit may cycle required output voltage regulation.
on and off. This cycling limits the dissipation of the On the QFN (RGW) package, the primary conduction
regulator, protecting it from damage as a result of path for heat is through the exposed pad to the
overheating. printed circuit board (PCB). The pad can be
Activation of the thermal protection circuit indicates connected to ground or be left floating; however, it
excessive power dissipation or inadequate should be attached to an appropriate amount of
heatsinking. For reliable operation, junction copper PCB area to ensure the device will not
temperature should be limited to +125°C maximum. overheat. On the DDPAK (KTW) package, the
To estimate the margin of safety in a complete design primary conduction path for heat is through the tab to
(including heatsink), increase the ambient the PCB. That tab should be connected to ground.
temperature until thermal protection is triggered; use The maximum junction-to-ambient thermal resistance
worst-case loads and signal conditions. For good depends on the maximum ambient temperature,
reliability, thermal protection should trigger at least maximum device junction temperature, and power
+40°C above the maximum expected ambient dissipation of the device and can be calculated using
condition of the application. This condition produces a Equation 5:
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load. (5)
The internal protection circuitry of the TPS749xx is Knowing the maximum RqJA, the minimum amount of
designed to protect against overload conditions. It is PCB copper area needed for appropriate heatsinking
not intended to replace proper heatsinking. can be estimated using Figure 29.
Continuously running the TPS749xx into thermal
shutdown degrades device reliability.
14 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
Y Y
JT J T JT D
:T =T + P·
Y Y
JB J B JB D
:T =T + P·
120
100
80
60
40
20
0
qJA ( C/W)
°
0 1 2 3 4 5 678 9 10
BoardCopperArea(in )
2
qJA (KTW)
qJA (RGW)
TPS749xx
www.ti.com
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction
Temperature section.
ESTIMATING JUNCTION TEMPERATURE
Using the thermal metrics ΨJT and ΨJB, shown in the
Thermal Information table, the junction temperature
can be estimated with corresponding formulas (given
in Equation 6). For backwards compatibility, an older
qJC,Top parameter is listed as well.
(6)
Where PDis the power dissipation shown by
Note: qJA value at board size of 9in2(that is, 3in × Equation 4, TTis the temperature at the center-top of
3in) is a JEDEC standard. the IC package, and TBis the PCB temperature
Figure 29. qJA vs Board Size measured 1mm away from the IC package on the
PCB surface (refer to Figure 30).
Figure 29 shows the variation of qJA as a function of NOTE: Both TTand TBcan be measured on actual
ground plane copper area in the board. It is intended application boards using a thermo-gun (an infrared
only as a guideline to demonstrate the effects of heat thermometer).
spreading in the ground plane and should not be For more information about measuring TTand TB, see
used to estimate actual thermal performance in real the application note Using New Thermal Metrics
application environments. (SBVA025), available for download at www.ti.com.
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
T on PCB
BT on of ICtop
T
1mm
(a) Example RGW (QFN) Package Measurement (b) Example KTW (DDPAK) Package Measurement
1mm
T on of IC
Ttop (1)
T on PCB
surface
B
(2)
TPS749xx
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
www.ti.com
(1) TTis measured at the center of both the X- and Y-dimensional axes.
(2) TBis measured below the package lead on the PCB surface.
Figure 30. Measuring Points for TTand TB
16 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
12
10
8
6
4
2
0
Y Yand ( C/W)
JT JB °
0 2 46 8 10
BoardCopperArea(in )
2
YJT (KTW)
YJT (RGW)
YJB (RGW)
YJB (KTW)
TPS749xx
www.ti.com
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
Compared with qJA, the new thermal metrics ΨJT and
ΨJB are less independent of board size, but they do
have a small dependency. Figure 31 shows
characteristic performance of ΨJT and ΨJB versus
board size.
Looking at Figure 31, the RGW package thermal
performance has negligible dependency on board
size. The KTW package, however, does have a
measurable dependency on board size. This
dependency exists because the package shape is not
point-symmetric to an IC center. In the KTW package,
for example (see Figure 30), silicon is not beneath
the measuring point of TTwhich is the center of the X
and Y dimension, so that ΨJT has a dependency.
Also, because of that non-point-symmetry, device
heat distribution on the PCB is not point-symmetric, Figure 31. ΨJT and ΨJB vs Board Size
either, so that ΨJB has a dependency.
space For a more detailed discussion of why TI does not
recommend using qJC,Top to determine thermal
characteristics, refer to the application note Using
New Thermal Metrics (SBVA025), available for
download at www.ti.com. Also, refer to the application
note IC Package Thermal Metrics (SPRA953) (also
available on the TI web site) for further information.
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
TPS749xx
SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August, 2010) to Revision G Page
• Corrected equation for and updated values for Table 2 ....................................................................................................... 5
Changes from Revision E (January, 2010) to Revision F Page
• Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 3
• Revised Layout Recommendations and Power Dissipation section ................................................................................... 14
• Added Estimating Junction Temperature ............................................................................................................................ 15
• Deleted (previously numbered) Figure 29 through Figure 33 ............................................................................................. 17
18 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 6-Nov-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS74901KTWR ACTIVE DDPAK KTW 7 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS74901KTWRG3 ACTIVE DDPAK KTW 7 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS74901KTWT ACTIVE DDPAK KTW 7 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS74901KTWTG3 ACTIVE DDPAK KTW 7 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS74901RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74901RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74901RGWT ACTIVE VQFN RGW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74901RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Nov-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS74901KTWR DDPAK KTW 7 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS74901KTWT DDPAK KTW 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS74901RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS74901RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS74901KTWR DDPAK KTW 7 500 367.0 367.0 45.0
TPS74901KTWT DDPAK KTW 7 50 367.0 367.0 45.0
TPS74901RGWR VQFN RGW 20 3000 367.0 367.0 35.0
TPS74901RGWT VQFN RGW 20 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPSF015 – AUGUST 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT
0.010 (0,25) AM
4201284/A 08/01
0.385 (9,78)
0.410 (10,41)
MM
BC
–A– 0.006
–B–
0.170 (4,32)
0.183 (4,65)
0.000 (0,00)
0.012 (0,305)
0.104 (2,64)
0.096 (2,44)
0.034 (0,86)
0.022 (0,57)
0.050 (1,27)
0.055 (1,40)
0.045 (1,14)
0.014 (0,36)
0.026 (0,66)
0.330 (8,38)
0.370 (9,40)
0.297 (7,54)
0.303 (7,70)
0.0585 (1,485)
0.0625 (1,587)
0.595 (15,1 1)
0.605 (15,37)
0.019 (0,48)
0.017 (0,43)
0°~3°
0.179 (4,55)
0.187 (4,75)
0.056 (1,42)
0.064 (1,63)
0.296 (7,52)
0.304 (7,72)
0.300 (7,62)
0.252 (6,40)
F
C
C
H
H
H
C
A
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.
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