TL082-N www.ti.com SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 TL082 Wide Bandwidth Dual JFET Input Operational Amplifier Check for Samples: TL082-N FEATURES DESCRIPTION * * * * * * * * * * * These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset voltage ( BI-FET IITM technology). They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The TL082 is pin compatible with the standard LM1558 allowing designers to immediately upgrade the overall performance of existing LM1558 and most LM358 designs. 1 23 Internally Trimmed Offset Voltage: 15 mV Low Input Bias Current: 50 pA Low Input Noise Voltage: 16nV/Hz Low Input Noise Current: 0.01 pA/Hz Wide Gain Bandwidth: 4 MHz High Slew Rate: 13 V/s Low Supply Current: 3.6 mA High Input Impedance: 1012 Low Total Harmonic Distortion: 0.02% Low 1/f Noise Corner: 50 Hz Fast Settling Time to 0.01%: 2 s These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift. Typical Connection Connection Diagram Figure 1. PDIP/SOIC Package (Top View) See Package Number D0008A or P0008E 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. BI-FET II is a trademark of dcl_owner. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1998-2013, Texas Instruments Incorporated TL082-N SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 www.ti.com Simplified Schematic These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage Power Dissipation 18V (3) (4) Operating Temperature Range 0C to +70C Tj(MAX) 150C Differential Input Voltage Input Voltage Range 30V (5) 15V Output Short Circuit Duration Continuous Storage Temperature Range -65C to +150C Lead Temp. (Soldering, 10 seconds) 260C ESD rating to be determined. (1) (2) (3) (4) (5) 2 "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The power dissipation limit, however, cannot be exceeded. For operating at elevated temperature, the device must be derated based on a thermal resistance of 115C/W junction to ambient for the P0008E package. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N TL082-N www.ti.com SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 DC Electrical Characteristics Symbol VOS (1) Parameter Conditions Input Offset Voltage TL082C Min RS = 10 k, TA = 25C Max 5 15 mV 20 mV Over Temperature VOS/T Average TC of Input Offset Voltage RS = 10 k IOS Input Offset Current Tj = 25C, 25 Tj 70C IB Input Bias Current Tj = 25C, V/C 10 (1) (2) (1) (2) Units Typ 50 Tj 70C 200 pA 4 nA 400 pA 8 nA 1012 100 V/mV RIN Input Resistance Tj = 25C AVOL Large Signal Voltage Gain VS = 15V, TA = 25C, VO = 10V, RL = 2 k Over Temperature 15 VO Output Voltage Swing VS = 15V, RL = 10 k 12 13.5 V VCM Input Common-Mode Voltage Range VS = 15V 11 +15 V CMRR Common-Mode Rejection Ratio RS 10 k PSRR Supply Voltage Rejection Ratio IS Supply Current (3) 25 V/mV -12 V 70 100 dB 70 100 3.6 dB 5.6 mA These specifications apply for VS = 15V and 0C TA +70C. VOS, IB and IOS are measured at VCM = 0. The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, Tj. Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj = TA + jA PD where jA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS = 6V to 15V. (1) (2) (3) AC Electrical Characteristics Symbol (1) Parameter Conditions TL082C Min Typ -120 Max Units Amplifier to Amplifier Coupling TA = 25C, f = 1Hz-20 kHz (Input Referred) SR Slew Rate VS = 15V, TA = 25C 13 V/s GBW Gain Bandwidth Product VS = 15V, TA = 25C 4 MHz en Equivalent Input Noise Voltage TA = 25C, RS = 100, f = 1000 Hz 25 nV/Hz in Equivalent Input Noise Current Tj = 25C, f = 1000 Hz 0.01 pA/Hz THD Total Harmonic Distortion AV = +10, RL = 10k, VO = 20 Vp - p, BW = 20 Hz-20 kHz <0.02 % (1) 8 dB These specifications apply for VS = 15V and 0C TA +70C. VOS, IB and IOS are measured at VCM = 0. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N 3 TL082-N SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics 4 Input Bias Current Input Bias Current Figure 2. Figure 3. Supply Current Positive Common-Mode Input Voltage Limit Figure 4. Figure 5. Negative Common-Mode Input Voltage Limit Positive Current Limit Figure 6. Figure 7. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N TL082-N www.ti.com SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 Typical Performance Characteristics (continued) Negative Current Limit Voltage Swing Figure 8. Figure 9. Output Voltage Swing Gain Bandwidth Figure 10. Figure 11. Bode Plot Slew Rate Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N 5 TL082-N SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) 6 Distortion vs Frequency Undistorted Output Voltage Swing Figure 14. Figure 15. Open Loop Frequency Response Common-Mode Rejection Ratio Figure 16. Figure 17. Power Supply Rejection Ratio Equivalent Input Noise Voltage Figure 18. Figure 19. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N TL082-N www.ti.com SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 Typical Performance Characteristics (continued) Open Loop Voltage Gain (V/V) Output Impedance Figure 20. Figure 21. Inverter Setting Time Figure 22. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N 7 TL082-N SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 www.ti.com Pulse Response 8 Small Signal Inverting Large Signal Inverting Figure 23. Figure 24. Small Signal Non-Inverting Large Signal Non-Inverting Figure 25. Figure 26. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N TL082-N www.ti.com SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 Pulse Response (continued) Current Limit (RL = 100) Figure 27. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N 9 TL082-N SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 www.ti.com APPLICATION HINTS These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and force the amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on 6V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 k load resistance to 10V over the full temperature range of 0C to +70C. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. Because these amplifiers are JFET rather than MOSFET input op amps they do not require special handling. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize "pick-up" and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. 10 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N TL082-N www.ti.com SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 Detailed Schematic Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N 11 TL082-N SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 www.ti.com Typical Applications * All potentiometers are linear taper * Use the LF347 Quad for stereo applications All controls flat. Bass and treble boost, mid flat. Bass and treble cut, mid flat. Mid boost, bass and treble flat. Mid cut, bass and treble flat. Figure 28. Three-Band Active Tone Control 12 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N TL082-N www.ti.com SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 and are separate isolated grounds Matching of R2's, R4's and R5's control CMRR With AVT = 1400, resistor matching = 0.01%: CMRR = 136 dB * Very high input impedance * Super high CMRR Figure 29. Improved CMRR Instrumentation Amplifier Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N 13 TL082-N SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 www.ti.com Figure 30. Fourth Order Low Pass Butterworth Filter Figure 31. Fourth Order High Pass Butterworth Filter 14 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N TL082-N www.ti.com SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 Figure 32. Ohms to Volts Converter Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N 15 TL082-N SNOSBW5C - APRIL 1998 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C * 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: TL082-N PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TL082CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 TL 082CM TL082CMX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 TL 082CM TL082CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 TL 082CM TL082CP/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 TL082 CP TL082CP/PB NRND PDIP P 8 40 TBD Call TI Call TI TL082 CP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TL082CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 TL082CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL082CMX SOIC D 8 2500 367.0 367.0 35.0 TL082CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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