ESDAVLC8-1BU2 - STMICROELECTRONICS

This is information on a product in full production.

May 2012 Doc ID 16546 Rev 2 1/11

ESDAVLC8-1BU2

Single-line low capacitance Transil™, transient surge voltage

suppressor (TVS) for bidirectional ESD protection

Datasheet − production data

Features

■Bidirectional device

■Withstands multiple ESD strikes

■Very low diode capacitance: 5 pF typ. at 0 V

■Low leakage current

■0201 SMD package size compatible

■Ultra small PCB area: 0.18 mm2

■RoHS compliant

Benefits

■High ESD protection level

■High integration

■Suitable for high density boards

■MSL1

Complies with the following standards:

■IEC 61000-4-2 level 4

– 15 kV (air discharge)

– 8 kV (contact discharge)

Applications

Where transient overvoltage protection in ESD

sensitive equipment is required, such as:

■Portable multimedia players and accessories

■Notebooks

■Digital cameras and camcorders

■Communication systems

■Cellular phone handsets and accessories

Figure 1. Functional diagram (top view)

Description

The ESDAVLC8-1BU2 is a bidirectional single line

TVS diode designed to protect the data lines or

other I/O ports against ESD transients.

The device is ideal for applications where both

reduced line capacitance and board space saving

are required.

TM: Transil is a trademark of STMicroelectronics

Pin 2 available in different forms

ST0201 package

www.st.com

Characteristics ESDAVLC8-1BU2

2/11 Doc ID 16546 Rev 2

1 Characteristics

Figure 2. Electrical characteristics (definitions)

Table 1. Absolute maximum ratings (Tamb = 25 °C)

Symbol Parameter Value Unit

VPP

Peak pulse voltage:

IEC 61000-4-2 contact discharge

EC 61000-4-2 air discharge

± 15

± 16

IPP Peak pulse current (8/20 µs) 1.5 A

TjJunction temperature 125 °C

Tstg Storage temperature range - 55 to +150 °C

TLMaximum lead temperature for soldering during 10 s 260 °C

Top Operating junction temperature range -40 to +125 °C

Symbol Parameter

V = Breakdown voltage

I = Leakage current @ V

V = Stand-off voltage

I = Forward current

I = Peak pulse current

I = Breakdown current

V = Forward voltage drop

RM RM

V = Clamping voltage

d= Dynamic impedance

T = Voltage temperaturea

Table 2. Electrical characteristics (values, Tamb = 25 °C)

Symbol Test Condition Min. Typ. Max. Unit

VBR

From pin1 to pin 2, IR = 1 mA 8.5 11 V

From pin 2 to pin1, IR = 1 mA 14.5 17

IRM VRM = 3 V 100 nA

RdSquare pulse, IPP = 1 A tp = 2.5 µs 2.5 Ω

αTΔVBR = αT(Tamb - 25 °C) x VBR (25 °C) 6 10-4/°C

Cline VR = 0 V, Fosc = 1 MHz, Vosc = 30 mV 5 7 pF

ESDAVLC8-1BU2 Characteristics

Doc ID 16546 Rev 2 3/11

Figure 3. Relative variation of peak pulse

power versus initial junction

temperature

Figure 4. Peak pulse power versus

exponential pulse duration

initial] / P

initial=25°C]

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

0 25 50 75 100 125 150

Tj(°C)

(W)

100

1000

1 10 100 1000

Tjinitial = 25°C

(µs)

Figure 5. Junction capacitance versus

reverse applied voltage

(typical values)

Figure 6. Relative variation of leakage

current versus junction

temperature (typical values)

C(pF)

-5.0

-4.0

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

4.0

5.0

F=1MHz

VOSC=30mVRMS

Tj=25°C

VR(V)

]/I

=25°C]

100

25 50 75 100 125

VR=3V

(°C)

Figure 7. ESD response to IEC 61000-4-2

(+8 kV contact discharge)

Figure 8. ESD response to IEC 61000-4-2

(-8 kV contact discharge)

10 V/Div

20 ns/Div

10 V/Div

20 ns/Div

Characteristics ESDAVLC8-1BU2

4/11 Doc ID 16546 Rev 2

Figure 9. S21 attenuation measurement results

Figure 10. Static characteristic (pin 2 to GND)

100.0k 1.0M 10.0M 100.0M 1.0G

- 30.00

-24.00

-18.00

-12.00

-6.00

0.00 dB

F (Hz)

-1

-2

-3

-4

-5

0510152025-25 -20 -15 -10 -5

ESDAVLC8-1BU2 Ordering information scheme

Doc ID 16546 Rev 2 5/11

2 Ordering information scheme

Figure 11. Ordering information scheme

ESDA VLC 8 - 1B U2

ESD array

Very low capacitance

Package

U2 = ST0201

Breakdown voltage

Direction

8 = 8.5 V min

B = Bidirectional

Package information ESDAVLC8-1BU2

6/11 Doc ID 16546 Rev 2

3 Package information

●Epoxy meets UL94, V0

●Lead-free package

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Note: Product marking may be rotated by multiples of 180° for assembly plant differentiation. In no

case should this product marking be used to orient the component for its placement on a

PCB. Only pin 1 mark is to be used for this purpose.

Table 3. ST0201 dimensions

Ref.

Dimensions

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.23 0.28 0.33 0.009 0.011 0.013

b1 0.13 0.18 0.23 0.005 0.007 0.009

b2 0.14 0.19 0.24 0.006 0.007 0.009

D 0.55 0.60 0.65 0.022 0.024 0.026

E 0.25 0.30 0.35 0.010 0.012 0.014

e - 0.35 - - 0.014 -

L1 0.20 0.25 0.30 0.008 0.010 0.012

L2 0.20 0.25 0.30 0.008 0.010 0.012

Figure 12. Footprint (dimensions in mm) Figure 13. Marking

Top

Side

Bottom

Pin 2 available in different forms

Pin 2

Bottom

0.425

0.20

0.30

0.425

1.05

Pin1 Pin 2

ESDAVLC8-1BU2 Package information

Doc ID 16546 Rev 2 7/11

Figure 14. Tape and reel specifications

Bar indicates Pin 1

User direction of unreeling

All dimensions in mm

4.0 ± 0.1

2.0 ± 0.05

8.0 ± 0.3

2.0 ± 0.1

1.75 ± 0.1 3.5 ±- 0.05

Ø 1.55 ± 0.05

0.34 ± 0.03 0.37 +0.03, -0.02

0.20 ± 0.05

0.67 ± 0.03

Recommendation on PCB assembly ESDAVLC8-1BU2

8/11 Doc ID 16546 Rev 2

4 Recommendation on PCB assembly

4.1 Stencil opening design

Figure 15. Recommended stencil windows position

4.2 Solder paste

1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.

2. “No clean” solder paste is recommended.

3. Offers a high tack force to resist component movement during high speed

4. Solder paste with fine particles: powder particle size is 20-45 µm.

0.425

0.20 0.038

0.065

Footprint Stencil window

0.040

0.038

0.30

0.320

0.425

1.05

0.225

ESDAVLC8-1BU2 Recommendation on PCB assembly

Doc ID 16546 Rev 2 9/11

4.3 Placement

1. Manual positioning is not recommended.

2. It is recommended to use the lead recognition capabilities of the placement system, not

the outline centering

3. Standard tolerance of ± 0.05 mm is recommended.

4. 3.5 N placement force is recommended. Too much placement force can lead to

squeezed out solder paste and cause solder joints to short. Too low placement force

can lead to insufficient contact between package and solder paste that could cause

open solder joints or badly centered packages.

5. To improve the package placement accuracy, a bottom side optical control should be

performed with a high resolution tool.

6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is

recommended during solder paste printing, pick and place and reflow soldering by

using optimized tools.

4.4 PCB design preference

1. To control the solder paste amount, the closed via is recommended instead of open

vias.

2. The position of tracks and open vias in the solder area should be well balanced. The

symmetrical layout is recommended, in case any tilt phenomena caused by

asymmetrical solder paste amount due to the solder flow away.

4.5 Reflow profile

Figure 16. ST ECOPACK® recommended soldering reflow profile for PCB mounting

Note: Minimize air convection currents in the reflow oven to avoid component movement.

60 sec

(90 max)

250

100

150

200

240210180150120906030 300

270

-2 °C/s to

-3 °C/s

-6 °C/s max

240-245 °C

2 - 3 °C/s

0.9 °C/s

Temperature (°C)

Time (s)

Ordering information ESDAVLC8-1BU2

10/11 Doc ID 16546 Rev 2

5 Ordering information

6 Revision history

Table 4. Ordering information

Order code Marking Weight Base qty Delivery mode

ESDAVLC8-1BU2 V2(1)

1. The marking can be rotated by multiples of 180° to differentiate assembly location

0.124 mg 15000 Tape and reel

Table 5. Document revision history

Date Revision Changes

03-Mar-2011 1Initial release.

15-May-2012 2

Updated Figure 10 for flow polarity. Updated graphic in Table 3 for

pin 2 form. Updated note under Figure 13 and Table 4 for marking

rotation. Updated Figure 16 for recommended soldering reflow.

Updated marking in Table 4.

ESDAVLC8-1BU2

Doc ID 16546 Rev 2 11/11

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