FAN5236 Dual Mobile-Friendly DDR / Dual-Output PWM Controller Features Description The FAN5236 PWM controller provides high efficiency and regulation for two output voltages adjustable in the range of 0.9V to 5.5V required to power I/O, chip-sets, and memory banks in high-performance notebook computers, PDAs, and Internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to high efficiency over a wide range of loads. The Hysteretic Mode can be disabled separately on each PWM converter if PWM Mode is desired for all load levels. Efficiency is enhanced by using MOSFET RDS(ON) as a current-sense component. Highly Flexible, Dual Synchronous Switching PWM Controller that Includes Modes for: - DDR Mode with In-phase Operation for Reduced Channel Interference - 90 Phase-shifted, Two-stage DDR Mode for Reduced Input Ripple - Dual Independent Regulators, 180 Phase Shifted Complete DDR Memory Power Solution - VTT Tracks VDDQ/2 VDDQ/2 Buffered Reference Output Lossless Current Sensing on Low-side MOSFET or Precision Over-Current Using Sense Resistor VCC Under-Voltage Lockout Excellent Dynamic Response with Voltage Feedforward and Average-Current-Mode Control Power-Good Signal Converters can Operate from +5V or 3.3V or Battery Power Input (5V to 24V) Supports DDR-II and HSTL Light-Load Hysteretic Mode Maximizes Efficiency TSSOP28 Package Applications DDR VDDQ and VTT Voltage Generation Mobile PC Dual Regulator Server DDR Power Feedforward ramp modulation, average-current-mode control scheme, and internal feedback compensation provide fast response to load transients. Out-of-phase operation with 180-degree phase shift reduces input current ripple. The controller can be transformed into a complete DDR memory power supply solution by activating a designated pin. In DDR mode, one of the channels tracks the output voltage of another channel and provides output current sink and source capability -- essential for proper powering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5236 monitors these outputs and generates separate PGx (power good) signals when the soft-start is completed and the output is within 10% of the set point. Built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the over-voltage conditions cease. Under-voltage protection latches the chip off when output drops below 75% of the set value after the softstart sequence for this output is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. If precision current-sensing is required, an external current-sense resistor may be used. Hand-held PC Power Related Resources Application Note -- AN-6002 Component Calculations and Simulation Tools for FAN5234 or FAN5236 Application Note -- AN-1029 Maximum Power Enhancement Techniques for SO-8 Power MOSFET (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 www.fairchildsemi.com FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller November 2010 Part Number Operating Temperature Range FAN5236MTCX -10 to +85C Package Packing Method 28-Lead Thin-Shrink Small-Outline Package (TSSOP) Block Diagrams +5 VCC VIN (BATTERY) = 5 to 24V FAN5236 Q1 ILIM1 L VO UT1 = 2.5V OUT1 PWM 1 C OUT1 Q2 DDR Q3 ILIM2/ REF2 L VO UT 2 = 1.8V OUT2 PWM 2 C OUT2 Q4 Figure 1. Dual-Output Regulator +5 VCC Tape and Reel FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Ordering Information VIN (BATTERY) = 5 to 24V FAN5236 Q1 ILIM1 L OUT1 PWM 1 VDDQ = 2.5V C OUT1 Q2 R +5 DDR R Q3 L PG2/REF 1.25V Q4 PWM 2 OUT2 VTT = VDDQ /2 C OUT2 IL IM2/REF2 Figure 2. Complete DDR Memory Power Supply (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 www.fairchildsemi.com 2 AGND LDRV1 PGND1 SW1 HDRV1 BOOT1 ISNS1 EN1 FPWM1 VSEN1 ILIM1 SS1 DDR VIN 1 2 28 27 3 4 26 25 5 6 24 23 7 22 FAN5236 8 21 9 10 20 19 11 12 18 17 13 14 16 15 VCC LDRV2 PGND2 SW2 HDRV2 BOOT2 ISNS2 EN2 FPWM2 VSEN2 ILIM2/REF2 SS2 PG2/REF2OUT PG1 Figure 3. Pin Configuration Pin Definitions Pin # Name 1 AGND 2 LDRV1 27 LDRV2 Description Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. 3 PGND1 26 PGND2 4 SW1 25 SW2 5 HDRV1 24 HDRV2 6 BOOT1 23 BOOT2 7 ISNS1 22 ISNS2 8 EN1 21 EN2 9 FPWM1 20 FPWM2 10 VSEN1 19 VSEN2 11 ILIM1 Current Limit 1. A resistor from this pin to GND sets the current limit. 12 SS1 17 SS2 Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5mA current source. Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side MOSFET. Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Pin Configuration High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 4. Current-Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator after a latched fault condition. These are CMOS inputs whose state is indeterminate if left open. Forced PWM Mode. When logic LOW, inhibits the regulator from entering Hysteretic Mode; otherwise tie to VOUT. The regulator uses VOUT on this pin to ensure a smooth transition from Hysteretic Mode to PWM Mode. When VOUT is expected to exceed VCC, tie to VCC. Output Voltage Sense. The feedback from the outputs. Used for regulation as well as PG, under-voltage, and over-voltage protection and monitoring. (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 www.fairchildsemi.com 3 Pin # Name Description 13 DDR DDR Mode Control. HIGH = DDR Mode. LOW = two separate regulators operating 180 out of phase. 14 VIN Input Voltage. Normally connected to battery, providing voltage feedforward to set the amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V input, connect through 100K resistor to ground, which sets the appropriate ramp gain and synchronizes the channels 90 out of phase. 15 PG1 Power Good Flag. An open-drain output that pulls LOW when VSEN is outside a 10% range of the 0.9V reference. 16 PG2 / REF2OUT 18 28 Power Good 2. When not in DDR Mode, open-drain output that pulls LOW when the VOUT is out of regulation or in a fault condition. Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as the VDDQ/2 reference. Current Limit 2. When not in DDR Mode, a resistor from this pin to GND sets the current ILIM2 / REF2 limit. Reference for reg #2 when in DDR Mode. Typically set to VOUT1 / 2. VCC VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Pin Descriptions (Continued) www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC VCC Supply Voltage 6.5 V VIN VIN Supply Voltage 27 V BOOT, SW, ISNS, HDRV 33 V BOOTx to SWx 6.5 V All Other Pins -0.3 VCC+0.3 V TJ Junction Temperature -40 +150 C TSTG Storage Temperature -65 +150 C +300 C TL Lead Temperature (Soldering,10 Seconds) Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC VCC Supply Voltage VIN VIN Supply Voltage TA Ambient Temperature JA Thermal Resistance, Junction to Ambient (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 Min. Typ. Max. 4.75 5.00 5.25 V 24 V +85 C 90 C/W -10 Unit FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Absolute Maximum Ratings www.fairchildsemi.com 5 Recommended operating conditions, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units 2.2 3.0 A Power Supplies IVCC VCC Current LDRV, HDRV Open, VSEN Forced Above Regulation Point ISINK VIN Current, Sinking VIN = 24V ISOURCE VIN Current, Sourcing VIN = 0V ISD VIN Current, Shutdown Shutdown (EN-0) VUVLO UVLO Threshold VUVLOH UVLO Hysteresis 10 -15 30 A 30 A -30 A 1 A Rising VCC 4.30 4.55 4.75 V Falling 4.10 4.25 4.45 V 300 mV Oscillator fosc Frequency VPP Ramp Amplitude VRAMP G 255 345 KHz VIN = 16V 2 V VIN = 5V 1.25 V 0.5 V VIN 3V 125 mV/V 1V < VIN < 3V 250 mV/V Ramp Offset Ramp / VIN Gain 300 Reference and Soft Start VREF Internal Reference Voltage ISS Soft-Start Current VSS Soft-Start Complete Threshold 0.891 At Startup 0.900 0.909 V 5 A 1.5 V FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Electrical Characteristics PWM Converters Load Regulators ISEN IOUTX from 0 to 5A, VIN from 5 to 24V -2 +2 % VSEN Bias Current 50 80 120 nA VOUT Pin Input Impedance 45 55 65 K % of Set Point, 2s Noise Filter 70 75 80 % UVLOTSD Under-Voltage Shutdown UVLO Over-Voltage Threshold % of Set Point, 2s Noise Filter 115 120 125 % ISNS Over-Current Threshold RILIM= 68.5K, Figure 12 112 140 168 A Sourcing 12.0 15.0 Sinking 2.4 4.0 Sourcing 12.0 15.0 Sinking 1.2 2.0 Output Drivers HDRV Output Resistance LDRV Output Resistance Continued on following page... (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 www.fairchildsemi.com 6 Symbol Parameter Conditions Min. Typ. Max. Units Power-Good Output and Control Pins Lower Threshold % of Set Point, 2s Noise Filter -86 -94 % Upper Threshold % of Set Point, 2s Noise Filter 108 116 % PG Output Low IPG = 4mA 0.5 V Leakage Current VPULLUP = 5V 1 A PG2/REF2OUT Voltage DDR = 1, 0mA < IREF2OUT 10mA 1.01 % VREF2 99.00 DDR, EN Inputs VINH Input High VINL Input Low 2 V 0.8 V 0.1 V FPWM Inputs FPWM Low FPWM High FPWM Connected to Output 0.9 V Block Diagram 5V VDD CBOOT BOOT EN VIN POR/UVLO Q1 FPWM DDR FPWM/VOUT SS HYST OVP DDR VIN Q2 VDD L OU T COUT LDRV RAMP OSC VO UT SW ADAPTIVE GATE CONTROL LOGIC CLK PGND Q S PWM R RAMP DUTY CYCLE CLAMP EA S/ H PWM/HYST PWM VSEN HDRV HYST FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Electrical Characteristics (Continued) ILIM det. MO ISNS RSENSE CURRENT PROCESSING IOU T FPWM/VOUT SS ILIM R ILIM VREF PGOOD Reference and Soft Start REF2 PWM/HYST DDR Figure 4. IC Block Diagram (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 www.fairchildsemi.com 7 VIN (BATTERY) = 5 to 24V VIN C1 14 VCC +5 28 6 C4 C9 D1 BOOT1 +5 Q1A 5 R3 ILIM1 EN1 C2 SS1 11 8 12 4 PW M 1 +5 7 PG1 9 15 10 DDR +5 EN2 C3 SS2 13 23 21 17 24 1.25V at 10mA AGND 1 PW M 2 27 26 22 FPWM2 C6A 20 19 18 C6B R5 LDRV1 R7 PGND2 ISNS1 FPWM1 (VOUT1) R1 VSEN1 BOOT2 D2 R6 +5 C7 HDRV2 SW2 L2 Q2B 16 VDDQ = 2.5V L1 SW1 Q2A 25 PG2/REF HDRV1 Q1B 2 3 R4 C5 VTT = VDDQ/2 R2 C8A LDRV2 PGND2 R8 ISNS2 C8B VSEN2 ILIM2/REF2 Figure 5. DDR Regulator Application Table 1. DDR Regulator BOM Description Qty. Ref. Vendor Capacitor 68f, Tantalum, 25V, ESR 150m Capacitor 10nf, Ceramic Capacitor 68f, Tantalum, 6V, ESR 1.8 Capacitor 150nF, Ceramic Capacitor 180f, Specialty Polymer 4V, ESR 15m Capacitor 1000f, Specialty Polymer 4V, ESR 10m Capacitor 0.1F, Ceramic 18.2K, 1% Resistor 1.82K, 1% Resistor 56.2K, 1% Resistor 10K, 5% Resistor 3.24K, 1% Resistor 1.5K, 1% Resistor 1 2 1 2 2 1 2 3 1 2 2 1 2 C1 C2, C3 C4 C5, C7 C6A, C6B C8 C9 R1, R2 R6 R3 R4 R5 R7, R8 Schottky Diode 30V 2 D1, D2 Inductor 6.4H, 6A, 8.64m Inductor 0.8H, 6A, 2.24m 1 1 L1 L2 Dual MOSFET with Schottky 1 Q1, Q2 DDR Controller 1 U1 AVX Any AVX Any Panasonic Kemet Any Any Any Any Any Any Any Fairchild Semiconductor Panasonic Panasonic Fairchild Semiconductor Fairchild Semiconductor Part Number TPSV686*025#0150 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Typical Application TAJB686*006 EEFUE0G181R T510E108(1)004AS4115 BAT54 ETQ-P6F6R4HFA ETQ-P6F0R8LFA (1) FDS6986AS FAN5236 Note: 1. Suitable for typical notebook computer application of 4A continuous, 6A peak for VDDQ. If continuous operation above 6A is required, use single SO-8 packages. For more information, refer to the Power MOSFET Selection Section and use AN-6002 for design calculations. (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 www.fairchildsemi.com 8 V IN (BATTERY) = 5 to 24V VIN VCC +5 28 6 D1 BOOT1 C4 +5 Q1A 5 R2 ILIM1 EN1 C2 +5 C9 C1 14 SS1 11 8 4 PW M 1 12 2 7 PG1 9 15 10 DDR L1 SW1 13 23 C6 LDRV1 R6 PGND2 R4 ISNS1 FPWM1 (VOUT1) VSEN1 V IN BOOT2 PG2 SS2 21 24 25 16 17 C3 PW M 2 1 26 22 FPWM2 +5 C7 HDRV2 SW2 L2 1.8V at 6A Q2B 27 AGND R5 D2 Q2A EN2 20 2.5V at 6A Q1B 3 R3 C5 HDRV1 19 18 C8 LDRV2 R7 PGND2 R8 ISNS2 R9 VSEN2 R1 ILIM2 Figure 6. Dual Regulator Application Table 2. DDR Regulator BOM Item Description Qty. Ref. 1 2 3 4 5 5 11 12 13 Capacitor 68f, Tantalum, 25V, ESR 95m Capacitor 10nf, Ceramic Capacitor 68f, Tantalum, 6V, ESR 1.8 Capacitor 150nF, Ceramic Capacitor 330f, Poscap, 4V, ESR 40m Capacitor 0.1F, Ceramic 56.2K, 1% Resistor 10K, 5% Resistor 3.24K, 1% Resistor 1 2 1 2 2 2 2 2 1 14 1.82K, 1% Resistor 3 15 1.5K, 1% Resistor 2 C1 C2, C3 C4 C5, C7 C6, C8 C9 R1, R2 R3 R4 R5, R8, R9 R6, R7 27 Schottky Diode 30V 2 D1, D2 28 Inductor 6.4H, 6A, 8.64m 1 L1, L2 29 Dual MOSFET with Schottky 1 Q1 30 DDR Controller 1 U1 Vendor AVX Any AVX Any Sanyo Any Any Any Any Part Number FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Typical Applications (Continued) TPSV686*025#095 TAJB686*006 4TPB330ML Any Any Fairchild Semiconductor Panasonic Fairchild Semiconductor Fairchild Semiconductor BAT54 ETQ-P6F6R4HFA FDS6986AS (2) FAN5236 Note: 2. If currents above 4A continuous are required, use single SO-8 packages. For more information, refer to the Power MOSFET Selection Section and AN-6002 for design calculations. (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 www.fairchildsemi.com 9 When VIN is from the battery, it's typically higher than 7.5V. As shown in Figure 7, 180 operation is undesirable because the turn-on of the VDDQ converter occurs very near the decision point of the VTT converter. Overview The FAN5236 is a multi-mode, dual-channel PWM controller intended for graphic chipset, SDRAM, DDR DRAM, or other low-voltage power applications in modern notebook, desktop, and sub-notebook PCs. The IC integrates control circuitry for two synchronous buck converters. The output voltage of each controller can be set in the range of 0.9V to 5.5V by an external resistor divider. CLK VD DQ VTT The two synchronous buck converters can operate from either an unregulated DC source (such as a notebook battery), with voltage ranging from 5.0V to 24V, or from a regulated system rail of 3.3V to 5.0V. In either mode, the IC is biased from a +5V source. The PWM modulators use an average-current-mode control with input voltage feedforward for simplified feedback loop compensation and improved line regulation. Both PWM controllers have integrated feedback loop compensation that reduces the external components needed. Figure 7. Noise-Susceptible 180 Phasing for DDR1 In-phase operation is optimal to reduce inter-converter interference when VIN is higher than 5V (when VIN is from a battery), as shown in Figure 8. Because the duty cycle of PWM1 (generating VDDQ) is short, the switching point occurs far away from the decision point for the VTT regulator, whose duty cycle is nominally 50%. CLK Depending on the load level, the converters can operate in fixed-frequency PWM Mode or in a Hysteretic Mode. Switch-over from PWM to Hysteretic Mode improves the converters' efficiency at light loads and prolongs battery run time. In Hysteretic Mode, comparators are synchronized to the main clock, which allows seamless transition between the modes and reduces channel-to-channel interaction. The Hysteretic Mode can be inhibited independently for each channel if variable frequency operation is not desired. VDDQ VTT Figure 8. Optimal In-Phase Operation for DDR1 When VIN 5V, 180 phase-shifted operation can be rejected for the reasons demonstrated in Figure 7. In-phase operation with VIN 5V is even worse, since the switch point of either converter occurs near the switch point of the other converter, as seen in Figure 9. In this case, as VIN is a little higher than 5V, it tends to cause early termination of the VTT pulse width. Conversely, the VTT switch point can cause early termination of the VDDQ pulse width when VIN is slightly lower than 5V. The FAN5236 can be configured to operate as a complete DDR solution. When the DDR pin is set HIGH, the second channel provides the capability to track the output voltage of the first channel. The PWM2 converter is prevented from going into Hysteretic Mode if the DDR pin is set HIGH. In DDR Mode, a buffered reference voltage (buffered voltage of the REF2 pin), required by DDR memory chips, is provided by the PG2 pin. FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Circuit Description CLK Converter Modes and Synchronization VDDQ Table 3. Converter Modes and Synchronization Mode DDR1 VIN VIN Pin DDR Pin PWM 2 w.r.t. PWM1 IN PHASE Battery VIN HIGH DDR2 +5V R to GND HIGH +90 DUAL ANY VIN LOW +180 VTT Figure 9. These problems are solved by delaying the second converter's clock by 90, as shown in Figure 10. In this way, all switching transitions in one converter take place far away from the decision points of the other converter. When used as a dual converter, as shown in Figure 6, out-of-phase operation with 180-degree phase shift reduces input current ripple. CLK For "two-step" conversion (where the VTT is converted from VDDQ as in Figure 5) used in DDR Mode, the duty cycle of the second converter is nominally 50% and the optimal phasing depends on VIN. The objective is to keep noise generated from the switching transition in one converter from influencing the "decision" to switch in the other converter. (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 Noise-Susceptible In-Phase Operation for DDR2 VDDQ VTT Figure 10. Optimal 90 Phasing for DDR2 www.fairchildsemi.com 10 Assuming EN is HIGH, FAN5236 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an internal power-on reset function disables the chip. The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin, which is charged with a 5A current source. Once CSS has charged to VREF (0.9V) the output voltage is in regulation. The time it takes SS to reach 0.9V is: t 0.9 = 0.9 xCSS 5 To prevent accidental mode change or "mode chatter," the transition from PWM to Hysteretic Mode occurs when the SW node is positive for eight consecutive clock cycles, as shown in Figure 11. The polarity of the SW node is sampled at the end of the lower MOSFET conduction time. At the transition between PWM and Hysteretic Mode, the upper and lower MOSFETs are turned off. The phase node "rings" based on the output inductor and the parasitic capacitance on the phase node and settles out at the value of the output voltage. (1) where t0.9 is in seconds if CSS is in F. When SS reaches 1.5V, the power-good outputs are enabled and Hysteretic Mode is allowed. The converter is forced into PWM Mode during soft-start. The boundary value of inductor current, where current becomes discontinuous, can be estimated by the following expression: Operation Mode Control The mode-control circuit changes the converter mode from PWM to hysteretic and vice versa, based on the voltage polarity of the SW node when the lower MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative when the lower MOSFET is conducting and the converters operate in fixed- (V - V )V OUT OUT I LOAD ( DIS ) = IN 2 F L V SW OUT IN (2) VCORE PWMMode IL HystereticMode 0 1 2 3 4 5 6 7 8 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller frequency PWM Mode, as shown in Figure 11. This mode achieves high efficiency at nominal load. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the `reverse' direction, the SW node becomes positive and the mode is changed to hysteretic, which achieves higher efficiency at low currents by decreasing the effective switching frequency. Initialization and Soft Start VCORE IL HystereticMode 0 1 Figure 11. 2 3 PWMMode 4 5 6 7 8 Transitioning Between PWM and Hysteretic Mode Hysteretic Mode Conversely, the transition from Hysteretic Mode to PWM Mode occurs when the SW node is negative for eight consecutive cycles. VDS(ON) is monitored and switched off when VDS(ON) goes positive (current flowing back from the load), allowing the diode to block reverse conduction. A sudden increase in the output current causes a change from Hysteretic to PWM Mode. This load increase causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor ESR. If the load causes the output voltage (as presented at VSNS) to drop below the hysteretic regulation level (20mV below VREF), the mode is changed to PWM on the next clock cycle. The hysteretic comparator initiates a PFM signal to turn on HDRV at the rising edge of the next oscillator clock, when the output voltage (at VSNS) falls below the lower threshold (10mV below VREF) and terminates the PFM signal or when VSNS rises over the higher threshold (5mV above VREF). The switching frequency is primarily a function of: In Hysteretic Mode, the PWM comparator and the error amplifier that provide control in PWM Mode are inhibited and the hysteretic comparator is activated. In Hysteretic Mode, the low-side MOSFET is operated as a synchronous rectifier, where the voltage across (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 Spread between the two hysteretic thresholds ILOAD Output inductor and capacitor ESR. www.fairchildsemi.com 11 VHYSTERESIS I LOAD( CCM ) = 2 ESR Because of the different control mechanisms, the value of the load current where transition into CCM operation takes place is typically higher compared to the load level at which transition into Hysteretic Mode occurs. Hysteretic Mode can be disabled by setting the FPWM pin LOW. (3) where VHYSTERESIS = 15mV and ESR is the equivalent series resistance of COUT. Figure 12. Current Limit / Summing Circuits Current Processing Section The current through the RSENSE resistor (ISNS) is sampled (typically 400ns) after Q2 is turned on, as shown in Figure 12. That current is held and summed with the output of the error amplifier. This effectively creates a current-mode control loop. The resistor connected to ISNSx pin (RSENSE) sets the gain in the current feedback loop. The following expression estimates the recommended value of RSENSE as a function of the maximum load current (ILOAD(MAX)) and the value of the MOSFET RDS(ON): I LOAD( MAX ) * RDS( ON ) RSENSE = - 100 75 A Since the tolerance on the current limit is largely dependent on the ratio of the external resistors, it is fairly accurate if the voltage drop on the switching-node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value varies from device to device and has a typical junction temperature coefficient of about 0.4%/C (consult the MOSFET datasheet for actual values), so the actual current limit set point decreases proportional to increasing MOSFET die temperature. A factor of 1.6 in the current limit set point should compensate for MOSFET RDS(ON) variations, assuming the MOSFET heat sinking keeps its operating die temperature below 125C. (4) RSENSE must, however, be kept higher than 700 even if the number calculated comes out to be less than 700. Q2 Setting the Current Limit LDRV A ratio of ISNS is compared to the current established when a 0.9V internal reference drives the ILIM pin: (100 + R 11 SENSE ) x I LOAD R DS( ON ) ISNS (5) PGND Figure 13. (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 RSENSE R1 R LIM = FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller A transition back to PWM continuous conduction mode (CCM) mode occurs when the inductor current rises sufficiently to stay positive for eight consecutive cycles. This occurs when: Improving Current-Sensing Accuracy www.fairchildsemi.com 12 Due to the implemented current-mode control, the modulator has a single-pole response with -1 slope at frequency determined by load: 1 f PO = (8) 2 ROCO Current limit (ILIMIT) should be set high enough to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.2 is sufficient. In addition, since ILIMIT is a peak current cut-off value, multiply ILOAD(MAX) by the inductor ripple current (e.g. 25%). For example, in Figure 6, the target for ILIMIT: ILIMIT > 1.2 x 1.25 x 1.6 x 6A 14.5A where RO is load resistance; CO is load capacitance. For this type of modulator, a Type-2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design, the PWM controller has an internally compensated error amplifier. Figure 14 shows a Type-2 amplifier, its response, and the responses of a current-mode modulator and the converter. The Type-2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. (6) Duty Cycle Clamp During severe load increase, the error amplifier output can go to its upper limit, pushing a duty cycle to almost 100% for significant amount of time. This could cause a large increase of the inductor current and lead to a long recovery from a transient, over-current condition, or even to a failure at especially high input voltages. To prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output voltage excursion is detected, limiting the maximum duty cycle to: DC MAX = V OUT V IN 2 .4 + VIN fZ = 1 = 6 kHz 2 R2 C1 (9) fP = 1 = 600kHz 2 2 C2 (10) This region is also associated with phase "bump" or reduced phase shift. The amount of phase-shift reduction depends on the width of the region of flat gain and has a maximum value of 90. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feedforward of VIN to the oscillator ramp. (7) This is designed to not interfere with normal PWM operation. When FPWM is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. The zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. The crossover frequency appears at the point where the modulator attenuation equals the amplifier high-frequency gain. The system designer must specify the output filter capacitors to position the load main pole somewhere within a decade lower than the amplifier zero frequency. With this type of compensation, plenty of phase margin is achieved due to zero-pole pair phase "boost." Gate Driver Section The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals, providing necessary amplification, level shifting, and shoot-through protection. It also has functions that optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction or shoot-through. C2 R2 C1 R1 VIN EA Out REF C r te am ve p r 18 or on err There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to function properly. Any delay along that path subtracts from the delay generated by the adaptive dead-time circuit and shootthrough may occur. modul ator 14 0 f P0 Figure 14. (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Frequency Loop Compensation More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET, as shown in Figure 13. This approach causes higher losses, but yields greater accuracy in both VDROOP and ILIMIT. R1 is a low value resistor (e.g. 10m). f Z f P Compensation www.fairchildsemi.com 13 If a larger inductor value or low-ESR values are required by the application, additional phase margin can be achieved by putting a zero at the LC crossover frequency. This can be achieved with a capacitor across the feedback resistor (e.g. R5 from Figure 6), as shown in Figure 15. L(OUT) VOUT R5 C(Z) C(OUT) VSEN R6 Figure 16. Figure 15. Over-Voltage / Under-Voltage Protection Should the VSNS voltage exceed 120% of VREF (0.9V) due to an upper MOSFET failure or for other reasons, the over-voltage protection comparator forces LDRV HIGH. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, eventually blows the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. The optimal value of C(Z) is: C(Z) = Over-Current Protection Waveforms Improving Phase Margin L(OUT) xC(OUT) R (11) Protections The converter output is monitored and protected against extreme overload, short-circuit, over-voltage, and under-voltage conditions. This OVP scheme provides a "soft" crowbar function, which accommodates severe load transients and does not invert the output voltage when activated -- a common problem for latched OVP schemes. A sustained overload on an output sets the PGx pin LOW and latches off the regulator on which the fault occurs. Operation can be restored by cycling the VCC voltage or by toggling the EN pin. Similarly, if an output short-circuit or severe load transient causes the output to drop to less than 75% of the regulation set point, the regulator shuts down. If VOUT drops below the under-voltage threshold, the regulator shuts down immediately. Over-Temperature Protection The chip incorporates an over-temperature protection circuit that shuts the chip down if a die temperature of about 150C is reached. Normal operation is restored at die temperature below 125C with internal power-on reset asserted, resulting in a full soft-start cycle. Over-Current Sensing If the circuit's current limit signal ("ILIM det" in Figure 12) is HIGH at the beginning of a clock cycle, a pulseskipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next eight clock cycles. If at any time from the ninth to the sixteenth clock cycle, the ILIM det is again reached, the over-current protection latch is set, disabling the (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller regulator. If ILIM det does not occur between cycles nine and sixteen, normal operation is restored and the over-current circuit resets itself. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz to 50kHz range gives some additional phase boost. There is an opposite trend in mobile applications to keep the output capacitor as small as possible. www.fairchildsemi.com 14 As an initial step, define operating input voltage range, output voltage, and minimum and maximum load currents for the controller. Output Capacitor Selection The output capacitor serves two major functions in a switching power supply. Along with the inductor, it filters the sequence of pulses produced by the switcher and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, inductor ripple current (I), and the allowable ripple voltage (V): Setting the Output Voltage The internal reference voltage is 0.9V. The output is divided down by a voltage divider to the VSEN pin (for example, R5 and R6 in Figure 5). The output voltage therefore is: 0.9V V OUT - 0.9V = R6 R5 ESR < (12) (1.82 K )(VOUT - 0. 9 0 .9 ) = 3.24 K (18) In addition, the capacitor's ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 6 is 120mVPP. Some additional ripple appears due to the capacitance value itself: To minimize noise pickup on this node, keep the resistor to GND (R6) below 2K; for example, R6 at 1.82K. Then choose R5: R5 = V I (13) V = For DDR applications converting from 3.3V to 2.5V or other applications requiring high duty cycles, the duty cycle clamp must be disabled by tying the converter's FPWM to GND. When converter's FPWM is at GND, the converter's maximum duty cycle is greater than 90%. When using as a DDR converter with 3.3V input, set up the converter for in-phase synchronization by tying the VIN pin to +5V. I COUT x 8 x fSW (19) which is only about 1.5mV, for the converter in Figure 6, and can be ignored. The capacitor must also be rated to withstand the RMS current, which is approximately 0.3 X (I), or about 400mA for the converter in Figure 6. High-frequency decoupling capacitors should be placed as close to the loads as physically possible. Output Inductor Selection Input Capacitor Selection The minimum practical output inductor value keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the minimum current somewhere from 15% to 35% of the nominal current. At light load, the controller can automatically switch to Hysteretic Mode of operation to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor: I = 2 x 1MIN V = OUT ESR The input capacitor should be selected by its ripple current rating. Two-Stage Converter Case In DDR Mode (shown in Figure 5), the VTT power input is powered by the VDDQ output; therefore, all of the input capacitor ripple current is produced by the VDDQ converter. A conservative estimate of the output current required for the 2.5V regulator is: (14) I REGI = I VDDQ + where I is the inductor ripple current and VOUT is the maximum ripple allowed: L= VIN - V OUT f SW x I x V OUT VIN I VTT (20) 2 As an example, if the average IVDDQ is 3A and average IVTT is 1A, IVDDQ current is about 3.5A. If average input voltage is 16V, RMS input ripple current is: (15) 2 for this example, use: I RMS = I OUT (MAX ) D - D VIN = 20, V OUT = 2.5 where D is the duty cycle of the PWM1 converter: I = 20 % * 6 A = 1.2A (16) D< f SW = 300KHz therefore: L 6H V OUT VIN = (21) 2.5 16 (22) therefore: (17) I (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Design and Component Selection Guidelines RMS 2.5 2.5 = 3.5 - 16 16 2 = 1.49 A (23) www.fairchildsemi.com 15 In dual mode (shown in Figure 6), both converters contribute to the capacitor input ripple current. With each converter operating 180 out of phase, the RMS currents add in the following fashion: I RMS = I IRMS = 2 RMS(1) +I 2 RMS( 2) or (I1 )2 (D1 - D12 ) + (I2 )2 (D 2 - D 2 2 ) VDS (24) CISS C GD QGS QGD C ISS (25) which, for the dual 3A converters shown in Figure 6, calculates to: I RMS = 1.4 A ID (26) Power MOSFET Selection 4.5V Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. VSP VTH In typical applications, the FAN5236 converter's output voltage is low with respect to its input voltage. Therefore, the lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should therefore be selected to minimize conduction losses, thereby selecting a MOSFET with low RDS(ON). QG(SW) VGS t1 t2 Figure 17. In contrast, the high-side MOSFET (Q1) has a shorter duty cycle and it's conduction loss has less impact. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge. t3 VIN 5V C GD RD HDRV SW Figure 18. ts = PCOND = V OUT VIN x I OUT 2 x R DS( ON ) (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 Q G( SW ) = Q G( SW ) V -V (30) CC SP R R + GATE DRIVER Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: These losses are given by: (28) Drive Equivalent Circuit The driver's impedance and CISS determine t2, while t3's period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP, use a constant current assumption for the driver to simplify the calculation of tS: Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses occur during the shaded time when the MOSFET has voltage across it and current through it. V xI PSW = DS L x 2 x t s f SW 2 RGATE G CGS Figure 17 shows a MOSFET's switching interval, with the upper graph being the voltage and current on the drain-to-source and the lower graph detailing VGS vs. time with a constant current charging the gate. The Xaxis, therefore, is also representative of gate charge (QG). CISS = CGD + CGS and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from MOSFET datasheets. (27) t5 Switching Losses and QG High-Side Losses PUPPER = PSW + PCOND t4 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller PUPPER is the upper MOSFET's total losses and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time), shown as t2+t3 in Figure 17. Dual Converter 180 Phased I DRIVER QG( SW ) = QGD + QGS - QTH (31) where QTH is the gate charge required to get the MOSFET to its threshold (VTH). (29) www.fairchildsemi.com 16 PG = Q G x V CC x f SW Layout Considerations Switching converters, even during normal operation, produce short pulses of current that could cause substantial ringing and be a source of EMI if layout constraints are not observed. (32) Low-Side Losses There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rates and are noise generators. The low-power components responsible for bias and feedback functions are sensitive to noise. Q2, however, switches on or off with its parallel Schottky diode conducting; therefore VDS 0.5V. Since PSW is proportional to VDS, Q2's switching losses are negligible and Q2 is selected based on RDS(ON) only. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Conduction losses for Q2 are given by: Notice all the nodes that are subjected to high-dV/dt voltage swing; such as SW, HDRV, and LDRV. All surrounding circuitry tends to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use highdensity interconnect systems, or micro-vias, on these signals. The use of blind or buried vias should be limited to the low-current signals only. The use of normal thermal vias is at the discretion of the designer. ATE where QG is the total gate charge to reach VCC. PCOND = (1 - D ) x I OUT 2 x R DS ( ON ) (33) where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature, and: D= V OUT (34) V IN is the minimum duty cycle for the converter. Since DMIN < 20% for portable computers, (1-D) 1 produces a conservative result, further simplifying the calculation. Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. The maximum power dissipation (PD(MAX)) is a function of the maximum allowable die temperature of the low-side MOSFET, the JA, and the maximum allowable ambient temperature rise: PD(MAX ) = T J(MAX ) - T A (MAX ) JA Locate small critical components, like the soft-start capacitor and current sense resistors, as close as possible to the respective pins of the IC. (35) The FAN5236 utilizes advanced packaging technology with lead pitch of 0.6mm. High-performance analog semiconductors utilizing narrow lead spacing may require special considerations in design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices. JA depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC Application Note AN-1029 -- Maximum Power Enhancement Techniques for SO-8 Power MOSFETs). (c) 2002 Fairchild Semiconductor Corporation FAN5236 * Rev. 1.3.2 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should be taken to include the delivery of the MOSFET's gate power (PGATE) in calculating the power dissipation required for the FAN5236: www.fairchildsemi.com 17 FAN5236 -- Dual Mobile-Friendly DDR/Dual-Output PWM Controller Physical Dimensions Figure 19. 28-Lead, Thin Shrink Outline Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2002 Fairchild Semiconductor Corporation FAN5236 Rev. 1.3.2 www.fairchildsemi.com 18 FAN5236 -- Dual Mobile-Friendly DDR/Dual-Output PWM Controller (c) 2002 Fairchild Semiconductor Corporation FAN5236 Rev. 1.3.2 www.fairchildsemi.com 19