SEMICONDUCTOR
1
Features
• Advanced 0.8 micron CMOS Technology
• These Devices are Pin Compatible with Bipolar
FAST™ Series at a Higher Speed and Lower Power
Consumption
•25Ω Series Resistor On All Outputs (FCT2XXX Only)
• TTL Input and Output Levels
• Low Ground Bounce Outputs (25ΩSeries Only)
• Extremely Low Static Power
• Hysteresis on All Inputs
Description
The CD74FCT153T, CD74FCT253T, CD74FCT2153T and
CD74FCT2253T are high-speed dual 4-input multiplexers.
The CD74FCT153T and CD74FCT2153T have TTL outputs,
while the CD74FCT253T and CD74FCT2253T have threes-
tate outputs. The output b uff ers are designed with a po w eroff
disable allo wing ‘liv e insertion’ of boards when used as back-
plane drivers.
The CD74FCT2153T and CD74FCT2253T devices have a
built-in 25Ωseries resistor on all outputs to reduce noise due
to reflections, thus eliminating the need for an external termi-
nating resistor.
Pinout
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CD74FCT153TM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT153ATM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT153CTM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT153TNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT153ATNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT153CTNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT153TQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT153ATQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT153CTQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT253TM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT253ATM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT253CTM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT253TNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT253ATNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT253CTNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT253TQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT253ATQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT253CTQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT2153TM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT2153ATM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT2153CTM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT2153TNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT2153ATNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT2153CTNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT2153TQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT2153ATQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT2153CTQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT2253TM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT2253ATM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT2253CTM -40 to 85 16 Ld SOIC M16.3-P
CD74FCT2253TNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT2253ATNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT2253CTNM -40 to 85 16 Ld SOIC M16.15-P
CD74FCT2253TQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT2253ATQM -40 to 85 16 Ld QSOP M16.15A-P
CD74FCT2253CTQM -40 to 85 16 Ld QSOP M16.15A-P
NO TE: When ordering, use the entire part number . Add the suffix 96
to obtain the variant in the tape and reel.
CD74FCT153T, CD74FCT253T,
CD74FCT2153T, CD74FCT2253T
(QSOP, SOIC)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
EA
S1
I3A
I2A
I1A
I0A
GND
OA
VCC
S0
I3B
I2B
I1B
I0B
OB
EB
December 1996
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1996
CD74FCT153T, CD74FCT253T,
CD74FCT2153T, CD74FCT2253T
High-Speed CMOS Dual 4-Input Multiplexer
File Number 4161.2
2
Functional Block Diagram
EBEAS1S0I0A I1A I2A I3A I0B I1B I2B I3B
OAOB
THREE-STATE ENABLE
ON CD74FCT253T ONLY
TRUTH TABLE (NOTE 1)
INPUTS
OUTPUTS
CD74FCT153, CD74FCT2153 CD74FCT253, CD74FCT2253
EAEBS1S0OAOBOAOB
HXXXLXZX
XHXXXLXZ
LLLLI
0A I0B I0A I0B
LLLHI
1A I1B I1A I1B
LLHLI
2A I2B I2A I2B
LLHHI
3A I3B I3A I3B
NOTE:
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care
Z = High Impedance
Pin Description
PIN NAME DESCRIPTION
I0A-I3A, I0B-I3B Data Inputs
S0, S1Select Inputs
EA, EBEnable Input
OA, OBData Outputs
GND Ground
VCC Power
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
3
Absolute Maximum Ratings Thermal Information
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120mA
Operating Conditions
Operating Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 85oC
Supply Voltage to Ground Potential
Inputs and VCC Only. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Supply Voltage to Ground Potential
Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Thermal Resistance (Typical, Note 2) θJA (oC/W)
16 Lead SOIC (150 mil) Package . . . . . . . . . . . . . . 110
16 Lead SOIC (300 mil) Package . . . . . . . . . . . . . . 97
16 Lead QSOP Package . . . . . . . . . . . . . . . . . . . . . 140
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(Lead Tips Only)
CA UTION: Stresses abo v e those listed in “Absolute Maximum Ratings” ma y cause permanent damage to the de vice. This is a stress only r ating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETERS SYMBOL (NOTE 3)
TEST CONDITIONS MIN (NOTE 4)
TYP MAX UNITS
DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40oC to 85oC, VCC = 5.0V ± 5%
Output HIGH Voltage VOH VCC = Min, VIN = VIH or VIL IOH = -15.0mA 2.4 3.0 - V
Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL IOL = 48mA - 0.3 0.50 V
Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL IOL = 12mA
(25Ω series) - 0.3 0.50 V
Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 - - V
Input LOW Voltage VIL Guaranteed Logic LOW Level - - 0.8 V
Input HIGH Current IIH VCC = Max VIN = VCC --1µA
Input LOW Current IIL VCC = Max VIN = GND - - -1 µA
High Impedance
Output Current IOZH,
IOZL VCC = Max VOUT = 2.7V 1 µA
VOUT = 0.5V -1 µA
Clamp Diode Voltage VIK VCC = Min, IIN = -18mA - -0.7 -1.2 V
Short Circuit Current IOS VCC = Max (Note 5),
VOUT = GND -60 -120 - mA
Power Down Disable IOFF VCC = GND, VOUT = 4.5V - - 100 µA
Input Hysteresis VH- 200 - mV
CAPACITANCE TA = 25oC, f = 1MHz
Input Capacitance
(Note 6) CIN VIN = 0V - 6 10 pF
Output Capacitance
(Note 6) COUT VOUT = 0V - 8 12 pF
POWER SUPPLY SPECIFICATIONS
Quiescent Power
Supply Current ICC VCC = Max VIN = GND or VCC - 0.1 500 µA
Supply Current per
Input at TTL HIGH ∆ICC VCC = Max VIN = 3.4V
(Note 7) - 0.5 2.0 mA
Supply Current per
Input per MHz
(Note 8)
ICCD VCC = Max, Outputs Open
Other Inputs at GND
One Bit Toggling
50% Duty Cycle
VIN = VCC
VIN = GND - 0.15 0.25 mA/
MHz
Total Power Supply
Current (Note 10) ICVCC = Max, Outputs Open
fI = 10MHz, 50% Duty Cycle
Other Inputs at GND
One Bit Toggling
VIN = VCC
VIN = GND - 3.2 6.5
(Note 9) mA
VIN = 3.4V
VIN = GND - 3.5 7.5
(Note 9) mA
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
4
Switching Specifications Over Operating Range
PARAMETER SYMBOL
(NOTE 11)
TEST
CONDITIONS
TATCT
UNIT
(NOTE 12)
MIN MAX (NOTE 12)
MIN MAX (NOTE 12)
MIN MAX
CD74FCT153T, CD74FCT2153T
Propagation Delay
Sn to O tPLH,
tPHL CL = 50pF
RL = 500Ω1.5 9.0 1.5 6.6 1.5 5.6 ns
Propagation Delay
In to O tPLH,
tPHL 1.5 7.0 1.5 5.2 1.5 4.5 ns
Propagation Delay
E to O tPLH,
tPHL 1.5 7.0 1.5 5.2 1.5 4.8 ns
CD74FCT253T, CD74FCT2253T
Propagation Delay
Sn to O tPLH,
tPHL CL = 50pF
RL = 500Ω1.5 9.0 1.5 6.6 1.5 5.6 ns
Propagation Delay
In to O tPLH,
tPHL 1.5 7.0 1.5 5.2 1.5 4.5 ns
Output Enable Time
E to O tPZH,
tPZL 1.5 9.0 1.5 6.0 1.5 5.0 ns
Output Enable Time
E to O (Note 13) tPHZ,
tPLZ 1.5 7.0 1.5 6.0 1.5 5.0 ns
NOTES:
3. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
4. Typical values are at VCC = 5.0V, 25oC ambient and maximum loading.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
6. This parameter is determined by device characterization but is not production tested.
7. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
8. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
9. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
10. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (Vin = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
11. See test circuit and wave forms.
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. This parameter is guaranteed but not production tested.
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
5
Test Circuits and Waveforms
NOTE:
14. Pulse Generator for All Pulses: Rate ≤1.0MHz; ZOUT ≤50Ω;
tf, tr≤ 2.5ns. FIGURE 1. TEST CIRCUIT
FIGURE 2. ENABLE AND DISABLE TIMING FIGURE 3. PROPAGATION DELAY
DUT
PULSE
GENERATOR
RTCL
50pF
VCC
VOUT
7.0V
500Ω
VIN
500Ω
SWITCH POSITION
TEST SWITCH
tPLZ, tPZL Closed
tPHZ, tPZH, tPLH, tPHL Open
DEFINITIONS:
CL = Load capacitance, includes jig and probe capacitance.
RT = Termination resistance, should be equal to ZOUT of the
Pulse Generator.
3V
1.5V
0V
CONTROL INPUT
OUTPUT
NORMALLY LOW
OUTPUT
NORMALLY HIGH SWITCH
OPEN
tPZL 3.5V
1.5V
1.5V
0V
tPLZ
tPHZ
tPZH
0V
3.5V
0.3V
0.3V
VOL
VOH
SWITCH
CLOSED
ENABLE DISABLE
1.5V
3V
0V
1.5V
3V
0V
tPLH
SAME PHASE
INPUT TRANSITION
tPHL
tPLH tPHL
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT 1.5V
VOH
VOL
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
6
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs.
2. Dimension “E” does not include interlead flash or protrusions.
3. “L” is the length of terminal for soldering to a substrate.
4. “N” is the number of terminal positions.
5. Terminal numbers are shown for reference only.
6. Controlling dimension: INCHES. Converted millimeter dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
e
L
B
A1
A
SEATING PLANE
0.10(0.004) C
H
α
h x 45o
0.25(0.010) M
Small Outline Plastic Packages (SOIC)
M16.15-P
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.053 0.069 1.35 1.75 -
A1 0.0040 0.0098 0.102 0.249 -
B 0.013 0.020 0.330 0.508 -
C 0.007 0.010 0.178 0.254 -
D 0.385 0.394 9.78 10.01 1
E 0.149 0.157 3.78 3.99 2
e 0.050 BSC 1.27 BSC -
H 0.231 0.241 5.86 6.12 -
h 0.0099 0.0196 0.25 0.50 -
L 0.016 0.050 0.41 1.27 3
N16 164
α
0
o
8
o
0
o
8
o
-
Rev. 0 6/96
7
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs.
2. Dimension “E” does not include interlead flash or protrusions.
3. “L” is the length of terminal for soldering to a substrate.
4. “N” is the number of terminal positions.
5. Terminal numbers are shown for reference only.
6. Controlling dimension: INCHES. Converted millimeter dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
e
L
B
A1
A
SEATING PLANE
0.10(0.004) C
H
α
h x 45o
0.25(0.010) M
Small Outline Plastic Packages (SOIC)
M16.3-P
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.092 0.105 2.34 2.67 -
A1 0.004 0.012 0.102 0.302 -
B 0.013 0.020 0.330 0.508 -
C 0.009 0.011 0.229 0.279 -
D 0.397 0.413 10.08 10.49 1
E 0.291 0.299 7.39 7.59 2
e 0.050 BSC 1.27 BSC -
H 0.401 0.411 10.18 10.44 -
h 0.010 0.029 0.254 0.737 -
L 0.016 0.050 0.41 1.27 3
N16 164
α
0
o
8
o
0
o
8
o
-
Rev. 0 5/96
8
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Harris Semiconductor products are sold by description only. Harr is Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which ma y result from its use . No license is g r anted b y implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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FAX: (65) 748-0400
SEMICONDUCTOR
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs.
2. Dimension “E” does not include interlead flash or protrusions.
3. “L” is the length of terminal for soldering to a substrate.
4. “N” is the number of terminal positions.
5. Terminal numbers are shown for reference only.
6. Controlling dimension: INCHES. Converted millimeter dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
e
L
B
A1
A
SEATING PLANE
0.10(0.004) C
H
α
h x 45o
0.17(0.007) M
Shrink Small Outline Plastic Packages (SSOP/QSOP)
M16.15A-P
16 LEAD SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.053 0.069 1.35 1.75 -
A1 0.007 0.011 0.178 0.279 -
B 0.008 0.012 0.203 0.305 -
C 0.007 0.010 0.178 0.254 -
D 0.189 0.197 4.80 5.00 1
E 0.149 0.157 3.78 3.99 2
e 0.025 BSC 0.635 BSC -
H 0.228 0.244 5.79 6.20 -
h 0.015 0.38 -
L 0.016 0.050 0.41 1.27 3
N16 164
α
0
o
8
o
0
o
8
o
-
Rev. 2 7/96
