ISL29010 Data Sheet November 11, 2011 Light-to-Digital Output Sensor with High Sensitivity, Gain Selection, and I2C Interface The ISL29010 is an integrated light sensor with I2C interface. It has an internal signed15-bit integrating type ADC designed based on the charge-balancing conversion technique. This ADC is capable of rejecting 50Hz and 60Hz flicker caused by artificial light sources. The lux range select feature allows the user to program the lux range for optimized counts/lux. In normal operation, power consumption is typically 250A. Furthermore, a power-down mode can be controlled by software via the I2C interface, reducing power consumption to less than 1A. Designed to operate on supplies from 2.5V to 3.3V, the ISL29010 is specified for operation over the -40C to +85C ambient temperature range. FN6414.1 Features * Range select via I2C - Range 1 = 0 lux to 2,000 lux - Range 2 = 0 lux to 8,000 lux - Range 3 = 0 lux to 32,000 lux - Range 4 = 0 lux to 128,000 lux * Human eye response (540nm peak sensitivity) * Temperature compensated * Signed 15-bit resolution * Adjustable resolution: up to 20 counts per lux * 1 bit I2C address selection * Simple output code, directly proportional to lux * IR + UV rejection * 50Hz/60Hz rejection * 2.5V to 3.3V supply Ordering Information L6.2x2.1 Evaluation Board 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL29010. For more information on MSL please see tech brief TB477. ISL29010 (6 LD ODFN) TOP VIEW * Operating temperature range: -40C to +85C Applications NOTES: Pinout * Pb-free (RoHS compliant) * Display and keypad backlight dimming for - Mobile Devices: Smart phone, PDA, and GPS - Computing devices: Notebook PC, UMPC web pod - Consumer devices: LCD-TV, digital picture frame, and digital cameras * Industrial and medical light sensing Block Diagram PHOTODIODE ARRAY VDD 1 LIGHT DATA PROCESS VDD 1 6 SDA GND 2 5 SCL IREF INTEGRATING ADC EXT TIMING DATA REGISTER I2C 5 SCL 6 SDA 216 COUNTER 3 REXT 1 COMMAND REGISTER FOSC 4 A0 REXT 3 SHDN 6 Ld ODFN PKG. DWG. # INT TIME -40 to +85 PACKAGE (Pb-Free) GAIN/RANGE ISL29010IROZ-T7 ISL29010IROZ-EVALZ * 6 Ld ODFN (2.1mmx2mm) TEMP. RANGE (C) MODE PART NUMBER (Notes 1, 2, 3) 2 GND ISL29010 4 A0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2008, 2011. All Rights Reserved I2C Bus is a registered trademark owned by NXP Semiconductors Netherlands, B.V Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL29010 Absolute Maximum Ratings (TA = +25C) Thermal Information VDD Supply Voltage between VDD and GND . . . . . . . . . . . . . 3.6V I2C Bus Pin Voltage (SCL, SDA) . . . . . . . . . . . . . . . . . -0.2V to 5.5V I2C Bus Pin Current (SCL, SDA) . . . . . . . . . . . . . . . . . . . . . . <10mA A0, REXT Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to VDD ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V Thermal Resistance (Typical Note 4) JA (C/W) 6 Ld ODFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +90C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-40C to +100C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VDD = 3V, TA = +25C, REXT = 100k, unless otherwise specified, Internal Timing Mode operation (See "Principles of Operation" on page 3). DESCRIPTION CONDITION MIN (Note 7) TYP MAX (Note 7) 0.5k to 10k UNIT Ee Detectable Input Light Intensity VDD Power Supply Range IDD Supply Current IDD1 Supply Current Disabled Software disabled fOSC1 Internal Oscillator Frequency Gain/Range = 1 or 2 fOSC2 Internal Oscillator Frequency Gain/Range = 3 or 4 fI2C I2C Clock Rate Range DATA0 Dark ADC Code DATA1 Full-Scale ADC Code DATA2 Light Count Output E = 300 lux, fluorescent light, Gain/Range = 1 (Note 5) DATA3 Light Count Output E = 300 lux, fluorescent light, Gain/Range = 2 (Note 5) 1100 Counts DATA4 Light Count Output E = 300 lux, fluorescent light, Gain/Range = 3 (Note 5) 275 Counts DATA5 Light Count Output E = 300 lux, fluorescent light, Gain/Range = 4 (Note 5) 69 Counts VREF Voltage of REXT Pin VTL SCL ,SDA and A0 Threshold LO (Note 6) 1.05 V VTH SCL ,SDA and A0 Threshold HI (Note 6) 1.95 V ISDA SDA Current Sinking Capability 5 mA 2.50 lux 3.30 V 0.25 0.33 mA 0.1 1 A 308 342 377 kHz 616 684 754 kHz 1 to 400 E = 0 lux, Gain/Range = 1 0 kHz 6 Counts 32767 3300 0.490 3 4400 0.515 Counts 5500 0.540 Counts V NOTES: 5. Fluorescent light is substituted by a green LED during production. 6. The voltage threshold levels of the SDA and SCL pins are VDD dependent: VTL = 0.35*VDD. VTH = 0.65*VDD. 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 2 FN6414.1 November 11, 2011 ISL29010 Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 VDD Positive supply; connect this pin to a regulated 2.5V to 3.3V supply 2 GND Ground pin. The thermal pad is connected to the GND pin 3 REXT External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100k resistor with 1% tolerance 4 A0 5 SCL I2C serial clock 6 SDA I2C serial data Bit 0 of I2C address Principles of Operation Photodiodes The ISL29010 contains two photodiode arrays which convert light into current. Some diodes are sensitive to both visible and infrared light, while the others are only sensitive to infrared light. Using the infrared portion of the light as baseline, the visible light can be extracted. The spectral response vs wavelength is shown in Figure 6 in the "Typical Performance Curves" on page 9. After light is converted to current during the light data process, the current output is converted to digital by a single built-in integrating type signed 15-bit Analog-to-Digital Converter (ADC). An I2C command reads the visible light intensity in counts. The converter is a charge-balancing integrating type signed 15-bit ADC. The chosen method for conversion is best for converting small current signals in the presence of an AC periodic noise. A 100ms integration time, for instance, highly rejects 50Hz and 60Hz power line noise simultaneously. See "Integration Time or Conversion Time" on page 7 and "Noise Rejection" on page 8. The built-in ADC offers user flexibility in integration time or conversion time. There are two timing modes: Internal Timing Mode and External Timing Mode. In Internal Timing Mode, integration time is determined by an internal dual speed oscillator (fOSC), and the n-bit (n = 4, 8, 12, 16) counter inside the ADC. In External Timing Mode, integration time is determined by the time between two consecutive I2C External Timing Mode commands. See External Timing Mode example. A good balancing act of integration time and resolution (depending on the application) is required for optimal results. The I2C bus lines can pulled above VDD, 5.5V max. set the high and low interrupt thresholds. There are four 8-bit data Read Only registers, two bytes for the sensor reading and another two bytes for the timer counts. The data registers contain the ADC's latest digital output, and the number of clock cycles in the previous integration period. The ISL29010 has a 7-bit I2C interface slave address. The six most significant bits are hardwired internally as 100010 while the least significant bit A0 can be either connected to Ground or VDD to allow two possible addresses 1000100 or 1000101. When 1000100x or 1000101x with x as R or W is sent after the Start condition, this device compares the first seven bits of this byte to its address and matches. Figure 1 shows a sample one-byte read. Figure 2 shows a sample one-byte write. Figure 3 shows a sync_I2C timing diagram sample for externally controlled integration time. The I2C bus master always drives the SCL (clock) line, while either the master or the slave can drive the SDA (data) line. Figure 2 shows a sample write. Every I2C transaction begins with the master asserting a start condition (SDA falling while SCL remains high). The following byte is driven by the master, and includes the slave address and read/write bit. The receiving device is responsible for pulling SDA low during the acknowledgement period. Every I2C transaction ends with the master asserting a stop condition (SDA rising while SCL remains high). For more information about the I2C standard, please consult the Philips(R) I2C specification documents. The ADC has four I2C programmable range select to dynamically accommodate various lighting conditions. For very dim conditions, the ADC can be configured at its lowest range. For very bright conditions, the ADC can be configured at its highest range. I2C Interface There are eight (8) 8-bit registers available inside the ISL29010. The command and control registers define the operation of the device. The command and control registers do not change until the registers are overwritten. There are two 8-bit registers that 3 FN6414.1 November 11, 2011 ISL29010 I2C DATA Start I2C SDA In DEVICE ADDRESS A6 I2C SDA Out I2C CLK A5 A4 A3 A2 A1 A0 W A W A SDA DRIVEN BY MASTER 1 2 3 4 5 6 REGISTER ADDRESS R7 8 R5 R4 R3 R2 R1 R0 SDA DRIVEN BY MASTER A 7 R6 A 9 1 2 3 4 5 6 7 8 STOP DEVICE ADDRESS START A A6 A5 A SDA DRIVEN BY MASTER 9 1 2 A4 3 A3 A2 4 5 A1 6 A0 7 W 8 A DATA BYTE0 A A SDA DRIVEN BY ISL29003 STOP NAK A D7 D6 D5 D4 D3 D2 D1 D0 A 9 1 2 3 4 5 6 7 8 9 FIGURE 1. I2C READ TIMING DIAGRAM SAMPLE I2C DATA I2C SDA In Start DEVICE ADDRESS W A A6 A5 A4 A3 A2 A1 A0 W A A I2C SDA Out I2C CLK In SDA DRIVEN BY MASTER 1 2 3 4 5 6 7 8 9 REGISTER ADDRESS A FUNCTIONS A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0 A SDA DRIVEN BY MASTER A SDA DRIVEN BY MASTER A 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 STOP 9 FIGURE 2. I2C WRITE TIMING DIAGRAM SAMPLE I2 C D A T A S t a rt D E V IC E A D D R E S S I2 C S D A In A6 I2 C S D A O u t A5 A4 A3 A2 A1 A0 W A W A S D A D R IV EN B Y M A S T ER 1 I2 C C L K In 2 3 4 5 6 R E G IS T E R A D D R E S S R7 8 9 R5 R4 R3 R2 R1 R0 S D A D R IV EN B Y M A S T ER A 7 R6 A S top 1 2 3 4 5 6 7 A A 8 9 FIGURE 3. I2C SYNC_I2C TIMING DIAGRAM SAMPLE 4 FN6414.1 November 11, 2011 ISL29010 Register Set There are eight registers that are available in the ISL29010. Table 1 summarizes the available registers and their functions. TABLE 1. REGISTER SET BIT ADDR REG NAME 7 6 5 4 3 2 1 0 DEFAULT 00h COMMAND ADCE ADCPD TIMM 0 ADCM1 ADCM0 RES1 RES0 00h 01h CONTROL 0 0 0 0 GAIN1 GAIN0 0 0 00h 04h LSB SENSOR S7 S6 S5 S4 S3 S2 S1 S0 00h 05h MSB SENSOR S15 S14 S13 S12 S11 S10 S9 S8 00h 06h LSB TIMER T7 T6 T5 T4 T3 T2 T1 T0 00h 07h MSB TIMER T15 T14 T13 T12 T11 T10 T9 T8 00h TABLE 2. WRITE ONLY REGISTERS ADDRESS REGISTER NAME b1xxx_xxxx sync_I2C bx1xx_xxxx clar_int TABLE 5. TIMING MODE BIT 5 FUNCTIONS/DESCRIPTION Writing a logic 1 to this address bit ends the current ADC-integration and starts another. Used only with External Timing Mode. Writing a logic 1 to this address bit clears the interrupt. Command Register 00(hex) The Read/Write command register has five functions: 1. Enable; Bit 7.This function either resets the ADC or enables the ADC in normal operation. A logic 0 disables ADC to reset-mode. A logic 1 enables ADC to normal operation. TABLE 3. ENABLE BIT 7 OPERATION 0 Disable ADC-core to reset-mode (default) 1 Enable ADC-core to normal operation 2. ADCPD; Bit 6. This function puts the device in a power-down mode. A logic 0 puts the device in normal operation. A logic 1 powers down the device. TABLE 4. ADCPD BIT 6 OPERATION 0 Normal operation (default) 1 Power Down OPERATION 0 Internal Timing Mode. Integration time is internally timed determined by fOSC, REXT, and number of clock cycles. 1 External Timing Mode. Integration time is externally timed by the I2C host. 4. Photodiode Select Mode; Bits 3 and 2. Setting Bit 3 and Bit 2 to 1 and 0 enables ADC to give light count DATA output. TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3 BITS 3:2 MODE 0:0 Disable ADC 0:1 Disable ADC 1:0 Light count DATA output in signed (n - 1) bit * 1:1 No operation. * n = 4, 8, 12,16 depending on the number of clock cycles function. 5. Width; Bits 1 and 0. This function determines the number of clock cycles per conversion. Changing the number of clock cycles does more than just change the resolution of the device. It also changes the integration time, which is the period the device's analog-to-digital (A/D) converter samples the photodiode current signal for a lux measurement. TABLE 7. WIDTH BITS 1:0 3. Timing Mode; Bit 5. This function determines whether the integration time is done internally or externally. In Internal Timing Mode, integration time is determined by an internal dual speed oscillator (fOSC), and the n-bit (n = 4, 8, 12, 16) counter inside the ADC. In External Timing Mode, integration time is determined by the time between three consecutive external-sync sync_I2C pulses commands. 5 NUMBER OF CLOCK CYCLES 0:0 216 = 65,536 0:1 212 = 4,096 1:0 28 = 256 1:1 24 = 16 FN6414.1 November 11, 2011 ISL29010 Control Register 01(hex) The Read/Write control register has one function: 1. Range/Gain; Bits 3 and 2. The Full Scale Range can be adjusted by an external resistor REXT and/or it can be adjusted via I2C using the Gain/Range function. Gain/Range has four possible values, Range(k) where k is 1 through 4. Table 8 lists the possible values of Range(k) and the resulting FSR for some typical value REXT resistors. TABLE 8. RANGE/GAIN TYPICAL FSR LUX RANGES FSR LUX RANGE@ BITS 3:2 k RANGE(k) REXT = 100k FSR LUX RANGE@ REXT = 50k FSR LUX RANGE@ REXT = 500k 0:0 1 2,000 2,000 4,000 400 0:1 2 8,000 8,000 16,000 1,600 1:0 3 32,000 32,000 64,000 6,400 1:1 4 128,000 128,000 256,000 25,600 I2Sensor Data Register 04(hex) and 05(hex) When the device is configured to output a signed 15-bit data, the most significant byte is accessed at 04(hex), and the least significant byte can be accessed at 05(hex). The sensor data register is refreshed after every integration cycle. Timer Data Register 06(hex) and 07(hex) Note that the timer counter value is only available when using the External Timing Mode. The 06(hex) and 07(hex) are the LSB and MSB, respectively, of a 16-bit timer counter value corresponding to the most recent sensor reading. Each clock cycle increments the counter. At the end of each integration period, the value of this counter is made available over the I2C. This value can be used to eliminate noise introduced by slight timing errors caused by imprecise external timing. Microcontrollers, for example, often cannot provide high-accuracy command-to-command timing, and the timer counter value can be used to eliminate the resulting noise. TABLE 9. DATA REGISTERS The proportionality constant is determined by the Full Scale Range (FSR), and the n-bit ADC, which is user defined in the command register. The proportionality constant can also be viewed as the resolution; the smallest lux measurement the device can measure is in Equation 2. FSR = -----------n 2 (EQ. 2) Full-Scale Range (FSR) is determined by the software programmable Range/Gain, Range(k), in the command register and an external scaling resistor REXT, which is referenced to 100k. (EQ. 3) 100k FSR = Range ( k ) x -----------------R EXT The transfer function effectively for each timing mode becomes: INTERNAL TIMING MODE 100k Range ( k ) x -----------------R EXT E = ---------------------------------------------------- x DATA n 2 (EQ. 4) EXTERNAL TIMING MODE 100k Range ( k ) x -----------------R EXT E = ---------------------------------------------------- x DATA COUNTER (EQ. 5) n = 3, 7, 11, or 15. This is the number of clock cycles programmed in the command register. Range(k) is the user defined range in the Gain/Range bit in the command register. REXT is an external scaling resistor hardwired to the REXT pin. DATA is the output sensor reading in number of counts available at the data register. 2n represents the maximum number of counts possible in Internal Timing Mode. For the External Timing Mode, the maximum number of counts is stored in the data register named COUNTER. COUNTER is the number of increments accrued between integration time for External Timing Mode. ADDRESS (hex) CONTENTS 04 Least-significant byte of most recent sensor reading. Gain/Range, Range(k) 05 Most-significant byte of most recent sensor reading. 06 Least-significant byte of timer counter value corresponding to most recent sensor reading. 07 Most-significant byte of timer counter value corresponding to most recent sensor reading. The Gain/Range can be programmed in the control register to give Range(k) determining the FSR. Note that Range(k) is not the FSR (see Equation 3). Range(k) provides four constants depending on programmed k that will be scaled by REXT (see Table 8). Unlike REXT, Range(k) dynamically adjusts the FSR. This function is especially useful when light conditions are varying drastically while maintaining excellent resolution. Calculating Lux The ISL29010's output codes, DATA, are directly proportional to lux. (EQ. 1) E = x DATA 6 FN6414.1 November 11, 2011 ISL29010 Number of Clock Cycles, n-bit ADC Integration Time or Conversion Time The number of clock cycles determines "n" in the n-bit ADC; 2n Integration time is the period during which the device's analog-to-digital ADC converter samples the photodiode current signal for a lux measurement. Integration time, in other words, is the time to complete the conversion of analog photodiode current into a digital signal (number of counts). clock cycles is a n-bit ADC. n is programmable in the command register in the width function. Depending on the application, a good balance of speed and resolution has to be considered when deciding for n. For fast and quick measurement, choose the smallest n = 3. For maximum resolution without regard of time, choose n = 15. Table 10 compares the trade-off between integration time and resolution. See Equations 10 and 11 for the relation between integration time and n. See Equation 3 for the relation of n and resolution. TABLE 10. RESOLUTION AND INTEGRATION TIME SELECTION RANGE1 fOSC = 327kHz RANGE4 fOSC = 655kHz n tINT (ms) RESOLUTION LUX/COUNT tINT (ms) RESOLUTION (LUX/COUNT) 15 200 0.06 100 2 11 12.8 1.0 6.4 62.5 7 0.8 15.6 0.4 1,000 3 0.05 250 0.025 16,000 Integration time affects the measurement resolution. For better resolution, use a longer integration time. For short and fast conversions use a shorter integration time. The ISL29010 offers user flexibility in the integration time to balance resolution, speed and noise rejection. Integration time can be set internally or externally and can be programmed in the command register 00(hex) Bit 5. INTEGRATION TIME IN INTERNAL TIMING MODE This timing mode is programmed in the command register 00(hex) Bit 5. Most applications will be using this timing mode. When using the Internal Timing Mode, fOSC and n-bits resolution determine the integration time. tINT is a function of the number of clock cycles and fOSC. t INT = 2 m 1 x ---------f osc (EQ. 9) for Internal Timing Mode only REXT = 100k m = 4, 8, 12, and16. n is the number of bits of resolution. External Scaling Resistor REXT and fosc The ISL29010 uses an external resistor REXT to fix its internal oscillator frequency, fOSC. Consequently, REXT determines the fOSC, integration time and the FSR of the device. fOSC, a dual speed mode oscillator, is inversely proportional to REXT. For user simplicity, the proportionality constant is referenced to fixed constants 100k and 655kHz: 1 100k f OSC 1 = --- x ------------------ x 655 kHz 2 R EXT (EQ. 6) 100k f OSC 2 = ------------------ x 655 kHz R EXT (EQ. 7) fOSC1 is oscillator frequency when Range1 or Range2 are set. This is nominally 327kHz when REXT is 100k. fOSC2 is the oscillator frequency when Range3 or Range4 are set. This is nominally 655kHz when REXT is 100k. When the Range/Gain bits are set to Range1 or Range2, fOSC runs at half speed compared to when Range/Gain bits are set to Range3 and Range4. (EQ. 8) 1 f OSC 1 = --- ( f OSC 2 ) 2 The automatic fOSC adjustment feature allows significant improvement of signal-to-noise ratio when detecting very low lux signals. 2m therefore is the number of clock cycles. n can be programmed at the command register 00(hex) Bits 1 and 0. Since fOSC is dual speed depending on the Gain/Range bit, tINT is dual time. The integration time as a function of REXT is shown in Equation 10: t INT 1 = 2 m R EXT x ---------------------------------------------327kHz x 100k (EQ. 10) tINT1 is the integration time when the device is configured for Internal Timing Mode and Gain/Range is set to Range1 or Range2. t INT 2 = 2 m R EXT x ---------------------------------------------655kHz x 100k (EQ. 11) tINT2 is the integration time when the device is configured for Internal Timing Mode and Gain/Range is set to Range3 or Range4. TABLE 11. INTEGRATION TIMES FOR TYPICAL REXT VALUES RANGE1 RANGE2 RANGE3 RANGE4 REXT (k) n = 15-BIT n = 11-BIT n = 11-BIT n=3 50 100 6.4 3.2 0.013 100** 200 13 6.5 0.025 200 400 26 13 0.050 500 1000 64 32 0.125 *Integration time in milliseconds **Recommended REXT resistor value 7 FN6414.1 November 11, 2011 ISL29010 INTEGRATION TIME IN EXTERNAL TIMING MODE This timing mode is programmed in the command register 00(hex) Bit 5. External Timing Mode is recommended when integration time can be synchronized to an external signal such as a PWM to eliminate noise. To read the light count DATA output, the device needs three sync_I2C commands to complete one measurement. The 1st sync_I2C command starts the conversion of the diode array 1. The 2nd sync_I2C completes the conversion of diode array 1 and starts the conversion of diode array 2. The 3rd sync_I2C pules ends the conversion of diode array 2, outputs the light count DATA, and starts over again to commence conversion of diode array 1. The integration time, tINT, is the sum of two identical time intervals between the three sync pulses. tINT is determined by Equation 12: k OSC t INT = --------------f OSC plastic material. A thickness of t = 1mm is recommended for a window lens design. The bigger the diameter of the window lens, the wider the viewing angle is of the ISL29010. Table 12 shows the recommended dimensions of the optical window to ensure both 35 and 45 viewing angle. These dimensions are based on a window lens thickness of 1.0mm and a refractive index of 1.59. WINDOW LENS t DTOTAL ISL29013 D1 DLENS (EQ. 12) E= where kOSC is the number of internal clock cycles obtained from Timer data register and fOSC is the internal I2C operating frequency. The internal oscillator, fOSC, operates identically in both the internal and external timing modes, with the same dependence on REXT. However, in External Timing Mode, the number of clock cycles per integration is no longer fixed at 2n. The number of clock cycles varies with the chosen integration time, and is limited to 216 = 65,536. In order to avoid erroneous lux readings the integration time must be short enough not to allow an overflow in the counter register. 65,535 t INT < -----------------f OSC (EQ. 13) fOSC = 327kHz*100k/REXT. When Range/Gain is set to Range1 or Range2. fOSC = 655kHz*100k/REXT. When Range/Gain is set to Range3 or Range4. DATA 215 x 2000 = VIEWING ANGLE FIGURE 4. FLAT WINDOW LENS TABLE 12. RECOMMENDED DIMENSIONS FOR A FLAT WINDOW DESIGN DTOTAL D1 DLENS @ 35 VIEWING ANGLE DLENS @ 45 VIEWING ANGLE 1.5 0.50 2.25 3.75 2.0 1.00 3.00 4.75 2.5 1.50 3.75 5.75 3.0 2.00 4.30 6.75 3.5 2.50 5.00 7.75 t=1 D1 DLENS DTOTAL Thickness of lens Distance between ISL29010 and inner edge of lens Diameter of lens Distance constraint between the ISL29010 and lens outer edge * All dimensions are in mm. Noise Rejection Suggested PCB Footprint In general, integrating type ADC's have excellent noise-rejection characteristics for periodic noise sources whose frequency is an integer multiple of the integration time. For instance, a 60Hz AC unwanted signal's sum from 0ms to k*16.66ms (k = 1,2...ki) is zero. Similarly, setting the device's integration time to be an integer multiple of the periodic noise signal greatly improves the light sensor output signal in the presence of noise. It is important that the users check the "Surface Mount Assembly Guidelines for Optical Dual FlatPack No Lead (ODFN) Package" before starting ODFN product board mounting. Flat Window Lens Design A window lens will surely limit the viewing angle of the ISL29010. The window lens should be placed directly on top of the device. The thickness of the lens should be kept at minimum to minimize loss of power due to reflection and also to minimize loss due to absorption of energy in the 8 http://www.intersil.com/data/tb/TB477.pdf Layout Considerations The ISL29010 is relatively insensitive to layout. Like other I2C devices, it is intended to provide excellent performance even in significantly noisy environments. There are only a few considerations that will ensure best performance. FN6414.1 November 11, 2011 ISL29010 Route the supply and I2C traces as far as possible from all sources of noise. Use two power-supply decoupling capacitors, 4.7F and 0.1F, placed close to the device. Soldering Considerations Convection heating is recommended for reflow soldering; direct-infrared heating is not recommended. The plastic ODFN package does not require a custom reflow soldering profile, and is qualified to +260C. A standard reflow soldering profile with a +260C maximum is recommended. Typical Circuit A typical application for the ISL29010 is shown in Figure 5. The ISL29010's I2C address is internally hardwired as 1000100. The device can be tied onto a system's I2C bus together with other I2C compliant devices. 1.8V TO 5.5V I2C MASTER R2 10k R1 10k MICROCONTROLLER SDA SCL 2.5V TO 3.3V I2C SLAVE_0 1 2 C1 4.7F C2 0.1F 3 VDD SDA GND SCL REXT A0 I2C SLAVE_1 I2C SLAVE_n 6 SDA SDA 5 SCL SCL 4 REXT ISL29010 100k FIGURE 5. ISL29010 TYPICAL CIRCUIT Typical Performance Curves (REXT = 100k) 1.2 RADIATION PATTERN NORMALIZED RESPONSE HUMAN EYE RESPONSE 1.0 20 LUMINOSITY 30 ANGLE 40 0.8 10 0 10 20 30 40 50 50 0.6 ISL29010 RESPONSE 60 60 0.4 70 70 0.2 80 0.0 -0.2 80 90 300 400 600 800 WAVELENGTH (nm) FIGURE 6. SPECTRAL RESPONSE 9 1.0k 1.1k 0.2 0.4 0.6 0.8 RELATIVE SENSITIVITY 90 1.0 FIGURE 7. RADIATION PATTERN FN6414.1 November 11, 2011 ISL29010 Typical Performance Curves (REXT = 100k) (Continued) 320 TA = +27C 1.0 SUN 0.8 HALOGEN 0.6 INCANDESCENT FLUORESCENT 0.4 SUPPLY CURRENT (mA) NORMALIZED LIGHT INTENSITY 1.2 306 5000 lux 292 278 200 lux 264 0.2 0 300 400 500 600 700 800 900 1000 250 2.0 1100 2.3 2.6 2.9 3.2 WAVELENGTH (nm) FIGURE 8. SPECTRUM OF LIGHT SOURCES FOR MEASUREMENT 1.015 TA = +27C 0 lux OUTPUT CODE RATIO (% FROM 3V) OUTPUT CODE (COUNTS) TA = +27C 6 4 RANGE 2 2 0 2.0 2.3 2.6 2.9 3.2 3.5 1.010 5000 lux 1.005 1.000 0.990 2.0 3.8 200 lux 0.995 2.3 SUPPLY VOLTAGE (V) 2.9 3.2 3.5 3.8 FIGURE 11. OUTPUT CODE vs SUPPLY VOLTAGE 315 320.0 VDD = 3V SUPPLY CURRENT (mA) TA = +27C 319.5 319.0 318.5 318.0 2.0 2.6 SUPPLY VOLTAGE (V) FIGURE 10. OUTPUT CODE FOR 0 LUX vs SUPPLY VOLTAGE OSCILLATOR FREQUENCY (kHz) 3.8 FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE 10 8 3.5 SUPPLY VOLTAGE (V) 2.3 2.6 2.9 3.2 3.5 3.8 SUPPLY VOLTAGE (V) FIGURE 12. OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE 10 305 5000 lux RANGE 3 295 285 200 lux RANGE 1 275 265 -60 -20 20 60 100 TEMPERATURE (C) FIGURE 13. SUPPLY CURRENT vs TEMPERATURE FN6414.1 November 11, 2011 ISL29010 Typical Performance Curves (REXT = 100k) (Continued) 1.080 VDD = 3V VDD = 3V 0 lux 8 OUTPUT CODE RATIO (% FROM +25C) OUTPUT CODE (COUNTS) 10 6 4 RANGE 2 2 0 -60 -20 20 1.048 5000 lux RANGE 3 1.016 200 lux RANGE 1 0.984 0.952 0.920 -60 60 -20 TEMPERATURE (C) FIGURE 14. OUTPUT CODE FOR 0 LUX vs TEMPERATURE 100 14000 CALCULATED ALS READING (LUX) OSCILLATOR FREQUENCY (kHz) 60 FIGURE 15. OUTPUT CODE vs TEMPERATURE 330 VDD = 3V 329 328 327 326 325 -60 -20 20 VDD = 3V 12000 HALOGEN 10000 FLUORESCENT 6000 4000 2000 TYPICAL OUTPUT LUX VARIATION BETWEEN FOUR LIGHT SOURCES: +15% 0 60 100 0 2k 4k 800 INCANDESCENT 600 FLUORESCENT 500 400 300 200 100 0 100 10k 12k 14k FIGURE 17. LIGHT SENSITIVITY vs LUX LEVEL CALCULATED ALS READING (LUX) HALOGEN 0 8k 100 VDD = 3V 900 700 6k LUX METER READING (LUX) FIGURE 16. OSCILLATOR FREQUENCY vs TEMPERATURE 1000 SUN INCANDESCENT 8000 TEMPERATURE (C) CALCULATED ALS READING (LUX) 20 TEMPERATURE (C) 200 300 400 500 600 700 800 900 LUX METER READING (LUX) FIGURE 18. LIGHT SENSITIVITY vs LUX LEVEL 11 1k VDD = 3V 90 HALOGEN 80 70 FLUORESCENT 60 50 40 INCANDESCENT 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 LUX METER READING (LUX) FIGURE 19. LIGHT SENSITIVITY vs LUX LEVEL FN6414.1 November 11, 2011 ISL29010 2.00mm SENSOR OFFSET 2.10mm 1 6 2 5 0.29mm 0.56mm 3 4 0.46mm FIGURE 20. 6 LD ODFN SENSOR LOCATION OUTLINE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN6414.1 November 11, 2011 ISL29010 Package Outline Drawing L6.2x2.1 6 LEAD OPTICAL DUAL FLAT NO-LEAD PLASTIC PACKAGE (ODFN) Rev 3, 5/11 2.10 A 6 PIN #1 INDEX AREA B 6 PIN 1 INDEX AREA 1 0.65 1.35 2.00 1.30 REF 4 6X 0.300.05 (4X) 0.10 0.10 M C A B 0.65 TOP VIEW 6x0.35 0.05 BOTTOM VIEW 2.50 PACKAGE OUTLINE 2.10 SEE DETAIL "X" 0.65 (4x0.65) 0.10 C MAX 0.75 C BASE PLANE SEATING PLANE 0.08 C SIDE VIEW (1.35) (6x0.30) C (6x0.20) 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. (6x0.55) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 13 FN6414.1 November 11, 2011