1
FN6414.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2008, 2011. All Rights Reserved
I2C Bus is a registered trademark owned by NXP Semiconductors Netherlands, B.V
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL29010
Light-to-Digital Output Sensor with High
Sensitivity, Gain Selection, and I2C
Interface
The ISL29010 is an integrated light sensor with I2C
interface. It has an internal signed15-bit integrating type
ADC designed based on the charge-balancing conversion
technique. This ADC is capable of rejecting 50Hz and 60Hz
flicker caused by artificial light sources. The lux range select
feature allows the user to program the lux range for
optimized counts/lux.
In normal operation, power consumption is typically 250µA.
Furthermore, a power-down mode can be controlled by
software via the I2C interface, reducing power consumption
to less than 1µA.
Designed to operate on su pplies from 2.5V to 3.3V, the
ISL29010 is specified for operation over the -40°C to +85°C
ambient temperature range.
Pinout ISL29010
(6 LD ODFN)
TOP VIEW
Features
• Range select via I2C
- Range 1 = 0 lux to 2,0 00 lux
- Range 2 = 0 lux to 8,0 00 lux
- Range 3 = 0 lux to 32,000 lux
- Range 4 = 0 lux to 128,00 0 lux
• Human eye response (540nm peak sensitivity)
• Temperature compensated
• Signed 15-bit resolution
• Adjustable resolution: up to 20 counts per lux
• 1 bit I2C address selection
• Simple output code, directly proportional to lux
• IR + UV rejection
• 50Hz/60Hz rejection
• 2.5V to 3.3V supply
• 6 Ld ODFN (2.1mmx2mm)
• Pb-free (RoHS compliant)
• Operating temperature range: -40°C to +85°C
Applications
• Display and keypad backlight dimming for
- Mobile Devices: Smart phone, PDA, and GPS
- Computi ng devices: Notebook PC, UMPC web pod
- Consumer devices: LCD-TV, digital picture frame, and
digital cameras
• Industrial and medical light sensing
Block Diagram
Ordering Information
PART NUMBER
(Notes 1, 2, 3) TEMP.
RANGE (°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISL29010IROZ-T7 -40 to +85 6 Ld ODFN L6.2x2.1
ISL29010IROZ-EVALZ Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials
and 100% matte tin plate - e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device
information page for ISL29010. For more information on MSL
please see tech brief TB477.
1
2
3
6
5
4
VDD
GND
REXT
SDA
SCL
A0
VDD
REXT GND
SDA
SCL
COMMAND
REGISTER
INTEGRATING
ADC DATA
REGISTER
I2C
PHOTODIODE
LIGHT
3 2
5
6
1
FOSC
IREF
COUNTER
216
GAIN/RANGE
EXT
SHDN
INT TIME
4
A0
ISL29010
TIMING
PROCESS
ARRAY
DATA
MODE
Data Sheet November 11, 2011
2FN6414.1
November 11, 2011
Absolute Maximum Ratings (TA = +25°C) Thermal Information
VDD Supply Voltage between VDD and GND . . . . . . . . . . . . . 3.6V
I2C Bus Pin Voltage (SCL, SDA) . . . . . . . . . . . . . . . . . -0.2V to 5.5V
I2C Bus Pin Current (SCL, SDA) . . . . . . . . . . . . . . . . . . . . . . <10mA
A0, REXT Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to VDD
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Resistance (Typical Note 4) θJA (°C/W)
6 Ld ODFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .+90°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VDD = 3V, TA = +25°C, REXT = 100kΩ, unless otherwise specified, Internal Timing Mode operation (S ee
“Principles of Operation” on page 3).
PARAMETER DESCRIPTION CONDITION MIN
(Note 7) TYP MAX
(Note 7) UNIT
EeDetectable Input Light Intensity 0.5k to 10k lux
VDD Power Supply Range 2.50 3.30 V
IDD Supply Current 0.25 0.33 mA
IDD1 Supply Current Disabled Software disabled 0.1 1 µA
fOSC1 Internal Oscillator Frequency Gain/Range = 1 or 2 308 342 377 kHz
fOSC2 Internal Oscillator Frequency Gain/Range = 3 or 4 616 684 754 kHz
fI2C I2C Clock Rate Range 1 to 400 kHz
DATA0 Dark ADC Code E = 0 lux, Gain/Range = 1 0 6 Counts
DATA1 Full-Scale ADC Code 32767 Counts
DA TA2 Light Count Output E = 300 lux, fluorescent light, Gain/Range = 1
(Note 5) 3300 4400 5500 Counts
DA TA3 Light Count Output E = 300 lux, fluorescent light, Gain/Range = 2
(Note 5) 1100 Counts
DA TA4 Light Count Output E = 300 lux, fluorescent light, Gain/Range = 3
(Note 5) 275 Counts
DA TA5 Light Count Output E = 300 lux, fluorescent light, Gain/Range = 4
(Note 5) 69 Counts
VREF Voltage of REXT Pin 0.490 0.515 0.540 V
VTL SCL ,SDA and A0 Threshold LO (Note 6) 1.05 V
VTH SCL ,SDA and A0 Threshold HI (Note 6) 1.95 V
ISDA SDA Current Sinking Capability 3 5 mA
NOTES:
5. Fluorescent light is substituted by a green LED during production.
6. The voltage threshold levels of the SDA and SCL pins are VDD dependent: VTL = 0.35*VDD. VTH = 0.65*VDD.
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
ISL29010
3FN6414.1
November 11, 2011
Principles of Operation
Photodiodes
The ISL29010 contains two photodi ode arrays which convert
light into current. Some diodes are sensitive to both visible
and infrared light, w hile the others are onl y sensitive to
infrared light. Using the infrared porti on of the light as
baseline, the visible light can be extracted. The spectral
response vs wavelength is shown in Figure 6 in the “Typical
Performance Curves” on p age 9. After l ight is converted to
current during the light dat a process, the curren t output is
converted to digital by a single bu ilt-in integrati ng type sig ned
15-bit Analog-to-D igital Converter (ADC). An I2C command
reads the visible light intensity in counts.
The converter is a charge-balancing integrating type signed
15-bit ADC. The chosen method for conversion is best for
converting small current signals in the presence of an AC
periodic noise. A 100ms integration time, for instance, highly
rejects 50Hz and 60Hz power line noise simultaneously. See
“Integration Time or Conversion T ime” on page 7 and “Noise
Rejection” on page 8.
The built-in ADC offers user flexibility in integration time or
conversion time. There are two timing modes: Internal Timing
Mode and External Timing Mode. In Internal T iming Mode,
integration time is determined by an internal dual speed
oscillator (fOSC), and the n-bit (n = 4, 8, 12, 16) counter inside
the ADC. In External T iming Mode, integration time is
determined by the time between two consecutive I2C External
T iming Mode commands. See External T iming Mode example.
A good balancing act of integration time and resolution
(depending on the application) is required for optimal results.
The ADC has four I2C programmable range select to
dynamically accommodate various lighting conditions. For
very dim conditions, the ADC can be configured at its lowest
range. For very bright conditions, the ADC can be configured
at its highest range.
I2C Interface
There are eight (8) 8-bit registers available inside the ISL29010.
The command and control registers define the operation of the
device. The command and control registers do not change until
the registers are overwritten. There are two 8- bit register s that
set the high and lo w interrupt thresholds . There are fo ur 8-bit
data Read Only registers, two bytes for the sensor reading and
another two bytes for the timer counts. The data registers
contain the ADC's latest digital output, and the number of clock
cycles in the previous integration period.
The ISL29010 has a 7-bit I2C interface slave address. The
six most significant bits are hardwired internally as 100010
while the least significant bit A0 can be either connecte d to
Ground or VDD to allow two possible addresses 1000100 or
1000101. When 1000100x or 1000101x with x as R or W is
sent after the Start condition, this device compares the first
seven bits of this byte to its address and matches.
Figure 1 shows a sample one-byte read. Figure 2 shows a
sample one-byte write. Figure 3 shows a sync_I 2C timing
diagram sample for externally controlled inte gration time.
The I2C bus master always drives the SCL (clock) line, while
either the master or the slave can drive the SDA (data) line.
Figure 2 shows a sample write. Every I2C transaction begins
with the master asserting a start condition (SDA falling while
SCL remains high). The following byte is driven by the
master, and includes the slave address and read/write bit.
The receiving device is responsible for pulling SDA low
during the acknowledgement period.
Every I2C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high).
For more information about the I2C standard, please consult
the Philips® I2C specification documents.
Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
1 VDD Positive supply; connect this pin to a regulated 2.5V to 3.3V supply
2 GND Ground pin. The thermal pad is connected to the GND pin
3 REXT External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100kΩ resistor with
1% tolerance
4 A0 Bit 0 of I2C address
5SCLI
2C serial clock The I2C bus lines can pulled above VDD, 5.5V max.
6SDAI
2C serial data
ISL29010
4FN6414.1
November 11, 2011
FIGURE 1. I2C READ TIMING DIAGRAM SAMPLE
Start WAA AA
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A A6 A5 A4 A3 A2 A1 A0 W A
A A A D7D6D5D4D3D2D1D0 A
123456789123456789 123456789123456789
STOP
STOP START
SDA DRIVEN BY MASTER
DEVICE ADDRESS
SDA DRIVEN BY ISL29003
DATA BYTE0
NAK
REGISTER ADDRE SS
I2C SDA
Out
DEVICE ADDRESS
I2C DATA
SDA DRIVEN BY MASTER
I2C CLK
I2C SDA
In
SDA DRIVEN BY MASTER
FIGURE 2. I2C WRITE TIMING DIAGRAM SAMPLE
Start
W
AAA
A6 A5 A4 A3 A2 A1 A0
W
A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0 A
AAA
123456789123456789123456789
STOP
I2C SDA In
I2C CLK In
SDA DRIVEN BY MASTER
FUNCTIONSREGISTER ADDRESS
I2C SDA Out
DE VICE ADDRESS
I2C DATA
SDA DRIVEN BY MASTER SDA DRIVEN BY MASTER
FIGURE 3. I2C SYNC_I2C TIMING DIAGRAM SAMPLE
Start WAAStop
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
AA
123456789123456789
REGISTER ADDRESS
SDA DRIV EN BY MA STER
I2C S DA O ut
DEVICE ADDRESS
I2C DATA
I2C S DA In
I2C CL K In
SDA DRIVEN BY MA STER
ISL29010
5FN6414.1
November 11, 2011
Register Set
There are eight registers that are available in th e ISL29010. Table 1 summarizes the available registers and their fu nctions.
Command Register 00(hex)
The Read/Write command register has five functions:
1. Enable; Bit 7.This function either resets the ADC or
enables the ADC in normal operation. A logic 0 disables
ADC to reset-mode. A logic 1 enables ADC to normal
operation.
2. ADCPD; Bit 6. This function puts the device in a
power-down mode. A logic 0 puts the device in normal
operation. A logic 1 power s down the device.
3. Timing Mode; Bit 5. This function determines whether the
integration time is done internally or externally . In Internal
Timing Mode, integration time is determined by an
internal dual speed oscillator (fOSC), and the n-bit
(n = 4, 8, 12, 16) counter inside the ADC. In External
Timing Mode, integration time is determined by the time
between three consecutive external-sync syn c _I2C
pulses commands.
4. Photodiode Select Mode; Bits 3 and 2. Setting Bit 3 and
Bit 2 to 1 and 0 enables ADC to give light count DATA
output.
* n = 4, 8, 12,16 depending on the number of clock cycl es
function.
5. Width; Bits 1 and 0. This function determines the number
of clock cycles per conversion. Changing the number of
clock cycles does more than just change the resolution of
the device. It also changes the integration time, which is
the period the device’s analog-to-digital (A/D) converter
samples the photodiode current signal for a lux
measurement.
TABLE 1. REGISTER SET
ADDR REG NAME
BIT
7 6 5 4 3 2 1 0 DEFAULT
00h COMMAND ADCE ADCPD TIMM 0 ADCM1 ADCM0 RES1 RES0 00h
01h CONTROL 0 0 0 0 GAIN1 GAIN0 0 0 00h
04h LSB
SENSOR S7 S6 S5 S4 S3 S2 S1 S0 00h
05h MSB
SENSOR S15 S14 S13 S12 S11 S10 S9 S8 00h
06h LSB TIMER T7 T6 T5 T4 T3 T2 T1 T0 00h
07h MSB TIMER T15 T14 T13 T12 T11 T10 T9 T8 00h
TABLE 2. WRITE ONLY REGISTERS
ADDRESS REGISTER
NAME FUNCTIONS/DESCRIPTION
b1xxx_xxxx sync_I2C Writing a logic 1 to this address bit
ends the current ADC-integration
and starts another. Used only with
External Timing Mode.
bx1xx_xxxx clar_int Writing a logic 1 to this address bit
clears the interrupt.
TABLE 3. ENABLE
BIT 7 OPERATION
0 Disable ADC-core to reset-mode (default)
1 Enable ADC-core to normal operation
TABLE 4. ADCPD
BIT 6 OPERATION
0 Normal operation (default)
1 Power Down
TABLE 5. TIMING MODE
BIT 5 OPERATION
0 Internal Timing Mode. Integration time is internally
timed determined by fOSC, REXT, and number of
clock cycles.
1 External Timing Mode. Integration time is externally
timed by the I2C host.
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
BITS 3:2 MODE
0:0 Disable ADC
0:1 Disable ADC
1:0 Light count DATA output in signed (n - 1) bit *
1:1 No operation.
TABLE 7. WIDTH
BITS 1:0 NUMBER OF CLOCK CYCLES
0:0 216 = 65,536
0:1 212 = 4,096
1:0 28 = 256
1:1 24 = 16
ISL29010
6FN6414.1
November 11, 2011
Control Register 01(hex)
The Read/Write control register has one function:
1. Range/Gain; Bits 3 and 2. The Full Scale Range can be
adjusted by an external resistor REXT and/or it can be
adjusted via I2C using th e Gain/Range function.
Gain/Range has four possible values, Range(k) where k
is 1 through 4. Table 8 lists the possible values of
Range(k) and the resulting FSR for some typical value
REXT resistors.
I2Sensor Data Register 04(hex) and 05(hex)
When the device is configured to output a signed 15-bit data,
the most significant byte is accessed at 04(hex), and the
least significa n t byte can be accessed at 05(hex ). Th e
sensor data register is refreshed after every integration
cycle.
Timer Data Register 06(hex) and 07(hex)
Note that the timer counter value is only available when
using the External Timing Mode. The 06(hex) and 07(hex)
are the LSB and MSB, respectively, of a 16-bit timer counter
value corresponding to the most recent sensor reading.
Each clock cycle increments the counter. At the end of each
integration period, the value of this counter is made available
over the I2C. This value can be used to eliminate noise
introduced by slight timing errors caused by imprecise
external timing. Microcontrollers, for example, often cannot
provide high-accuracy command-to-command timing , and
the timer counter value can be used to eliminate the
resulting noise.
Calculating Lux
The ISL29010’s output codes, DATA, are directly
proportional to lux.
The proportionality constant α is determined by the Full
Scale Range (FSR), and the n-bit ADC, which is user
defined in the command register. The proportionality
constant can also be viewed as the resolution; the smallest
lux measurement the device can measure is α in Equation 2.
Full-Scale Range (FSR) is determined by the software
programmable Range/Gain, Range(k), in the command
register and an external scaling resistor REXT, which is
referenced to 100kΩ.
The transfer function effectively for each timing mode
becomes:
INTERNAL TIMING MODE
EXTERNAL TIMING MODE
n = 3, 7, 11 , or 15. This is the number of clock cycles
programmed in the command regi ster.
Range(k) is the user defined range in the Gain/Range bit
in the command register.
REXT is an external scaling resistor hardw ired to the REXT
pin.
DATA is the output sensor reading in number of counts
available at the data register.
2n represents the maximum number of counts possible in
Internal Timing Mode. For the External Timing Mode, the
maximum number of counts is stored in the data register
named COUNTER.
COUNTER is the number of increments accrued between
integration time for External Timing Mode.
Gain/Range, Range(k)
The Gain/Range can be programme d in the control register
to give Range(k) determining the FSR. Note that Range(k) is
not the FSR (see Equation 3). Range (k) provides four
constants depending on programmed k that will be scaled by
REXT (see Table 8). Unlike REXT, Range(k) dynamically
adjusts the FSR. This function is especially useful when light
conditions are varying drastically while maintaining excellent
resolution.
TABLE 8. RANGE/GAIN TYPICAL FSR LUX RANGES
BITS
3:2 k RANGE(k)
FSR LUX
RANGE@
REXT = 100k
FSR LUX
RANGE@
REXT = 50k
FSR LUX
RANGE@
REXT = 500k
0:0 1 2,000 2,000 4,000 400
0:1 2 8,000 8,000 16,000 1,600
1:0 3 32,000 32,000 64,000 6,400
1:1 4 128,000 128,000 256,000 25,600
TABLE 9. DATA REGISTERS
ADDRESS
(hex) CONTENTS
04 Least-significant byte of most recent sensor reading.
05 Most-significant byte of most recent sensor reading.
06 Least-significant byte of timer counter value
corresponding to most recent sensor reading.
07 Most-significant byte of timer counter value
corresponding to most recent sensor reading.
EαDATA×=(EQ. 1)
α
FSR
2n
------------
=(EQ. 2)
(EQ. 3)
FSR Range k() 100kΩ
REXT
------------------
×=
(EQ. 4)
ERange k() 100kΩ
REXT
------------------
×
2n
---------------------------------------------------- DATA×=
(EQ. 5)
ERange k() 100kΩ
REXT
------------------
×
COUNTER
---------------------------------------------------- DATA×=
ISL29010
7FN6414.1
November 11, 2011
Number of Clock Cycles, n-bit ADC
The number of clock cycles determines “n” in the n-bit ADC; 2n
clock cycles is a n-bit ADC. n is programmable in the command
register in the width function. Depending on the application, a
good balance of speed and resolution has to be considered
when deciding for n. For fast and quick measurement, choose
the smallest n = 3. For maximum resolution without regard of
time, choose n = 15. Table 10 compares the trade-off between
integration time and resolution. See Equations 10 and 1 1 for the
relation between integration time and n. See Equation 3 for the
relation of n and resolution.
External Scaling Resistor REXT and fosc
The ISL29010 uses an external resistor REXT to fix its
internal oscillator frequency, fOSC. Consequently, REXT
determines the fOSC, integration time and the FSR of the
device. fOSC, a dual speed mode oscillator, is inversel y
proportional to REXT. Fo r use r simplicity, the proportionality
constant is referenced to fixed constants 100kΩ and
655kHz:
fOSC1 is oscillator frequency when Range1 or Range2 are
set. This is nominally 327kHz when REXT is 100kΩ.
fOSC2 is the oscillator frequency when Range3 or Range4
are set. This is nominally 655kHz when REXT is 100kΩ.
When the Range/Gain bits are set to Range1 or Range2,
fOSC runs at half speed compared to when Range/Gain bits
are set to Range3 and Range4.
The automatic fOSC adjustment feature allows significant
improvement of signal-to-noise ratio when detecting very low
lux signals.
Integration Time or Conversion Time
Integration time is the period during which the device’s
analog-to-digital ADC converter samples the photodiode
current signal for a lux measurement. Integration time, in
other words, is the time to complete the conversion of analog
photodiode current into a digital signal (number of counts).
Integration time affects the measurement resolution. For
better resolution, use a longer integration time. For short and
fast conversions use a shorter integration time .
The ISL29010 offers user flexibility in the integration time to
balance resolution, speed and noise rejection. Integration time
can be set internally or externally and can be programmed in
the command register 00(hex) Bit 5.
INTEGRATION TIME IN INTERNAL TIMING MODE
This timing mode is programmed in the command regi ster
00(hex) Bit 5. Most applications will be using this timing
mode. When using the Internal Timing Mode, fOSC and
n-bits resolution determine the integration time. tINT is a
function of the number of clock cycles and f OSC.
m = 4, 8, 12, and16. n is the number of bits of resolution.
2m therefore is the number of clock cycles. n can be
programmed at the command register 00(he x) Bit s 1 and 0.
Since fOSC is dual speed depending on the Gain/Range bit,
tINT is dual time. The integration time as a function of REXT
is shown in Equation 10:
tINT1 is the integration time when the device is configured
for Internal Timing Mode and Gain/Range is set to Range1
or Range2.
tINT2 is the integration time when the device is configured
for Internal Timing Mode and Gain/Range is set to Range3
or Range4.
T ABLE 10. RESOLUTION AND INTEGRA TION TIME
SELECTION
n
RANGE1
fOSC = 327kHz RANGE4
fOSC = 655kHz
tINT
(ms) RESOLUTION
LUX/COUNT tINT
(ms) RESOLUTION
(LUX/COUNT)
15 200 0.06 100 2
11 12.8 1.0 6.4 62.5
7 0.8 15.6 0.4 1,000
3 0.05 250 0.025 16,000
REXT = 100kΩ
(EQ. 6)
f
OSC11
2
---100kΩ
REXT
------------------ 655×kHz×=
(EQ. 7)
fOSC2100kΩ
REXT
------------------ 655×kHz=
(EQ. 8)
f
OSC11
2
---fOSC2()=
TABLE 11. INTEGRATION TIMES FOR TYPICAL REXT VALUES
REXT
(kΩ)
RANGE1
RANGE2 RANGE3
RANGE4
n = 15-BIT n = 11-BIT n = 11-BIT n = 3
50 100 6.4 3.2 0.013
100** 200 13 6.5 0.025
200 400 26 13 0.050
500 1000 64 32 0.125
*Integration time in milliseconds
**Recommended REXT resistor value
tINT 2m1
fosc
----------
×=(EQ. 9)
for Internal Timi ng Mode only
tINT12
mREXT
327kHz 100kΩ×
----------------------------------------------
×=(EQ. 10)
tINT22
mREXT
655kHz 100kΩ×
----------------------------------------------
×=(EQ. 11)
ISL29010
8FN6414.1
November 11, 2011
INTEGRATION TIME IN EXTERNAL TIMING MODE
This timing mode is programmed in the command register
00(hex) Bit 5. External Timing Mode is recommended when
integration time can be synchronized to an external signal
such as a PWM to eliminate noise.
To read the light count DATA output, the device needs three
sync_I2C commands to complete one measurement. The 1st
sync_I2C command starts the conversion of the dio de array 1.
The 2nd sync_I2C complete s the conversio n of diode array 1
and start s the con version of diode array 2. The 3rd sync_I2C
pules ends the conversion of diode array 2, output s the light
count DATA, and starts over again to commence con version
of diode array 1.
The integration time, tINT, is the sum of two identical time
intervals between the three sync pulse s. t INT is determined
by Equation 12:
where kOSC is the number of internal clock cycles obtained
from Timer data register and fOSC is the internal I2C
operating frequency.
The internal oscillator, fOSC, operates identically in both the
internal and external timing modes, with the same
dependence on REXT. However, in External Timing Mode,
the number of clock cycles per integration is no longer fixed
at 2n. The number of clock cycles varies with the chosen
integration time, an d is limited to 216 = 65,536. In order to
avoid erroneous lux readings the integration time must be
short enough not to allow an overflow in the counter register.
fOSC = 327kHz*100kΩ/REXT. When Range/Gain is set to
Range1 or Range2.
fOSC = 655kHz*100kΩ/REXT. When Range/Gain is set to
Range3 or Range4.
Noise Rejection
In general, integrating type ADC’s have excellent
noise-rejection characteristics for periodic noise sources
whose frequency is an integer multiple of the integration
time. For instance, a 60Hz AC unwanted signal’s sum from
0ms to k*16.66ms (k = 1,2...ki) is zero. Similarly, setting the
device’s integration time to be an integer multiple of the
periodic noise signal greatly improves the light sensor output
signal in the presence of noise.
Flat Window Lens Design
A window lens will surely limit the viewing angle of the
ISL29010. The window lens should be placed directly on top
of the device. The thickness of the lens should be kept at
minimum to minimize loss of power due to reflection and
also to minimize loss due to absorption of energy in the
plastic material. A thickness of t = 1mm is recommended for
a window lens design. The bigger the diameter of the
window lens, the wider the viewing angle is of the ISL29010.
Table 12 shows the recommended dimensions of the optical
window to ensure both 35° and 45° viewing angle. These
dimensions are based on a window lens thickness of 1.0mm
and a refractive index of 1.59.
Suggested PCB Footprint
It is important that the users check the “Surface Mount
Assembly Guidelines for Optical Dual FlatPack No Lead
(ODFN) Package” before starting ODFN product board
mounting.
http://www.intersil.com/data/tb/TB477.pdf
Layout Considerations
The ISL29010 is relatively insensitive to layout. Like other
I2C devices, it is intended to provide excellent performance
even in significantly noisy environments. There are only a
few considerations that will ensure best performance.
tINT kOSC
fOSC
---------------
=(EQ. 12)
tINT 65,535
fOSC
------------------
<(EQ. 13)
T ABLE 12. RECOMMENDED DIMENSIONS FOR A FLAT
WINDOW DESIGN
DTOTAL D1 DLENS @ 35
VIEWING ANGLE DLENS @ 45
VIEWING ANGLE
1.5 0.50 2.25 3.75
2.0 1.00 3.00 4.75
2.5 1.50 3.75 5.75
3.0 2.00 4.30 6.75
3.5 2.50 5.00 7.75
t = 1 Thickness of lens
D1 Distance between ISL29010 and inner edge of lens
DLENS Diameter of lens
DTOTAL Distance constraint between the ISL29010 and lens
outer edge
* All dimensions are in mm.
DLENS
∅
t
D1 DTOTAL
∅ = VIEWING ANGLE
WINDOW LENS
ISL29013
FIGURE 4. FLAT WINDOW LENS
E = DATA
215 x 2000
ISL29010
9FN6414.1
November 11, 2011
Route the supply and I2C traces as far as possible from all
sources of noise. Use two power-supply decoupling
capacitors, 4.7µF and 0.1µF, placed close to the device.
Typical Circuit
A typical application for the ISL29010 is shown in Figure 5.
The ISL29010’s I2C address is internally hardwired as
1000100. The device can be tied onto a system’s I2C bus
together with other I2C compliant devices.
Soldering Considerations
Convection heati ng is recommended for reflow soldering;
direct-infrared heating is not recommended. The plastic
ODFN package does not require a custom reflow soldering
profile, and is qualified to +260°C. A standard reflow
soldering profile with a +260°C maximum is recommended.
FIGURE 5. ISL29010 TYPICAL CIRCUIT
VDD
1
GND
2
REXT
3A04
SCL 5
SDA 6
ISL29010
R1
10k R2
10k
REXT
100kΩ
C2
0.1µF
C1
4.7µF
2.5V TO 3.3V
MICROCONTROLLER
SDA
SCL
I2C SLAVE_0 I2C SLAVE_1 I2C SLAVE_n
I2C MASTER
SCL
SDA
SCL
SDA
1.8V TO 5.5V
Typical Performance Curves (REXT = 100kΩ)
FIGURE 6. SPECTRAL RESPONSE FIGURE 7. RADIATION PATTERN
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
300 400 600 800 1.0k
WAVELENGTH (nm)
NORMALIZED RESPONSE
ISL29010 RESPONSE
1.1k
HUMAN EYE RESPONSE RADIATION PATTERN
LUMINOSITY
ANGLE
RELATIVE SENSITIVITY
90°
80°
70°
60°
50°
40°
30° 20° 10° 0° 10° 20° 30° 40°
50°
60°
70°
80°
90°
0.2 0.4 0.6 0.8 1.0
ISL29010
10 FN6414.1
November 11, 2011
FIGURE 8. SPECTRUM OF LIGHT SOURCES FOR
MEASUREMENT FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 10. OUTPUT CODE FOR 0 LUX vs SUPPLY VOLTAGE FIGURE 11. OUTPUT CODE vs SUPPLY VOLTAGE
FIGURE 12. OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE FIGURE 13. SUPPLY CURRENT vs TEMPERATURE
Typical Performance Curves (REXT = 100kΩ) (Continu ed)
0
0.2
0.4
0.6
0.8
1.0
1.2
300 400 500 600 700 800 900 1000 1100
WAVELENGTH (nm)
NORMALIZED LIGHT INTENSITY
SUN
HALOGEN
INCANDESCENT
FLUORESCENT
2.0 2.3 2.6 2.9 3.2 3.5 3.8
320
306
292
278
264
250
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (V)
TA = +27°C
5000 lux
200 lux
2.0 2.3 2.6 2.9 3.2 3.5
10
8
6
4
2
0
OUTPUT CODE (COUNTS)
SUPPLY VOLTAGE (V)
TA = +27°C
0 lux
3.8
RANGE 2
2.0 2.3 2.6 2.9 3.2 3.5 3.8
1.015
1.010
1.005
1.000
0.995
0.990
OUTPUT CODE RATIO
(% FROM 3V)
SUPPLY VOLTAGE (V)
TA = +27°C
5000 lux
200 lux
2.0 2.3 2.6 2.9 3.2 3.5
320.0
319.5
319.0
318.5
318.0
OSCILLATOR FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
TA = +27°C
3.8 -60 -20 20 60 100
315
305
295
285
275
265
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
VDD = 3V
200 lux
RANGE 1
5000 lux
RANGE 3
ISL29010
11 FN6414.1
November 11, 2011
FIGURE 14. OUTPUT CODE FOR 0 LUX vs TEMPERATURE FIGURE 15. OUTPUT CODE vs TEMPERATURE
FIGURE 16. OSCILLATOR FREQUENCY vs TEMPERATURE FIGURE 17. LIGHT SENSITIVITY vs LUX LEVEL
FIGURE 18. LIGHT SENSITIVITY vs LUX LEVEL FIGURE 19. LIGHT SENSITIVITY vs LUX LEVEL
Typical Performance Curves (REXT = 100kΩ) (Continued)
-60 -20 20 60
10
8
6
4
2
0
OUTPUT CODE (COUNTS)
TEMPERATURE (°C)
VDD = 3V
0 lux
RANGE 2
-60 -20 20 60 100
1.080
1.048
1.016
0.984
0.952
0.920
OUTPUT CODE RATIO
(% FROM +25°C)
TEMPERATURE (°C)
VDD = 3V
5000 lux
200 lux
RANGE 3
RANGE 1
-60 -20 20 60
330
329
328
327
326
325
OSCILLATOR FREQUENCY (kHz)
TEMPERATURE (°C)
VDD = 3V
100 0
2000
4000
6000
8000
10000
12000
14000
0 2k 4k 6k 8k 10k 12k 14k
LUX METER READING (LUX)
CALCULATED ALS READING (LUX)
TYPICAL OUTPUT LUX VARIATION
BETWEEN FOUR LIGHT SOURCES: +15%
FLUORESCENT
SUN
HALOGEN
INCANDESCENT
VDD = 3V
0
100
200
300
400
500
600
700
800
900
1000
0 100 200 300 400 500 600 700 800 900 1k
LUX METER READING (LUX)
CALCULATED ALS READING (LUX)
VDD = 3V
FLUORESCENT
INCANDESCENT
HALOGEN
0
10
20
30
40
50
60
70
80
90
100
0 102030405060708090100
LUX METER READING (LUX)
CALCULATED ALS READING (LUX)
VDD = 3V
FLUORESCENT
INCANDESCENT
HALOGEN
ISL29010
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6414.1
November 11, 2011
FIGURE 20. 6 LD ODFN SENSOR LOCATION OUTLINE
2.10mm
2.00mm
0.29mm
0.56mm
0.46mm
SENSOR OFFSET
1
2
3
6
5
4
ISL29010
13 FN6414.1
November 11, 2011
ISL29010
Package Outline Drawing
L6.2x2.1
6 LEAD OPTICAL DUAL FLAT NO-LEAD PLASTIC PACKAGE (ODFN)
Rev 3, 5/11
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
(4X) 0.10
INDEX AREA
PIN 1
ABPIN #1
B0.10 MAC
C
SEATING PLANE
BASE PLANE
0.08
0.10
SEE DETAIL "X"
C
C
0 . 00 MIN.
0 . 05 MAX.
0 . 2 REF
C5
1
6
6
2.10
2.00
2.10
2.50
(1.35)
(6x0.30)
0.65
(6x0.55)
(6x0.20)
(4x0.65)
1.30 REF1.35
0.65
0.65
6x0.35 ± 0.05
PACKAGE
6X 0.30±0.05
INDEX AREA
OUTLINE
4
MAX 0.75
