PRELIMINARY TECHNICAL DATA I2C, Nonvolatile Memory, Dual 64/256Position Digital potentiometers Preliminary Technical Data AD5251/AD5252 a FEATURES AD5251: Dual 64-Position Resolution AD5252: Dual 256-Position Resolution Nonvolatile Memory1 Maintains Wiper Settings Resistance Tolerance Stored In Nonvolatile Memory 1 k, 10 k, 50 k 100 k I2C Compatible Serial Interface Wiper Settings Read Back Linear Increment/Decrement Predefined Instructions +/-6dB Log taper Increment/Decrement Predefined Instructions Single Supply 2.7V to 5.5V Logic Operation Voltage 3V to 5V Power On Presets to EEMEM Settings with Refresh Time < 1ms Nonvolatile Memory Write Protection 100-Year Typical Data Retention TA = 55 oC Operating Temperature -40C to +125C TSSOP-14 APPLICATIONS Mechanical Potentiometer Replacement Low Resolution DAC Replacement Sensors Calibrations Electronics Level Settings RF Base Station Power Amp Bias Control Programmable Gain and Offset Control Programmable Attentuator Programmable Voltage to Current Conversion Programmable Power Supply Programmable Filters Line Impedance Matching A-and-B. This linearly changes the wiper-to-B terminal resistance (RWB) by one out of 64/256 positions of the AD5251/AD5252 endto-end resistance (RAB). For non-linear changes in wiper setting, a left/right shift command adjusts levels in 6dB steps which can be useful for sound and light alarm applications. The AD5251/AD5252 is available in the thin TSSOP-14 package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +125C. FUNCTIONAL BLOCK DIAGRAMS VDD RDAC1 VSS RDAC EEPROM DGND W1 6/8 SCL I2C SERIAL INTERFACE ADD0 DATA RDAC3 RDAC3 REGISTER 6/8 CONTROL COMMAND DECODE LOGIC ADD1 POWER ON RESET In the direct program mode a predetermined setting of the RDAC register can be loaded directly from the micro controller. Another key mode of operation allows the RDAC register to be refreshed with the setting previously stored in the EEMEM register. When changes are made to the RDAC register to establish a new wiper position, the value of the setting can be saved into the EEMEM by executing an EEMEM save operation. Once the settings are saved in the EEMEM register, these values will be transferred automatically to the RDAC register to set the wiper position at system power ON. Such operation is enabled by the internal preset strobe and the preset can also be accessed externally. ADDRESS DECODE LOGIC CONTROL LOGIC Notes 1: The terms Nonvolatile Memory and EEMEM are used interchangeably. 2: The terms digital potentiometer, VR, and RDAC are used interchangeably. The basic mode of adjustment is the increment and decrement from the present setting of the Wiper position setting (RDAC) register. An internal scratch pad RDAC register can be moved UP or DOWN, one step of the nominal resistance between terminals REV PrB 2 DEC 99 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 617/329-4700 A3 W3 B3 GENERAL DESCRIPTION The AD5251/AD5252 is a dual channel, digitally controlled variable resistor (VR) with resolutions of 1024 positions. This device performs the same electronic adjustment function as a potentiometer or variable resistor. The AD5251/AD5252's versatile programming via a Micro Controller allows multiple modes of operation and adjustment. A1 B1 WP SDA RDAC1 REGISTER Fax:617/326-8703 PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 ELECTRICAL CHARACTERISTICS 1k, 10k , 50k, 100k VERSIONS (VDD = +3V10% or +5V10% and VSS=0V, VA = +VDD, VB = 0V, -40C < TA < +125C unless otherwise noted.) Parameter Symbol Conditions Min Typ1 Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs Resistor Differential NL2 R-DNL RWB, VA=NC -1 1/4 +1 LSB Resistor Nonlinearity2 R-INL RWB, VA=NC -2 1/2 +2 LSB Nominal resistor tolerance Resistance Temperature Coefficent Wiper Resistance Wiper Resistance R RAB/T RW RW TA = 25C, VAB = VDD,Wiper (VW) = No connect VAB = VDD, Wiper (VW) = No Connect IW = 1 V/R, VDD = +5V IW = 1 V/R, VDD = +3V -30 30 % ppm/C X 50 200 100 DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution Integral Nonlinearity3 Differential Nonlinearity3 Voltage Divider Temperature Coefficent Full-Scale Error Zero-Scale Error N INL DNL VW/T VWFSE VWZSE AD5251/AD5252 Code = Half-scale Code = Full-scale Code = Zero-scale Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx VA,B,W CA,B CW f = 1 MHz, measured to GND, Code = Half-scale f = 1 MHz, measured to GND, Code = Half-scale Common-mode Leakage Current7 ICM VA = VB = VDD/2 Input Logic High Input Logic Low Output Logic High Output Logic High Output Logic Low Input Current VIH VIL VOH VOH VOL IIL with respect to GND with respect to GND RPULL-UP = 2.2K to +5V IOH = 40A, VLOGIC = +5V IOL = 1.6mA, VLOGIC = +5V VIN = 0V or VDD Input Capacitance5 CIL -2 -1 -3 0 1/2 1/4 X -1 +1 6/8 +2 +1 +0 +3 Bits LSB LSB ppm/C LSB LSB RESISTOR TERMINALS VSS VDD V pF pF 1 A 45 60 0.01 DIGITAL INPUTS & OUTPUTS 0.3*VDD 0.7*VDD 4.9 4 0.4 1 5 V V V V V A pF POWER SUPPLIES Single-Supply Power Range VDD VSS = 0V 2.7 5.5 V Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current Negative Supply Current VDD/VSS IDD IDD(PG) IDD(READ) ISS VSS = 0V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = 2.5V, VSS = -2.5V 2.2 2.7 10 10 V A mA A A Power Dissipation6 Power Supply Sensitivity PDISS PSS VIH = VDD or VIL = GND VDD = +5V 10% 0.05 0.01 mW %/% Bandwidth -3dB Total Harmonic Distortion VW Settling Time BW THDW tS RAB = 1k/10k/50k/100k VA =1Vrms, VB = 0V, f=1KHz VA= VDD, VB=0V, 50% of final value TBD 0.003 kHz % Resistor Noise Voltage eN_WB 1k/10k/50k/100k RWB = 5K, f = 1KHz TBD 9 s nVHz Crosstalk CT VA = VDD, VB = 0V, Measue VW with adjacent VR making full scale change -65 dB 2 15 650 0.002 DYNAMIC CHARACTERISTICS5, 7 REV PrB 2 DEC 99 2 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 ELECTRICAL CHARACTERISTICS 1k, 10k , 50k, 100k VERSIONS (VDD = +3V10% to +5V10% and VSS=0V, VA = +VDD, VB = 0V, -40C < TA < +125C unless otherwise noted.) Parameter Symbol Conditions INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5,8) SCL Clock Frequency fSCL tBUF Bus free time between STOP & START t1 tHD;STA Hold Time (repeated START) t2 After this period the first clock pulse is generated tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time For START Condition t5 tHD;DAT Data Hold Time t6 tSU;DAT Data Setup Time t7 tF Fall Time of both SDA & SCL signals t8 tR Rise Time of both SDA & SCL signals t9 tSU;STO Setup time for STOP Condition t10 Store to Nonvolatile EEMEM Save Time9 t12 Applies to Command 2H, 3H RDY Rise to CS Fall t15 Preset Pulse Width tPR Min 0 1.3 0.6 1.3 0.6 0.6 0 100 Typ1 Max Units 400 kHz s s s s s s ns ns ns s ms ns ns 0.9 300 300 0.6 25 50 NOTES: 1. 2. 3. 4 5. 6. 7. 8. 9. Typicals represent average readings at +25C and VDD = +5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. IW = VDD/R for both VDD=+3V or VDD=+5V. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of 1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit. Resistor terminals A,B,W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. PDISS is calculated from (IDD x VDD=+5V). All dynamic characteristics use VDD = +5V. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using both VDD = +3V or +5V. Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms REV PrB 2 DEC 99 3 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 Timing Diagram t8 SDA t1 t8 t6 t9 SCL t2 P t3 S t4 t5 Sr t7 P t10 Figure 1. Timing Diagram Data of AD5251/AD5252 is accepted from the I2C bus in the following serial format: S 0 1 0 1 1 A A R/ A I7 I6 I5 I4 I3 I2 I1 I0 A D D D D D D D D A P 7 6 5 4 3 2 1 0 D D W D D 1 0 Slave Address Byte Instruction Byte Data Byte Where: S = Start Condition P = Stop Condition A = Acknowledge X = Don't Care ADD1, ADD0 = Package pin programmable address bits R/W= Read Enable at High and Write Enable at Low I7 - I0 = Instruction bits D5 - D0 = 6 Data Bits. D7 and D6 = X (AD5251) D7 - D0 = 8 Data Bits (AD5252) S LA VE AD D RE SS AN D R/W B YTE SDA AD 6 MS B AD 5 AD 0 IN STR U C TION BY TE R /W L SB A/B AC K M SB AM 0 RS D A TA B YTE SD L SB D7 A CK M SB D6 D1 D0 LS B A CK SCL S TAR T C o nd i tio n ST OP C o nd i ti o n Figure 2.Complete Serial Transmission REV PrB 2 DEC 99 4 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 AD5251/AD5252 PIN CONFIGURATION Absolute Maximum Rating (TA = +25C, unless otherwise noted) VDD to GND ..............................................................-0.3, +7V VSS to GND ................................................................. 0V, -7V VDD to VSS .........................................................................+7V VA, VB, VW to GND..................................................VSS, VDD AX - BX, AX - WX, BX - WX Pulse .............................................................20mA Continuous......................................................5mA Digital Inputs & Output Voltage to GND................... 0V, +7V Operating Temperature Range......................... -40C to +85C Maximum Junction Temperature (TJ MAX)...................+150C Storage Temperature...................................... -65C to +150C Lead Temperature (Soldering, 10 sec)..........................+300C Thermal Resistance JA, TSSOP-14................................................... XXXC/W Package Power Dissipation = (TJMAX - TA) / JA Ordering Guide Model Step RAB (k) Temp Range (oC) AD5251BRU1 64 1 -40/+125 AD5251BRU10 64 10 -40/+125 AD5251BRU50 64 50 -40/+125 AD5251BRU100 64 100 -40/+125 AD5252BRU1 256 1 -40/+125 AD5252BRU10 256 10 -40/+125 AD5252BRU50 256 50 -40/+125 AD5252BRU100 256 100 -40/+125 The AD5251/AD5252 contain x,xxx transistors. Die size: x' mil x y' mil, z' sq. mil Package Descripti on TSSOP14 TSSOP14 TSSOP14 TSSOP14 TSSOP14 TSSOP14 TSSOP14 TSSOP14 Package Option RU-14 RU-14 # RU-14 RU-14 W3 19 B3 WP 3 18 A3 W1 4 17 ADD1 B1 5 16 DGND A1 6 15 SCL SDA 7 14 VSS Name Description Positive Power Supply Pin 1 VDD 2 ADD0 I2C Device Address 0 3 WP Write Protect, Active Logic Low 4 W1 Wiper terminal of RDAC1 (1st Channel. ADD0=0 ADD1 = 1) 5 B1 B terminal of RDAC1 (1st Channel. ADD0=0, ADD1 =1) 6 A1 A terminal of RDAC1 (1st Channel. ADD0=0, ADD1=1) 7 SDA Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. 8 VSS Negative Supply. Connect to zero volt for single supply 9 SCL Serial Input Register clock pin. Shifts in one bit at a time on positive clock edges. 10 DGND Digital Ground. Connect to System Analog Ground at a Single Point RU-14 RU-14 20 AD5251/AD5252 PIN FUNCTION DESCRIPTION RU-14 RU-14 VDD 1 ADD0 2 11 ADD1 I2C Device Address 1 12 A3 A terminal of RDAC3 (2nd Channel. ADD0=1, ADD1=1) 13 B3 B terminal of RDAC3 (2nd Channel. ADD0=1, ADD1=1) 14 W3 Wiper terminal of RDAC3(2nd Channel. ADD0=1, ADD1=1) REV PrB 2 DEC 99 5 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 OPERATIONAL OVERVIEW The AD5251/AD5252 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSS<VTERM<VDD. The basic voltage range is limited to a VDD VSS<5.5V. Control of the digital potentiometer allows both scratch pad register (RDAC register) changes to be made, as well as 100,000 times of nonvolatile electrically erasable memory (EEMEM) register operations. The EEMEM update process takes approximately 20.2ms, during this time the shift register is locked preventing any changes from taking place. The EEMEM retention is designed to last 10 years without refresh. The scratch pad register can be changed incrementally by using the software controlled Increment/Decrement instruction or the Shift Left/Right instruction command. Alternately the scratch pad register can be programmed with any position value using the standard I2C serial interface mode by loading the representative data word. The scratch pad register can be loaded with the current contents of the nonvolatile EEMEM register under program control. At system power ON, the default value of the scratch pad memory is the value previously saved in the EEMEM register. The factory EEMEM preset values are mid-scale 32/128 for AD5251/AD5252 respectively. The serial input data register uses a 32-bit slave address/instruction/data WORD. SERIAL DATA INTERFACE The AD5251/AD5252 employs a two-wire I2C serial interface requiring only two I/O lines of a standard microprocessor port. Key features of this interface include: * Read & Write capability to all registers * Direct parallel refresh of all RDAC wiper registers from corresponding EEMEM registers * Increment & Decrement instructions for each RDAC wiper register * Left & right Bit Shift of all RDAC wiper registers to achieve 6dB level changes * Permanent storage of the present scratch pad RDAC register values into the corresponding EEMEM register * EEMEM Write Protect Figure 1 shows the timing diagram for signals on the wire bus. The 2-wire bus can have several devices attached in addition to the AD5251/AD5252. The two bus lines (SDA and SCL) must be high when the bus is not in use. When in use, the port bits are toggled to generate the appropriate signals for SDA and SCL. For I2C applications, two pull up resistors are required at both the SDA and SCL pins to VDD. The AD5251/AD5252 can operate SCL of up to 400kHz. A master device sends information to the AD5251/AD5252 by transmitting the AD5251/AD5252's address over the bus and then transmitting the desired information. Each transmission consists of a START condition, the AD5251/AD5252's programmable slave address, an instruction byte, 2 data bytes consist of 10 data bits, and a STOP condition. The address byte, instruction byte, and data bytes are transmitted between the START and STOP conditions. The state of SDA is allowed to change only if SCL is low, with the exceptions at START and STOP conditions. SDA must remain stable and is sampled ( read or write depends upon the state of R/W) when SCL is high. Data is transmitted in 8-bit bytes. The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 3). When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. SDA SCL START Condition STOP Condition Figure 3.START and STOP Conditions The Slave Address The AD5251/AD5252's slave address is seven bits long (Figure 4). The first five bits (MSBs) of the slave address have been factory programmed to 01011. The state of the AD5251/AD5252 inputs AD0 and AD1 determine the final two bits of the 7-bit slave address, These input pins may be connected to VDD or GND, or may be actively driven by TTL or CMOS logic levels. There are four possible addresses for the AD5251/AD5252, and therefore a maximum of four such devices may be on the bus at the same time. The eighth bit (LSB) in the slave address byte is for read write purpose. Active high allows data to be read back from the input register. Active low allows data to be written to the input register. The AD5251/AD5252 watches the bus continuously, waiting for a START condition followed by its slave address. When it recognizes its slave address, it is ready to accept data. SLAVE ADDRESS ANDR/WBYTE SDA 0 1 MSB 0 1 1 AD1 AD0 R/W LSB ACK SCL Figure 4. Slave Address and R/W Byte The Instruction Byte (To be determined) The Data Bytes (To be determined) REV PrB 2 DEC 99 6 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 Table 1. AD5251/AD5252 Instruction/Operation Truth Table Slave Address & R/W Byte B31 ........................................ B24 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 Instruction Byte B23 ....................................... B16 I7 I6 I5 I4 I3 I2 I1 I0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Data Byte B7 ......... B0 D7 ......... D0 X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X X ........... X Operation NOTES: 1. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile EEMEM register. 2. The increment, decrement and shift commands ignore the contents of the shift register Data Byte. REV PrB 2 DEC 99 7 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 Detail Potentiometer Operation The actual structure of the RDAC is designed to emulate the performance of a mechanical potentiometer. The RDAC contains a string of connected resistor segments, with an array of analog switches that act as the wiper connection to several points along the resistor array. The number of points is the resolution of the device. For example, the AD5251/AD5252 emulates 64/256 connection points with 64/256 equal resistance, Rs, allowing it to provide better than 1.5%/0.4% set-ability resolution. Figure 5 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC. The switches SWA and SWB will always be ON while one of the switches SW(0) to SW(2N-1) will be ON one at a time depends upon the resistance step decoded from the data. The total resistance of the active switches makes up the wiper resistance, RW. SW A AX RDAC RS WX N SW(2 -2) REGISTER & DECODER RS RS SW(1 ) SW(0 ) N RS = R AB /2 DIGITAL CIRCUITRY OMITTED FOR CLARITY SW B The general equation, which determines the digitally programmed output resistance between Wx and Bx, is: RWB(Dx) = (Dx/2N)*RAB + RW eqn. 1 Where N is the resolution of the VR, Dx is the data contained in the RDACx latch, and RAB is the nominal end-to-end resistance. Since N=6/8-bit and RW=50 for AD5251/AD5252, eqn. 1 becomes: RWB(Dx) = (Dx/64)*RAB + 50 for AD5251 eqn. 2 RWB(Dx) = (Dx/256)*RAB + 50 for AD5252 eqn. 3 SW(2 N -1) WIPER 156+50)] for data 01H. The third connection is the next tap point representing RWB=312+50= 362 for data 02H. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB=9893. See figure 6 for a simplified diagram of the equivalent RDAC circuit. BX Figure 5. Equivalent RDAC structure PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between terminals A and B are available with values of 1k, 10k, 50k, and 100k. The final digits of the part number determine the nominal resistance value, e.g., 1k = 1, 10k = 10, 50k = 50, and 100k = 100. The nominal resistance (RAB) of the AD5251/AD5252 VR has 64/256 contact points accessed by the wiper terminal, plus the B terminal contact. The 6/8-bit data word in the RDAC latch is decoded to select one of the 64/256 possible settings. The wiper's first connection starts at the B terminal for data 00H. This B-terminal connection has a wiper contact resistance, RW of 50, regardless of what the nominal resistance is. The second connection (AD5251 10k part) is the first tap point where RWB=206 [RWB =RAB/64 + RW = For example, when VB = 0V and A-terminal is open circuit, the following output resistance values will be set by the corresponding RDAC latch codes (applies to AD5251 RAB=10k potentiometers): Dx (DEC) RWB () Output State 63 32 1 0 9893 5050 206 50 Full-Scale Mid-Scale 1 LSB Zero-Scale (Wiper contact resistance) Note that in the zero-scale condition a finite wiper resistance of 50 is present. Care should be taken to limit the current conduction between W and B in this state to a no more than 5mA continuous or 20mA pulse to avoid degradation or possible destruction of the internal switch contact. Figure 6. Symmetrical RDAC Operation REV PrB 2 DEC 99 8 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 Like the mechanical potentiometer the RDAC replaces, the AD5251/AD5252 part is totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled resistance RWA. Figure 6 shows the symmetrical programmability of the various terminal connections. When these terminals are used, the B-terminal should be tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general equation for this operation is: ESD PROTECTION CIRCUITS VDD INPUTS LOGIC PINS RWA(Dx) = [(64-Dx)/64]*RAB + 50 (AD5251) eqn. 4 RWA(Dx) = [(256-Dx)/256]*RAB + 50 (AD5252) eqn. 5 For example, when VA = 0V and B-terminal is tied to the wiper W the following output resistance values will be set by the corresponding RDAC latch codes (applies to AD5251 RAB=10k potentiometers): GND Figure 7A. Equivalent Digital Input ESD Protection VDD OUTPUTS Dx (DEC) RWA () Output State 63 32 1 0 206 5050 9893 10050 Full-Scale Mid-Scale 1 LSB Zero-Scale O1 & O2 PINS GND The typical distribution of RAB from channel-to-channel matches of less than 1% within the same package. On the other hand, device to device matching is process lot dependent such that a maximum of 30% variation is possible. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting A-terminal to +5V and B-terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than +5V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 2N position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW(Dx) = (Dx/64) * VAB + VB (AD5251) eqn. 6 VW(Dx) = (Dx/256) * VAB + VB (AD5252) eqn. 7 Figure 7B. Equivalent Digital Output ESD Protection Figure 7 shows the equivalent ESD protection circuit for digital pins. Figure 8 shows the equivalent analog-terminal protection circuit for the variable resistors. POTENTIOMETER TERMINALS A, B, W PINS VSS Figure 8. Equivalent VR-Terminal ESD Protection TEST CIRCUITS Figures 9 to 17 define the test conditions used in the product specification's table. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors and not the absolute value. Therefore, the drift reduces to 50ppm/C. REV PrB 2 DEC 99 9 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 Figure 9. Potentiometer Divider Nonlinearity error test circuit (INL, DNL) Figure 14. Non-Inverting Gain test circuit Figure 10. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 15. Gain Vs Frequency test circuit Figure 11. Wiper Resistance test Circuit Figure 16. Incremental ON Resistance Test Circuit Figure 12. Power supply sensitivity test circuit (PSS, PSSR) Figure 17. Common Mode Leakage current test circuit Figure 13. Inverting Gain test Circuit Figure 18. Analog Crosstalk Test Circuit REV PrB 2 DEC 99 10 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5251/AD5252 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) REV PrB 2 DEC 99 11 Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com