PRELIMINARY TECHNICAL DATA
a
I2C, Nonvolatile Memory, Dual 64/256-
Position Digital potentiometers
AD5251/AD5252
REV PrB 2 DEC 99
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use; nor for any infringements of patents
or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 617/329-4700 Fax:617/326-8703
FEATURES
AD5251: Dual 64-Position Resolution
AD5252: Dual 256-Position Resolution
Nonvolatile Memory1 Maintains Wiper Settings
Resistance Tolerance Stored In Nonvolatile Memory
1 kΩ, 10 kΩ, 50 kΩ 100 kΩ
I2C Compatible Serial Interface
Wiper Settings Read Back
Linear Increment/Decrement Predefined Instructions
+/-6dB Log taper Increment/Decrement Predefined Instructions
Single Supply 2.7V to 5.5V
Logic Operation Voltage 3V to 5V
Power On Presets to EEMEM Settings with Refresh Time < 1ms
Nonvolatile Memory Write Protection
100-Year Typical Data Retention TA = 55 oC
Operating Temperature -40°C to +125°C
TSSOP-14
APPLICATIONS
Mechanical Potentiometer Replacement
Low Resolution DAC Replacement
Sensors Calibrations
Electronics Level Settings
RF Base Station Power Amp Bias Control
Programmable Gain and Offset Control
Programmable Attentuator
Programmable Voltage to Current Conversion
Programmable Power Supply
Programmable Filters
Line Impedance Matching
GENERAL DESCRIPTION
The AD5251/AD5252 is a dual channel, digitally controlled
variable resistor (VR) with resolutions of 1024 positions. This
device performs the same electronic adjustment function as a
potentiometer or variable resistor. The AD5251/AD5252’s versatile
programming via a Micro Controller allows multiple modes of
operation and adjustment.
In the direct program mode a predetermined setting of the RDAC
register can be loaded directly from the micro controller. Another
key mode of operation allows the RDAC register to be refreshed
with the setting previously stored in the EEMEM register. When
changes are made to the RDAC register to establish a new wiper
position, the value of the setting can be saved into the EEMEM by
executing an EEMEM save operation. Once the settings are saved
in the EEMEM register, these values will be transferred
automatically to the RDAC register to set the wiper position at
system power ON. Such operation is enabled by the internal preset
strobe and the preset can also be accessed externally.
The basic mode of adjustment is the increment and decrement from
the present setting of the Wiper position setting (RDAC) register.
An internal scratch pad RDAC register can be moved UP or
DOWN, one step of the nominal resistance between terminals
A-and-B. This linearly changes the wiper-to-B terminal resistance
(RWB) by one out of 64/256 positions of the AD5251/AD5252 end-
to-end resistance (RAB). For non-linear changes in wiper setting, a
left/right shift command adjusts levels in 6dB steps which can be
useful for sound and light alarm applications.
The AD5251/AD5252 is available in the thin TSSOP-14 package.
All parts are guaranteed to operate over the extended industrial
temperature range of -40°C to +125°C.
FUNCTIONAL BLOCK DIAGRAMS
DATA
CONTROL
RDAC EEPROM
COMMAND DECODE LOGIC
ADDRESS DECODE LOGIC
CONTROL LOGIC
RDAC1
REGISTER
A1
W1
B1
RDAC1
RDAC3
REGISTER
A3
W3
B3
RDAC3
SCL
SDA I2C
SERIAL
INTERFACE
ADD0
ADD1
VDD
VSS
6/8
POWER
ON RESET
6/8
DGND
W
P
Notes
1: The terms Nonvolatile Memory and EEMEM are used interchangeably.
2: The terms digital potentiometer, VR, and RDAC are used
interchangeably.
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 2
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS 1k, 10k , 50k, 100kΩ VERSIONS (VDD = +3V±10% or +5V±10% and
VSS=0V, VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)
Parameter Symbol Conditions Min Typ1 Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL2 R-DNL RWB, VA=NC -1 ±1/4 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA=NC -2 ±1/2 +2 LSB
Nominal resistor tolerance ∆R TA = 25°C, VAB = VDD,Wiper (VW) = No connect -30 30 %
Resistance Temperature Coefficent RAB/∆T VAB = VDD, Wiper (VW) = No Connect X ppm/°C
Wiper Resistance RW I
W = 1 V/R, VDD = +5V 50 100 Ω
Wiper Resistance RW I
W = 1 V/R, VDD = +3V 200 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution N AD5251/AD5252 6/8 Bits
Integral Nonlinearity3 INL –2 ±1/2 +2 LSB
Differential Nonlinearity3 DNL –1 ±1/4 +1 LSB
Voltage Divider Temperature Coefficent ∆VW/∆T Code = Half-scale X ppm/°C
Full-Scale Error VWFSE Code = Full-scale –3 -1 +0 LSB
Zero-Scale Error VWZSE Code = Zero-scale 0 +1 +3 LSB
RESISTOR TERMINALS
Voltage Range4 V
A,B,W V
SS V
DD V
Capacitance5 Ax, Bx CA,B f = 1 MHz, measured to GND, Code = Half-scale 45 pF
Capacitance5 Wx CW f = 1 MHz, measured to GND, Code = Half-scale 60 pF
Common-mode Leakage Current7 I
CM V
A = VB = VDD/2 0.01 1 µA
DIGITAL INPUTS & OUTPUTS
Input Logic High VIH with respect to GND 0.3•VDD V
Input Logic Low VIL with respect to GND 0.7•VDD V
Output Logic High VOH R
PULL-UP = 2.2KΩ to +5V 4.9 V
Output Logic High VOH IOH = 40µA, VLOGIC = +5V 4 V
Output Logic Low VOL I
OL = 1.6mA, VLOGIC = +5V 0.4 V
Input Current IIL V
IN = 0V or VDD ±1 µA
Input Capacitance5 C
IL 5 pF
POWER SUPPLIES
Single-Supply Power Range VDD V
SS = 0V 2.7 5.5 V
Dual-Supply Power Range VDD/VSS V
SS = 0V ±2.2 ±2.7 V
Positive Supply Current IDD V
IH = VDD or VIL = GND 2 10 µA
Programming Mode Current IDD(PG) V
IH = VDD or VIL = GND 15 mA
Read Mode Current IDD(READ) V
IH = VDD or VIL = GND 650 µA
Negative Supply Current ISS V
IH = VDD or VIL = GND, VDD = 2.5V, VSS = -2.5V 10 µA
Power Dissipation6 P
DISS V
IH = VDD or VIL = GND 0.05 mW
Power Supply Sensitivity PSS ∆VDD = +5V ±10% 0.002 0.01 %/%
DYNAMIC CHARACTERISTICS5, 7
Bandwidth –3dB BW RAB = 1k/10k/50k/100kΩ TBD kHz
Total Harmonic Distortion THDW V
A =1Vrms, VB = 0V, f=1KHz 0.003 %
VW Settling Time tS V
A= VDD, VB=0V, 50% of final value
1k/10k/50k/100k TBD µs
Resistor Noise Voltage eN_WB R
WB = 5KΩ, f = 1KHz 9 nV√Hz
Crosstalk CT V
A = VDD, VB = 0V, Measue VW with adjacent
VR making full scale change -65 dB
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 3
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS 1k, 10k , 50k, 100kΩ VERSIONS (VDD = +3V±10% to +5V±10% and
VSS=0V, VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)
Parameter Symbol Conditions Min Typ1 Max Units
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5,8)
SCL Clock Frequency fSCL 0 400 kHz
tBUF Bus free time between STOP & START t
1 1.3 µs
tHD;STA Hold Time (repeated START) t2 After this period the first clock pulse is generated 0.6 µs
tLOW Low Period of SCL Clock t3 1.3 µs
tHIGH High Period of SCL Clock t4 0.6 µs
tSU;STA Setup Time For START Condition t5 0.6 µs
tHD;DAT Data Hold Time t6 0 0.9 µs
tSU;DAT Data Setup Time t7 100 ns
tF Fall Time of both SDA & SCL signals t8 300 ns
tR Rise Time of both SDA & SCL signals t9 300 ns
tSU;STO Setup time for STOP Condition t10 0.6 µs
Store to Nonvolatile EEMEM Save Time9 t
12 Applies to Command 2H, 3H 25 ms
RDY Rise to CS Fall t15 ns
Preset Pulse Width tPR 50 ns
NOTES:
1. Typicals represent average readings at +25°C and VDD = +5V.
2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. IW = VDD/R for both VDD=+3V or VDD=+5V.
3. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.
4 Resistor terminals A,B,W have no limitations on polarity with respect to each other.
5. Guaranteed by design and not subject to production test.
6. PDISS is calculated from (IDD x VDD=+5V).
7. All dynamic characteristics use VDD = +5V.
8. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching
characteristics are measured using both VDD = +3V or +5V.
9. Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 4
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Timing Diagram
t
4
SDA
SCL
PS Sr P
t
1
t
2
t
3
t
5
t
6
t
7
t
8
t
8
t
9
t
10
Figure 1. Timing Diagram
Data of AD5251/AD5252 is accepted from the I2C bus in the following serial format:
S 0 1 0 1 1 A
D
D
1
A
D
D
0
R/
W
A I7 I6 I5 I4 I3 I2 I1 I0 A D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
AP
Slave Address Byte Instruction Byte Data Byte
Where:
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
ADD1, ADD0 = Package pin programmable address bits
R/W= Read Enable at High and Write Enable at Low
I7 – I0 = Instruction bits
D5 - D0 = 6 Data Bits. D7 and D6 = X (AD5251)
D7 - D0 = 8 Data Bits (AD5252)
Figure 2.Complete Serial Transmission
SCL
SDA
SLAVE ADDRESS AND
R/WBYTE
MS B L SB AC K
START Condition
INSTRUCTION BYTE
LSBMSB ACK
ST OP Condition
LSBMSB ACK
DATA B YTE
D7 D6 D1 D0A/B AM 0 RS SDAD0 R/WAD 6 AD 5
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 5
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Absolute Maximum Rating (TA = +25°C, unless
otherwise noted)
VDD to GND..............................................................-0.3, +7V
VSS to GND .................................................................0V, -7V
VDD to VSS .........................................................................+7V
VA, VB, VW to GND..................................................VSS, VDD
AX – BX, AX – WX, BX – WX
Pulse .............................................................±20mA
Continuous......................................................±5mA
Digital Inputs & Output Voltage to GND................... 0V, +7V
Operating Temperature Range.........................-40°C to +85°C
Maximum Junction Temperature (TJ MAX)...................+150°C
Storage Temperature......................................-65°C to +150°C
Lead Temperature (Soldering, 10 sec)..........................+300°C
Thermal Resistance θJA,
TSSOP-14................................................... XXX°C/W
Package Power Dissipation = (TJMAX - TA) / θJA
Ordering Guide
Model Step RAB
(kΩ)
Temp
Range (oC)
Package
Descripti
on
Package
Option
AD5251BRU1 64 1 -40/+125 TSSOP-
14
RU-14
AD5251BRU10 64 10 -40/+125 TSSOP-
14
RU-14
AD5251BRU50 64 50 -40/+125 TSSOP-
14
RU-14
AD5251BRU100 64 100 -40/+125 TSSOP-
14
RU-14
AD5252BRU1 256 1 -40/+125 TSSOP-
14
RU-14
AD5252BRU10 256 10 -40/+125 TSSOP-
14
RU-14
AD5252BRU50 256 50 -40/+125 TSSOP-
14
RU-14
AD5252BRU100 256 100 -40/+125 TSSOP-
14
RU-14
The AD5251/AD5252 contain x,xxx transistors.
Die size: x' mil x y' mil, z' sq. mil
AD5251/AD5252 PIN CONFIGURATION
V
DD
ADD0
WP
W1
B1
A1
SD
A
W3
B3
A3
ADD1
DGND
SCL
VSS
20
19
18
17
16
15
14
1
2
3
4
5
6
7
AD5251/AD5252 PIN FUNCTION
DESCRIPTION
# Name Description
1 VDD Positive Power Supply Pin
2 ADD0 I2C Device Address 0
3 WP Write Protect, Active Logic Low
4 W1 Wiper terminal of RDAC1 (1st Channel. ADD0=0
ADD1 = 1)
5 B1 B terminal of RDAC1 (1st Channel. ADD0=0, ADD1
=1)
6 A1 A terminal of RDAC1 (1st Channel. ADD0=0,
ADD1=1)
7 SDA Serial Data Input Pin. Shifts in one bit at a time on
positive clock CLK edges. MSB loaded first.
8 VSS Negative Supply. Connect to zero volt for single
supply
9 SCL Serial Input Register clock pin. Shifts in one bit at a
time on positive clock edges.
10 DGND Digital Ground. Connect to System Analog Ground
at a Single Point
11 ADD1 I2C Device Address 1
12 A3 A terminal of RDAC3 (2nd Channel. ADD0=1,
ADD1=1)
13 B3 B terminal of RDAC3 (2nd Channel. ADD0=1,
ADD1=1)
14 W3 Wiper terminal of RDAC3(2nd Channel. ADD0=1,
ADD1=1)
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 6
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
OPERATIONAL OVERVIEW
The AD5251/AD5252 digital potentiometer is designed to
operate as a true variable resistor replacement device for analog
signals that remain within the terminal voltage range of
VSS<VTERM<VDD. The basic voltage range is limited to a VDD -
VSS<5.5V. Control of the digital potentiometer allows both
scratch pad register (RDAC register) changes to be made, as
well as 100,000 times of nonvolatile electrically erasable
memory (EEMEM) register operations. The EEMEM update
process takes approximately 20.2ms, during this time the shift
register is locked preventing any changes from taking place.
The EEMEM retention is designed to last 10 years without
refresh. The scratch pad register can be changed incrementally
by using the software controlled Increment/Decrement
instruction or the Shift Left/Right instruction command.
Alternately the scratch pad register can be programmed with
any position value using the standard I2C serial interface mode
by loading the representative data word. The scratch pad
register can be loaded with the current contents of the
nonvolatile EEMEM register under program control. At system
power ON, the default value of the scratch pad memory is the
value previously saved in the EEMEM register. The factory
EEMEM preset values are mid-scale 32/128 for
AD5251/AD5252 respectively.
The serial input data register uses a 32-bit slave
address/instruction/data WORD.
SERIAL DATA INTERFACE
The AD5251/AD5252 employs a two-wire I2C serial interface
requiring only two I/O lines of a standard microprocessor port.
Key features of this interface include:
• Read & Write capability to all registers
• Direct parallel refresh of all RDAC wiper registers from
corresponding EEMEM registers
• Increment & Decrement instructions for each RDAC wiper
register
• Left & right Bit Shift of all RDAC wiper registers to
achieve 6dB level changes
• Permanent storage of the present scratch pad RDAC
register values into the corresponding EEMEM register
• EEMEM Write Protect
Figure 1 shows the timing diagram for signals on the wire bus.
The 2-wire bus can have several devices attached in addition to
the AD5251/AD5252. The two bus lines (SDA and SCL) must
be high when the bus is not in use. When in use, the port bits are
toggled to generate the appropriate signals for SDA and SCL.
For I2C applications, two pull up resistors are required at both
the SDA and SCL pins to VDD.
The AD5251/AD5252 can operate SCL of up to 400kHz. A
master device sends information to the AD5251/AD5252 by
transmitting the AD5251/AD5252’s address over the bus and
then transmitting the desired information. Each transmission
consists of a START condition, the AD5251/AD5252’s
programmable slave address, an instruction byte, 2 data bytes
consist of 10 data bits, and a STOP condition.
The address byte, instruction byte, and data bytes are
transmitted between the START and STOP conditions. The state
of SDA is allowed to change only if SCL is low, with the
exceptions at START and STOP conditions. SDA must remain
stable and is sampled ( read or write depends upon the state of
R/W) when SCL is high. Data is transmitted in 8-bit bytes.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with a
START condition by transitioning SDA from high to low while
SCL is high (Figure 3). When the master has finished
communicating with the slave, it issues a STOP condition by
transitioning SDA from low to high while SCL is high. The bus
is then free for another transmission.
Figure 3.START and STOP Conditions
The Slave Address
The AD5251/AD5252’s slave address is seven bits long (Figure
4). The first five bits (MSBs) of the slave address have been
factory programmed to 01011. The state of the
AD5251/AD5252 inputs AD0 and AD1 determine the final two
bits of the 7-bit slave address, These input pins may be
connected to VDD or GND, or may be actively driven by TTL
or CMOS logic levels. There are four possible addresses for the
AD5251/AD5252, and therefore a maximum of four such
devices may be on the bus at the same time. The eighth bit
(LSB) in the slave address byte is for read write purpose. Active
high allows data to be read back from the input register. Active
low allows data to be written to the input register. The
AD5251/AD5252 watches the bus continuously, waiting for a
START condition followed by its slave address. When it
recognizes its slave address, it is ready to accept data.
Figure 4. Slave Address and R/W Byte
The Instruction Byte
(To be determined)
The Data Bytes
(To be determined)
SCL
SDA
START Condition
STOP Condition
SCL
SDA
LSBMSB ACK
AD0
R/W
AD1
10011
SLAVE ADDRESS AND R/W BYTE
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 7
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Table 1. AD5251/AD5252 Instruction/Operation Truth Table
Slave Address & R/W Byte Instruction Byte Data Byte Operation
B31 …………………………………. B24 B23 ………………………………… B16 B7 ……… B0
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W I7 I6 I5 I4 I3 I2 I1 I0 D7 ……… D0
0 1 0 1 1 0 0 0 0 X ……….. X
0 1 0 1 1 0 0 1 0 X ……….. X
0 1 0 1 1 0 0 0 1 X ……….. X
0 1 0 1 1 0 0 1 1 X ……….. X
0 1 0 1 1 0 0 0 0 X ……….. X
0 1 0 1 1 0 0 1 0 X ……….. X
0 1 0 1 1 0 0 0 1 X ……….. X
0 1 0 1 1 0 0 1 1 X ……….. X
0 1 0 1 1 0 0 0 0 X ……….. X
0 1 0 1 1 0 0 1 0 X ……….. X
0 1 0 1 1 0 0 0 1 X ……….. X
0 1 0 1 1 0 0 1 1 X ……….. X
0 1 0 1 1 0 0 0 0 X ……….. X
0 1 0 1 1 0 0 1 0 X ……….. X
0 1 0 1 1 0 0 0 1 X ……….. X
0 1 0 1 1 0 0 1 1 X ……….. X
NOTES:
1. The RDAC register is a volatile scratch pad register
that is refreshed at power ON from the corresponding
non-volatile EEMEM register.
2. The increment, decrement and shift commands
ignore the contents of the shift register Data Byte.
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 8
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Detail Potentiometer Operation
The actual structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. The RDAC
contains a string of connected resistor segments, with an array
of analog switches that act as the wiper connection to several
points along the resistor array. The number of points is the
resolution of the device. For example, the AD5251/AD5252
emulates 64/256 connection points with 64/256 equal resistance,
Rs, allowing it to provide better than 1.5%/0.4% set-ability
resolution. Figure 5 provides an equivalent diagram of the
connections between the three terminals that make up one
channel of the RDAC. The switches SWA and SWB will always
be ON while one of the switches SW(0) to SW(2N-1) will be ON
one at a time depends upon the resistance step decoded from the
data. The total resistance of the active switches makes up the
wiper resistance, RW.
A
X
RS
RS
RS
WX
BX
RDAC
WIPER
REGISTER
&
DECODER
RS = RAB /2N
SW A
SW B
SW(2 N-1)
SW(2 N-2)
SW(0 )
SW(1 )
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
Figure 5. Equivalent RDAC structure
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B are available with values of 1kΩ, 10kΩ, 50kΩ, and 100kΩ.
The final digits of the part number determine the nominal
resistance value, e.g., 1kΩ = 1, 10kΩ = 10, 50kΩ = 50, and
100kΩ = 100. The nominal resistance (RAB) of the
AD5251/AD5252 VR has 64/256 contact points accessed by the
wiper terminal, plus the B terminal contact. The 6/8-bit data
word in the RDAC latch is decoded to select one of the 64/256
possible settings. The wiper's first connection starts at the B
terminal for data 00H. This B–terminal connection has a wiper
contact resistance, RW of 50Ω, regardless of what the nominal
resistance is. The second connection (AD5251 10kΩ part) is the
first tap point where RWB=206Ω [RWB =RAB/64 + RW =
156Ω+50Ω)] for data 01H. The third connection is the next tap
point representing RWB=312+50= 362Ω for data 02H. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at RWB=9893Ω. See figure 6 for a
simplified diagram of the equivalent RDAC circuit.
The general equation, which determines the digitally
programmed output resistance between Wx and Bx, is:
RWB(Dx) = (Dx/2N)*RAB + RW eqn. 1
Where N is the resolution of the VR, Dx is the data contained in
the RDACx latch, and RAB is the nominal end-to-end resistance.
Since N=6/8-bit and RW=50Ω for AD5251/AD5252, eqn. 1
becomes:
RWB(Dx) = (Dx/64)*RAB + 50Ω for AD5251 eqn. 2
RWB(Dx) = (Dx/256)*RAB + 50Ω for AD5252 eqn. 3
For example, when VB = 0V and A–terminal is open circuit, the
following output resistance values will be set by the
corresponding RDAC latch codes (applies to AD5251
RAB=10kΩ potentiometers):
Dx RWB Output State
(DEC) (Ω)
63 9893Ω Full-Scale
32 5050Ω Mid-Scale
1 206Ω 1 LSB
0 50Ω Zero-Scale (Wiper contact resistance)
Note that in the zero-scale condition a finite wiper resistance of
50Ω is present. Care should be taken to limit the current
conduction between W and B in this state to a no more than
±5mA continuous or ±20mA pulse to avoid degradation or
possible destruction of the internal switch contact.
Figure 6. Symmetrical RDAC Operation
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 9
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Like the mechanical potentiometer the RDAC replaces, the
AD5251/AD5252 part is totally symmetrical. The resistance
between the wiper W and terminal A also produces a digitally
controlled resistance RWA. Figure 6 shows the symmetrical
programmability of the various terminal connections. When
these terminals are used, the B–terminal should be tied to the
wiper. Setting the resistance value for RWA starts at a maximum
value of resistance and decreases as the data loaded in the latch
is increased in value. The general equation for this operation is:
RWA(Dx) = [(64-Dx)/64]*RAB + 50Ω (AD5251) eqn. 4
RWA(Dx) = [(256-Dx)/256]*RAB + 50Ω (AD5252) eqn. 5
For example, when VA = 0V and B–terminal is tied to the wiper
W the following output resistance values will be set by the
corresponding RDAC latch codes (applies to AD5251
RAB=10kΩ potentiometers):
Dx RWA Output State
(DEC) (Ω)
63 206 Full-Scale
32 5050 Mid-Scale
1 9893 1 LSB
0 10050 Zero-Scale
The typical distribution of RAB from channel-to-channel
matches of less than ±1% within the same package. On the other
hand, device to device matching is process lot dependent such
that a maximum of ±30% variation is possible.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal. For
example connecting A–terminal to +5V and B–terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5V. Each
LSB of voltage is equal to the voltage applied across terminal
AB divided by the 2N position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to
terminals AB is:
VW(Dx) = (Dx/64) * VAB + VB (AD5251) eqn. 6
VW(Dx) = (Dx/256) * VAB + VB (AD5252) eqn. 7
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors
and not the absolute value. Therefore, the drift reduces to
50ppm/°C.
ESD PROTECTION CIRCUITS
INPUTS
LOGIC
PINS
GND
V
DD
Figure 7A. Equivalent Digital Input ESD Protection
OUTPUTS
O1 & O2
PINS
GND
V
DD
Figure 7B. Equivalent Digital Output ESD Protection
Figure 7 shows the equivalent ESD protection circuit for digital
pins. Figure 8 shows the equivalent analog-terminal protection
circuit for the variable resistors.
POTENTIOMETER
TERMINALS
A, B, W
PINS
V
SS
Figure 8. Equivalent VR-Terminal ESD Protection
TEST CIRCUITS
Figures 9 to 17 define the test conditions used in the product
specification's table.
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 10
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
Figure 9. Potentiometer Divider Nonlinearity error test circuit
(INL, DNL)
Figure 10. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 11. Wiper Resistance test Circuit
Figure 12. Power supply sensitivity test circuit (PSS, PSSR)
Figure 13. Inverting Gain test Circuit
Figure 14. Non-Inverting Gain test circuit
Figure 15. Gain Vs Frequency test circuit
Figure 16. Incremental ON Resistance Test Circuit
Figure 17. Common Mode Leakage current test circuit
Figure 18. Analog Crosstalk Test Circuit
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5251/AD5252
REV PrB 2 DEC 99 11
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
