LM3424QMHX/NOPB - NATIONAL SEMICONDUCTOR

LM3424

LM3424 Constant Current N-Channel Controller with Thermal Foldback for

Driving LEDs

Literature Number: SNVS603B

LM3424

October 13, 2009

Constant Current N-Channel Controller with Thermal

Foldback for Driving LEDs

General Description

The LM3424 is a versatile high voltage N-channel MosFET

controller for LED drivers . It can be easily configured in buck,

boost, buck-boost and SEPIC topologies. In addition, the

LM3424 includes a thermal foldback feature for temperature

management of the LEDs. This flexibility, along with an input

voltage rating of 75V, makes the LM3424 ideal for illuminating

LEDs in a large family of applications.

Adjustable high-side current sense voltage allows for tight

regulation of the LED current with the highest efficiency pos-

sible. The LM3424 uses standard peak current-mode control

providing inherent input voltage feed-forward compensation

for better noise immunity. It is designed to provide accurate

thermal foldback with a programmable foldback breakpoint

and slope. In addition, a 2.45V reference is provided.

The LM3424 includes a high-voltage startup regulator that

operates over a wide input range of 4.5V to 75V. The internal

PWM controller is designed for adjustable switching frequen-

cies of up to 2.0 MHz and external synchronization is possible.

The controller is capable of high speed PWM dimming and

analog dimming. Additional features include slope compen-

sation, softstart, over-voltage and under-voltage lock-out, cy-

cle-by-cycle current limit, and thermal shutdown.

The LM3424Q is an Automotive Grade product that is AEC-

Q100 grade 1 qualified.

Features

■LM3424Q is an Automotive Grade product that is AEC-

Q100 grade 1 qualified (-40°C to +125°C operating

junction temperarure)

■VIN range from 4.5V to 75V

■High-side adjustable current sense

■2Ω, 1A Peak MosFET gate driver

■Input under-voltage and output over-voltage protection

■PWM and analog dimming

■Cycle-by-cycle current limit

■Programmable slope compensation

■Programmable, synchronizable switching frequency

■Programmable thermal foldback

■Programmable softstart

■Precision voltage reference

■Low power shutdown and thermal shutdown

Applications

■LED Drivers - Buck, Boost, Buck-Boost, and SEPIC

■Indoor and Outdoor Area SSL

■Automotive

■General Illumination

■Constant-Current Regulators

Typical Boost Application Circuit

300857k9

300857b6

Boost Evaluation Board

9 Series LEDs at 1A

LM3424 Constant Current N-Channel Controller with Thermal Foldback for Driving LEDs

Connection Diagram

30085704

20-Lead TSSOP EP

Ordering Information

Order

Number

Spec. Package Type NSC Package

Drawing

Supplied As Features

LM3424MH NOPB TSSOP-20 EP MXA20A 73 Units, Rail

LM3424MHX NOPB TSSOP-20 EP MXA20A 2500 Units, Tape and Reel

LM3424QMH NOPB TSSOP-20 EP MXA20A 73 Units, Rail AEC-Q100 Grade 1 qualified.

Automotive Grade Production

Flow*

LM3424QMHX NOPB TSSOP-20 EP MXA20A 2500 Units, Tape and Reel

*Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.

Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identified

with the letter Q. For more information go to http://www.national.com/automotive.

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LM3424

Pin Descriptions

Pin Name Description Application Information

1VIN Input Voltage Bypass with 100 nF capacitor to GND as close to the device as possible.

2 EN Enable Connect to > 2.4V to enable the device or to < 0.8V for low power shutdown.

3 COMP Compensation Connect a capacitor to GND to compensate control loop.

4 CSH Current Sense High Connect a resistor to GND to set the signal current. Can also be used to analog

dim as explained in the Thermal Foldback / Analog Dimming section.

5 RT Resistor Timing Connect a resistor to GND to set the switching frequency. Can also be used

to synchronize external clock as explained in the Switching Frequency section.

6 nDIM Dimming Input /

Under-Voltage Protection

Connect a PWM signal for dimming as detailed in the PWM Dimming section

and/or a resistor divider from VIN to program input under-voltage lockout.

7 SS Soft-start Connect a capacitor to GND to extend start-up time.

8 TGAIN Temp Foldback Gain Connect a resistor to GND to set the foldback slope.

9 TSENSE Temp Sense Input Connect a resistor/ thermistor divider from VS to sense the temperature as

explained in the Thermal Foldback / Analog Dimming section.

10 TREF Temp Foldback Reference Connect a resistor divider from VS to set the foldback reference voltage.

11 VSVoltage Reference 2.45V reference for temperature foldback circuit and other external circuitry.

12 OVP Over-Voltage Protection Connect a resistor divider from VO to program output over-voltage lockout.

13 DDRV Dimming Gate Drive Output Connect to gate of dimming MosFET.

14 GND Ground Connect to DAP to provide proper system GND

15 GATE Main Gate Drive Output Connect to gate of main switching MosFET.

16 VCC Internal Regulator Output Bypass with a 2.2 µF – 3.3 µF, ceramic capacitor to GND.

17 IS Main Switch Current Sense Connect to the drain of the main N-channel MosFET switch for RDS-ON sensing

or to a sense resistor installed in the source of the same device.

18 SLOPE Slope Compensation Connect a resistor to GND to set slope of additional ramp.

19 HSN LED Current Sense Negative Connect through a series resistor to LED current sense resistor (negative).

20 HSP LED Current Sense Positive Connect through a series resistor to LED current sense resistor (positive).

DAP DAP Thermal pad on bottom of IC Connect to GND. Refer to (Note 2) for thermal considerations.

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LM3424

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VIN, EN, nDIM -0.3V to 76.0V

-1 mA continuous

OVP, HSP, HSN -0.3V to 76.0V

-100 µA continuous

IS -0.3V to 76.0V

-2V for 100 ns

-1 mA continuous

VCC -0.3V to 8.0V

VS, TREF, TSENSE, TGAIN,

COMP, CSH, RT, SLOPE, SS -0.3V to 6.0V

SS -30 µA to +30 µA

continuous

GATE, DDRV -0.3V to VCC

-2.5V for 100 ns

VCC+2.5V for 100 ns

-1 mA to +1 mA continuous

GND -0.3V to 0.3V

-2.5V to 2.5V for 100 ns

Maximum Junction

Temperature

Internally Limited

Storage Temperature Range −65°C to +150°C

Maximum Lead Temperature

(Reflow and Solder) (Note 3)

260°C

Continuous Power Dissipation Internally Limited

ESD Susceptibility (Note 4)

Human Body Model 2 kV

Operating Conditions (Note 1)

Operating Junction

Temperature Range −40°C to +125°C

Input Voltage VIN 4.5V to 75V

Electrical Characteristics (Note 1)

Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature

Range ( TJ = −40°C to +125°C). Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical

values represent the most likely parametric norm at TJ = +25°C, and are provided for reference purposes only. Unless otherwise

stated the following condition applies: VIN = +14V.

Symbol Parameter Conditions Min

(Note 5)

Typ

(Note 6)

Max

(Note 5)Units

STARTUP REGULATOR (VCC)

VCC-REG VCC Regulation ICC = 0 mA 6.30 6.90 7.35 V

ICC-LIM VCC Current Limit VCC = 0V 20 25 mA

IQQuiescent Current EN = 3.0V, Static 2.0 3.0

ISD Shutdown Current EN = 0V 0.1 1.0 µA

VCC-UVLO VCC UVLO Threshold VCC Increasing 4.17 4.50

VCC Decreasing 3.70 4.08

VCC-HYS VCC UVLO Hysteresis 0.1

ENABLE (EN)

VEN-ST EN Startup Threshold EN Increasing 1.75 2.40

EN decreasing 0.80 1.63

VEN-HYS EN Startup Hysteresis 0.1

REN EN Pull-down Resistance 0.45 0.82 1.30 MΩ

OVER-VOLTAGE PROTECTION (OVP)

VTH-OVP OVP OVLO Threshold OVP Increasing 1.185 1.240 1.285 V

IHYS-OVP OVP Hysteresis Source

Current

OVP Active (high) 13 20 27 µA

ERROR AMPLIFIER

VCSH CSH Reference Voltage With Respect to GND 1.210 1.235 1.260 V

Error Amplifier Input Bias

Current

-0.6 0 0.6 µA

COMP Sink / Source Current 17 26 35

Transconductance 100 µA/V

Linear Input Range (Note 7) ±125 mV

Transconductance

Bandwidth

-6dB Unloaded Response (Note 7) 1.0 MHz

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LM3424

Symbol Parameter Conditions Min

(Note 5)

Typ

(Note 6)

Max

(Note 5)Units

OSCILLATOR (RT)

fSW Switching Frequency RT = 36 kΩ164 207 250 kHz

RT = 12 kΩ525 597 669

VRT-SYNC Sync Threshold 3.5 V

PWM COMPARATOR

VCP-BASE COMP to PWM Offset - No

Slope Compensation

750 900 1050 mV

SLOPE COMPENSATION (SLOPE)

ΔVCP Slope Compensation

Amplitude

Additional COMP to PWM Offset -

SLOPE sinking 100 µA

85 mV

CURRENT LIMIT (IS)

VLIM Current Limit Threshold 215 245 275 mV

VLIM Delay to Output 35 75 ns

tON-MIN Leading Edge Blanking Time 140 240 340

HIGH SIDE TRANSCONDUCTANCE AMPLIFIER

Input Bias Current 10 µA

Transconductance 20 mA/V

Input Offset Current -1.5 01.5 µA

Input Offset Voltage -5 05mV

Transconductance

Bandwidth

ICSH = 100 µA (Note 7) 500 kHz

GATE DRIVER (GATE)

RSRC-GATE GATE Sourcing Resistance GATE = High 2.0 6.0 Ω

RSNK-GATE GATE Sinking Resistance GATE = Low 1.3 4.5

UNDER-VOLTAGE LOCKOUT and DIM INPUT (nDIM)

VTH-nDIM nDIM / UVLO Threshold 1.185 1.240 1.285 V

IHYS-nDIM nDIM Hysteresis Current 13 20 27 µA

DIM DRIVER (DDRV)

RSRC-DDRV DDRV Sourcing Resistance DDRV = High 13.5 30.0 Ω

RSNK-DDRV DDRV Sinking Resistance DDRV = Low 3.5 10.0

nDIM rising to DDRV rising 700 ns

nDIM rising to DDRV falling 360

SOFT-START (SS)

ISS Soft-start current 10 µA

THERMAL CONTROL

VSVS Voltage IVS = 0A 2.40 2.45 2.50 V

IVS = 1 mA

TREF input bias current VTREF = 1.5V

VTSENSE = 1.5V

0.1

µA

TSENSE Input Bias Current VTREF = 1.5V

VTSENSE = 1.5V

0.1

ITGAIN-MAX TGAIN Maximum Sourcing

Current

VTGAIN = 2V 200 600

ITF CSH Current with High-side

Amplifier Disabled

RTGAIN = 10

kΩ

VTREF = 1.5V

VTSENSE = 0.5V

100

VTREF = 1.5V

VTSENSE = 1.4V

VTREF = 1.5V

VTSENSE = 1.5V

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LM3424

Symbol Parameter Conditions Min

(Note 5)

Typ

(Note 6)

Max

(Note 5)Units

THERMAL SHUTDOWN

TSD Thermal Shutdown

Threshold

(Note 7) 165

°C

THYS Thermal Shutdown

Hysteresis

(Note 7) 25

THERMAL RESISTANCE

θJA Junction to Ambient 20L TSSOP EP (Note 2) 34 °C/W

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and the device should not be

operated beyond such conditions. All voltages are with respect to the potential at the GND pin, unless otherwise specified.

Note 2: Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for a reference layout wherein the

20L TSSOP EP package has its DAP pad populated with 9 vias. In applications where high maximum power dissipation exists, namely driving a large MosFET

at high switching frequency from a high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation

applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating

junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance

of the package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). In most applications there is little need for the full

power dissipation capability of this advanced package. Under these circumstances, no vias would be required and the thermal resistances would be 104 °C/W

for the 20L TSSOP EP. It is possible to conservatively interpolate between the full via count thermal resistance and the no via count thermal resistance with a

straight line to get a thermal resistance for any number of vias in between these two limits.

Note 3: Refer to National’s packaging website for more detailed information and mounting techniques. http://www.national.com/analog/packaging/

Note 4: Human Body Model, applicable std. JESD22-A114-C.

Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%

production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used

to calculate Average Outgoing Quality Level (AOQL).

Note 6: Typical numbers are at 25°C and represent the most likely norm.

Note 7: These electrical parameters are guaranteed by design, and are not verified by test.

Note 8: The measurements were made using the standard buck-boost evaluation board from AN-1967.

Note 9: The measurements were made using the standard boost evaluation board from AN-1969.

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LM3424

Typical Performance Characteristics TA=+25°C and VIN = 14V unless otherwise specified

Boost Efficiency vs. Input Voltage

VO = 32V (9 LEDs) (Note 9)

300857b6

Buck-Boost Efficiency vs. Input Voltage

VO = 21V (6 LEDs) (Note 8)

300857b5

Boost LED Current vs. Input Voltage

VO = 32V (9 LEDs) (Note 9)

300857b8

Buck-Boost LED Current vs. Input Voltage

VO = 21V (6 LEDs) (Note 8)

300857b7

Analog Dimming

VO = 21V (6 LEDs); VIN = 24V (Note 8)

300857b9

PWM Dimming

VO = 32V (9 LEDs); VIN = 24V (Note 9)

300857c0

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LM3424

VCSH vs. Junction Temperature

300857b0

VCC vs. Junction Temperature

300857b1

VS vs. Junction Temperature

300857b2

VLIM vs. Junction Temperature

300857b3

tON-MIN vs. Junction Temperature

300857b4

fSW vs. Junction Temperature

30085701

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LM3424

ITF vs. Junction Temperature

RGAIN = 10 kΩ; VTSENSE = 0.5V; VTREF = 1.5V

30085702

fSW vs. RT

30085705

Ideal Thermal Foldback - Varied Slope

RREF1 = RREF2 = 49.9 kΩ; RNTC-BK = RBIAS = 43.2 kΩ

300857k4

Ideal Thermal Foldback - Varied Breakpoint

RREF1 = RREF2 = 49.9 kΩ; RGAIN = 10 kΩ

300857k5

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LM3424

Block Diagram

30085703

Theory of Operation

The LM3424 is an N-channel MosFET (NFET) controller for

buck, boost and buck-boost current regulators which are ideal

for driving LED loads. The controller has wide input voltage

range allowing for regulation of a variety of LED loads. The

high-side differential current sense, with low adjustable

threshold voltage, provides an excellent method for regulating

output current while maintaining high system efficiency. The

LM3424 uses peak current mode control providing good noise

immunity and an inherent cycle-by-cycle current limit. The

adjustable current sense threshold provides the capability to

amplitude (analog) dim the LED current and the thermal fold-

back circuitry allows for precise temperature management of

the LEDs. Tthe output enable/disable function coupled with

an internal dimming drive circuit provides high speed PWM

dimming through the use of an external MosFET placed at the

LED load. When designing, the maximum attainable LED cur-

rent is not internally limited because the LM3424 is a con-

troller. Instead it is a function of the system operating point,

component choices, and switching frequency allowing the

LM3424 to easily provide constant currents up to 5A. This

simple controller contains all the features necessary to im-

plement a high efficiency versatile LED driver.

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LM3424

30085798

FIGURE 1. Ideal CCM Regulator Inductor Current iL(t)

CURRENT REGULATORS

Current regulators can be designed to accomplish three basic

functions: buck, boost, and buck-boost. All three topologies

in their most basic form contain a main switching MosFET, a

recirculating diode, an inductor and capacitors. The LM3424

is designed to drive a ground referenced NFET which is per-

fect for a standard boost regulator. Buck and buck-boost

regulators, on the other hand, usually have a high-side switch.

When driving an LED load, a ground referenced load is often

not necessary, therefore a ground referenced switch can be

used to drive a floating load instead. The LM3424 can then

be used to drive all three basic topologies as shown in the

Basic Topology Schematics section. Other topologies such

as the SEPIC and flyback converter (both derivatives of the

buck-boost) can be implemented as well.

Looking at the buck-boost design, the basic operation of a

current regulator can be analyzed. During the time that the

NFET (Q1) is turned on (tON), the input voltage source stores

energy in the inductor (L1) while the output capacitor (CO)

provides energy to the LED load. When Q1 is turned off

(tOFF), the re-circulating diode (D1) becomes forward biased

and L1 provides energy to both CO and the LED load. Figure

1 shows the inductor current (iL(t)) waveform for a regulator

operating in CCM.

The average output LED current (ILED) is proportional to the

average inductor current (IL) , therefore if IL is tightly con-

trolled, ILED will be well regulated. As the system changes

input voltage or output voltage, the ideal duty cycle (D) is var-

ied to regulate IL and ultimately ILED. For any current regulator,

D is a function of the conversion ratio:

Buck

Boost

Buck-boost

PEAK CURRENT MODE CONTROL

Peak current mode control is used by the LM3424 to regulate

the average LED current through an array of HBLEDs. This

method of control uses a series resistor in the LED path to

sense LED current and can use either a series resistor in the

MosFET path or the MosFET RDS-ON for both cycle-by-cycle

current limit and input voltage feed forward. The controller has

a fixed switching frequency set by an internal programmable

oscillator which means current mode instability can occur at

duty cycles higher than 50%. To mitigate this standard prob-

lem, an aritifical ramp is added to the control signal internally.

The slope of this ramp is programmable to allow for a wider

range of component choices for a given design. A detailed

explanation of this control method is presented in the follow-

ing sections.

SWITCHING FREQUENCY

The switching frequency of the LM3424 is programmed using

an external resistor (RT) connected from the RT pin to GND

as shown in Figure 2.

Alternatively, an external PWM signal can be applied to the

RT pin through a filter (RFLT and CFLT) and an AC coupling

capacitor (CAC) to synchronize the part to an external clock

as shown in Figure 2. If the external PWM signal is applied at

a frequency higher than the base frequency set by the RT re-

sistor, the internal oscillator is bypassed and the switching

frequency becomes the synchronized frequency. The exter-

nal synchronization signal should have a pulse width of

100ns, an amplitude between 3V and 6V, and be AC coupled

to the RT pin with a ceramic capacitor (CAC = 100pF). A

10MHz RC filter (RFLT = 150Ω and CFLT = 100 pF) should be

placed between the PWM signal and CAC to eliminate un-

wanted high frequency noise from coupling into the RT pin.

The switching frequency is defined:

See the Typical Performance Characteristics section for a plot

of RT vs. fSW.

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LM3424

30085799

FIGURE 2. Timing Circuitry

AVERAGE LED CURRENT

To first understand how the LM3424 regulates LED current,

the thermal foldback functionality will be ignored. Figure 3

shows the physical implementation of the LED current sense

circuitry assuming the thermal foldback circuitry is a simple

current source which, for now, will be set to zero (ITF = 0A).

The LM3424 uses an external current sense resistor (RSNS)

placed in series with the LED load to convert the LED current

(ILED) into a voltage (VSNS). The HSP and HSN pins are the

inputs to the high-side sense amplifier which are forced to be

equal potential (VHSP=VHSN) through negative feedback. Be-

cause of this, the VSNS voltage is forced across RHSP which

generates a current that is summed with the thermal foldback

current (ITF) to generate the signal current (ICSH) which flows

out of the CSH pin and through the RCSH resistor. The error

amplifier will regulate the CSH pin to 1.24V and assuming

ITF = 0A, ICSH can be calculated:

This means VSNS will be regulated as follows:

ILED can then be calculated:

The selection of the three resistors (RSNS, RCSH, and RHSP) is

not arbitrary. For matching and noise performance, the sug-

gested signal current ICSH is approximately 100 µA. This

current does not flow in the LEDs and will not affect either the

off-state LED current or the regulated LED current. ICSH can

be above or below this value, but the high-side amplifier offset

characteristics may be affected slightly. In addition, to mini-

mize the effect of the high-side amplifier voltage offset on LED

current accuracy, the minimum VSNS is suggested to be

50 mV. Finally, a resistor (RHSN = RHSP) should be placed in

series with the HSN pin to cancel out the effects of the input

bias current (~10 µA) of both inputs of the high-side sense

amplifier.

Note that he CSH pin can also be used as a low-side current

sense input regulated to 1.24V. The high-side sense amplifier

is disabled if HSP and HSN are tied to GND.

30085757

FIGURE 3. LED Current Sense Circuitry

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LM3424

300857a1

FIGURE 4. Thermal Foldback Circuitry

THERMAL FOLDBACK / ANALOG DIMMING

Thermal foldback is necessary in many applications due to

the extreme temperatures created in LED environments. In

general, two functions are necessary: a temperature break-

point (TBK) after which the nominal operating current needs to

be reduced, and a slope corresponding to the amount of LED

current decrease per temperature increase as shown in Fig-

ure 5. The LM3424 allows the user to program both the

breakpoint and slope of the thermal foldback profile.

300857c2

FIGURE 5. Ideal Thermal Foldback Profile

Foldback is accomplished by adding current (ITF) to the CSH

summing node. As more current is added, less current is

needed from the high side amplifier and correspondingly, the

LED current is regulated to a lower value. The final tempera-

ture (TEND) is reached when ITF = ICSH causing no current to

be needed from the high-side amplifier, yielding ILED = 0A.

Figure 4 shows how the thermal foldback circuitry is physically

implemented in the system. ITF is set by placing a differential

voltage (VDIF = VTREF – VTSENSE) across TSENSE and TREF.

VTREF can be set with a simple resistor divider (RREF1 and

RREF2) supplied from the VS voltage reference (typical 2.45V).

VTSENSE is set with a temperature dependant voltage (as tem-

perature increases, voltage should decrease).

An NTC thermistor is the most cost effective device used to

sense temperature. As the temperature of the thermistor in-

creases, its resistance decreases (albeit non-linearly). Usu-

ally, the NTC manufacturer's datasheet will detail the

resistance-temperature characteristic of the thermistor. The

thermistor will have a different resistance (RNTC) at each tem-

perature. The nominal resistance of an NTC is the resistance

when the temperature is 25°C (R25) and in many datasheets

this will be given a multiplier of 1. Then the resistance at a

higher temperature will have a multiplier less than 1 (i.e. R85

multiplier is 0.161 therefore R85 = 0.161 x R25). Given a de-

sired TBK and TEND, the corresponding resistances at those

temperatures (RNTC-BK and RNTC-END) can be found.

Using the NTC method, a resistor divider from VS can be im-

plemented with a resistor connected between VS and

TSENSE and the NTC thermistor placed at the desired loca-

tion and connected from TSENSE to GND. This will ensure

that the desired temperature-voltage characteristic occurs at

TSENSE.

If a linear decrease over the foldback range is necessary, a

precision temperature sensor such as the LM94022 can be

used instead as shown in Figure 4. Either method can be used

to set VTSENSE according to the temperature. However, for the

rest of this datasheet, the NTC method will be used for thermal

foldback calculations.

During operation, if VDIF < 0V, then the sensed temperature

is less than TBK and the differential sense amplifier will regu-

late its output to zero forcing ITF = 0. This maintains the

nominal LED current and no foldback is observed.

At TBK, VDIF = 0V exactly and ITF is still zero. Looking at the

manufacturer's datasheet for the NTC thermistor, RNTC-BK can

be obtained for the desired TBK and the voltage relationship

at the breakpoint (VTSENSE-BK = VTREF) can be defined:

A general rule of thumb is to set RREF1 = RREF2 simplifying the

breakpoint relationship to RBIAS = RNTC-BK.

If VDIF > 0V (temperature is above TBK), then the amplifier will

regulate its output equal to the input forcing VDIF across the

resistor (RGAIN) connected from TGAIN to GND. RGAIN ulti-

mately sets the slope of the LED current decrease with re-

spect to increasing temperature by changing ITF:

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LM3424

If an analog temperature sensor such as the LM94022 is

used, then RBIAS and the NTC are not necessary and

VTENSE will be the direct voltage output of the sensor.

Since the NTC is not usually local to the controller, a bypass

capacitor (CNTC) is suggested from TSENSE to GND. If a ca-

pacitor is used at TSENSE, then a capacitor (CREF) of equal

or greater value should be placed from TREF to GND in order

to ensure the controller does not start-up in foldback. Alter-

natively, a smaller CREF can be used to create a fade-up

function at start-up (see Application Information section).

Thermal foldback is simply analog dimming according to a

specific profile, therefore any method of controlling the differ-

ential voltage between TREF and TSENSE can be use to

analog dim the LED current. The corresponding LED current

for any VDIF > 0V is defined:

The CSH pin can also be used to analog dim the LED current

by adjusting the current sense voltage (VSNS), similar to ther-

mal foldback. There are several different methods to adjust

VSNS using the CSH pin:

1. External variable resistance : Adjust a potentiometer

placed in series with RCSH to vary VSNS.

2. External variable current source: Source current (0 µA to

ICSH) into the CSH pin to adjust VSNS.

300857k3

FIGURE 6. Analog Dimming Circuitry

In general, analog dimming applications require a lower

switching frequency to minimize the effect of the leading edge

blanking circuit. As the LED current is reduced, the output

voltage and the duty cycle decreases. Eventually, the mini-

mum on-time is reached. The lower the switching frequency,

the wider the linear dimming range. Figure 6 shows how both

CSH methods are physically implemented.

Method 1 uses an external potentiometer in the CSH path

which is a simple addition to the existing circuitry. However,

the LEDs cannot dim completely because there is always

some resistance causing signal current to flow. This method

is also susceptible to noise coupling at the CSH pin since the

potentiometer increases the size of the signal current loop.

Method 2 provides a complete dimming range and better

noise performance, though it is more complex. Like thermal

foldback, it simply sources current into the CSH pin, decreas-

ing the amount of signal current that is necessary. This

method consists of a PNP current mirror and a bias network

consisting of an NPN, 2 resistors and a potentiometer

(RADJ), where RADJ controls the amount of current sourced

into the CSH pin. A higher resistance value will source more

current into the CSH pin causing less regulated signal current

through RHSP, effectively dimming the LEDs. Q7 and Q8

should be a dual pair PNP for best matching and perfor-

mance. The additional current (IADD) sourced into the CSH pin

can be calculated:

The corresponding ILED for a specific IADD is:

THERMAL SHUTDOWN

The LM3424 includes thermal shutdown. If the die tempera-

ture reaches approximately 165°C the device will shut down

(GATE pin low), until it reaches approximately 140°C where

it turns on again.

www.national.com 14

LM3424

CURRENT SENSE/CURRENT LIMIT

The LM3424 achieves peak current mode control using a

comparator that monitors the main MosFET (Q1) transistor

current, comparing it with the COMP pin voltage as shown in

Figure 7. Further, it incorporates a cycle-by-cycle over-current

protection function. Current limit is accomplished by a redun-

dant internal current sense comparator. If the voltage at the

current sense comparator input (IS) exceeds 245 mV (typi-

cal), the on cycle is immediately terminated. The IS input pin

has an internal N-channel MosFET which pulls it down at the

conclusion of every cycle. The discharge device remains on

an additional 240 ns (typical) after the beginning of a new cy-

cle to blank the leading edge spike on the current sense

signal. The leading edge blanking (LEB) determines the min-

imum achievable on-time (tON-MIN).

300857a2

FIGURE 7. Current Sense / Current Limit Circuitry

There are two possible methods to sense the transistor cur-

rent. The RDS-ON of the main power MosFET can be used as

the current sense resistance because the IS pin was designed

to withstand the high voltages present on the drain when the

MosFET is in the off state. Alternatively, a sense resistor lo-

cated in the source of the MosFET may be used for current

sensing, however a low inductance (ESL) type is suggested.

The cycle-by-cycle current limit (ILIM) can be calculated using

either method as the limiting resistance (RLIM):

In general, the external series resistor allows for more design

flexibility, however it is important to ensure all of the noise

sensitive low power ground connections are connected to-

gether local to the controller and a single connection is made

to GND.

SLOPE COMPENSATION

The LM3424 has programmable slope compensation in order

to provide stability over a wide range of operating conditions.

Without slope compensation, a well-known condition called

current mode instability (or sub-harmonic oscillation) can re-

sult if there is a perturbation of the MosFET current sense

voltage at the IS pin, due to noise or a some type of transient.

Through a mathematical / geometrical analysis of the inductor

current (IL) and the corresponding control current (IC, it can

be shown that if D < 0.5, the effect of the perturbation will

decrease each switching cycle and the system will remain

stable. However, if D > 0.5 then the perturbation will grow as

shown in Figure 8, eventually causing a "period doubling" ef-

fect where the effect of the perturbation remains, yielding

current mode instability.

Looking at Figure 7, the positive PWM comparator input is the

IS voltage, a mirror of IL during tON, plus a typical 900 mV

offset. The negative input of the PWM comparator is the

COMP pin which is proportional to IC, the threshold at which

the main MosFET (Q1) is turned off.

The LM3424 mitigates current mode instability by implement-

ing an aritifical ramp (commonly called slope compensation)

which is summed with the sensed MosFET current at the IS

pin as shown in Figure 7. This combined signal is compared

to the COMP pin to generate the PWM signal. An increase in

the ramp that is added to the sense voltage will increase the

maximum achievable duty cycle. It should be noted that as

the artificial ramp is increased more and more, the control

method approaches standard voltage mode control and the

benefits of current mode control are reduced.

To program the slope compensation, an external resistor,

RSLP, is connected from SLOPE to GND. This sets the slope

of the artificial ramp that is added to the MosFET current

sense voltage. A smaller RSLP value will increase the slope of

the added ramp. A simple calculation is suggested to ensure

any duty cycle is attainable while preventing the addition of

excessive ramp. This method requires the artifical ramp slope

(MA) to be equal to half the inductor slope during tOFF:

30085706

FIGURE 8. "Period Doubling" due to Current Mode

Instability

15 www.national.com

LM3424

CONTROL LOOP COMPENSATION

The LM3424 control loop is modeled like any current mode

controller. Using a first order approximation, the uncompen-

sated loop can be modeled as a single pole created by the

output capacitor and, in the boost and buck-boost topologies,

a right half plane zero created by the inductor, where both

have a dependence on the LED string dynamic resistance.

There is also a high frequency pole in the model, however it

is near the switching frequency and plays no part in the com-

pensation design process therefore it will be neglected. Since

ceramic capacitance is recommended for use with LED

drivers due to long lifetimes and high ripple current rating, the

ESR of the output capacitor can also be neglected in the loop

analysis. Finally, there is a DC gain of the uncompensated

loop which is dependent on internal controller gains and the

external sensing network.

A buck-boost regulator will be used as an example case. See

the Design Guide section for compensation of all topologies.

The uncompensated loop gain for a buck-boost regulator is

given by the following equation:

Where the uncompensated DC loop gain of the system is de-

scribed as:

And the output pole (ωP1) is approximated:

And the right half plane zero (ωZ1) is:

300857a7

FIGURE 9. Uncompensated Loop Gain Frequency

Response

Figure 9 shows the uncompensated loop gain in a worst-case

scenario when the RHP zero is below the output pole. This

occurs at high duty cycles when the regulator is trying to boost

the output voltage significantly. The RHP zero adds 20dB/

decade of gain while loosing 45°/decade of phase which

places the crossover frequency (when the gain is zero dB)

extremely high because the gain only starts falling again due

to the high frequency pole (not modeled or shown in figure).

The phase will be below -180° at the crossover frequency

which means there is no phase margin (180° + phase at

crossover frequency) causing system instability. Even if the

output pole is below the RHP zero, the phase will still reach

-180° before the crossover frequency in most cases yielding

instability.

300857a3

FIGURE 10. Compensation Circuitry

www.national.com 16

LM3424

To mitigate this problem, a compensator should be designed

to give adequate phase margin (above 45°) at the crossover

frequency. A simple compensator using a single capacitor at

the COMP pin (CCMP) will add a dominant pole to the system,

which will ensure adequate phase margin if placed low

enough. At high duty cycles (as shown in Figure 9), the RHP

zero places extreme limits on the achievable bandwidth with

this type of compensation. However, because an LED driver

is essentially free of output transients (except catastrophic

failures open or short), the dominant pole approach, even with

reduced bandwidth, is usually the best approach. The domi-

nant compensation pole (ωP2) is determined by CCMP and the

output resistance (RO) of the error amplifier (typically 5 MΩ):

It may also be necessary to add one final pole at least one

decade above the crossover frequency to attenuate switching

noise and, in some cases, provide better gain margin. This

pole can be placed across RSNS to filter the ESL of the sense

resistor at the same time. Figure 10 shows how the compen-

sation is physically implemented in the system.

The high frequency pole (ωP3) can be calculated:

The total system transfer function becomes:

The resulting compensated loop gain frequency response

shown in Figure 11 indicates that the system has adequate

phase margin (above 45°) if the dominant compensation pole

is placed low enough, ensuring stability:

300857a4

FIGURE 11. Compensated Loop Gain Frequency

Response

30085761

FIGURE 12. Start-up Waveforms

START-UP REGULATOR and SOFT-START

The LM3424 includes a high voltage, low dropout bias regu-

lator. When power is applied, the regulator is enabled and

sources current into an external capacitor (CBYP) connected

to the VCC pin. The recommended bypass capacitance for the

VCC regulator is 2.2 µF to 3.3 µF. The output of the VCC reg-

ulator is monitored by an internal UVLO circuit that protects

the device from attempting to operate with insufficient supply

voltage and the supply is also internally current limited.

The LM3424 also has programmable soft-start, set by an ex-

ternal capacitor (CSS), connected from SS to GND. For CSS

to affect start-up, CREF > CNTC must be maintained so that the

converter does not start in foldback mode. Figure 12 shows

the typical start-up waveforms for the LM3424 assuming

CREF > CNTC.

First, CBYP is charged to be above VCC UVLO threshold

(~4.2V). The CVCC charging time (tVCC) can be estimated as:

Assuming there is no CSS or if CSS is less than 40% of

CCMP , CCMP is then charged to 0.9V over the charging time

(tCMP) which can be estimated as:

Once CCMP = 0.9V, the part starts switching to charge CO until

the LED current is in regulation. The CO charging time (tCO)

can be roughly estimated as:

If CSS is greater than 40% of CCMP, the compensation capac-

itor will only charge to 0.7V over a smaller CCMP charging time

(tCMP-SS) which can be estimated as:

17 www.national.com

LM3424

Then COMP will clamp to SS, forcing COMP to rise (the last

200 mV before switching begins) according to the CSS charg-

ing time (tSS) which can be estimated as:

The system start-up time (tSU or tSU-SS) is defined as:

CSS < 0.4 x CCMP

CSS > 0.4 x CCMP

As a general rule of thumb, standard smooth startup operation

can be achieved with CSS = CCMP.

OVER-VOLTAGE LOCKOUT (OVLO)

30085758

FIGURE 13. Over-Voltage Protection Circuitry

The LM3424 can be configured to detect an output (or input)

over-voltage condition via the OVP pin. The pin features a

precision 1.24V threshold with 20 µA (typical) of hysteresis

current as shown in Figure 13. When the OVLO threshold is

exceeded, the GATE pin is immediately pulled low and a 20

µA current source provides hysteresis to the lower threshold

of the OVLO hysteretic band.

If the LEDs are referenced to a potential other than ground

(floating), as in the buck-boost and buck configuration, the

output voltage (VO) should be sensed and translated to

ground by using a single PNP as shown in Figure 14.

The over-voltage turn-off threshold (VTURN-OFF) is defined:

Ground Referenced

Floating

In the ground referenced configuration, the voltage across

ROV2 is VO - 1.24V whereas in the floating configuration it is

VO - 620 mV where 620 mV approximates VBE of the PNP.

The over-voltage hysteresis (VHYSO) is defined:

30085759

FIGURE 14. Floating Output OVP Circuitry

INPUT UNDER-VOLTAGE LOCKOUT (UVLO)

The nDIM pin is a dual-function input that features an accurate

1.24V threshold with programmable hysteresis as shown in

Figure 15. This pin functions as both the PWM dimming input

for the LEDs and as a VIN UVLO. When the pin voltage rises

and exceeds the 1.24V threshold, 20 µA (typical) of current is

driven out of the nDIM pin into the resistor divider providing

programmable hysteresis.

300857a5

FIGURE 15. UVLO Circuit

When using the nDIM pin for UVLO and PWM dimming con-

currently, the UVLO circuit can have an extra series resistor

to set the hysteresis. This allows the standard resistor divider

to have smaller resistor values minimizing PWM delays due

to a pull-down MosFET at the nDIM pin (see PWM Dimming

section). In general, at least 3V of hysteresis is preferable

when PWM dimming, if operating near the UVLO threshold.

The turn-on threshold (VTURN-ON) is defined as follows:

The hysteresis (VHYS) is defined as follows:

UVLO only

PWM dimming and UVLO

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LM3424

PWM DIMMING

The active low nDIM pin can be driven with a PWM signal

which controls the main NFET and the dimming FET (dim-

FET). The brightness of the LEDs can be varied by modulat-

ing the duty cycle of this signal. LED brightness is approxi-

mately proportional to the PWM signal duty cycle, (i.e. 30%

duty cycle ~ 30% LED brightness). This function can be ig-

nored if PWM dimming is not required by using nDIM solely

as a VIN UVLO input as described in the Input Under-Voltage

Lockout section or by tying it directly to VCC or VIN.

300857a6

FIGURE 16. PWM Dimming Circuit

Figure 16 shows how the PWM signal is applied to nDIM:

1. Connect the dimming MosFET (QDIM) with the drain to

the nDIM pin and the source to GND. Apply an external

logic-level PWM signal to the gate of QDIM.

2. Connect the anode of a Schottky diode (DDIM) to the

nDIM pin. Apply an inverted external logic-level PWM

signal to the cathode of the same diode.

The DDRV pin is a PWM output that follows the nDIM PWM

input signal. When the nDIM pin rises, the DDRV pin rises and

the PWM latch reset signal is removed allowing the main

MosFET Q1 to turn on at the beginning of the next clock set

pulse. In boost and buck-boost topologies, the DDRV pin is

used to control a N-channel MosFET placed in series with the

LED load, while it would control a P-channel MosFET in par-

allel with the load for a buck topology.

The series dimFET will open the LED load, when nDIM is low,

effectively speeding up the rise and fall times of the LED cur-

rent. Without any dimFET, the rise and fall times are limited

by the inductor slew rate and dimming frequencies above

1 kHz are impractical. Using the series dimFET, dimming fre-

quencies up to 30 kHz are achievable. With a parallel dimFET

(buck topology), even higher dimming frequencies are

achievable.

When using the PWM functionality in a boost regulator, the

PWM signal drives a ground referenced FET. However, with

buck-boost and buck topologies, level shifting circuitry is nec-

essary to translate the PWM dim signal to the floating dimFET

as shown in Figure 17 and Figure 18.

When using a series dimFET to PWM dim the LED current,

more output capacitance is always better. A general rule of

thumb is to use a minimum of 40 µF when PWM dimming. For

most applications, this will provide adequate energy storage

at the output when the dimFET turns off and opens the LED

load. Then when the dimFET is turned back on, the capaci-

tance helps source current into the load, improving the LED

current rise time.

A minimum on-time must be maintained in order for PWM

dimming to operate in the linear region of its transfer function.

Because the controller is disabled during dimming, the PWM

pulse must be long enough such that the energy intercepted

from the input is greater than or equal to the energy being put

into the LEDs. For boost and buck-boost regulators, the min-

imum dimming pulse length in seconds (tPULSE) is:

Even maintaining a dimming pulse greater than tPULSE, pre-

serving linearity at low dimming duty cycles is difficult. Several

modifications are suggested for applications requiring low

dimming duty cycles. Since nDIM rising releases the latch but

does not trigger the on-time specifically, there will be an ef-

fective jitter on the rising edge of the LED current. This jitter

can be easily removed by tying the PWM input signal through

the synchronization network at the RT pin (shown in Figure

2), forcing the on-time to synchronize with the nDIM pulse.

The second helpful modification is to remove the CFS capac-

itor and RFS resistor, eliminating the high frequency compen-

sation pole. This should not affect stability, but it will speed up

the response of the CSH pin, specifically at the rising edge of

the LED current when PWM dimming, thus improving the

achievable linearity at low dimming duty cycles.

300857a0

FIGURE 17. Buck-boost Level-Shifted PWM Circuit

30085731

FIGURE 18. Buck Level-Shifted PWM Circuit

19 www.national.com

LM3424

Design Considerations

This section describes the application level considerations

when designing with the LM3424. For corresponding calcu-

lations, refer to the Design Guide section.

INDUCTOR

The inductor (L1) is the main energy storage device in a

switching regulator. Depending on the topology, energy is

stored in the inductor and transfered to the load in different

ways (as an example, buck-boost operation is detailed in the

Current Regulators section). The size of the inductor, the volt-

age across it, and the length of the switching subinterval

(tON or tOFF) determines the inductor current ripple (ΔiL-PP ). In

the design process, L1 is chosen to provide a desired ΔiL-PP.

For a buck regulator the inductor has a direct connection to

the load, which is good for a current regulator. This requires

little to no output capacitance therefore ΔiL-PP is basically

equal to the LED ripple current ΔiLED-PP. However, for boost

and buck-boost regulators, there is always an output capaci-

tor which reduces ΔiLED-PP, therefore the inductor ripple can

be larger than in the buck regulator case where output ca-

pacitance is minimal or completely absent.

In general, ΔiLED-PP is recommended by manufacturers to be

less than 40% of the average LED current (ILED). Therefore,

for the buck regulator with no output capacitance, ΔiL-PP

should also be less than 40% of ILED. For the boost and buck-

boost topologies, ΔiL-PP can be much higher depending on the

output capacitance value. However, ΔiL-PP is suggested to be

less than 100% of the average inductor current (IL) to limit the

RMS inductor current.

L1 is also suggested to have an RMS current rating at least

25% higher than the calculated minimum allowable RMS in-

ductor current (IL-RMS).

LED DYNAMIC RESISTANCE

When the load is a string of LEDs, the output load resistance

is the LED string dynamic resistance plus RSNS. LEDs are PN

junction diodes, and their dynamic resistance shifts as their

forward current changes. Dividing the forward voltage of a

single LED (VLED) by the forward current (ILED) leads to an

incorrect calculation of the dynamic resistance of a single LED

(rLED). The result can be 5 to 10 times higher than the true

rLED value.

30085774

FIGURE 19. Dynamic Resistance

Obtaining rLED is accomplished by refering to the

manufacturer's LED I-V characteristic. It can be calculated as

the slope at the nominal operating point as shown in Figure

19. For any application with more than 2 series LEDs, RSNS

can be neglected allowing rD to be approximated as the num-

ber of LEDs multiplied by rLED.

OUTPUT CAPACITOR

For boost and buck-boost regulators, the output capacitor

(CO) provides energy to the load when the recirculating diode

(D1) is reverse biased during the first switching subinterval.

An output capacitor in a buck topology will simply reduce the

LED current ripple (ΔiLED-PP) below the inductor current ripple

(ΔiL-PP). In all cases, CO is sized to provide a desired ΔiLED-

PP. As mentioned in the Inductor section, ΔiLED-PP is recom-

mended by manufacturers to be less than 40% of the average

LED current (ILED-PP).

CO should be carefully chosen to account for derating due to

temperature and operating voltage. It must also have the nec-

essary RMS current rating. Ceramic capacitors are the best

choice due to their high ripple current rating, long lifetime, and

good temperature performance. An X7R dieletric rating is

suggested.

INPUT CAPACITORS

The input capacitance (CIN) provides energy during the dis-

continuous portions of the switching period. For buck and

buck-boost regulators, CIN provides energy during tON and

during tOFF, the input voltage source charges up CIN with the

average input current (IIN). For boost regulators, CIN only

needs to provide the ripple current due to the direct connec-

tion to the inductor. CIN is selected given the maximum input

voltage ripple (ΔvIN-PP) which can be tolerated. ΔvIN-PP is sug-

gested to be less than 10% of the input voltage (VIN).

An input capacitance at least 100% greater than the calcu-

lated CIN value is recommended to account for derating due

to temperature and operating voltage. When PWM dimming,

even more capacitance can be helpful to minimize the large

current draw from the input voltage source during the rising

transistion of the LED current waveform.

The chosen input capacitors must also have the necessary

RMS current rating. Ceramic capacitors are again the best

choice due to their high ripple current rating, long lifetime, and

good temperature performance. An X7R dieletric rating is

suggested.

For most applications, it is recommended to bypass the VIN

pin will an 0.1 µF ceramic capacitor placed as close as pos-

sible to the pin. In situations where the bulk input capacitance

may be far from the LM3424 device, a 10 Ω series resistor

can be placed between the bulk input capacitance and the

bypass capacitor, creating a 150 kHz filter to eliminate unde-

sired high frequency noise.

www.national.com 20

LM3424

MAIN MosFET / DIMMING MosFET

The LM3424 requires an external NFET (Q1) as the main

power MosFET for the switching regulator. Q1 is recommend-

ed to have a voltage rating at least 15% higher than the

maximum transistor voltage to ensure safe operation during

the ringing of the switch node. In practice, all switching regu-

lators have some ringing at the switch node due to the diode

parasitic capacitance and the lead inductance. The current

rating is recommended to be at least 10% higher than the

average transistor current. The power rating is then verified

by calculating the power loss given the RMS transistor current

and the NFET on-resistance (RDS-ON).

When PWM dimming, the LM3424 requires another MosFET

(Q2) placed in series (or parallel for a buck regulator) with the

LED load. This MosFET should have a voltage rating equal

to the output voltage (VO) and a current rating at least 10%

higher than the nominal LED current (ILED) . The power rating

is simply VO multiplied by ILED, assuming 100% dimming duty

cycle (continuous operation) will occur.

In general, the NFETs should be chosen to minimize total gate

charge (Qg) when fSW is high and minimize RDS-ON otherwise.

This will minimize the dominant power losses in the system.

Frequently, higher current NFETs in larger packages are cho-

sen for better thermal performance.

RE-CIRCULATING DIODE

A re-circulating diode (D1) is required to carry the inductor

current during tOFF. The most efficient choice for D1 is a

Schottky diode due to low forward voltage drop and near-zero

reverse recovery time. Similar to Q1, D1 is recommended to

have a voltage rating at least 15% higher than the maximum

transistor voltage to ensure safe operation during the ringing

of the switch node and a current rating at least 10% higher

than the average diode current. The power rating is verified

by calculating the power loss through the diode. This is ac-

complished by checking the typical diode forward voltage

from the I-V curve on the product datasheet and multiplying

by the average diode current. In general, higher current

diodes have a lower forward voltage and come in better per-

forming packages minimizing both power losses and temper-

ature rise.

CIRCUIT LAYOUT

The performance of any switching regulator depends as much

upon the layout of the PCB as the component selection. Fol-

lowing a few simple guidelines will maximimize noise rejection

and minimize the generation of EMI within the circuit.

Discontinuous currents are the most likely to generate EMI,

therefore care should be taken when routing these paths. The

main path for discontinuous current in the LM3424 buck reg-

ulator contains the input capacitor (CIN), the recirculating

diode (D1), the N-channel MosFET (Q1), and the sense re-

sistor (RLIM). In the LM3424 boost regulator, the discontinu-

ous current flows through the output capacitor (CO), D1, Q1,

and RLIM. In the buck-boost regulator both loops are discon-

tinuous and should be carefully layed out. These loops should

be kept as small as possible and the connections between all

the components should be short and thick to minimize para-

sitic inductance. In particular, the switch node (where L1, D1

and Q1 connect) should be just large enough to connect the

components. To minimize excessive heating, large copper

pours can be placed adjacent to the short current path of the

switch node.

The RT, COMP, CSH, IS, TSENSE, TREF, HSP and HSN

pins are all high-impedance inputs which couple external

noise easily, therefore the loops containing these nodes

should be minimized whenever possible.

In some applications the LED or LED array can be far away

(several inches or more) from the LM3424, or on a separate

PCB connected by a wiring harness. When an output capac-

itor is used and the LED array is large or separated from the

rest of the regulator, the output capacitor should be placed

close to the LEDs to reduce the effects of parasitic inductance

on the AC impedance of the capacitor.

21 www.national.com

LM3424

Basic Topology Schematics

BOOST REGULATOR (VIN < VO)

30085722

www.national.com 22

LM3424

BUCK REGULATOR (VIN > VO)

30085751

23 www.national.com

LM3424

BUCK-BOOST REGULATOR

30085750

www.national.com 24

LM3424

Design Guide

Refer to Basic Topology Schematics section.

SPECIFICATIONS

Number of series LEDs: N

Single LED forward voltage: VLED

Single LED dynamic resistance: rLED

Nominal input voltage: VIN

Input voltage range: VIN-MAX, VIN-MIN

Switching frequency: fSW

Current sense voltage: VSNS

Average LED current: ILED

Inductor current ripple: ΔiL-PP

LED current ripple: ΔiLED-PP

Peak current limit: ILIM

Input voltage ripple: ΔvIN-PP

Output OVLO characteristics: VTURN-OFF, VHYSO

Input UVLO characteristics: VTURN-ON, VHYS

Thermal foldback characteristics: TBK, TEND

Total start-up time: tTSU

1. OPERATING POINT

Given the number of series LEDs (N), the forward voltage

(VLED) and dynamic resistance (rLED) for a single LED, solve

for the nominal output voltage (VO) and the nominal LED

string dynamic resistance (rD):

Solve for the ideal nominal duty cycle (D):

Buck

Boost

Buck-boost

Using the same equations, find the minimum duty cycle

(DMIN) using maximum input voltage (VIN-MAX) and the maxi-

mum duty cycle (DMAX) using the minimum input voltage (VIN-

MIN). Also, remember that D' = 1 - D.

2. SWITCHING FREQUENCY

Set the switching frequency (fSW) by solving for RT:

3. AVERAGE LED CURRENT

For all topologies, set the average LED current (ILED) knowing

the desired current sense voltage (VSNS) and solving for

RSNS:

If the calculated RSNS is too far from a desired standard value,

then VSNS will have to be adjusted to obtain a standard value.

Setup the suggested signal current of 100 µA by assuming

RCSH = 12.4 kΩ and solving for RHSP:

If the calculated RHSP is too far from a desired standard value,

then RCSH can be adjusted to obtain a standard value.

4. THERMAL FOLDBACK

For all topologies, set the thermal foldback breakpoint (TBK)

by finding corresponding RNTC-BK from manufacturer's

datasheet and solving for RBIAS:

The easiest approach is to set RREF1 = RREF2, therefore set-

ting RBIAS = RNTC-BK will properly set TBK. Remember, capac-

itance is recommended at the TSENSE and TREF pins, so

ensure CREF > CNTC to prevent start-up in foldback.

Then set the thermal foldback endpoint (TEND) by finding the

corresponding RNTC-END from manufacturer's datasheet and

solving for RGAIN:

5. INDUCTOR RIPPLE CURRENT

Set the nominal inductor ripple current (ΔiL-PP) by solving for

the appropriate inductor (L1):

Buck

Boost and Buck-boost

To set the worst case inductor ripple current, use VIN-MAX and

DMIN when solving for L1.

25 www.national.com

LM3424

The minimum allowable inductor RMS current rating (IL-RMS)

can be calculated as:

Buck

Boost and Buck-boost

6. LED RIPPLE CURRENT

Set the nominal LED ripple current (ΔiLED-PP), by solving for

the output capacitance (CO):

Buck

Boost and Buck-boost

To set the worst case LED ripple current, use DMAX when

solving for CO. Remember, when PWM dimming it is recom-

mended to use a minimum of 40 µF of output capacitance to

improve performance.

The minimum allowable RMS output capacitor current rating

(ICO-RMS) can be approximated:

Buck

Boost and Buck-boost

7. PEAK CURRENT LIMIT

Set the peak current limit (ILIM) by solving for the transistor

path sense resistor (RLIM):

8. SLOPE COMPENSATION

For all topologies, the preferred method to set slope compen-

sation is to ensure any duty cycle is attainable for the nominal

VO and chosen L by solving for RSLP:

9. LOOP COMPENSATION

Using a simple first order peak current mode control model,

neglecting any output capacitor ESR dynamics, the neces-

sary loop compensation can be determined.

First, the uncompensated loop gain (TU) of the regulator can

be approximated:

Buck

Boost and Buck-boost

Where the pole (ωP1) is approximated:

Buck

Boost

Buck-boost

And the RHP zero (ωZ1) is approximated:

Boost

Buck-boost

www.national.com 26

LM3424

And the uncompensated DC loop gain (TU0) is approximated:

Buck

Boost

Buck-boost

For all topologies, the primary method of compensation is to

place a low frequency dominant pole (ωP2) which will ensure

that there is ample phase margin at the crossover frequency.

This is accomplished by placing a capacitor (CCMP) from the

COMP pin to GND, which is calculated according to the lower

value of the pole and the RHP zero of the system (shown as

a minimizing function):

If analog dimming is used, CCMP should be approximately 4x

larger to maintain stability as the LEDs are dimmed to zero.

A high frequency compensation pole (ωP3) can be used to

attenuate switching noise and provide better gain margin. As-

suming RFS = 10Ω, CFS is calculated according to the higher

value of the pole and the RHP zero of the system (shown as

a maximizing function):

The total system loop gain (T) can then be written as:

Buck

Boost and Buck-boost

10. INPUT CAPACITANCE

Set the nominal input voltage ripple (ΔvIN-PP) by solving for

the required capacitance (CIN):

Buck

Boost

Buck-boost

Use DMAX to set the worst case input voltage ripple, when

solving for CIN in a buck-boost regulator and DMID = 0.5 when

solving for CIN in a buck regulator.

The minimum allowable RMS input current rating (ICIN-RMS)

can be approximated:

Buck

Boost

Buck-boost

11. NFET

The NFET voltage rating should be at least 15% higher than

the maximum NFET drain-to-source voltage (VT-MAX):

Buck

Boost

Buck-boost

27 www.national.com

LM3424

The current rating should be at least 10% higher than the

maximum average NFET current (IT-MAX):

Buck

Boost and Buck-boost

Approximate the nominal RMS transistor current (IT-RMS) :

Buck

Boost and Buck-boost

Given an NFET with on-resistance (RDS-ON), solve for the

nominal power dissipation (PT):

12. DIODE

The Schottky diode voltage rating should be at least 15%

higher than the maximum blocking voltage (VRD-MAX):

Buck

Boost

Buck-boost

The current rating should be at least 10% higher than the

maximum average diode current (ID-MAX):

Buck

Boost and Buck-boost

Replace DMAX with D in the ID-MAX equation to solve for the

average diode current (ID). Given a diode with forward voltage

(VFD), solve for the nominal power dissipation (PD):

13. OUTPUT OVLO

For boost and buck-boost regulators, output OVLO is pro-

grammed with the turn-off threshold voltage (VTURN-OFF) and

the desired hysteresis (VHYSO). To set VHYSO, solve for ROV2:

To set VTURN-OFF, solve for ROV1:

Boost

Buck-boost

A small filter capacitor (COVP = 47 pF) should be added from

the OVP pin to ground to reduce coupled switching noise.

14. INPUT UVLO

For all topologies, input UVLO is programmed with the turn-

on threshold voltage (VTURN-ON) and the desired hysteresis

(VHYS).

Method #1: If no PWM dimming is required, a two resistor

network can be used. To set VHYS, solve for RUV2:

To set VTURN-ON, solve for RUV1:

Method #2: If PWM dimming is required, a three resistor net-

work is suggested. To set VTURN-ON, assume RUV2 = 10 kΩ

and solve for RUV1 as in Method #1. To set VHYS, solve for

RUVH:

www.national.com 28

LM3424

15. SOFT-START

For all topologies, if soft-start is desired, find the start-up time

without CSS (tSU):

Then, if the desired total start-up time (tTSU) is larger than

tSU, solve for the base start-up time (tSU-SS-BASE), assuming

that a CSS greater than 40% of CCMP will be used:

Then solve for CSS:

16. PWM DIMMING METHOD

PWM dimming can be performed several ways:

Method #1: Connect the dimming MosFET (Q3) with the drain

to the nDIM pin and the source to GND. Apply an external

PWM signal to the gate of QDIM. A pull down resistor may be

necessary to properly turn off Q3.

Method #2: Connect the anode of a Schottky diode to the

nDIM pin. Apply an external inverted PWM signal to the cath-

ode of the same diode.

The DDRV pin should be connected to the gate of the dimFET

with or without level-shifting circuitry as described in the PWM

Dimming section. The dimFET should be rated to handle the

average LED current and the nominal output voltage.

17. ANALOG DIMMING METHOD

Analog dimming can be performed several ways:

Method #1: Place a potentiometer in place of the thermistor

in the thermal foldback circuit shown in the Thermal Folback /

Analog Dimming section.

Method #2: Place a potentiometer in series with the RCSH

resistor to dim the LED current from the nominal ILED to near

zero.

Method #3: Connect a controlled current source as detailed

in the Thermal Folback / Analog Dimming section to the CSH

pin. Increasing the current sourced into the CSH node will

decrease the LEDs from the nominal ILED to zero current in

the same manner as the thermal foldback circuit.

29 www.national.com

LM3424

Design Example

DESIGN #1 - BUCK-BOOST Application

300857i1

SPECIFICATIONS

N = 6

VLED = 3.5V

rLED = 325 mΩ

VIN = 24V

VIN-MIN = 10V

VIN-MAX = 70V

fSW = 500 kHz

VSNS = 100 mV

ILED = 1A

ΔiL-PP = 700 mA

ΔiLED-PP = 12 mA

ΔvIN-PP = 100 mV

ILIM = 6A

VTURN-ON = 10V

VHYS = 3V

VTURN-OFF = 40V

VHYSO = 10V

TBK = 70°C

TEND= 120°C

tTSU = 30 ms

www.national.com 30

LM3424

1. OPERATING POINT

Solve for VO and rD:

Solve for D, D', DMAX, and DMIN:

2. SWITCHING FREQUENCY

Solve for RT:

The closest standard resistor is 14.3 kΩ therefore fSW is:

The chosen component from step 2 is:

3. AVERAGE LED CURRENT

Solve for RSNS:

Assume RCSH = 12.4 kΩ and solve for RHSP:

The closest standard resistor for RSNS is actually 0.1Ω and for

RHSP is actually 1 kΩ therefore ILED is:

The chosen components from step 3 are:

4. THERMAL FOLDBACK

Find the resistances corresponding to TBK and TEND (RNTC-

BK = 24.3 kΩ and RNTC-END = 7.15 kΩ) from the manufacturer's

datasheet. Assuming RREF1 = RREF2 = 49.9 kΩ, then RBIAS =

RNTC-BK= 24.3 kΩ.

Solve for RGAIN:

The chosen components from step 4 are:

5. INDUCTOR RIPPLE CURRENT

Solve for L1:

The closest standard inductor is 33 µH therefore ΔiL-PP is:

Determine minimum allowable RMS current rating:

The chosen component from step 5 is:

31 www.national.com

LM3424

6. OUTPUT CAPACITANCE

Solve for CO:

The closest capacitance totals 40 µF therefore ΔiLED-PP is:

Determine minimum allowable RMS current rating:

The chosen components from step 6 are:

7. PEAK CURRENT LIMIT

Solve for RLIM:

The closest standard resistor is 0.04 Ω therefore ILIM is:

The chosen component from step 7 is:

8. SLOPE COMPENSATION

Solve for RSLP:

The chosen component from step 8 is:

9. LOOP COMPENSATION

ωP1 is approximated:

ωZ1 is approximated:

TU0 is approximated:

To ensure stability, calculate ωP2:

Solve for CCMP:

To attenuate switching noise, calculate ωP3:

Assume RFS = 10Ω and solve for CFS:

The chosen components from step 9 are:

www.national.com 32

LM3424

10. INPUT CAPACITANCE

Solve for the minimum CIN:

To minimize power supply interaction a 200% larger capaci-

tance of approximately 20 µF is used, therefore the actual

ΔvIN-PP is much lower. Since high voltage ceramic capacitor

selection is limited, four 4.7 µF X7R capacitors are chosen.

Determine minimum allowable RMS current rating:

The chosen components from step 10 are:

11. NFET

Determine minimum Q1 voltage rating and current rating:

A 100V NFET is chosen with a current rating of 32A due to

the low RDS-ON = 50 mΩ. Determine IT-RMS and PT:

The chosen component from step 11 is:

12. DIODE

Determine minimum D1 voltage rating and current rating:

A 100V diode is chosen with a current rating of 12A and VD =

600 mV. Determine PD:

The chosen component from step 12 is:

13. INPUT UVLO

Solve for RUV2:

The closest standard resistor is 150 kΩ therefore VHYS is:

Solve for RUV1:

The closest standard resistor is 21 kΩ making VTURN-ON:

The chosen components from step 13 are:

14. OUTPUT OVLO

Solve for ROV2:

The closest standard resistor is 499 kΩ therefore VHYSO is:

Solve for ROV1:

The closest standard resistor is 15.8 kΩ making VTURN-OFF:

The chosen components from step 14 are:

33 www.national.com

LM3424

15. SOFT-START

Solve for tSU:

If tSU is less than tTSU, solve for tSU-SS-BASE:

Solve for CSS:

The chosen component from step 15 is:

DESIGN #1 Bill of Materials

Qty Part ID Part Value Manufacturer Part Number

1 LM3424 Boost controller NSC LM3424MH

1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L

2 CCMP, CNTC 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L

1 CFS 0.27 µF X7R 10% 25V MURATA GRM21BR71E274KA01L

4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K

4 CO10 µF X7R 10% 50V TDK C4532X7R1H106K

1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A

1 CREF, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L

1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF

1 L1 33 µH 20% 6.3A COILCRAFT MSS1278-333MLB

1 Q1 NMOS 100V 32A FAIRCHILD FDD3682

1 Q2 PNP 150V 600 mA FAIRCHILD MMBT5401

1 RBIAS 24.3 kΩ 1% VISHAY CRCW080524K3FKEA

1 RCSH 12.4 kΩ 1% VISHAY CRCW080512K4FKEA

1 RFS 10Ω 1% VISHAY CRCW080510R0FKEA

1 RGAIN 6.81 kΩ 1% VISHAY CRCW08056K81FKEA

2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA

1 RLIM 0.04Ω 1% 1W VISHAY WSL2512R0400FEA

1 ROV1 15.8 kΩ 1% VISHAY CRCW080515K8FKEA

1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA

2 RREF1, RREF2 49.9 kΩ 1% VISHAY CRCW080549K9FKEA

1 RSLP 16.5 kΩ 1% VISHAY CRCW080516K5FKEA

1 RSNS 0.1Ω 1% 1W VISHAY WSL2512R1000FEA

1 RT14.3 kΩ 1% VISHAY CRCW080514K3FKEA

1 RUV1 21 kΩ 1% VISHAY CRCW080521K0FKEA

1 RUV2 150 kΩ 1% VISHAY CRCW0805150KFKEA

1 NTC Thermistor 100 kΩ 5% TDK NTCG204H154J

www.national.com 34

LM3424

Applications Information

The following designs are provided as reference circuits. For a specific design, the steps in the Design Procedure section should

be performed. In all designs, an RC filter (0.1 µF, 10Ω) is recommended at VIN placed as close as possible to the LM3424 device.

This filter is not shown in the following designs.

DESIGN #2 - BOOST Application

300857h5

Features

•Input: 8V to 28V

•Output: 9 LEDs at 1A

•65°C - 100°C Thermal Foldback

•PWM Dimming up to 30kHz

•700 kHz Switching Frequency

35 www.national.com

LM3424

DESIGN #2 Bill of Materials

Qty Part ID Part Value Manufacturer Part Number

1 LM3424 Boost controller NSC LM3424MH

1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L

1 CCMP 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L

0 CFS DNP

4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K

4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K

1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A

2 CNTC, CSS 0.27 µF X7R 10% 25V MURATA GRM21BR71E274KA01L

1 CREF 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L

1 D1 Schottky 60V 5A COMCHIP CDBC560-G

1 L1 33 µH 20% 6.3A COILCRAFT MSS1278-333MLB

2 Q1, Q2 NMOS 60V 8A VISHAY SI4436DY

1 Q3 NMOS 60V 115mA ON-SEMI 2N7002ET1G

1 RBIAS 19.6 kΩ 1% VISHAY CRCW080519K6FKEA

2 RCSH, ROV1 12.4 kΩ 1% VISHAY CRCW080512K4FKEA

1 RFS 0Ω 1% VISHAY CRCW08050000Z0EA

1 RGAIN 6.49 kΩ 1% VISHAY CRCW08056K49FKEA

2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA

1 RLIM 0.06Ω 1% 1W VISHAY WSL2512R0600FEA

1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA

2 RREF1, RREF2 49.9 kΩ 1% VISHAY CRCW080549K9FKEA

1 RSNS 0.1Ω 1% 1W VISHAY WSL2512R1000FEA

2 RSLP, RUV2 10.0 kΩ 1% VISHAY CRCW080510K0FKEA

1 RT14.3 kΩ 1% VISHAY CRCW080514K3FKEA

1 RUV1 1.82 kΩ 1% VISHAY CRCW08051K82FKEA

1 RUVH 17.8 kΩ 1% VISHAY CRCW080517K8FKEA

1 NTC Thermistor 100 kΩ 5% TDK NTCG204H154J

www.national.com 36

LM3424

DESIGN #3 - BUCK-BOOST Application

300857h6

Features

•Input: 10V to 30V

•Output: 4 LEDs at 2A

•PWM Dimming up to 10kHz

•Analog Dimming

•600 kHz Switching Frequency

37 www.national.com

LM3424

DESIGN #3 Bill of Materials

Qty Part ID Part Value Manufacturer Part Number

1 LM3424 Boost controller NSC LM3424MH

1 CB100 pF COG/NPO 5% 50V MURATA GRM2165C1H101JA01D

1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L

3 CCMP, CREF, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L

1 CF0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L

0 CFS DNP

4 CIN 6.8 µF X7R 10% 50V TDK C5750X7R1H685K

1 CNTC 0.47 µF X7R 10% 25V MURATA GRM21BR71E474KA01L

4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K

1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A

1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF

1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G

1 L1 22 µH 20% 7.2A COILCRAFT MSS1278-223MLB

2 Q1, Q2 NMOS 60V 8A VISHAY SI4436DY

1 Q3 NMOS 60V 260mA ON-SEMI 2N7002ET1G

1 Q4 PNP 40V 200 mA FAIRCHILD MMBT5087

1 Q5 PNP 150V 600 mA FAIRCHILD MMBT5401

1 Q6 NPN 300V 600 mA FAIRCHILD MMBTA42

1 Q7 NPN 40V 200 mA FAIRCHILD MMBT6428

3 RBIAS, RREF1, RREF2 49.9 kΩ 1% VISHAY CRCW080549K9FKEA

2 RCSH, RT12.4 kΩ 1% VISHAY CRCW080512K4FKEA

1 RF10Ω 1% VISHAY CRCW080510R0FKEA

1 RFS 0Ω 1% VISHAY CRCW08050000Z0EA

2 RGAIN, RUV2 10.0 kΩ 1% VISHAY CRCW080510K0FKEA

2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA

1 RLIM 0.04Ω 1% 1W VISHAY WSL2512R0400FEA

1 ROV1 18.2 kΩ 1% VISHAY CRCW080518K2FKEA

1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA

1 RPOT 50 kΩ potentiometer BOURNS 3352P-1-503

1 RPU 4.99 kΩ 1% VISHAY CRCW08054K99FKEA

1 RSER 499Ω 1% VISHAY CRCW0805499RFKEA

1 RSLP 34.0 kΩ 1% VISHAY CRCW080534K0FKEA

1 RSNS 0.05Ω 1% 1W VISHAY WSL2512R0500FEA

1 RUV1 1.43 kΩ 1% VISHAY CRCW08051K43FKEA

1 RUVH 17.4 kΩ 1% VISHAY CRCW080517K4FKEA

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LM3424

DESIGN #4 - BOOST Application

300857h7

Features

•Input: 18V to 38V

•Output: 12 LEDs at 700mA

•85°C - 125°C Thermal Foldback

•Analog Dimming

•700 kHz Switching Frequency

39 www.national.com

LM3424

DESIGN #4 Bill of Materials

Qty Part ID Part Value Manufacturer Part Number

1 LM3424 Boost controller NSC LM3424MH

1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L

3 CCMP, CREF, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L

1 CNTC 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L

1 CFS 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L

4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K

4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K

1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A

1 D1 Schottky 60V 5A COMCHIP CDBC560-G

1 L1 47 µH 20% 5.3A COILCRAFT MSS1278-473MLB

1 Q1 NMOS 60V 8A VISHAY SI4436DY

1 Q2 NPN 40V 200 mA FAIRCHILD MMBT3904

1 Q3, Q4 (dual pack) Dual PNP 40V 200mA FAIRCHILD FFB3906

1 RADJ 100 kΩ potentiometer BOURNS 3352P-1-104

1 RBIAS 9.76 kΩ 1% VISHAY CRCW08059K76FKEA

1 RBIAS2 17.4 kΩ 1% VISHAY CRCW080517K4FKEA

3 RCSH, ROV1, RUV1 12.4 kΩ 1% VISHAY CRCW080512K4FKEA

1 RFS 10Ω 1% VISHAY CRCW080510R0FKEA

1 RGAIN 6.55 kΩ 1% VISHAY CRCW08056K55FKEA

3 RHSP, RHSN, RMAX 1.0 kΩ 1% VISHAY CRCW08051K00FKEA

1 RLIM 0.06Ω 1% 1W VISHAY WSL2512R0600FEA

1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA

2 RREF1, RREF2 49.9 kΩ 1% VISHAY CRCW080549K9FKEA

2 RSLP, RT10.0 kΩ 1% VISHAY CRCW080510K0FKEA

1 RSNS 0.15Ω 1% 1W VISHAY WSL2512R1500FEA

1 RUV2 100 kΩ 1% VISHAY CRCW0805100KFKEA

1 NTC Thermistor 100 kΩ 5% TDK NTCG204H154J

www.national.com 40

LM3424

DESIGN #5 - BUCK-BOOST Application

300857h9

Features

•Input: 10V to 70V

•Output: 6 LEDs at 500mA

•PWM Dimming up to 10 kHz

•5 sec Fade-up

•MosFET RDS-ON Sensing

•700 kHz Switching Frequency

41 www.national.com

LM3424

DESIGN #5 Bill of Materials

Qty Part ID Part Value Manufacturer Part Number

1 LM3424 Boost controller NSC LM3424MH

1 CB100 pF COG/NPO 5% 50V MURATA GRM2165C1H101JA01D

1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L

2 CCMP, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L

1 CREF 0.01 µF X7R 10% 25V MURATA GRM21BR71E103KA01L

1 CF0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L

0 CFS DNP

4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K

1 CNTC 10 µF X7R 10% 10V MURATA GRM21BR71A106KE51L

4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K

1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A

1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF

1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G

1 L1 68 µH 20% 4.3A COILCRAFT MSS1278-683MLB

2 Q1, Q2 NMOS 100V 32A FAIRCHILD FDD3682

1 Q3 NMOS 60V 260mA ON-SEMI 2N7002ET1G

1 Q4 PNP 40V 200mA FAIRCHILD MMBT5087

1 Q5 PNP 150V 600 mA FAIRCHILD MMBT5401

1 Q6 NPN 300V 600mA FAIRCHILD MMBTA42

1 Q7 NPN 40V 200mA FAIRCHILD MMBT6428

3 RBIAS, RREF1, RREF2 49.9 kΩ 1% VISHAY CRCW080549K9FKEA

1 RCSH 12.4 kΩ 1% VISHAY CRCW080512K4FKEA

1 RFS 0Ω 1% VISHAY CRCW08050000Z0EA

3 RGAIN, RT, RUV2 10.0 kΩ 1% VISHAY CRCW080510K0FKEA

2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA

1 ROV1 15.8 kΩ 1% VISHAY CRCW080515K8FKEA

1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA

1 RPU 4.99 kΩ 1% VISHAY CRCW08054K99FKEA

1 RSER 499Ω 1% VISHAY CRCW0805499RFKEA

1 RSNS 0.2Ω 1% 1W VISHAY WSL2512R2000FEA

1 RSLP 24.3 kΩ 1% VISHAY CRCW080524K3FKEA

1 RUV1 1.43 kΩ 1% VISHAY CRCW08051K43FKEA

1 RUVH 17.4 kΩ 1% VISHAY CRCW080517K4FKEA

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LM3424

DESIGN #6 - BUCK Application

300857h8

Features

•Input: 15V to 50V

•Output: 3 LEDS AT 1.25A

•PWM Dimming up to 50 kHz

•Analog Dimming

•700 kHz Switching Frequency

43 www.national.com

LM3424

DESIGN #6 Bill of Materials

Qty Part ID Part Value Manufacturer Part Number

1 LM3424 Boost controller NSC LM3424MH

1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L

2 CCMP, CDIM 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L

0 CFS DNP

1 CNTC 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L

4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K

0 COUT DNP

1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A

1 CREF, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L

1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF

1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G

1 L1 22 µH 20% 7.3A COILCRAFT MSS1278-223MLB

1 Q1 NMOS 60V 8A VISHAY SI4436DY

1 Q2 PMOS 30V 6.2A VISHAY SI3483DV

1 Q3 NMOS 60V 115mA ON-SEMI 2N7002ET1G

1 Q4 PNP 150V 600 mA FAIRCHILD MMBT5401

3 RBIAS, RREF1, RREF2 49.9 kΩ 1% VISHAY CRCW080549K9FKEA

1 RCSH 12.4 kΩ 1% VISHAY CRCW080512K4FKEA

1 RFS 0Ω 1% VISHAY CRCW08050000OZEA

1 RGAIN, RT10.0 kΩ 1% VISHAY CRCW080510K0FKEA

2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA

1 RLIM 0.04Ω 1% 1W VISHAY WSL2512R0400FEA

1 ROV1 21.5 kΩ 1% VISHAY CRCW080521K5FKEA

1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA

1 RPOT 50 kΩ potentiometer BOURNS 3352P-1-503

2 RPU, RUV2 100 kΩ 1% VISHAY CRCW0805100KFKEA

1 RSLP 36.5 kΩ 1% VISHAY CRCW080536K5FKEA

1 RSNS 0.08Ω 1% 1W VISHAY WSL2512R0800FEA

1 RUV1 11.5 kΩ 1% VISHAY CRCW080511K5FKEA

www.national.com 44

LM3424

DESIGN #7 - BUCK-BOOST Application

300857i0

Features

•Input: 15V to 60V

•Output: 8 LEDs at 2.5A

•80°C - 110°C Thermal Foldback

•500 kHz Switching Frequency

•External Synchronization > 500 kHz

45 www.national.com

LM3424

DESIGN #7 Bill of Materials

Qty Part ID Part Value Manufacturer Part Number

1 LM3424 Boost controller NSC LM3424MH

2 CAC, CFLT 100 pF COG/NPO 5% 50V MURATA GRM2165C1H101JA01D

1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L

3 CCMP, CNTC, CSS 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L

1 CFS 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L

4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K

4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K

1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A

1 CREF 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L

1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF

1 L1 22 µH 20% 7.2A COILCRAFT MSS1278-223MLB

1 Q1 NMOS 100V 32A FAIRCHILD FDD3682

1 Q2 PNP 150V 600 mA FAIRCHILD MMBT5401

1 RBIAS 11.5 kΩ 1% VISHAY CRCW080511K5FKEA

2 RCSH, ROV1 12.4 kΩ 1% VISHAY CRCW080512K4FKEA

1 RFS 10Ω 1% VISHAY CRCW080510R0FKEA

1 RFLT 150Ω 1% VISHAY CRCW0805150RFKEA

1 RGAIN 5.49 kΩ 1% VISHAY CRCW08055K49FKEA

2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA

2 RLIM, RSNS 0.04Ω 1% 1W VISHAY WSL2512R0400FEA

1 ROV1 15.8 kΩ 1% VISHAY CRCW080515K8FKEA

1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA

2 RREF1, RREF2 49.9 kΩ 1% VISHAY CRCW080549K9FKEA

1 RSLP 20.5 kΩ 1% VISHAY CRCW080520K5FKEA

1 RT14.3 kΩ 1% VISHAY CRCW080514K3FKEA

1 RUV1 13.7 kΩ 1% VISHAY CRCW080513K7FKEA

1 RUV2 150 kΩ 1% VISHAY CRCW0805150KFKEA

1 NTC Thermistor 100 kΩ 5% TDK NTCG204H154J

www.national.com 46

LM3424

DESIGN #8 - SEPIC Application

300857i8

Features

•Input: 9V to 36V

•Output: 5 LEDs at 750mA

•60°C - 120°C Thermal Foldback

•PWM Dimming up to 30 kHz

•500 kHz Switching Frequency

47 www.national.com

LM3424

DESIGN #8 Bill of Materials

Qty Part ID Part Value Manufacturer Part Number

1 LM3424 Boost controller NSC LM3424MH

1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L

3 CCMP, CNTC, CSS 0.47 µF X7R 10% 25V MURATA GRM21BR71E474KA01L

0 CFS DNP

4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K

4 COUT 10 µF X7R 10% 50V TDK C4532X7R1H106K

1 CSEP 1.0 µF X7R 10% 100V TDK C4532X7R2A105K

1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A

1 CREF 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L

1 D1 Schottky 60V 5A COMCHIP CDBC560-G

2 L1, L2 68 µH 20% 4.3A COILCRAFT DO3340P-683

2 Q1, Q2 NMOS 60V 8A VISHAY SI4436DY

1 Q3 NMOS 60V 115 mA ON-SEMI 2N7002ET1G

1 RBIAS 23.7 kΩ 1% VISHAY CRCW080523K7FKEA

1 RCSH 12.4 kΩ 1% VISHAY CRCW080512K4FKEA

1 RFS 0Ω 1% VISHAY CRCW08050000OZEA

1 RGAIN 9.31 kΩ 1% VISHAY CRCW08059K31FKEA

2 RHSP, RHSN 750Ω 1% VISHAY CRCW0805750RFKEA

1 RLIM 0.04Ω 1% 1W VISHAY WSL2512R0400FEA

1 ROV1 15.8 kΩ 1% VISHAY CRCW080515K8FKEA

1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA

2 RREF1, RREF2 49.9 kΩ 1% VISHAY CRCW080549K9FKEA

1 RSLP 20.0 kΩ 1% VISHAY CRCW080520K0FKEA

1 RSNS 0.1Ω 1% 1W VISHAY WSL2512R1000FEA

1 RT14.3 kΩ 1% VISHAY CRCW080514K3FKEA

1 RUV1 1.62 kΩ 1% VISHAY CRCW08051K62FKEA

1 RUV2 10.0 kΩ 1% VISHAY CRCW080510K0FKEA

1 RUVH 16.9 kΩ 1% VISHAY CRCW080516K9FKEA

1 NTC Thermistor 100 kΩ 5% TDK NTCG204H154J

www.national.com 48

LM3424

Physical Dimensions inches (millimeters) unless otherwise noted

TSSOP-20 Pin EP Package (MXA)

For Ordering, Refer to Ordering Information Table

NS Package Number MXA20A

49 www.national.com

LM3424

Notes

LM3424 Constant Current N-Channel Controller with Thermal Foldback for Driving LEDs

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