LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
®
REVISION HISTORY
Revision Description Issue Date
Rev. 1.0. Initial Issue Jul.25.2004
Rev. 2.0. Revised Vcc Range(Vcc=4.5~5.5V => 2.7~5.5V) Ma
y
.4.2005
Rev. 2.1. Revised ISB1 Ma
y
.13.2005
Rev. 2.2
A
dding PKG type : skinny P-DIP
A
ug.29.2005
Rev. 2.3 Revised VIH(min)=2.4V, VIL(max)=0.6V Feb.24.2006
Rev. 2.4 Revised VIH(min)=2.4V, VIL(max)=0.6V (VCC=2.7~3.6V)
VIH(min)=2.4V, VIL(max)=0.8V (VCC=4.5~5.5V)
Jul.31.2006
Rev. 2.5 Revised STSOP Package Outline Dimension Mar.26.2008
Rev. 2.6
A
dded SL grade
Added ISB1/IDR values when TA = 25℃ and TA = 40℃
Revised FEATURES & ORDERING INFORMATION Lead
free and green package available to Green p ackage available
Added packing type in ORDERING INFORMATION
Revised ISB1(MAX)
Revised VTERM to VT1 and VT2
Revised Test Condition of ISB1/IDR
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Mar.30.2009
Rev. 2.7 Revised PACKAGE OUTLINE DIMENSION in page 8 & 9 Dec.18.2009
Rev. 2.8
Rev. 2.9
Revised PACKAGE OUTLINE DIMENSION in page 10
Revised ORDERING INFORMATION in page 12
Revised PACKAGE OUTLINE DIMENSION in page 9
Ma
y
.7.2010
Aug.25.2010
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
FEATURES
Fast access time : 35/55/70ns
Low power consumption:
Operating current : 20/15/10mA (TYP.)
Standby current : 1μA (TYP.)
Single 2.7~5.5V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage : 1.5V (MIN.)
Green package av ailable
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mm x 13.4mm STSOP
28-pin 300 mil Skinny P-DIP
GENERAL DESCRIPTION
The LY62256 is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The LY62256 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The LY62256 operates from a single power
supply of 2.7~5.5V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product
Family
Operating
Temperature Vcc Range Speed Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
LY62256 0 ~ 70℃ 2.7 ~ 5.5V 35/55/70ns 1µA 20/15/10mA
LY62256(E) -20 ~ 80℃ 2.7 ~ 5.5V 35/55/70ns 1µA 20/15/10mA
LY62256(I) -40 ~ 85℃ 2.7 ~ 5.5V 35/55/70ns 1µA 20/15/10mA
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
32Kx8
MEMORY ARRAY
COLUMN I/O
A0-A14
Vcc
Vss
DQ0-DQ7
CE#
WE#
OE#
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A14 Address Inputs
DQ0 – DQ7 Data Inputs/Outputs
CE# Chip Enable Input
WE# Write Enable Input
OE# Output Enable Input
VCC Power Supply
VSS Ground
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
A14 Vcc
A8
A9
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
LY62256
Skinny P-DIP/P-DIP/SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
A13
CE#
OE#
WE#
STSOP
DQ3
A11
A9
A8
A13
DQ2
A10
A14
A12
A7
A6
A5
Vcc
DQ7
DQ6
DQ5
DQ4
Vss
DQ1
DQ0
A0
A1
A2
A4
A3
LY62256
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
OE#
WE#
CE#
ABSOLUTE MAXIMUN RATINGS*
PARAMETER SYMBOL RATING UNIT
Voltage on VCC relative to VSS VT1 -0.5 to 6.5 V
Voltage on any other pin relative to VSS VT2 -0.5 to VCC+0.5 V
Operating Temperature TA
0 to 70(C grade)
℃
-20 to 80(E grade)
-40 to 85(I grade)
Storage Temperature TSTG -65 to 150 ℃
Power Dissipation PD 1 W
DC Output Current IOUT 50 mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE CE# OE# WE#
I/O OPERATION SUPPLY CURRENT
Standby H X X High-Z ISB,ISB1
Output Disable L H H High-Z ICC,ICC1
Read L L H DOUT I
CC,ICC1
Write L X L DIN I
CC,ICC1
Note: H = VIH, L = VIL, X = Don't care.
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
®
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. TYP.
*
4
MAX. UNIT
Supply Voltage VCC 2.7 3.3 5.5 V
Input High Voltage VIH
*1
2.4 - VCC+0.5 V
Input Low Voltage VIL*2 VCC=2.7~3.6V - 0.5 - 0.6 V
VCC=4.5~5.5V - 0.5 - 0.8 V
Input Leakage Current ILI V
CC ≧ VIN ≧ VSS - 1 - 1
µA
Output Leakage
Current ILO VCC ≧ VOUT ≧VSS,
Output Disabled - 1 - 1 µA
Output High Voltage VOH I
OH = -1m
A
2.4 3.0 - V
Output Low Voltage VOL I
OL = 2m
A
- - 0.4 V
Average Operating
Power supply Current
ICC
Cycle time = Min.
CE# = VIL , II/O = 0mA
Other pins at VIL or VIH
-35 - 20 50
m
A
-55 - 15 45
m
A
-70 - 10 40 m
A
ICC1
Cycle time = 1µs
CE#≦0.2V and II/O = 0mA
other pins at 0.2V or VCC-0.2V
- 3 10 mA
Standby Power
Supply Current
ISB CE# = VIH, other pins at VIL or VIH -1 3 m
A
ISB1
CE# V≧CC-0.2V
Others at 0.2V or
VCC - 0.2V
LL - 1 20
µA
LLE/LLI - 1 30
µA
SL*5
SLE*5
SLI*5
25℃- 1 3
µA
40℃- 1.5 4 µA
SL - 1 10
µA
SLE/SLI - 1 20
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃
5. This parameter is measured at VCC = 3.0V
CAPACITANCE (TA = 25 , f℃ = 1.0MHz)
PARAMETER SYMBOL MIN. MA
X
UNIT
Input Capacitance CIN -6 pF
Input/Output Capacitance CI/O -8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0.2V to VCC -0.2V
Input Rise and Fall Times 3ns
Input and Output Timing Reference Levels 1.5V
Output Load CL= 50pF + 1TTL, IOH
/
IOL = -1mA/2m
A
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
®
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER SYM. LY62256-35 LY62256-55 LY62256-70
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time tRC 35 - 55 - 70 - ns
A
ddress Access Time tAA - 35 - 55 - 70 ns
Chip Enable Access Time tACE - 35 - 55 - 70 ns
Output Enable Access Time tOE - 25 - 30 - 35 ns
Chip Enable to Output in Low-Z tCLZ* 10 - 10 - 10 - ns
Output Enable to Output in Low-Z tOLZ* 5 - 5 - 5 - ns
Chip Disable to Output in High-Z tCHZ* - 15 - 20 - 25 ns
Output Disable to Output in High-Z tOHZ* - 15 - 20 - 25 ns
Output Hold from Address Change tOH 10 - 10 - 10 - ns
(2) WRITE CYCLE
PARAMETER SYM. LY62256-35 LY62256-55 LY62256-70
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
t
WC 35 - 55 - 70 - ns
A
ddress Valid to End of Write tAW 30 - 50 - 60 - ns
Chip Enable to End of Write tCW 30 - 50 - 60 - ns
A
ddress Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width
t
WP 25 - 45 - 55 - ns
Write Recovery Time
t
WR 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 20 - 25 - 30 - ns
Data Hold from End of Write Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High-Z
t
WHZ* - 15 - 20 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
®
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Dout Data Valid
tOHtAA
Address
tRC
Previous Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
Dout Data Valid
tOH
OE#
tACE
CE#
tAA
Address
tRC
High-ZHigh-Z
tCLZ
tOLZ
tOE
tCHZ
tOHZ
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
tWP
tCW
CE#
tWRtAS
tAW
Address
tWC
(4)
TOW
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
tWP
tCW
CE# tWRtAS
tAW
Address
tWC
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBO
L
TEST CONDITION MIN. TYP. MAX. UNIT
VCC for Data Retention VDR CE# V≧CC - 0.2V 1.5 - 5.5 V
Data Retention Current IDR
VCC = 1.5V
CE# V≧CC - 0.2V
Others at 0.2V or VCC-0.2V
LL/LLE/LLI - 0.5 20
µA
SL
SLE
SLI
25℃- 0.5 2 µA
40℃- 1 3
µA
SL - 0.5 8
µA
SLE/SLI - 0.5 15
µA
Chip Disable to Data
Retention Time tCDR See Data Retention
Waveforms (below) 0 - - ns
Recovery Time tR t
RC*- - ns
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Vcc
CE#
VDR ≧1.5V
CE# V≧cc-0.2V
Vcc(min.)
VIH
tRtCDR
VIH
Vcc(min.)
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
®
PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP Package Outline Dimension
UNIT
SYM. INCH.(BASE) MM(REF)
A1 0.015(MIN) 0.381(MIN)
A2 0.155±0.005 3.937±0.127
B 0.020(MAX) 0.508(MAX)
B1 0.060(TYP) 1.524(TYP)
c 0.012(MAX) 0.304(MAX)
D 1.470(MAX) 37.338(MAX)
E 0.6(TYP) 15.24(TYP)
E1 0.55(MAX) 13.970(MAX)
e 0.100(TYP) 2.540(TYP)
eB 0.650±0.020 16.510±0.508
L 0.200(MAX) 5.080(MAX)
S 0.06(MAX) 1.524(MAX)
Q1 0.08(MAX) 2.032(MAX)
Θ 15o(MAX) 15o(MAX)
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
28 pin 330 mil SOP Package Outline Dimension
UNIT
SYM. INCH(BASE) MM(REF)
A 0.120(MAX) 3.048(MAX)
A1 0.002(MIN) 0.05(MIN)
A2 0.098±0.005 2.489±0.127
b 0.016(TYP) 0.406(TYP)
c 0.010(TYP) 0.254(TYP)
D 0.728(MAX) 18.491(MAX)
E 0.340(MAX) 8.636(MAX)
E1 0.465±0.012 11.811±0.305
e 0.050(TYP) 1.270(TYP)
L 0.038(MAX) 0.965(MAX)
L1 0.067±0.008 1.702 ±0.203
S 0.047(MAX) 1.194(MAX)
y 0.004(MAX) 0.102(MAX)
Θ 0o～10o 0
o～10o
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
®
28 pin 8x13.4mm STSOP Package Outline Dimension
1
14 15
28
c
L
HD
D
"A"
b
E
e
12° (2x)12° (2x)
Seating Plane y
28
15
14
1
c
A2A1
L
A
0.254
0
GAUGE PLANE
12° (2X)
12° (2X)
SEATING PLANE
"A" DATAIL VIEW L1
SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES
MIN NOM MAX MIN NOM MAX
A
1.00 1.10 1.20 0.040 0.043 0.047
A
1 0.05 - 0.15 0.002 - 0.006
A
2 0.91 1.00 1.05 0.036 0.039 0.041
b 0.17 0.22 0.27 0.007 0.009 0.011
c 0.07 0.15 0.23 0.003 0.006 0.009
HD 13.20 13.40 13.60 0.520 0.528 0.535
D 11.60 11.80 12.00 0.457 0.465 0.472
E 7.80 8.00 8.20 0.307 0.315 0.323
e - 0.55 - - 0.0216 -
L 0.30 0.50 0.70 0.012 0.020 0.028
L1 0.675 - - 0.027 - -
Y 0.00 - 0.076 0.000 - 0.003
Θ 0° 3° 5° 0° 3° 5°
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
®
28 pin 300 mil PDIP Package Outline Dimension
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
®
ORDERING INFORMATION
LY62256
Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
13
®
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