Compact +30 V / ±15 V 256-Position
Digital Potentiometer
Data Sheet AD5290
Rev. C
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FEATURES
256 position
10 kΩ, 50 kΩ, 100 kΩ
+20 V to +30 V single-supply operation
±10 V to ±15 V dual-supply operation
3-wire SPI®-compatible serial interface
Low temperature coefficient 35 ppm/°C typical
THD 0.006% typical
Midscale preset
Compact MSOP-10 package
Automotive temperature range: −40°C to +125°C
iCMOS™1 process technology
APPLICATIONS
High voltage DAC
Programmable power supply
Programmable gain and offset adjustment
Programmable filters and delays
Actuator control
Audio volume control
Mechanical potentiometer replacement
FUNCTIONAL BLOCK DIAGRAM
V
DD
A
W
B
V
SS
SDI
CLK
CS
SDO
DGND
POR
8 8
RS
8-BIT
LATCH
8-BIT
SERIAL
REGISTER
Q
DCK
AD5290
04716-001
Figure 1.
GENERAL DESCRIPTION
The AD5290 is one of the few high voltage, high performance,
and compact digital potentiometers2, 3 in the market at present.
This device can be used as a programmable resistor or resistor
divider. The AD5290 performs the same electronic adjustment
function as mechanical potentiometers, variable resistors, and
trimmers, with enhanced resolution, solid-state reliability, and
superior temperature stability.
With digital rather than manual control, the AD5290 provides
layout flexibility and allows closed-loop dynamic controllability.
The AD5290 is available in MSOP-10 package and has 10 kΩ,
50 kΩ, and 100 kΩ options. All parts are guaranteed to operate
over the −40°C to +125°C extended automotive temperature range.
1 iCMOS™ Process Technology. For analog systems designers who need high performance ICs at higher voltage levels, iCMOS is a technology platform that enables the
development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, and
increased ac and dc performance.
2 The terms digital potentiometer and RDAC are used interchangeably.
3 The RDAC segmentation is protected by U.S. Patent Number 5,495,245.
AD5290 Data Sheet
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—10 kΩ Version ................................ 3
Electrical Characteristics—50 kΩ, 100 kΩ Versions ............... 5
Interface Timing Characteristics ................................................ 7
3-Wire Digital Interface ................................................................... 8
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Descriptions ............................................ 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 15
Programming the Variable Resistor ......................................... 15
Programming the Potentiometer Divider ............................... 16
3-Wire Serial Bus Digital Interface .......................................... 16
Daisy Chain Operation .............................................................. 16
ESD Protection ........................................................................... 17
Terminal Voltage Operating Range ......................................... 17
Power-Up and Power-Down Sequences .................................. 17
Layout and Power Supply Biasing ............................................ 17
Applications ..................................................................................... 18
High Voltage DAC ...................................................................... 18
Programmable Power Supply ................................................... 18
Audio Volume Control .............................................................. 18
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
11/11—Rev. B to Rev. C
Change to Figure 33 ....................................................................... 18
4/10—Rev. A to Rev. B
Changes to Figure 29 ...................................................................... 16
Updated Outline Dimensions ....................................................... 20
7/09—Rev. 0 to Re v. A
Changes to Features Section ............................................................ 1
Changes to Ordering Guide .......................................................... 20
12/05—Revision 0: Initial Version
Data Sheet AD5290
Rev. C | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 kΩ VERSION
VDD/VSS = ±15 V ± 10%, VA = VDD, VB = VSS or 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ 1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential NL2 R-DNL RWB, VA = NC −1 ±0.3 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = NC −1.5 ±0.7 +1.5 LSB
Nominal Resistor Tolerance
∆R
AB
T
A
= +25°C
−30
+30
%
Resistance Temperature Coefficient3 (∆RAB/RAB)/∆T×106 VAB = VDD, wiper = no connect 35 ppm/°C
Wiper Resistance RW 50 100 Ω
DC CHARACTERISTICS POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4 INL −1 ±0.3 +1 LSB
Differential Nonlinearity4 DNL −1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T×106 Code = 0x80 5 ppm/°C
Full-Scale Error
V
WFSE
Code = 0xFF
−6
−4
0
LSB
Zero-Scale Error VWZSE Code = 0x00 0 +3 +5 LSB
RESISTOR TERMINALS
Voltage Range
5
V
A, B, W
V
SS
V
DD
V
Capacitance6 A, B CA, B f = 1 MHz, measured to GND,
code = 0x80
45 pF
Capacitance6 CW f = 1 MHz, measured to GND,
code = 0x80
60 pF
Common-Mode Leakage ICM VA = VB = VW 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High (CS, CLK, SDI) VIH 2.4 V
Input Logic Low (CS, CLK, SDI)
V
IL
0.8
V
Output Logic High (SDO) VOH RPull-up = 2.2 kΩ to 5 V 4.9 V
Output Logic Low (SDO) VOL IOL = 1.6 mA 0.4 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance6 CIL 5 pF
POWER SUPPLIES
Positive Supply Current IDD VIH = +5 V or VIL = 0 V,
VDD/VSS = ±15 V
15 50 μA
Negative Supply Current
I
SS
V
IH
= +5 V or V
IL
= 0 V,
VDD/VSS = ±15 V
−0.01
−1
μA
Power Dissipation7 PDISS VIH = +5 V or VIL = 0 V,
VDD/VSS = ±15 V
765 μW
Power Supply Rejection Ratio PSRR ΔVDD/ΔVSS = ±15 V ± 10% −0.15 ±0.08 +0.15 %/%
AD5290 Data Sheet
Rev. C | Page 4 of 20
Parameter Symbol Conditions Min Typ 1 Max Unit
DYNAMIC CHARACTERISTICS6, 8, 9
Bandwidth −3 dB BW Code = 0x80 470 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.006 %
VW Settling Time tS VA = 10 V, VB = 0 V, ±1 LSB error
band
4 µs
Resistor Noise Voltage eN_WB RWB = 5 kΩ, f = 1 kHz 9 nV/√Hz
1 Typical represents average reading at +25°C, VDD = +15 V, and VSS = −15 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
3 All parts have a 35 ppm/°C temperature coefficient.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic-level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = +15 V and VSS = −15 V.
Data Sheet AD5290
Rev. C | Page 5 of 20
ELECTRICAL CHARACTERISTICS—50 KΩ, 100 KΩ VERSIONS
VDD/VSS = ±15 V ± 10%, VA = +VDD, VB = VSS or 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ 1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential NL2 R-DNL RWB, VA = NC −0.5 ±0.1 +0.5 LSB
Resistor Nonlinearity2 R-INL RWB, VA = NC −1 ±0.5 +1 LSB
Nominal Resistor Tolerance ∆RAB TA = +25°C −30 +30 %
Resistance Temperature Coefficient3 (∆RAB/RAB)/∆T×106 VAB = VDD, wiper = no connect 35 ppm/°C
Wiper Resistance
R
W
50
100
Ω
DC CHARACTERISTICS POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity
4
INL
−1
±0.5
+1
LSB
Differential Nonlinearity4 DNL −1 ±0.5 +1 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T×106 Code = 0x80 5 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −2.5 −1.6 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 +0.6 +1.5 LSB
RESISTOR TERMINALS
Voltage Range5 VA, B, W VSS VDD V
Capacitance6 A, B
C
A, B
f = 1 MHz, measured to GND,
code = 0x80
45
pF
Capacitance6 CW f = 1 MHz, measured to GND,
code = 0x80
60 pF
Common-Mode Leakage ICM VA = VB = VW 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High (CS, CLK, SDI) VIH 2.4 V
Input Logic Low (CS, CLK, SDI) VIL 0.8 V
Output Logic High (SDO) VOH RPull-up = 2.2 kΩ to 5 V 4.9 V
Output Logic Low (SDO)
V
OL
I
OL
= 1.6 mA
0.4
V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance6 CIL 5 pF
POWER SUPPLIES
Positive Supply Current IDD VIH = +5 V or VIL = 0 V,
VDD/VSS = ±15 V
15 50 μA
Negative Supply Current ISS VIH = +5 V or VIL = 0 V,
VDD/VSS = ±15 V
−0.01 −1 μA
Power Dissipation
7
P
DISS
VIH = +5 V or VIL = 0 V,
VDD/VSS = ±15 V
765
μW
Power Supply Rejection Ratio PSRR ΔVDD/ΔVSS = ±15 V ± 10% −0.05 ±0.01 +0.05 %/%
AD5290 Data Sheet
Rev. C | Page 6 of 20
Parameter Symbol Conditions Min Typ 1 Max Unit
DYNAMIC CHARACTERISTICS6, 8, 9
Bandwidth −3 dB BW RAB = 50 kΩ, code = 0x80 90 kHz
RAB = 100 kΩ, code = 0x80 50 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.002 %
V
W
Settling Time
t
S
V
A
= 10 V, V
B
= 0 V,
±1 LSB error band
4
µs
Resistor Noise Voltage eN_WB RWB = 25 kΩ, f = 1 kHz 20 nV√Hz
1 Typical represents average reading at +25°C, VDD = +15 V, and VSS = −15 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
3 All parts have a 35 ppm/°C temperature coefficient.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification
limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = +15 V and VSS = −15 V.
Data Sheet AD5290
Rev. C | Page 7 of 20
INTERFACE TIMING CHARACTERISTICS
Table 3.
Parameter 1, 2 Symbol Conditions Min Typ Max Unit
Clock Frequency fCLK 4 MHz
Input Clock Pulse Width tCH, tCL Clock level high or low 120 ns
Data Setup Time tDS 30 ns
Data Hold Time tDH 20 ns
CLK to SDO Propagation Delay3 tPD RPull-up = 2.2 kΩ, CL < 20 pF 10 100 ns
CS Setup Time tCSS 120 ns
CS High Pulse Width
t
CSW
150
ns
CLK Fall to CS Fall Hold Time tCSH0 10 ns
CLK Rise to CS Rise Hold Time tCSH 120 ns
CS Rise to Clock Rise Setup tCS1 120 ns
1 See Figure 3 for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. Switching characteristics are measured using VDD = +15 V and VSS = −15 V.
2 Guaranteed by design and not subject to production test.
3 Propagation delay depends on the value of VDD, RPull-up, and CL.
AD5290 Data Sheet
Rev. C | Page 8 of 20
3-WIRE DIGITAL INTERFACE
Data is loaded MSB first.
Table 4. AD5290 Serial Data-Word Format
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
27 20
D7 D6 D5 D4 D3 D2 D1 D0
1
SDI 0
1
CLK 0
1
CS 0
1
V
OUT
0
04716-002
RDAC REGISTER LOAD
Figure 2. AD5290 3-Wire Digital Interface Timing Diagram
(VA = VDD, VB = 0 V, VW = VOUT)
±1 LSB ERROR BAND
±1 LSB
t
S
t
CSW
t
CSH
t
CL
V
DD
V
OUT
0V
CS 0
1
t
CSH0
t
CSS
t
CH
0
1
1
0
0
1
SDI
(DATA IN)
SDO
(DATA OUT)
CLK
D
X
D
X
t
DS
t
DH
D'
X
D'
X
t
PD_MAX
t
CS1
04716-003
Figure 3. Detail Timing Diagram
Data Sheet AD5290
Rev. C | Page 9 of 20
ABSOLUTE MAXIMUM RATINGS
TA = +25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V, +35 V
VSS to GND +0.3 V, −16.5 V
VDD to VSS −0.3 V, +35 V
VA, VB, VW to GND VSS, VDD
Maximum Current
IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 6 kΩ, A Open, ±5 mA
VDD/VSS = 30 V/0 V)1
IWA Continuous (RWA ≤ 6 kΩ, B Open, ±5 mA
VDD/VSS = 30 V/0 V)1
Digital Input and Output Voltages to GND 0 V, +7 V
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature (T
JMAX
)
2
+150°C
Storage Temperature −65°C to +150°C
Lead Temperature
(Soldering, 10 sec to 30 sec)
245°C
Thermal Resistance2 θJA: MSOP-10 230°C/W
1 The maximum terminal current is bound by the maximum current handling
of the switches, maximum power dissipation of the package, and the
maximum applied voltage across any two of the following at a given
resistance: A terminal, B terminal, and W terminal.
2 Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5290 Data Sheet
Rev. C | Page 10 of 20
PIN CONFIGURATION AND DESCRIPTIONS
04716-004
A
1
B
2
V
SS 3
GND
4
CS
5
W
10
V
DD
9
SDO
8
SDI
7
CLK
6
AD5290
TOP VIEW
(Not to Scale)
Figure 4. AD5290 Pin Configuration
Table 6. AD5290 Pin Function Descriptions
Pin No. Mnemonic Description
1 A A Terminal. VSS ≤ VA ≤ VDD.
2 B B Terminal. VSS ≤ VB ≤ VDD.
3 VSS Negative Supply. Connect to 0 V for single-supply applications.
4 GND Digital Ground.
5 CS Chip Select Input; Active Low. When CS returns high, data is loaded into the wiper register.
6 CLK Serial Clock Input. Positive edge triggered.
7 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
8 SDO Serial Data Output Pin. Internal N-Ch FET with open-drain output that requires external pull-up resistor.
It shifts out the previous eight SDI bits that allow daisy-chain operation of multiple packages.
9
V
DD
Positive Power Supply.
10 W W Terminal. VSS ≤ VW ≤ VDD.
Data Sheet AD5290
Rev. C | Page 11 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
–1.00
04716-029
CODE (Decimal)
RHEOSTAT MODE INL (LSB)
256
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
32 64 96 128 160 192 224
VDD = 16.5V
–40°C
+25°C
+125°C
Figure 5. Resistance Step Position Nonlinearity Error vs. Code
1.0
–1.00
04716-030
CODE (Decimal)
RHEOSTAT MODE DNL (LSB)
256
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
32 64 96 128 160 192 224
VDD = 16.5V
–40°C
+25°C
+125°C
Figure 6. Resistance Step Change Differential Nonlinearity Error vs. Code
1.0
–1.00
04716-031
CODE (Decimal)
POTENTIOMETER MODE INL (LSB)
256
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
32 64 96 128 160 192 224
VDD = 16.5V
–40°C
+25°C
+125°C
Figure 7. Potentiometer Divider Nonlinearity Error vs. Code
1.0
–1.00
04716-032
CODE (Decimal)
POTENTIOMETER MODE DNL (LSB)
256
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
32 64 96 128 160 192 224
VDD = 16.5V
–40°C
+25°C
+125°C
Figure 8. Potentiometer Divider Differential Nonlinearity Error vs. Code
20
–4
–40
04716-005
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
16
12
8
4
0
–20 0 20 40 60 80 100 120
IDD @ VDD/V
SS
= 30V/0V
I
DD
@ V
DD
/V
SS
= ±15V
I
SS
@ V
DD
/V
SS
= 30V/0V
I
SS
@ V
DD
/V
SS
= ±15V
Figure 9. Supply Current IDD vs. Temperature
–40
04716-007
TOTAL RESISTANCE, R
AB
(kΩ)
–20 0 20 40 60 80 100 120
120
100
80
60
40
20
0
TEMPERATURE (°C)
10kΩ
50kΩ
100kΩV
DD
/V
SS
= ±15V
Figure 10. Total Resistance vs. Temperature
AD5290 Data Sheet
Rev. C | Page 12 of 20
100
–1000
04716-033
CODE (Decimal)
RHEOSTAT MODE TEMPCO (ppm/°C)
256
80
60
40
20
0
–20
–40
–60
–80
32 64 96 128 160 192 224
10k
50k
100k
Figure 11. (ΔRWB/RWB)/ΔT Rheostat Mode Tempco
100
–1000
04716-034
CODE (Decimal)
POTENTIOMETER MODE TEMPCO (ppm/°C)
256
80
60
40
20
0
–20
–40
–60
–80
32 64 96 128 160 192 224
10k
50k
100k
Figure 12. (ΔVWB/VWB)/ΔT Potentiometer Mode Tempco
0
–601k
04716-022
(Hz)
(dB)
1M
10k 100k
–6
–12
–18
–24
–30
–36
–42
–48
–54
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
Figure 13. 10 kΩ Gain vs. Frequency vs. Code
0
–601k
04716-023
(Hz)
(dB)
1M
10k 100k
–6
–12
–18
–24
–30
–36
–42
–48
–54
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
Figure 14. 50 kΩ Gain vs. Frequency vs. Code
0
–601k
04716-024
(Hz)
(dB)
1M
10k 100k
–6
–12
–18
–24
–30
–36
–42
–48
–54
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
Figure 15. 100 kΩ Gain vs. Frequency vs. Code
04716-035
Figure 16. Midscale Transition Glitch
Data Sheet AD5290
Rev. C | Page 13 of 20
–60
0
100
04716-036
FREQUENCY (Hz)
POWER SUPPLY REJECTION RATIO (dB)
1M
1k 10k 100k
–40
–20
CODE = 80H, VDD/VSS = ±15V, V
A
/V
B
= ±10V
–PSRR @ V
DD
/V
SS
= ±15V DC ± 10% p-p AC
+PSRR @ V
DD
/V
SS
= ±15V DC ± 10% p-p AC
Figure 17. Power Supply Rejection vs. Frequency
1
0.000110
04716-009
FREQUENCY (Hz)
THD + N (%)
100k
100 1k 10k
0.001
0.01 10kΩ
50kΩ
100kΩ
V
DD
/V
SS
= ±15V
CODE = MIDSCALE
V
IN
= 1V
RMS
Figure 18. Total Harmonic Distortion Plus Noise vs. Frequency
1
0.001
0.001
04716-010
AMPLITUDE (V)
THD + N (%)
10
0.01 0.1 1
0.01
0.1
V
DD
/V
SS
= ±15V
CODE = MIDSCALE
f
IN
= 1kHz
10kΩ
50kΩ
100kΩ
Figure 19. Total Harmonic Distortion Plus Noise vs. Amplitude
6
00
04716-027
CODE (Decimal)
THEORETICAL IWB_MAX (mA)
256
5
4
3
2
1
64 128 192
VDD/VSS = 30V/0V
VA = VDD
VB = 0V
RAB = 10kΩ
R
AB
= 50kΩ
R
AB
= 100kΩ
Figure 20. Theoretical Maximum Current vs. Code
140
0
10k
04716-037
FREQUENCY (Hz)
SUPPLY CURRENT IDD (µA)
10M
100k 1M
120
100
80
60
40
20
VDD = +15V
VSS = –15V
VDIG = +5V
CODE = FF
CODE = AA
Figure 21. Supply Current IDD vs. Frequency
10
0
10k
04716-038
FREQUENCY (Hz)
SUPPLY CURRENT ISS (nA)
10M
100k 1M
VDD = +15V
VSS = –15V
VDIG = +5V
CODE = FF
CODE = AA
8
6
4
2
Figure 22. Supply Current ISS vs. Frequency
AD5290 Data Sheet
Rev. C | Page 14 of 20
1000
100
04716-039
DIGITAL INPUT VOLTAGE V
IH
(V)
SUPPLY CURRENT I
DD
(µA)
5
100
1234
V
DD
/V
SS
= ±16.5V
Figure 23. Supply Current vs. Digital Input Voltage
04716-040
Figure 24. Digital Feedthrough
04716-041
Figure 25. Large Signal Settling Time, Code = 0x00 to 0xFF
Data Sheet AD5290
Rev. C | Page 15 of 20
THEORY OF OPERATION
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The part operates in the rheostat mode when only two termi-
nals are used as a variable resistor. The unused terminal can
be floating or tied to the W terminal as shown in Figure 26.
A
W
B
A
W
B
A
W
B
04716-011
Figure 26. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 10 kΩ, 50 kΩ, and 100 kΩ with ±30% toler-
ance and has 256 tap points accessed by the wiper terminal. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings. Figure 27 shows a simplified RDAC structure.
4R
S
4R
S
4R
S
2R
S
2R
S
R
S
R
W
R
W
W
R
S
2R
S
2R
S
4R
S
4R
S
A
R
W
B
8-BIT ADDRESS
DECODER
04716-012
Figure 27. AD5290 Simplified RDAC Circuit.
(RS = Step Resistor, RW = Wiper Resistor)
In order to achieve optimum cost performance, Analog Devices
has patented the RDAC segmentation architecture for all the
digital potentiometers. In particular, the AD5290 employs a
3-stage segmentation approach as shown in Figure 27. As
a result, the general equation determining the digitally
programmed output resistance between the W terminal
and B terminal is
W
AB
WB RR
D
DR ×+×= 3
256
)( (1)
where:
D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register from 0 to 255.
RAB is the end-to-end resistance.
RW is one of the wiper resistances contributed by the on
resistance of an internal switch.
The AD5290 wiper switch is designed with the transmission
gate CMOS topology and with the gate voltage derived from
VDD. The wiper resistance, RW, is a function of VDD and
temperature. Contrary to the temperature coefficient of the RAB,
which is only 35 ppm/°C, the temperature coefficient of the wiper
resistance is significantly higher because the wiper resistance
doubles from 25°C to 125°C. As a result, the user must take into
consideration the contribution of RW on the desirable
resistance. On the other hand, the wiper resistance is insensitive
to the tap point potential. As a result, RW remains relatively flat
at a given VDD and temperature at various codes.
Assuming that an ideal 10 kΩ part is used, the wiper’s first
connection starts at the B terminal for the programming code
of 0x00 where SWB is closed. The minimum resistance between
Terminal W and Terminal B is, therefore, generally 150 Ω. The
second connection is the first tap point, which corresponds to
189 Ω (RWB = 1/256 × RAB + 3RW = 39 Ω + 150 Ω) for code 0x01,
and so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at 10,110 Ω.
In the zero-scale condition, a finite total wiper resistance of
150 Ω is present. Regardless of which setting the part is oper-
ating in, care should be taken to limit the current between
the A terminal to B terminal, W terminal to A terminal, and
W terminal to B terminal, to the maximum dc current of 5 mA
or pulse current of 20 mA. Otherwise, degradation, or possible
destruction of the internal switch contact, can occur.
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, RWA .
RWA starts at the maximum resistance value and decreases as
the data loaded into the latch increases. The general equation
for this operation is
W
ABWA RR
D
DR ×+×
−
=3
256
256
)(
(2)
AD5290 Data Sheet
Rev. C | Page 16 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider
at wiper to B and wiper to A proportional to the input voltage
at A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
V
I
W
B
V
O
04716-013
Figure 28. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage
is equal to the voltage applied across Terminal A and Terminal B,
divided by the 256 positions of the potentiometer divider. The
general equation defining the output voltage at VW with respect
to ground for any valid input voltage applied to Terminal A and
Terminal B is
B
A
W
V
D
V
D
DV ×
−
+×= 256
256
256
)(
(3)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
3-WIRE SERIAL BUS DIGITAL INTERFACE
The AD5290 contains a 3-wire digital interface (CS, CLK,
and SDI). The 8-bit serial word must be loaded MSB first.
The format of the word is shown in Tabl e 4. The positive edge
sensitive CLK input requires clean transitions to avoid clocking
incorrect data into the serial input register. Standard logic fami-
lies work well. When CS is low, the clock loads data into the
serial register on each positive clock edge.
The data setup and data hold times in the Specifications section
determine the valid timing requirements. The AD5290 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
DAISY CHAIN OPERATION
SDO shifts out the SDI content in the previous frame; thus it
can be used for daisy-chaining multiple devices. The SDO pin
contains an open drain N-Ch MOSFET and requires a pull-
up resistor if the SDO function is used. Users need to tie the
SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
resistor and the capacitive loading at the SDO to SDI interface
can induce time delay to the subsequent devices.
For example, in Figure 29, if two AD5290s are daisy-chained, a
total of 16 bits of data are required for each operation. The first
set of eight bits goes to U2, and the second set of eight bits goes
to U1. The CS should be kept low until all 16 bits are clocked
into their respective serial registers. The CS is then pulled high
to complete the operation.
AD5290
U1
SDOSDI
CLKCS
AD5290
U2
SDO
SDI
CLK
CS
µC
+5V
R
PU
2.2kΩ
MOSI
SSSCLK
04716-014
Figure 29. Daisy Chain Configuration
Data Sheet AD5290
Rev. C | Page 17 of 20
ESD PROTECTION
All digital inputs are protected with a series input resistor and
a Zener ESD structure, as shown in Figure 30. These structures
apply to digital input pins, Pin CS, Pin CLK, Pin SDI, and
Pin SDO.
LOGIC
340Ω
GND
04716-015
Figure 30. Equivalent ESD Protection Circuit
All analog terminals are also protected by Zener ESD protection
diodes, as shown in Figure 31.
V
SS
V
DD
A
W
B
04716-016
Figure 31. Equivalent ESD Protection Analog Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD5290 VDD and VSS power supplies define the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. The AD5290 can operate in single supply from +4.5 V to
+33 V or dual supply from ±4.5 V to ±16.5 V. T h e AD5290 is
functional at low supply voltages such as 4.5 V, but the
performance parameters are not guaranteed.
The voltages present on Terminal A, Terminal B, and Terminal W
that are more positive than VDD or more negative than VSS are
clamped by the internal forward-biased diodes (Figure 31).
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W
(Figure 31), it is important to power VDD/VSS before applying
any voltage to Terminal A, Terminal B, and Terminal W.
Otherwise, the diodes are forward-biased such that VDD/VSS
are powered unintentionally and affect the system. Similarly,
VDD/VSS should be powered down last. The ideal power-up
sequence is as follows: GND, VDD, VSS, digital inputs, and
VA/VB/VW. The order of powering VA, VB, VW, and the digital
inputs is not important, as long as they are powered after
VDD/VSS.
LAYOUT AND POWER SUPPLY BIASING
It is good practice to use a compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible, with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR),
1 µF to 10 µF tantalum or electrolytic capacitors, should be
applied at the supplies to minimize any transient disturbance
and to filter low frequency ripple. Figure 32 illustrates the basic
supply-bypassing configuration for the AD5290.
The ground pin of the AD5290 is a digital ground reference.
To minimize the digital ground bounce, the AD5290 digital
ground terminal should be joined remotely to the analog
ground (Figure 32).
VDD
VDD
VSS VSS GND
C3
AD5290
C4
C1
+
+C2
10µF
10µF0.1µF
0.1µF
04716-017
Figure 32. Power Supply Bypassing
AD5290 Data Sheet
Rev. C | Page 18 of 20
APPLICATIONS
HIGH VOLTAGE DAC
AD5290 can be configured as a high voltage DAC, with out-
put voltage as high as 30 V. The circuit is shown in Figure 33.
The output is
)]1(V2.1[
256
)(
1
2
R
RD
DVO (4)
where D is the decimal code from 0 to 255.
AD5290
U2
OP284
V+
V–
OP284
V
OUT
V
DD
U1B
V
DD
R
BIAS
ADR512
D1
R2
R1
B
100kΩ
0
4716-018
U1A
Figure 33. High Voltage DAC
PROGRAMMABLE POWER SUPPLY
With a boost regulator, such as ADP1611, AD5290 can be used
as the variable resistor at the regulator’s FB pin to provide the
programmable power supply (Figure 34). The output is
]
)(
1[V23.1
2
256
R
R
VAB
D
O
(5)
AD5290’s VDD is derived from the output. Initially, L1 acts as
a short, and VDD is one diode voltage drop below +5 V. The
output slowly establishes the final value.
AD5290
ADP1611
1.23V
C
C
150pF
R
C
220k
C
OUT
10F
V
OUT
D1
L1
4.7H
IN
GND
SS
FB
RT SW
COMP
U2
C1
0.1F
V
DD
R1
100k
A
W
B
C
IN
10F
5V
R2
8.5kC
SS
22nF
04716-019
U1
Figure 34. Programmable Power Supply
AUDIO VOLUME CONTROL
Because of its good THD performance and high voltage
capability, AD5290 can be used as a digital volume control.
If AD5290 is used directly as an audio attenuator or gain
amplifier, a large step change in the volume level at any arbi-
trary time can lead to an abrupt discontinuity of the audio
signal causing an audible zipper noise. To prevent this, a zero-
crossing window detector can be inserted to the CS line to
delay the device update until the audio signal crosses the
window. Since the input signal can operate on top of any
dc level rather than absolute zero volt level, zero-crossing in
this case means the signal is ac-coupled, and the dc offset
level is the signal zero reference point.
The configuration to reduce zipper noise (Figure 35) and the
results of using this configuration are shown in Figure 36. The
input is ac-coupled by C1 and attenuated down before feeding
into the window comparator formed by U2, U3, and U4B
(Figure 35). U6 is used to establish the signal zero reference.
The upper limit of the comparator is set above its offset and,
therefore, the output pulses high whenever the input falls
between 2.502 V and 2.497 V (or 0.005 V window) in this
example. This output is AND’ed with the chip select signal
such that the AD5290 updates whenever the signal crosses
the window. To avoid a constant update of the device, the
chip select signal should be programmed as two pulses, rather
than as one shown in Figure 36.
In Figure 35, the lower trace shows that the volume level changes
from a quarter-scale to full-scale when a signal change occurs
near the zero-crossing window.
Data Sheet AD5290
Rev. C | Page 19 of 20
R1
100kΩ
R2
200Ω
5V
V
IN
V+
V–
AD8541
5V
U6
R3
100kΩ
R4
90kΩ
R5
10kΩ
C1
1µF
V
DD
V
SS
CS
CLK
SDI
V+
V–
AD5290
100kΩ
+15V
–15V
C3
0.1µF
C2
0.1µF
A
B
W
GND
SDI
CLK
CS
U1
V+
V+
V–
V–
ADCM371
ADCM371
+15V
–15V
+5V
+5V
U3
U2
V
OUT
U5
U4A
U4B
16
2
4
5
04716-028
7408 7408
Figure 35. Audio Volume Control with Zipper Noise Reduction
04716-021
CHANNEL 1
FREQ = 20.25kHz
1.03V p-p
1
2
Figure 36. Input (Trace 1) and Output (Trace 2) of the Circuit in Figure 35
(The Command of Volume Change May Occur at Any Time, but the Level Change Occurs Only Near the Zero-Crossing Window)
AD5290 Data Sheet
Rev. C | Page 20 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 37. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 RAB (kΩ) Temperature Range Package Description Package Option Branding
AD5290YRMZ10 10 –40°C to +125°C 10-Lead MSOP RM-10 D4U
AD5290YRMZ10-R7 10 –40°C to +125°C 10-Lead MSOP RM-10 D4U
AD5290YRMZ50 50 –40°C to +125°C 10-Lead MSOP RM-10 D4T
AD5290YRMZ50-R7
50
–40°C to +125°C
10-Lead MSOP
RM-10
D4T
AD5290YRMZ100 100 –40°C to +125°C 10-Lead MSOP RM-10 D4V
AD5290YRMZ100-R7 100 –40°C to +125°C 10-Lead MSOP RM-10 D4V
EVAL-AD5290EBZ 10 Evaluation Board
1 Z = RoHS Compliant Part.
©2005-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04716-0-11/11(C)
