General Description
The MAX13030E–MAX13035E 6-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13030E–MAX13035E are ideally suited for memo-
ry-card level translation, as well as generic level trans-
lation in systems with six channels. Externally applied
voltages, VCC and VL, set the logic levels on either side
of the device. Logic signals present on the VLside of
the device appear as a higher voltage logic signal on
the VCC side of the device and vice versa. The
MAX13035E features a CLK_RET output that returns the
same clock signal applied to the CLK_VLinput.
The MAX13030E–MAX13035E operate at full speed
with external drivers that source as little as 4mA output
current. Each I/O channel is pulled up to VCC or VLby
an internal 30µA current source, allowing the
MAX13030E–MAX13035E to be driven by either push-
pull or open-drain drivers.
The MAX13030E–MAX13034E feature an enable (EN)
input that places the device into a low-power shutdown
mode when driven low. The MAX13030E–MAX13035E
features an automatic shutdown mode that disables the
part when VCC is less than VL. The state of I/O VCC_
and I/O VL_ during shutdown is chosen by selecting the
appropriate part version (see
Ordering Information/
Selector Guide
).
The MAX13030E–MAX13035E accept VCC voltages
from +2.2V to +3.6V and VLvoltages from +1.62V to
+3.2V, making them ideal for data transfer between
low-voltage ASIC/PLDs and higher voltage systems.
The MAX13030E–MAX13035E are available in 16-bump
UCSP (2mm x 2mm) and 16-pin TQFN (4mm x 4mm)
packages, and operate over the extended -40°C to
+85°C temperature range.
Applications
SD Card Level Translation
MiniSD Card Level Translation
MMC Level Translation
Transflash Level Translation
Memory Stick Card Level Translation
Features
oCompatible with 4mA Input Drivers or Larger
o100Mbps Guaranteed Data Rate
oSix Bidirectional Channels
oClock Return Output (MAX13035E)
oEnable Input (MAX13030E–MAX13034E)
o±15kV ESD Protection on I/O VCC Lines
o+1.62V ≤VL≤+3.2V and +2.2V ≤VCC ≤+3.6V
Supply Voltage Range
oLead-Free, 16-Bump UCSP (2mm x 2mm) and
16-pin TQFN (4mm x 4mm) Packages
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
________________________________________________________________
Maxim Integrated Products
1
19-0626; Rev 0; 1/07
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Ordering Information/Selector Guide
GND GND GND
+1.8V
SYSTEM
CONTROLLER
+3.3V
SD CARD
VLVCC
CLK_RET
CLK_VCC
CLOCK_IN
+3.3V
+1.8V
CLK_VL
0.1μF1μF
0.1μF
MAX13035E
DAT3
DAT2
DAT1
DAT0
CMD
CLOCK
I/O VL_
I/O VL_
I/O VL_
I/O VL_
I/O VL_
I/O VCC_
I/O VCC_
I/O VCC_
I/O VCC_
I/O VCC_
DAT3
DAT2
DAT1
DAT0
CMD
CLOCK
Typical Operating Circuits
PART PIN-PACKAGE I/O VL_ STATE DURING
SHUTDOWN
I/O VCC_ STATE DURING
SHUTDOWN PKG CODE
MAX13030EEBE+ 16 UCSP High impedance High impedance B16-1
MAX13030EETE+ 16 TQFN-EP** High impedance High impedance T1644-4
Functional Diagram and Pin Configurations appear at end
of data sheet.
Typical Operating Circuits continued at end of data sheet.
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
+
Denotes a lead-free package.
**
EP = Exposed paddle.
Ordering Information/Selector guide continued at end of
data sheet.
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VCC, VL.....................................................................-0.3V to +4V
I/O VCC_, CLK_VCC ....................................-0.3V to (VCC + 0.3V)
I/O VL_, CLK_VL, CLK_RET ..........................-0.3V to (VL+ 0.3V)
EN.............................................................................-0.3V to +4V
Short-Circuit Duration I/O VL_, I/O VCC_,
CLK_VCC, CLK_VL, CLK_RET to GND.......................Continuous
Continuous Power Dissipation (TA= +70°C)
16-Bump UCSP (derate 8.2mW/°C)..............................660mW
16-Pin TQFN (derate 25.0mW/°C)...............................2000mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Bump Temperature (soldering)........................................+235°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(VCC = +2.2V to +3.6V, VL= +1.62V to +3.2V, EN = VL, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC =
+3.3V, VL= +1.8V and TA= +25°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
VL Supply Range VL(Note 2) 1.62 3.20 V
VCC Supply Range VCC 2.2 3.6 V
Supply Current from VCC IQVCC I/O VCC_ = VCC, I/O VL_ = VL16 25 µA
Supply Current from VLIQVL I/O VCC_ = VCC, I/O VL_ = VL610µA
TA = +25°C, EN = GND or VL > VCC + 0.7V,
MAX13030E–MAX13034E 24
VCC Shutdown Supply Current ISHDN-VCC TA = +25°C, VL > VCC + 0.7V,
MAX13035E, 24
µA
TA = +25°C, EN = GND or VL > VCC + 0.7V,
MAX13030E–MAX13034E 0.1 4
VL Shutdown Supply Current ISHDN-VL
TA = +25°C, VL > VCC + 0.7V, MAX13035E 0.1 4
µA
I/O VCC_, I/O VL_, CLK_VCC
Tri-State Leakage Current ILEAK TA = +25°C, EN = GND or VL > VCC + 0.7V 0.1 2 µA
EN Input Leakage Current ILEAK_EN TA = +25°C, MAX13030E–MAX13034E 1 µA
VL - VCC Shutdown Threshold
High VTH_H VCC rising -0.2 0.05VL0.7 V
VL - VCC Shutdown Threshold
Low VTH_L VCC falling -0.2 0.1VL0.7 V
I/O VCC_ Pulldown Resistance
During Shutdown RVCC_PD_SD EN = GND, MAX13032E/MAX13034E 10 16.5 23 kΩ
I/O VCC_ Pullup Resistance
During Shutdown RVCC_PU_SD EN = GND, MAX13031E 10 16.5 23 kΩ
I/O VL_ Pulldown Resistance
During Shutdown RVL_PD_SD EN = GND, MAX13033E/MAX13034E 10 16.5 23 kΩ
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O VL_, CLK_VL, CLK_RET
Pullup Resistance During
Shutdown
RVL_PU_SD (VL > VCC + 0.7V), MAX13035E 45 75 105 kΩ
I/O VL_, CLK_VL, CLK_RET
Pullup Current RVL_PU EN = VCC or VL, I/O VL_ = GND 20 µA
I/O VCC_, CLK_VCC Pullup
Current RVCC_PU EN = VCC or VL, I/O VCC_ = GND 20 µA
I/O VL to I/O VCC DC
Resistance RIOVL_IOVCC (Note 3) 3 kΩ
ESD PROTECTION (Note 3)
Human Body Model, CVCC = 1.0µF ±15
IEC 61000-4-2 Air-Gap Discharge,
CVCC = 1.0µF ±12
I/O VCC_, CLK_VCC
IEC 61000-4-2 Contact Discharge,
CVCC = 1.0µF ±8
kV
LOGIC-LEVEL THRESHOLDS
I/O VL_, CLK_VL Input-Voltage
High Threshold VIHL (Note 4) VL -
0.2 V
I/O VL_, CLK_VL Input-Voltage
Low Threshold VILL (Note 4) 0.15 V
I/O VCC_, CLK_VCC Input-
Voltage High Threshold VIHC (Note 4) VCC -
0.4 V
I/O VCC_, CLK_VCC Input-
Voltage Low Threshold VILC (Note 4) 0.2 V
EN Input-Voltage High
Threshold VIH MAX13030E–MAX13034E VL -
0.4 V
EN Input-Voltage Low VIL MAX13030E–MAX13034E 0.4 V
I/O VL_, CLK_VL, CLK_RET
Output-Voltage High VOHL I/O VL_, CLK_VL, CLK_RET source current
= 20µA, I/O VCC_ ≥ VCC - 0.4V 2/3 VLV
I/O VL_, CLK_VL, CLK_RET
Output-Voltage Low VOLL I/O VL_, CLK_VL, CLK_RET sink current =
20µA, I/O VCC_ ≤ 0.2V 1/3 VLV
I/O VCC_, CLK_VCC Output-
Voltage High VOHC I/O VCC_, CLK_VCC source current = 20µA,
I/O VL_ ≥ VL - 0.2V
2/3
VCC V
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.2V to +3.6V, VL= +1.62V to +3.2V, EN = VL, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC =
+3.3V, VL= 1.8V and TA= +25°C.) (Notes 1, 2)
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O VCC_, CLK_VCC Output-
Voltage Low VOLC I/O VCC_, CLK_VCC sink current = 20µA,
I/O VL_ ≤ 0.15V
1/3
VCC V
RISE/FALL TIME ACCELERATOR STAGE (Note 3)
On falling edge 3
Accelerator Pulse Duration On rising edge 3 ns
VL = 1.62V 11
VL-Output-Accelerator Source
Impedance VL = 3.2V 6 Ω
VCC = 2.2V 9
VCC-Output-Accelerator Source
Impedance VCC = 3.6V 8 Ω
VL = 1.62V 9
VL-Output-Accelerator Sink
Impedance VL = 3.2V 8 Ω
VCC = 2.2V 10
VCC-Output-Accelerator Sink
Impedance VCC = 3.6V 9 Ω
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.2V to +3.6V, VL= +1.62V to +3.2V, EN = VL, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC =
+3.3V, VL= 1.8V and TA= +25°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O VCC_, CLK_VCC Rise Time tRVCC RS = 150Ω, CI/OVCC = 10pF, CCLK_VCC =
10pF, push-pull drivers (Figure 1) 2.5 ns
I/O VCC_, CLK_VCC Fall Time tFVCC RS
= 150Ω, C
I /OV C C
= 10p F, C
C LK _V C C
=
10p F ( Figures 1, 2) 2.5 ns
I/O VL_, CLK_VL Rise Time tRVL RS
= 150Ω, C
I /OV L
= 15p F, C
C LK _V L = 15p F,
push-pull drivers (Figure 3) 2.5 ns
I/O VL_, CLK_VL Fall Time tFVL RS
= 150Ω, C
I /OV L
= 15p F, C
C LK _V L = 15p F
( Figures 3, 4) 2.5 ns
Propagation Delay
(Driving I/O VL_, CLK_VL)tPVL-VCC RS = 150Ω, CI/OVCC = 10pF, CCLK_VCC =
10pF, push-pull drivers (Figure 1) 6.5 ns
Propagation Delay
(Driving I/O VCC_, CLK_VCC)tPVCC-VL RS
= 150Ω, C
I /OV L
= 15p F, C
C LK _V L = 15p F,
push-pull drivers (Figure 3) 6.5 ns
Channel-to-Channel Skew tSKEW RS
= 150Ω, C
I /OV C C
= 10p F, C
I /OV L
= 15p F 0.8 ns
Propagation Delay from
I/O VL_ to I/O VCC_ after EN tEN-VCC RLOAD = 1MΩ, CI/OVCC = 10pF (Figure 5)
(MAX13030E–MAX13034E) 5µs
TIMING CHARACTERISTICS
(VCC = +2.2V to +3.6V, VL= +1.62V to +3.2V, CI/OVL ≤15pF, CI/OVCC ≤15pF, RSOURCE = 150Ω, EN = VL, I/O VL_ to I/O VCC_
rise/fall time = 3ns, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL= 1.8V and TA= +25°C.)
(Note 1)
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Propagation Delay from
I/O VCC_ to I/O VL_ after EN tEN-VL RLOAD = 1MΩ, CI/OVL = 15pF (Figure 5)
(MAX13030E–MAX13034E) 5µs
Maximum Data Rate
Push-pull operation, RSOURCE = 150_,
CI/OVCC_ = 10pF, CI/OVL_ = 15pF,
CCLK_VCC = 10pF, CCLK_VL = 15pF
100 Mbps
TIMING CHARACTERISTICS (continued)
(VCC = +2.2V to +3.6V, VL= +1.62V to +3.2V, CI/OVL ≤15pF, CI/OVCC ≤15pF, RSOURCE = 150Ω, EN = VL, I/O VL_ to I/O VCC_
rise/fall time = 3ns, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL= 1.8V and TA= +25°C.)
(Note 1)
Note 1: All units are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: VLmust be less than or equal to VCC - 0.2V during normal operation. However, VLcan be greater than VCC during startup
and shutdown conditions and the part will not latch-up or be damaged.
Note 3: Guaranteed by design.
Note 4: Input thresholds are referenced to the boost circuit.
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
6 _______________________________________________________________________________________
Typical Operating Characteristics
(VCC = 3.3V, VL= 1.8V, CL= 15pF, RSOURCE = 150Ω, data rate = 100Mbps, push-pull driver, TA= +25°C, unless otherwise noted.)
750
780
770
760
800
790
840
830
820
810
850
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VL SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING I/O VL_, VL = 1.8V)
MAX13030E toc01
VCC SUPPLY VOLTAGE (V)
VL SUPPLY CURRENT (μA)
DRIVING ONE I/O VL
0
2
1
4
3
6
5
7
9
8
10
1.6 2.0 2.21.8 2.4 2.6 2.8 3.0 3.2
VL SUPPLY CURRENT vs. VL SUPPLY
VOLTAGE (DRIVING I/O VCC_, VCC = 3.6V)
MAX13030E toc02
VL SUPPLY VOLTAGE (V)
VL SUPPLY CURRENT (mA)
DRIVING ONE I/O VCC
5.0
10.0
7.5
15.0
12.5
22.5
20.0
17.5
25.0
2.2 2.62.4 2.8 3.0 3.2 3.4 3.6
VCC SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING I/O VL_, VL = 1.8V)
MAX13030E toc03
VCC SUPPLY VOLTAGE (V)
VCC SUPPLY CURRENT (mA)
DRIVING ONE I/O VL
15.0
16.0
15.5
17.0
16.5
18.0
17.5
18.5
19.5
19.0
20.0
1.6 2.0 2.21.8 2.4 2.6 2.8 3.0 3.2
VCC SUPPLY CURRENT vs. VL SUPPLY
VOLTAGE (DRIVING I/O VCC_, VCC = 3.6V)
MAX13030E toc04
VL SUPPLY VOLTAGE (V)
VCC SUPPLY CURRENT (mA)
DRIVING ONE I/O VCC
0
4
2
10
8
6
16
14
12
18
-40 10-15 35 60 85
SUPPLY CURRENT
vs. TEMPERATURE (DRIVING I/O VCC_)
MAX13030E toc05
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
DRIVING ONE I/O VCC
ICC
IL
0
6
4
2
8
10
12
14
16
18
20
-40 10-15 35 60 85
SUPPLY CURRENT
vs. TEMPERATURE (DRIVING I/O VL_)
MAX13030E toc06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
ICC
IL
DRIVING ONE I/O VL
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10 2015 25 30 35 40
VL SUPPLY CURRENT vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING I/O VCC_)
MAX13030E toc07
CAPACITIVE LOAD (pF)
VL SUPPLY CURRENT (mA)
DRIVING ONE I/O VCC
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
10 2015 25 30 35 40
VCC SUPPLY CURRENT vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING I/O VL_)
MAX13030E toc08
CAPACITIVE LOAD (pF)
VCC SUPPLY CURRENT (mA)
DRIVING ONE I/O VL
500
800
700
600
900
1000
1100
1200
1300
1400
1500
10 2015 25 30 35 40
RISE/FALL TIME vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING I/O VL_)
MAX13030E toc09
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ps)
tRVCC
tFVCC
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL= 1.8V, CL= 15pF, RSOURCE = 150Ω, data rate = 100Mbps, push-pull driver, TA= +25°C, unless otherwise noted.)
500
1250
1000
750
1500
1750
2000
2250
2500
2750
3000
10 2015 25 30 35 40
RISE/FALL TIME vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING I/O VCC_)
MAX13030E toc10
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ps)
tRVL
tFVL
2.0
3.0
2.5
4.0
3.5
4.5
5.0
10 20 2515 30 35 40
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING I/O VL_)
MAX13030E toc11
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
tPLH
tPHL
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10 2015 25 30 35 40
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING I/O VCC_)
MAX13030E toc12
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
tPHL
tPLH
10ns/div
TYPICAL I/O VL_ DRIVING
(FREQUENCY = 26MHz, CIOVCC = 40pF)
I/O VL_
1V/div
I/O VCC_
2V/div
MAX13030E toc13
10ns/div
TYPICAL I/O VCC_ DRIVING
(FREQUENCY = 26MHz, CIOVL = 15pF)
I/O VCC_
2V/div
I/O VL_
1V/div
MAX13030E toc14
10ns/div
TYPICAL CLK_ VL DRIVING
(FREQUENCY = 26MHz, CCLK_VCC = 40pF)
CLK_ VL
1V/div
CLK_RET
1V/div
MAX13030E toc15
CLK_ VCC
2V/div
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
8 _______________________________________________________________________________________
Pin Description
PIN
MAX13030E–MAX13034E MAX13035E
UCSP TQFN UCSP TQFN
NAME FUNCTION
A1 4 A1 4 I/O VL3 Input/Output 3. Referenced to VL.
A2 6 A2 6 I/O VCC3 Input/Output 3. Referenced to VCC.
A3 7 A3 7 I/O VCC4 Input/Output 4. Referenced to VCC.
A4 9 A4 9 I/O VL4 Input/Output 4. Referenced to VL.
B1 3 B1 3 I/O VL2 Input/Output 2. Referenced to VL.
B2 5 B2 5 I/O VCC2 Input/Output 2. Referenced to VCC.
B3 8 B3 8 I/O VCC5 Input/Output 5. Referenced to VCC.
B4 10 B4 10 I/O VL5 Input/Output 5. Referenced to VL.
C1 2 C1 2 VLLogic-Supply Voltage, +1.62V to +3.2V. Bypass VL to GND with
a 0.1µF capacitor placed as close as possible to the device.
C2 16 C2 16 VCC
Power-Supply Voltage, +2.2V to +3.6V. Bypass VCC to GND with
a 0.1µF ceramic capacitor. For full ESD protection, connect a
1µF ceramic capacitor from VCC to GND as close as possible to
the VCC input.
C3 13 C3 13 GND Ground
C4 11 — — EN Enable Input. Drive EN to GND for shutdown mode, or drive EN to
VL or VCC for normal operation.
D1 1 D1 1 I/O VL1 Input/Output 1. Referenced to VL.
D2 15 D2 15 I/O VCC1 Input/Output 1. Referenced to VCC.
D3 14 — — I/O VCC6 Input/Output 6. Referenced to VCC.
D4 12 — — I/O VL6 Input/Output 6. Referenced to VL.
— — C4 11 CLK_RET Clock Return Output. CLK_RET is the returned signal of a clock
applied to CLK_VL. CLK_RET is referenced to VL.
— — D3 14 CLK_VCC Translator Channel for a Clock Applied to VCC
— — D4 12 CLK_VLTranslator Channel for a Clock Applied to VL
— EP — EP EP Exposed Paddle. Connect exposed paddle to GND.
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
_______________________________________________________________________________________ 9
Test Circuits/Timing Diagrams
MAX13030E–
MAX13035E
tFVCC
tRVCC
I/O VL_
(CLK_VL*) I/O VCC_
(CLK_VCC*)
150Ω
VL
VLVCC
10%
10%
90%
90%
50% 50%
50%
50%
VCC
CIOVCC
tPLH tPHL
tPVL-VCC = tPLH OR tPHL
VCC
EN**
VL
I/O VCC
I/O VL
*MAX13035E ONLY
(CCLK_VCC*)
**MAX13030E–MAX13034E ONLY
Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing
MAX13030E–
MAX13035E
tFVCC
tRVCC
VL
VLVCC
10%
10%
90%
90%
50% 50%
50%
50%
VCC
CIOVCC
I/O VCC
VGATE
VLVCC
EN**
VGATE
I/O VL_
(CLK_VL*)
I/O VCC_
(CLK_VCC*)
*MAX13035E ONLY **MAX13030E–MAX13034E ONLY
(CCLK_VCC*)
tPLH tPHL
tPVL-VCC = tPHL
Figure 2. Open-Drain Driving I/O VL_ Test Circuit and Timing
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
10 ______________________________________________________________________________________
Test Circuits/Timing Diagrams (continued)
MAX13030E–
MAX13035E
tFVL
tRVL
VL
VLVCC
10%
10%
90%
90%
50% 50%
50%
50%
VCC
CIOVL
I/O VCC
VLVCC
EN**
150ΩI/O VL
I/O VL_
(CLK_VL*)
(CCLK_VL*)
I/O VCC_
(CLK_VCC*)
*MAX13035E ONLY **MAX13030E–MAX13034E ONLY
tPLH tPHL
tPVCC-VL = tPLH OR tPHL
Figure 3. Push-Pull Driving I/O VCC_ Test Circuit and Timing
MAX13030E–
MAX13035E
VL
VLVCC
10%
10%
90%
90%
50% 50%
50%
50%
VCC
CIOVL
I/O VL
VLVCC
EN**
tFVL
tRVL
VGATE
I/O VL_
(CLK_VL*)
(CCLK_VL*)
(CCLK_VL*)
I/O VCC_
(CLK_VCC*)
*MAX13035E ONLY **MAX13030E–MAX13034E ONLY
tPLH tPHL
tPVCC-VL = tPHL
Figure 4. Open-Drain Driving I/O VCC_ Test Circuit and Timing
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
______________________________________________________________________________________ 11
Test Circuits/Timing Diagrams (continued)
MAX13030E–
MAX13034E
SOURCE I/O VCC_
CIOVCC
RLOAD
EN
VL
0
VL
VCC
0
0
I/O VL_
I/O VCC_ VCC / 2
EN
VL
I/O VL_
SOURCE
CIOVCC
I/O VCC_
EN
I/O VL_
RLOAD
VCC
t'EN-VCC
EN
VL
0
VL
VCC
0
0
I/O VL_
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
I/O VCC_
VCC / 2
t"EN-VCC
VLVCC
VLVCC
VLVCC
VLVCC
MAX13030E–
MAX13034E
SOURCE
VCC
EN
VL
0
VCC
VL
0
0
I/O VCC_
I/O VL_ VL / 2
EN
I/O VL_ I/O VCC_
SOURCE
EN
t'EN-VL
EN
VL
0
VCC
VL
0
0
I/O VCC_
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
I/O VL_
VL / 2
t"EN-VL
CIOVL
RLOAD
RLOAD
CIOVL
I/O VL_
I/O VCC_
VL
MAX13030E–
MAX13034E
MAX13030E–
MAX13034E
Figure 5. Enable Test Circuit and Timing
MAX13030E–MAX13035E
Detailed Description
The MAX13030E–MAX13035E 6-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13030E–MAX13035E are ideally suited for memory
card level translation, as well as generic level translation
in systems with six channels. Externally applied volt-
ages, VCC and VL, set the logic levels on either side of
the device. Logic signals present on the VLside of the
device appear as a higher voltage logic signal on the
VCC side of the device, and vice versa. The MAX13035E
features a CLK_RET output that returns the same clock
signal applied to the CLK_VL input.
The MAX13030E–MAX13035E operate at full speed
with external drivers that source as little as 4mA output
current. Each I/O channel is pulled up to VCC or VLby
an internal 30µA current source, allowing the
MAX13030E–MAX13035E to be driven by either push-
pull or open-drain drivers.
The MAX13030E–MAX13034E feature an enable (EN)
input that places the device into a low-power shutdown
mode when driven low. The MAX13030E–MAX13035E
features an automatic shutdown mode that disables the
part when VCC is less than VL. The state of I/O VCC_ and
I/O VL_ during shutdown is chosen by selecting the
appropriate part version (see
Ordering Information/
Selector Guide
).
The MAX13030E–MAX13035E accept VCC voltages from
+2.2V to +3.6V and VLvoltages from +1.62V to +3.2V.
Level Translation
For proper operation, ensure that +2.2V ≤VCC ≤+3.6V,
and +1.62V ≤VL≤VCC - 0.2V. When power is supplied to
VLwhile VCC is either missing or less than VL,
the MAX13030E–MAX13035E automatically enters a
low- power mode. In addition, the MAX13030E–
MAX13034E enters a low-power mode if EN = 0V. This
allows VCC to be disconnected and still have a known
state on I/O VL_. The maximum data rate depends heavily
on the load capacitance (see the
Typical Operating
Characteristics Rise/Fall Times
), output impedance of the
driver, and the operating voltage range.
Input Driver Requirements
The MAX13030E–MAX13035E architecture is based on
an nMOS pass gate and output accelerator stages (see
Figure 6). Output accelerator stages are always in tri-
state mode except when there is a transition on any of
the translators on the input side, either I/O VL_, CLK_VL,
I/O VCC_, or CLK_VCC. A short pulse is then generated
during which the output accelerator stages become
active and charge/discharge the capacitances at the
I/Os. Due to its architecture, both input stages become
active during the one-shot pulse. This can lead to some
current feeding into the external source that is driving the
translator. However, this behavior helps to speed up the
transition on the driven side.
The MAX13030E–MAX13035E have internal current
sources capable of sourcing 30µA to pullup the I/O
lines. These internal pullup current sources allow the
inputs to be driven with open-drain drivers, as well as
push-pull drivers. It is not recommended to use exter-
nal pullup resistors on the I/O lines. The architecture of
the MAX13030E–MAX13035E permit either side to be
driven with a minimum of 4mA drivers or larger.
Output Load Requirements
The MAX13030E–MAX13035E I/O are designed to drive
CMOS inputs. Do not load the I/O lines with a resistive
load less than 25kΩand do not place an RC circuit at
the input of these devices to slow down the edges. If a
slower rise/fall time is required, refer to the MAX3000E/
MAX3001E logic-level translator datasheet. For I2C
level translation, refer to the MAX3372E–MAX3379E/
MAX3390E–MAX3393E datasheet.
Shutdown Mode
The MAX13030E–MAX13034E feature an enable (EN)
input that places the device into a low-power shutdown
mode when driven low. The MAX13030E–MAX13035E
features an automatic shutdown mode that disables the
part when VCC is missing or less than VL.
6-Channel High-Speed Logic-Level Translators
12 ______________________________________________________________________________________
30μA
V
L
ENABLE
ENABLE
ENABLE
V
CC
30μA
BOOST
CIRCUIT
I/O V
L_
V
L
V
CC
BOOST
CIRCUIT
V
CC
V
L
I/O V
CC_
NOTES: 1) THE MAX13030E–MAX13034E ARE ENABLED WHEN
V
L
<
VCC - 0.2V
AND EN = V
L
.
2) THE MAX13035E IS ENABLED WHEN V
L
<
VCC - 0.2V
.
Figure 6. Simplified Functional Diagram for One I/O Line
Clock Return (CLK_RET)
The MAX13035E features a CLK_RET output that returns
the clock signal applied to CLK_VL. CLK_VLand
CLK_VCC are identical to the other I/O channels, the only
difference being that CLK_VCC is internally tied to the
VCC side of CLK_RET (see the
Functional Diagram
).
Application Information
Layout Recommendations
Use standard high-speed layout practices when laying
out a board with the MAX13030E–MAX13035E. For
example, to minimize line coupling, place all other signal
lines not connected to the MAX13030E–MAX13035E at
least 1x the substrate height of the PCB away from the
input and output lines of the MAX13030E–MAX13035E.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass VLand VCC to ground with 0.1µF ceram-
ic capacitors. Place all capacitors as close as possible
to the power-supply inputs. For full ESD protection,
bypass VCC with a 1µF ceramic capacitor located as
close as possible to the VCC input.
Unidirectional vs. Bidirectional Level
Translator
The MAX13030E–MAX13035E bidirectional level trans-
lators can operate as a unidirectional device to trans-
late signals without inversion. These devices provide
the smallest solution (UCSP package) for unidirectional
level translation without inversion.
Use with External Pullup/Pulldown
Resistors
Due to the architecture of the MAX13030E–
MAX13035E, it is not recommended to use external
pullup or pulldown resistors on the bus. In certain appli-
cations, the use of external pullup or pulldown resistors
is desired to have a known bus state when there is no
active driver on the bus. For example, this may happen
when interfacing to a memory card slot with no memory
card inserted. The MAX13030E–MAX13035E include
internal pullup current sources that set the bus state
when the device is enabled. In shutdown mode,
the state of I/O VCC_ and I/O VL_ is dependent on
the selected part version (see
Ordering Information/
Selector Guide
for further information).
Open-Drain Signaling
The MAX13030E–MAX13035E are designed to pass
open-drain as well as CMOS push-pull signals. When
used with open-drain signaling, the rise time is domi-
nated by the interaction of the internal pullup current
source and the parasitic load capacitance. The
MAX13030E–MAX13035E include internal rise time
accelerators to speed up transitions, eliminating any
need for external pullup resistors.
SD Card Detection
SD, MiniSD, MMC and similar types of cards provide
detection of a card through a pullup resistor on one of
the DAT lines, or by use of a mechanical switch. This
pullup resistor is internal to the memory card itself. The
MAX13030E–MAX13035E only support detection of
a memory card through a mechanical switch, and it
is recommended that the internal resistor for card
detection be switched off by the command interface.
For example, when using SD cards, the command
SET_CLR_CARD_DETECT (ACMD42) disables this
resistor.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow tempera-
ture profiles, as well as the latest information on reliabil-
ity testing results, go to Maxim’s web site at
www.maxim-ic.com/ucsp to find the Application Note:
UCSP – A Wafer-Level Chip-Scale Package.
Chip Information
Process: BiCMOS
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
______________________________________________________________________________________ 13
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
14 ______________________________________________________________________________________
MAX13030E–
MAX13034E
VLVCC
MAX13035E
VLVCC
I/O VL1
I/O VL2
I/O VL3
I/O VL4
I/O VL5
CLK_ VL
CLK_RET
I/O VL1
I/O VL2
I/O VL3
I/O VL4
I/O VL5
I/O VL6
I/O VL1I/O VCC1
I/O VCC2
I/O VCC3
I/O VCC4
I/O VCC5
I/O VCC6
GND
EN
GND
I/O VCC1
I/O VCC2
I/O VCC3
I/O VCC4
I/O VCC5
CLK_ VCC
Functional Diagram
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
______________________________________________________________________________________ 15
16 TQFN (4mm x 4mm)
GND
16
1234
12 11 10 9
15
14
13
5
6
7
8
VCC
I/O VCC1
I/O VCC6
I/O VL6
EN
I/O VL5
I/O VL4
VL
I/O VL2
I/O VL3
I/O VCC2
I/O VCC3
I/O VCC4
I/O VCC5
I/O VL1
MAX13030E–
MAX13034E
TOP VIEW
*EP
+
*CONNECT EXPOSED PADDLE TO GROUND
16 UCSP (2mm x 2mm)
A
B
C
12 3
4
I/O VCC3I/O VL4
I/O VL3I/O VCC4
I/O VCC2I/O VL5
I/O VL2I/O VCC5
MAX13030E–MAX13034E
VCC EN
VLGND
TOP VIEW
(BUMPS ON BOTTOM)
D
I/O VCC1I/O VL6
I/O VL1I/O VCC6
+
Pin Configurations
16 TQFN (4mm x 4mm)
GND
16
1234
12 11 10 9
15
14
13
5
6
7
8
VCC
I/O VCC1
CLK_VCC
CLK_VL
CLK_RET
I/O VL5
I/O VL4
VL
I/O VL2
I/O VL3
I/O VCC2
I/O VCC3
I/O VCC4
I/O VCC5
I/O VL1
MAX13035E
TOP VIEW
*EP
+
*CONNECT EXPOSED PADDLE TO GROUND
16 UCSP (2mm x 2mm)
A
B
C
12 3
4
I/O VCC3I/O VL4
I/O VL3I/O VCC4
I/O VCC2I/O VL5
I/O VL2I/O VCC5
MAX13035E
VCC CLK_RET
VLGND
TOP VIEW
(BUMPS ON BOTTOM)
D
I/O VCC1CLK_VL
I/O VL1CLK_VCC
+
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
16 ______________________________________________________________________________________
GND GND GND
+1.8V
SYSTEM
CONTROLLER
+3.3V
SYSTEM
VLVCC
I/O VL_ I/O VCC_
DATA DATA
+3.3V
+1.8V
EN
EN
0.1μF1μF
0.1μF
MAX13030E–
MAX13034E
66
Typical Operating Circuits (continued)
PART PIN-PACKAGE I/O VL_ STATE DURING
SHUTDOWN
I/O VCC_ STATE DURING
SHUTDOWN PKG CODE
MAX13031EEBE+* 16 UCSP High impedance 16.5kΩ to VCC B16-1
MAX13031EETE+* 16 TQFN-EP** High impedance 16.5kΩ to VCC T1644-4
MAX13032EEBE+ 16 UCSP High impedance 16.5kΩ to GND B16-1
MAX13032EETE+ 16 TQFN-EP** High impedance 16.5kΩ to GND T1644-4
MAX13033EEBE+* 16 UCSP 16.5kΩ to GND High impedance B16-1
MAX13033EETE+* 16 TQFN-EP** 16.5kΩ to GND High impedance T1644-4
MAX13034EEBE+* 16 UCSP 16.5kΩ to GND 16.5kΩ to GND B16-1
MAX13034EETE+* 16 TQFN-EP** 16.5kΩ to GND 16.5kΩ to GND T1644-4
MAX13035EEBE+ 16 UCSP 75kΩ to VLHigh impedance B16-1
MAX13035EETE+ 16 TQFN-EP** 75kΩ to VLHigh impedance T1644-4
Ordering Information/Selector Guide (continued)
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
+
Denotes a lead-free package.
**
EP = Exposed paddle.
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
______________________________________________________________________________________ 17
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
16L,UCSP.EPS
H1
1
21-0101
PACKAGE OUTLINE, 4x4 UCSP
MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Boblet
24L QFN THIN.EPS
PACKAGE OUTLINE,
21-0139
2
1
E
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
PACKAGE OUTLINE,
21-0139
2
2
E
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
