128-Position I2C-Compatible
Digital Potentiometer
AD5247
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2003–2011 Analog Devices, Inc. All rights reserved.
FEATURES
128 positions
End-to-end resistance: 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Ultracompact, SC70-6 (2 mm × 2.1 mm) package
I2C-compatible interface
Full read/write of wiper register
Power-on preset to midscale
Single-supply 2.7 V to 5.5 V
Low temperature coefficient: 45 ppm/°C
Low power, IDD = 3 µA typical
Wide operating temperature range: −40°C to +125°C
Available in Pb–free package
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier-biasing
LCD brightness and contrast adjustment
Automotive electronics adjustment
Gain control and offset adjustment
FUNCTIONAL BLOCK DIAGRAM
I2C INT E RFACE
WIPER
REGISTER
SCL
SDA
GND
VDD
A
W
B
03876-001
Figure 1.
GENERAL DESCRIPTION
The AD5247 provides a compact, 2 mm × 2.1 mm, packaged
solution for 128-position adjustment applications. This device
performs the same electronic adjustment function as a mechanical
potentiometer or a variable resistor. Available in four different
end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ),
these low temperature coefficient devices are ideal for high
accuracy and stability variable resistance adjustments.
The wiper settings are controllable through the I2C-compatible
digital interface, which can also be used to read back the present
wiper register control word. The 10 k Ω and 100 kΩ options each
have three hard-coded slave address options available to allow
users access to three of these devices on one I2C bus (see Table 8
for a full list of slave address locations).
The resistance between the wiper and either end point of
the fixed resistor varies linearly with respect to the digital
code transferred into the RDAC latch. Note the terms digital
potentiometer, VR (variable resistor), and RDAC are used
interchangeably in this document.
Operating from a 2.7 V to 5.5 V power supply and consuming
3 µA allows the AD5247 to be used in portable battery-operated
applications.
AD5247
Rev. E | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 kΩ Version .................................. 3
Electrical Characteristics—10 kΩ, 50 kΩ, and 100 kΩ
Versions .......................................................................................... 4
Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Versions .......................................................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
I2C Interface .................................................................................... 13
Theory of Operation ...................................................................... 14
Programming the Variable Resistor ......................................... 14
Programming the Potentiometer Divider ............................... 15
I2C-Compatible 2-Wire Serial Bus ........................................... 15
Level Shifting for Bidirectional Interface ................................ 16
ESD Protection ........................................................................... 16
Terminal Voltage Operating Range ......................................... 16
Maximum Operating Current .................................................. 16
Power-Up Sequence ................................................................... 16
Layout and Power Supply Bypassing ....................................... 17
Constant Bias to Retain Resistance Setting ............................. 17
Evaluation Board ........................................................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
1/11—Rev. D to Rev. E
Change to Table 1, Added Output Logic Low .............................. 3
Change to Table 2, Added Output Logic Low .............................. 4
3/10—Rev. C to Re v. D
Changes to Table 9 and Table 10 ................................................... 14
10/09—Rev. B to Rev. C
Changes to Zero-Scale Error (10 kΩ) Parameter, Table 2 ........... 4
Changes to Ordering Guide .......................................................... 18
3/07—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Added Table 8 .................................................................................. 13
Changes to I2C-Compatible 2-Wire Serial Bus Section ............. 15
Changes to Ordering Guide .......................................................... 18
7/06—Rev. 0 to Re v. A
Updated Format .................................................................. Universal
Changes to Absolute Maximum Ratings section ......................... 6
Changes to Ordering Guide .......................................................... 18
9/03—Revision 0: Initial Version
AD5247
Rev. E | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1.5 ±0.1 +1.5 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −4 ±0.75 +4 LSB
Nominal Resistor Tolerance3 ∆RAB −30 +30 %
Resistance Temperature Coefficient3 ∆RAB/∆T 45 ppm/°C
Output Resistance RWB Code = 0x00 75 300 Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Differential Nonlinearity4 DNL −1 ±0.1 +1 LSB
Integral Nonlinearity4 INL −1 ±0.2 +1 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x40 15 ppm/°C
Full-Scale Error VWFSE Code = 0x7F −3 −2 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 1 2 LSB
RESISTOR TERMINALS
Voltage Range5 VA, VW GND VDD V
Capacitance A6 CA f = 1 MHz, measured to GND,
code = 0x40
45 pF
Capacitance W6 CW f = 1 MHz, measured to GND,
code = 0x40
60 pF
Common-Mode Leakage ICM VA = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V 2.4 V
Input Logic Low VIL VDD = 5 V 0.8 V
Input Logic High VIH VDD = 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance6 CIL 5 pF
Output Logic Low (SDA) VOL IOL = 3 mA 0.4 V
IOL = 6 mA 0.6 V
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3 8 µA
Power Dissipation7 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 40 µW
Power Supply Sensitivity PSSR VDD = 5 V ± 10%,
code = midscale
±0.003 ±0.05 %/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB BW_5 K RAB = 5 kΩ, code = 0x40 1.2 MHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS VA = 5 V, ±1 LSB error band 1 µs
Resistor Noise Voltage Density eN_WB RWB = 2.5 kΩ, RS = 0 Ω 6 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW, with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic under operating conditions.
5 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
AD5247
Rev. E | Page 4 of 20
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −2 ±0.25 +2 LSB
Nominal Resistor Tolerance3 ∆RAB −20 +20 %
Resistance Temperature Coefficient3 ∆RAB/∆T 45 ppm/°C
Output Resistance RWB Code = 0x00 75 300 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Differential Nonlinearity4 DNL −1 ±0.1 +1 LSB
Integral Nonlinearity4 INL −1 ±0.2 +1 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x40 15 ppm/°C
Full-Scale Error (50 kΩ, 100 kΩ) VWFSE Code = 0x7F −1 −1 0 LSB
Zero-Scale Error (50 kΩ, 100 kΩ) VWZSE Code = 0x00 0 0.4 1 LSB
Full-Scale Error (10 kΩ) VWFSE Code = 0x7F −2 −0.5 0 LSB
Zero-Scale Error (10 kΩ) VWZSE VDD = 4.5 V to 5.5 V, code = 0x00 0 0.5 1 LSB
VDD = 2.7 V to 4.4 V, code = 0x00 0 0.5 1.2 LSB
RESISTOR TERMINALS
Voltage Range5 VA, VW GND VDD V
Capacitance A6 CA f = 1 MHz, measured to GND,
code = 0x40
45 pF
Capacitance W6 CW f = 1 MHz, measured to GND,
code = 0x40
60 pF
Common-Mode Leakage ICM VA = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V 2.4 V
Input Logic Low VIL VDD = 5 V 0.8 V
Input Logic High VIH VDD = 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance6 CIL 5 pF
Output Logic Low (SDA) VOL IOL = 3 mA 0.4 V
IOL = 6 mA 0.6 V
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3 8 µA
Power Dissipation7 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 40 µW
Power Supply Sensitivity PSSR VDD = 5 V ± 10%, code = midscale ±0.01 ±0.02 %/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB BW RAB = 10 kΩ/50 kΩ/100 kΩ,
code = 0x40
600/100/40
kHz
Total Harmonic Distortion THDW VA =1 V rms, f = 1 kHz, RAB = 10 kΩ 0.05 %
VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS VA = 5 V ±1 LSB error band 2 µs
Resistor Noise Voltage Density eN_WB RWB = 5 kΩ, RS = 0 9 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW, with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
AD5247
Rev. E | Page 5 of 20
6 Guaranteed by design, not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter1, 2, 3 Symbol Min Typ4 Max Unit
SCL Clock Frequency fSCL 400 kHz
Bus Free Time Between Stop and Start, tBUF t1 1.3 µs
Hold Time (Repeated Start), tHD;STA5 t2 0.6 µs
Low Period of SCL Clock, tLOW t3 1.3 µs
High Period of SCL Clock, tHIGH t4 0.6 50 µs
Setup Time for Repeated Start Condition, tSU;STA t5 0.6 µs
Data Hold Time, tHD;DAT t6 0.9 µs
Data Setup Time, tSU;DAT t7 100 ns
Fall Time of Both SDA and SCL Signals, tF t8 300 ns
Rise Time of Both SDA and SCL Signals, tR t9 300 ns
Setup Time for Stop Condition, tSU;STO t10 0.6 µs
1 Specifications apply to all parts.
2 Guaranteed by design, not subject to production test.
3 See timing diagrams (Figure 2, Figure 33, and Figure 34) for locations of measured values.
4 Typical specifications represent average readings at 25°C and VDD = 5 V.
5 After this period, the first clock pulse is generated.
t7
t8
t9
P S P
S
t10
t5
t9
t8
SCL
SDA
t6
03876-031
t1
t2t3t4
t2
Figure 2. I2C Interface, Detailed Timing Diagram
AD5247
Rev. E | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND –0.3 V to +7 V
VA, VW to GND VDD
Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx
Pulsed1 ±20 mA
Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to VDD + 0.3 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature Range –65°C to +150°C
Thermal Resistance θJA2: (SC70-6) 340°C/W
Reflow Soldering Peak Temperature
SnPb 240°C
Pb-Free 260°C
1 Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5247
Rev. E | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD 1
GND
2
SCL
3
A
6
W
5
SDA
4
AD5247
TOP VIEW
(Not to Scale)
03876-043
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Positive Power Supply.
2 GND Digital Ground and B Termination Voltage.
3 SCL Serial Clock Input; Positive Edge Triggered.
4 SDA Serial Data Input/Output.
5 W Terminal W.
6 A Terminal A.
AD5247
Rev. E | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
CODE (Decimal)
RHEOSTAT MODE INL (LSB)
0
–1.0
0
0.2
1.0
16 32 48 64 80 96 112128
–0.8
–0.6
–0.4
–0.2
0.4
0.6
0.8
VDD = 2.7V
VDD = 5.5V
TA= 25°
C
R
AB
=10k
Ω
RHEOSTAT MODE INL (LSB)
03876-002
Figure 4. R-INL vs. Code vs. Supply Voltages
CODE (Decimal)
RHEO S TAT M ODE DNL (LSB)
0
–0.5
–0.4
–0.3
–0.2
16 32 48
64 80 96 112128
–0.1
0
0.1
0.2
0.3
0.4
0.5
VDD = 2.7V
VDD = 5.5V
TA= 25°C
RAB =10kΩ
03876-003
Figure 5. R-DNL vs. Code vs. Supply Voltages
CODE (Decimal)
0
–0.25
0
0.05
0.25
16 32 48 64 80 96 112 128
–0.20
–0.15
–0.10
–0.05
0.10
0.15
0.20 VDD = 2.7V
RAB = 10kΩ
POTENTIOMETER MODE INL (LSB)
TA= –40°C
TA= +25°C
TA= +85°C
TA= +125°C
TA= –40°C
TA= +25°C, +85°C, +125°C
03876-004
Figure 6. INL vs. Code vs. Temperature
Figure 7. DNL vs. Code vs. Temperature
CODE (Decimal)
0
–0.25
0
0.05
0.25
16 32 48 64 80 96 112128
–0.20
–0.15
–0.10
–0.05
0.10
0.15
0.20
V
DD
= 2.7V
V
DD
= 5.
5V
TA= 25°C
RAB =10kΩ
POTENTIOMETER MODE INL (LSB)
03876-006
Figure 8. INL vs. Code vs. Supply Voltages
CODE (Decimal)
0
–0.25
0
0.05
0.25
16 32 48 64 80 96 112128
–0.20
–0.15
–0.10
–0.05
0.10
0.15
0.20 TA= 25°C
RAB
=10kΩ
POTENTI O MET ER MODE DNL (LSB)
VDD = 2.7V
VDD = 5.5V
VDD = 2.7V
VDD = 5.5V
03876-007
Figure 9. DNL vs. Code vs. Supply Voltages
AD5247
Rev. E | Page 9 of 20
CODE (Decimal)
RHEOSTAT MODE INL (LSB)
0
–1.0
–0.8
–0.6
–0.4
16 32 48
–0.2
0
0.2
0.4
0.6
0.8
1.0
64 80 96 112128
T
A
=–40°C
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
=–40°C
T
A
= +85°C
T
A
= +25°C T
A
= +125°C
03876-008
Figure 10. R-INL vs. Code vs. Temperature
CODE (Decimal)
RHEO S TAT M ODE DNL (LSB)
0
–0.5
–0.4
–0.3
–0.2
16 32 48
–0.1
0
0.1
0.2
0.3
0.4
0.5
64 80 96 112128
T
A
=–40°C, +25°C, +85°C, +125°C
–40°C
+25°C
+85°C
+125°C
V
DD
= 2.7V
R
AB
=10kΩ
03876-009
Figure 11. R-DNL vs. Code vs. Temperature
TEMPERATURE (°C)
RHEOSTAT MODE INL (LSB)
–40
–3.0
–0.5
0
–25 –10 520 35 50 65 80
–2.5
–2.0
–1.5
–1.0
FULL- S CALE E RROR (LSB)
95 110 125
V
DD
= 5.5V , V
A
= 5.5V
V
DD
= 2.7V , V
A
= 2.7V
03876-010
Figure 12. Full-Scale Error vs. Temperature
TEMPERATURE (°C)
ZE RO-SCALE E RROR (LSB)
–40
0
0.25
0.50
0.75
–25 –10 5
1.00
1.25
1.50
20 35 50 65 80 95 110 125
VDD = 5.5V, VA = 5.5V
VDD = 2.7V, VA = 2.7V
03876-011
Figure 13. Zero-Scale Error vs. Temperature
TEMPERATURE (°C)
I
DD,
SUPP LY CURRENT (µA)
–40
0.01
0.1
1
10
–25–10
100
5 20 35 50 65 80 95 110125
V
DD
= 5.5V
V
DD
= 2.7V
DIGITAL INPUTS = 0V
CODE = 0x40
03876-012
Figure 14. Supply Current vs. Temperature
Figure 15. ∆RWB/∆T vs. Code
AD5247
Rev. E | Page 10 of 20
CODE (Decimal)
POTENTIOMETER (ppm/°C)
0
–10
–5
0
5
16 32 48
25
30
15
20
10
64 80 96 112128
T
A
=–40°C TO +125°C
T
A
=–40°C TO +85°C
V
DD
= 2.7V
R
AB
= 10kΩ
03876-014
Figure 16. ∆VWB/∆T vs. Code
GAIN (d B)
10k
–6
–12
–18
–24
–30
–36
0
–42
–54
100k
1M 10M
–60
0x40
1k
–48
0x20
0x10
0x08
0x04
0x02
0x01
FREQUENCY (Hz)
03876-015
Figure 17. Gain vs. Frequency vs. Code, RAB = 5 kΩ
10k
–6
–12
–18
–24
–30
–36
0
–42
–54
100k 1M 10M
–60
0x40
1k
–48
0x20
0x10
0x08
0x04
0x02
0x01
GAIN (d B)
FREQUENCY (Hz)
03876-016
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 kΩ
10k
–6
–12
–18
–24
–30
–36
0
–42
–54
100k 1M 10M
–60
0x40
1k
–48
0x20
0x10
0x08
0x04
0x02
0x01
GAIN (d B)
FREQUENCY (Hz)
03876-017
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 kΩ
10k
–6
–12
–18
–24
–30
–36
0
–42
–54
100k 1M 10M
–60
0x40
1k
–48
0x20
0x10
0x08
0x04
0x02
0x01
GAIN (d B)
FREQUENCY (Hz)
03876-018
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Figure 21. −3 dB Bandwidth @ Code = 0x80
AD5247
Rev. E | Page 11 of 20
FRE QUENCY ( Hz )
I
DD
(µA)
1k
0.25
0.20
0.15
0.30
0.10
0.05
10k 100k 1M
0
C
T
A
= 25° C
A-V
DD
= 5.5V
CODE = 0x55
B-V
DD
= 5.5V
CODE = 0x7F
C-V
DD
= 2.7V
CODE = 0x55
D-V
DD
= 2.7V
CODE = 0x7F
D
B
A
03876-020
Figure 22. IDD vs. Frequency
WIPER RESISTANCE (Ω)
CODE (Decimal)
0
125
100
75
150
50
25
16 80 128
0
TA=25°C
RAB = 50kΩ
VDD = 2.7V
VDD = 5.5V
32 48 64 96 112
03876-021
Figure 23. Wiper Resistance vs. Code vs. VDD
V
DD
= 5.5V
V
A
= 5.0V
V
B
= 0V
V
W
CLK
T
A
= 25°C
R
AB
=10kΩ
F
CLK
=100kHz
5V
0V
1µs/DIV
03876-022
Figure 24. Digital Feedthrough
V
DD
= 5.5V
V
A
= 5.0V
V
B
= 0V
CODE 0x40 TO CODE 0x3F
T
A
= 25°C
R
AB
= 10kΩ
V
W
200ns/DIV
03876-023
Figure 25. Midscale Glitch, Code 0x40 to Code 0x3F
V
DD
= 5.5V
V
A
= 5.0V
V
B
= 0V
CODE 0x00 TO CODE 0x7F
T
A
= 25°C
R
AB
= 10kΩ
V
W
4µs/DIV
03876-024
Figure 26. Large Signal Settling Time
AD5247
Rev. E | Page 12 of 20
TEST CIRCUITS
Figure 27 to Figure 32 define the test conditions used in the Specifications section.
AW
B
DUT
V+
03876-025
V+ = VDD
1LSB = V+/2N
VMS
Figure 27. Potentiometer Divider Nonlinearity Error (INL, DNL)
V
MS
NO CONNECT
AW
B
DUT
03876-026
I
W
Figure 28. Resistor Position Nonlinearity Error (R-INL, R-DNL)
V
MS2
AW
B
DUT
03876-027
V
MS1
V
W
I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
– V
MS2
]/I
W
Figure 29. Wiper Resistance
V+ = V
DD
± 10%
DUT
AW
B
V+
03876-028
V
MS
V
A
V
DD
ΔV
MS
%
ΔV
DD
%
PSSR (%/%) =
Figure 30. Power Supply Sensitivity (PSS, PSSR)
W
A
B
+15V
DUT
–15V
V
OUT
OP27
V
IN
03876-029
Figure 31. Gain vs. Frequency
VDD AW
B
GND
ICM
VCM
NC
DUT
NC
03876-030
Figure 32. Common-Mode Leakage Current
AD5247
Rev. E | Page 13 of 20
I2C INTERFACE
The following abbreviations are used in this section:
• S = start condition
• P = stop condition
• A = acknowledge
• X = don’t care
• W = write
• R = read
• A6, A5, A4, A3, A2, A1, A0 = address bits
• D6, D5, D4, D3, D2, D1, D0 = data bits
Table 6. Write Mode
S A6 A5 A4 A3 A2 A1 A0 W A X D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
Table 7. Read Mode
S A6 A5 A4 A3 A2 A1 A0 R A 0 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
SCL
FRAME 1
SLAVE ADDRESS BYTE FRAME 2
DATA BYTE
START BY
MASTER
ACK BY
AD5247 STOP BY
MASTER
SDA R/W XD6 D4 D3 D2 D1 D0
1
19
ACK BY
AD5247
19
D5
03876-032
A6 A4 A3 A2 A1 A0
ACK
A5
Figure 33. Writing to the RDAC Register
SCL
FRAME 1
SLAVE ADDRESS BYTE FRAME 2
RDAC REGISTER
START BY
MASTER
ACK BY
AD5247 STOP BY
MASTER
SR/W 0D6 D4 D3 D2 D1 D0
11 9
NO ACK BY
MASTER
9
D5
03876-033
A6 A4 A3 A2 A1 A0
A5
Figure 34. Reading from the RDAC Register
Table 8. I2C Slave Addresses
Model
Slave Addresses
Model
Slave Address
A6 A5 A4 A3 A2 A1 A0 A6 A5 A4 A3 A2 A1 A0
AD5247BKS5-R2 0 1 0 1 1 1 0 AD5247BKS50-RL7 0 1 0 1 1 1 0
AD5247BKS5-RL7 0 1 0 1 1 1 0 AD5247BKSZ50-RL7 0 1 0 1 1 1 0
AD5247BKSZ5-RL7 0 1 0 1 1 1 0 AD5247BKS100-R2 0 1 0 1 1 1 0
AD5247BKS10-R2 0 1 0 1 1 1 0 AD5247BKSZ100-R2 0 1 0 1 1 1 0
AD5247BKS10-RL7 0 1 0 1 1 1 0 AD5247BKS100-RL7 0 1 0 1 1 1 0
AD5247BKSZ10-RL7 0 1 0 1 1 1 0 AD5247BKSZ100-RL7 0 1 0 1 1 1 0
AD5247BKSZ10-1RL7 0 0 1 0 1 1 1 AD5247BKSZ100-1RL7 0 0 1 0 1 1 1
AD5247BKSZ10-2RL7 0 0 1 0 1 1 0 AD5247BKSZ100-2RL7 0 0 1 0 1 1 0
AD5247BKS50-R2 0 1 0 1 1 1 0
AD5247
Rev. E | Page 14 of 20
THEORY OF OPERATION
The AD5247 is a 128-position, digitally-controlled variable
resistor (VR) device. An internal power-on preset places the
wiper at midscale during power-on, which simplifies the
default condition recovery at power-up.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance (RAB) of the RDAC between Terminal A
and Terminal B is available in 5 k Ω, 10 kΩ, 50 kΩ, and 100 kΩ. The
final two or three digits of the part number determine the nominal
resistance value; for example, 10 kΩ = 10 and 50 kΩ = 50. The
RAB of the VR has 128 contact points accessed by the wiper
terminal, plus the B terminal contact. The 7-bit data in the
RDAC latch is decoded to select one of the 128 possible settings.
Assuming a 10 k Ω part is used, the wiper’s first connection starts
at the B terminal for Data 0x00. Because there is a 50 Ω wiper
contact resistance, such a connection yields a minimum of 100 Ω
(2 × 50 Ω) resistance between Terminal W and Terminal B. The
second connection is the first tap point, corresponding to 178 Ω
(RWB = RAB/128 + RW = 78 Ω + 2 × 50 Ω) for Data 0x01. The third
connection is the next tap point, representing 256 Ω (2 × 78 Ω
+ 2 × 50 Ω) for Data 0x02, and so on. Each LSB data value increase
moves the wiper up the resistor ladder until the last tap point is
reached at 10,100 Ω (RAB + 2 × RW).
Figure 35 shows a simplified diagram of the equivalent RDAC
circuit where the last resistor string is not accessed.
Bx
Wx
Ax
D6
D4
D5
D2
D3
D1
D0
RDAC
LATCH
AND
DECODER RS
RS
RS
03876-034
Figure 35. AD5247 Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB RR
D
(D)R×+×= 2
128
(1)
where:
D is the decimal equivalent of the binary code loaded in the
7-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and the Terminal A is open-circuited,
the output resistance RWB, shown in Table 9, is set for the indicated
RDAC latch codes.
Table 9. Codes and Corresponding RWB Resistance
D (Decimal) RWB (Ω) Output State
127 10,072 Full scale (RAB + 2 × RW)
64 5150 Midscale
1 228 1 LSB
0 150 Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite resistance of
100 Ω between Terminal W and Terminal B is present. Care
should be taken to limit the current flow between W and B in
this state to a maximum pulse current of no more than 20 mA.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
Similar to the mechanical potentiometer, the resistance of
the RDAC between Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA . When
these terminals are used, the Terminal B can be opened. Set the
resistance value for RWA to start at a maximum value of resistance
and to decrease the data loaded in the latch increases in value.
The general equation for this operation is
W
ABWA RR
D
(D)R×+×
−
=2
128
128 (2)
If RAB = 10 k Ω and the B terminal is open-circuited, the output
resistance, RWA, shown in Table 10, is set for the indicated RDAC
latch codes.
Table 10. Codes and Corresponding RWA Resistance
D (Decimal) RWA (Ω) Output State
127 228 Full scale
64 5150 Midscale
1 10,071 1 LSB
0 10,150 Zero scale
Typical device-to-device matching is process lot dependent
and can vary by up to ±30%. Because the resistance element
is processed in thin film technology, the change in RAB with
temperature has a very low 45 ppm/°C temperature coefficient.
AD5247
Rev. E | Page 15 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A, proportional to the input voltage
at A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A-to-B, W-to-A, and W-to-B can be at
either polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the Terminal A to 5 V and the Terminal B to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal A and Terminal B divided by the 128
positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
A
WV
D
DV ×=
128
)(
(3)
A more accurate calculation that includes the effect of wiper
resistance, VW, is
A
AB
WB
W
V
R
(D)R
(D)V×=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
rheostat mode, divider mode makes the output voltage mainly on
the ratio of Internal Resistor RWA to Internal Resistor RWB, and
not the absolute values. Therefore, the temperature drift reduces
to 15 ppm/°C.
I2C-COMPATIBLE 2-WIRE SERIAL BUS
The first byte of the AD5247 is a slave address byte (see the I2C
Interface section). It has a 7-bit slave address and an R/W bit.
The 5 kΩ and 50 kΩ options support one 7-bit slave address
while the 10 k Ω and 100 kΩ options each have three hard-coded
slave address options available (see Tabl e 8 for a full list of slave
address locations). The extra hard coded slave addresses on the
10 kΩ and 100 kΩ options allow users to employ up to three of
these devices on one I2C bus. The seven MSBs of the slave address
are followed by 0 for a write command or 1 to place the device
in read mode.
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 33). The
following byte is the slave address byte, consisting of the
7-bit slave address followed by an R/W bit (this bit determines
whether data is read from or written to the slave device). The
slave, whose address corresponds to the transmitted address,
responds by pulling the SDA line low during the ninth clock
pulse (this is termed the acknowledge bit). At this stage, all
other devices on the bus remain idle while the selected
device waits for data to be written to or read from its serial
register. If the R/W bit is high, the master reads from the
slave device. If the R/W bit is low, the master writes to the
slave device.
2. In write mode, after acknowledgement of the slave address
byte, the next byte is the data byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (eight data
bits followed by an acknowledge bit). The transitions on
the SDA line must occur during the low period of SCL
and remain stable during the high period of SCL (see
Figure 33).
3. In read mode, after acknowledgment of the slave address
byte, data is received over the serial bus in sequences of
nine clock pulses (a slight difference from write mode,
where eight data bits are followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during
the high period of SCL (see Figure 34).
4. When all data bits have been read or written, a stop con-
dition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a stop condition
(see Figure 33). In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master then brings the SDA line
low before the 10th clock pulse, which goes high to establish
a stop condition (see Figure 34).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing the part only
once. For example, after the RDAC has acknowledged its slave
address in the write mode, the RDAC output updates on each
successive byte. If different instructions are needed, the write/read
mode has to start again with a new slave address and data byte.
Similarly, a repeated read function of the RDAC is also allowed.
AD5247
Rev. E | Page 16 of 20
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems can be operated at one voltage, a
new component can be optimized at another voltage. When
two systems operate the same signal at two different voltages,
proper level shifting is needed. For instance, users can employ
a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A
level shifting scheme is needed to enable a bidirectional commu-
nication so that the setting of the digital potentiometer can be
stored in and retrieved from the E2PROM. Figure 36 shows one
of the level-shifting implementations. M1 and M2 can be any
N-channel signal FETs, or if VDD falls below 2.5 V, M1 and M2
can be low threshold FETs such as the FDV301N.
E
2
PROM
AD5247
SDA1
SCL1
D
G
R
P
R
P
3.3V 5V
S
M1 SCL2
SDA2
R
P
R
P
G
S
M2
V
DD1
= 3.3V V
DD2=
5V
D
03876-035
Figure 36. Level-Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures as shown in Figure 37. This applies
to digital input pins (SDA and SCL).
340Ω
GND
03876-036
LOGIC
SDA/
SCL
Figure 37. ESD Protection of Digital Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD5247 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer operation.
Supply signals present on Terminal A and Terminal W that exceed
VDD or GND are clamped by the internal forward biased diodes
(see Figure 38).
A
V
DD
W
GND
03876-038
Figure 38. Maximum Terminal Voltages Set by VDD and GND
MAXIMUM OPERATING CURRENT
At low code values, the user should be aware that, due to low
resistance values, the current through the RDAC might exceed
the 5 mA limit. In Figure 39, a 5 V supply is placed on the wiper,
and the current through Terminal W and Terminal B is plotted
with respect to code. A line is also drawn denoting the 5 mA
current limit. Note that at low code values (particularly for the
5 kΩ and 10 kΩ options), the current level increases signifi-
cantly. Care should be taken to limit the current flow between
W and B in this state to a maximum continuous current of
5 mA and a maximum pulse current of no more than 20 mA.
Otherwise, degradation or possible destruction of the internal
switch contacts can occur.
CODE ( Decimal)
IWB CURRENT ( mA)
0
0.01
0.1
1
10
16 32 48 64 80 96 112 128
100
5mA CURRENT LIM IT
RAB = 5kΩ
RAB = 10kΩ
RAB = 100kΩ
RAB = 50kΩ
03876-039
Figure 39. Maximum Operating Current
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A and Terminal W (see Figure 38), it is important
to power VDD/GND before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that VDD is powered unintentionally and can affect the rest of the
user’s circuit. The ideal power-up sequence is in the following
order: GND, VDD, digital inputs, VA, and VW. The relative order
of powering VA and VW and the digital inputs is not important
as long as they are powered after VDD/GND.
AD5247
Rev. E | Page 17 of 20
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ a compact, minimum lead-length
layout design. The leads to the inputs should be as direct as pos-
sible with minimum conductor length. Ground paths should
have low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic
capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capaci-
tors should also be applied at the supplies to minimize any transient
disturbance and low frequency ripple (see Figure 40). Note that the
digital ground should also be joined remotely to the analog ground
at one point to minimize the ground bounce.
AD5247
VDD C1
0.1µF
C3
10µF
GND
+VDD
03876-040
Figure 40. Power Supply Bypassing
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the additional
cost for the EEMEM, the AD5247 can be considered a low cost
alternative because it maintains a constant bias to retain the
wiper setting. The AD5247 is specifically designed with low
power in mind, which allows low power consumption even in
battery-operated systems.
Figure 41 demonstrates the power consumption from a 3.4 V
450 mA/hr Li-Ion cell phone battery, which is connected to the
AD5247. The measurement over time shows that the device
draws approximately 1.3 µA and consumes negligible power.
Over a course of 30 days, the battery was depleted by less than
2%, the majority of which was due to the intrinsic leakage
current of the battery itself.
Figure 41. Battery Operating Life Depletion
This demonstrates that constantly biasing the potentiometer
is a practical approach. Most portable devices do not require
the removal of batteries for charging. Although the resistance
setting of the AD5247 is lost when the battery needs replace-
ment, such events occur rather infrequently. As a result, this
inconvenience is justified by the lower cost and smaller size
offered by the AD5247. If total power is lost, the user should
be provided with a means to adjust the setting accordingly.
EVALUATION BOARD
An evaluation board, along with all necessary software, is avail-
able to program the AD5247 from any PC running Windows® 98,
Windows 2000, or Windows XP. The graphical user interface,
shown in Figure 42, is straightforward and easy to use. More
information is available in the data sheet that comes with the
evaluation board.
03876-042
Figure 42. AD5247 Evaluation Board Software
AD5247
Rev. E | Page 18 of 20
OUTLINE DIMENSIONS
1.30 BSC
COMPLIANT TO JEDEC STANDARDS MO-203-AB
1.00
0.90
0.70
0.46
0.36
0.26
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
072809-A
0.10 MAX
1.10
0.80
0.40
0.10
0.22
0.08
312
46 5
0.65 BSC
COPLANARITY
0.10
SEATING
PLANE
0.30
0.15
Figure 43. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 R
AB (kΩ) Temperature Range Package Description2
Package
Option Branding
AD5247BKSZ5-RL7 5 –40°C to +125°C 6-lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D96
AD5247BKSZ10-RL7 10 –40°C to +125°C 6-lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D95
AD5247BKSZ10-1RL7 10 –40°C to +125°C 6-lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D5E
AD5247BKSZ10-2RL7 10 –40°C to +125°C 6-lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 DAK
AD5247BKSZ50-RL7 50 –40°C to +125°C 6-lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D97
AD5247BKSZ100-R2 100 –40°C to +125°C 6-lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D98
AD5247BKSZ100-RL7 100 –40°C to +125°C 6-lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D98
AD5247BKSZ100-1RL7 100 –40°C to +125°C 6-lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 DAJ
AD5247BKSZ100-2RL7 100 –40°C to +125°C 6-lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 DAL
AD5247EVAL Evaluation Board
1 Z = RoHS compliant part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
AD5247
Rev. E | Page 19 of 20
NOTES
AD5247
Rev. E | Page 20 of 20
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03876-0-1/11(E)