ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8701 is a low skew, /1, /2 LVCMOS/ LVTTL Clock Generator and a member of the HiPerClockSTM HiPerClockSTMfamily of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines. * Twenty LVCMOS outputs, 7 typical output impedance The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/ OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. * Part-to-part skew: 600ps (maximum) The ICS8701 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701 ideal for those clock distribution applications demanding well defined performance and repeatability. * 0C to 70C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT ICS /1 1 /2 0 * Maximum output frequency: 250MHz * Bank enable logic allows unused banks to be disabled in reduced fanout applications * Output skew: 250ps (maximum) * Bank skew: 200ps (maximum) * Multiple frequency skew: 300ps (maximum) * 3.3V or mixed 3.3V input, 2.5V output operating supply modes * Other divide values available on request * Available in both standard and lead-free RoHS compliant packages GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND CLK * One LVCMOS/LVTTL clock input QA0:QA4 QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4 DIV_SELA 1 QB0:QB4 0 DIV_SELB 1 QC0:QC4 0 DIV_SELC 1 QD0:QD4 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS8701 QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0 0 DIV_SELA DIV_SELB CLK GND VDD BANK_EN0 GND BANK_EN1 VDD nMR/OE DIV_SELC DIV_SELD DIV_SELD nMR/OE BANK_EN0 BANK_EN1 Bank Enable Logic 48-Pin LQFP 7mm x 7mm x 1.4mm Y Package Top View 8701CY www.icst.com/products/hiperclocks.html 1 REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number 2, 5, 11, 26, 32, 35, 41, 44 7, 9, 18, 21, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 Name Type Description VDDO Power Output supply pins. GND Power Power supply ground. VDD QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 CLK Power Positive supply pins. Bank A outputs.LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Bank B outputs.LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Bank C outputs.LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Bank D outputs. LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Input Pulldown LVCMOS / LVTTL clock input. Controls frequency division for Bank D outputs. 13 DIV_SELD Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank C outputs. 14 DIV_SELC Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank B outputs. 23 DIV_SELB Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank A outputs. 24 DIV_SELA Input Pullup LVCMOS / LVTTLinterface levels. BANK_EN1, Enables and disables outputs by banks. 17, 19 Input Pullup LVCMOS / LVTTLinterface levels. BANK_EN0 Master Reset and output enable. When HIGH, output drivers are 15 nMR/OE Input Pullup enabled. Whe LOW, output drivers are in HiZ and dividers are reset. LVCMOS / LVTTLinterface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 8701CY www.icst.com/products/hiperclocks.html 2 REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 k CPD ROUT Test Conditions Minimum Typical Maximum VDD, VDDO = 3.465V 15 Units pF 7 TABLE 3. FUNCTION TABLE nMR/OE 0 1 1 1 1 1 1 1 1 8701CY Inputs BANK_EN1 BANK_EN0 X X 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 DIV_SELx X 0 0 0 0 1 1 1 1 QA0:QA4 Hi Z Active Active Active Active Active Active Active Active QB0:QB4 Hi Z Hi Z Active Active Active Hi Z Active Active Active www.icst.com/products/hiperclocks.html 3 Outputs QC0:QC4 QD0:QD4 Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Active Hi Z Active Active Hi Z Hi Z Hi Z Hi Z Active Hi Z Active Active Qx Frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol VDD Parameter Positive Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current 8701CY Test Conditions www.icst.com/products/hiperclocks.html 4 Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 Maximum 3.465 3.465 2.625 Units V V V 95 mA REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol VIH VIL IIH IIL VOH VOL 8701CY Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK Output High Voltage Output Low Voltage Minimum Typical Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 3.465V 5 A VDD = VIN = 3.465V 150 A VDD = 3.465V, VIN = 0V -150 A VDD = 3.465V, VIN = 0V -5 A 2.6 V 1.8 V VDD = VDDO = 3.135V IOH = -36mA VDD = 3.135V, VDDO = 2.375 IOH = -27mA VDD = VDDO = 3.135V IOL = 36mA VDD = 3.135V, VDDO = 2.375 IOL = 27mA www.icst.com/products/hiperclocks.html 5 0.5 V 0.5 V REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C Symbol Parameter fMAX Output Frequency Test Conditions Minimum f 200MHz Typical Maximum Units 250 MHz tPD Propagation Delay; NOTE 1 3.4 ns t sk(b) Bank Skew; NOTE 2, 7 Measured on rising edge atVDDO/2 200 ps t sk(o) Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Measured on rising edge atVDDO/2 250 ps Measured on rising edge atVDDO/2 30 0 ps Measured on rising edge atVDDO/2 600 ps t sk(w) t sk(pp) 2.2 tR Output Rise Time; NOTE 6 30% to 70% 280 850 ps tF Output Fall Time; NOTE 6 30% to 70% Output Duty Cycle 850 tCYCLE/2 + 0.5 3 ps odc 280 tCYCLE/2 - 0.5 2 f 200MHz tCYCLE/2 f = 200MHz 2.5 Output Enable Time; tEN f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. ns ns ns ns TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter fMAX Output Frequency Test Conditions Minimum f 200MHz Typical Maximum Units 250 MHz tPD Propagation Delay; NOTE 1 3.6 ns t sk(b) Bank Skew; NOTE 2, 7 Measured on rising edge atVDDO/2 225 ps t sk(o) Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Measured on rising edge atVDDO/2 250 ps Measured on rising edge atVDDO/2 30 0 ps Measured on rising edge atVDDO/2 600 ps t sk(w) t sk(pp) 2.6 tR Output Rise Time; NOTE 6 30% to 70% 280 850 ps tF Output Fall Time; NOTE 6 30% to 70% Output Duty Cycle 850 tCYCLE/2 + 0.5 3 ps odc 280 tCYCLE/2 - 0.5 2 f = 10MHz 6 ns f = 10MHz 6 ns f 200MHz f = 200MHz Output Enable Time; tEN NOTE 6 Output Disable Time; tDIS NOTE 6 For notes, please see T5A above. 8701CY www.icst.com/products/hiperclocks.html 6 tCYCLE/2 2.5 ns ns REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2.05V5% 1.65V5% 1.25V5% SCOPE VDD, VDDO VDDO Qx LVCMOS SCOPE VDD Qx LVCMOS GND GND VDDO 2 -1.165V5% -1.25V5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT Part 1 V DDO Qx V DDO Qx 2 2 Part 2 V V DDO Qy DDO Qy 2 tsk(o) OUTPUT SKEW QX0:QX4 PART-TO-PART SKEW VDDO 2 BANK SKEW (where X denotes outputs in the same bank) VDDO VDDO VDDO 2 2 2 t PD PROPAGATION DELAY t PW Clock Outputs t PERIOD 70% 70% tR tF 30% 30% t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIIOD 8701CY VDDO 2 QA0:QA4, QB0:QB4, QC0:QC4, QD0:QD4 tsk(b) odc = VDD 2 CLK VDDO 2 QX0:QX4 QA0:QA4, QB0:QB4, QC0:QC4, QD0:QD4 2 tsk(pp) OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 7 REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION Driver Termination For LVCMOS Output Termination, please refer to a separate Application Note: LVCMOS Driver Termination. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. POWER CONSIDERATIONS For Power Dissipation, please refer to a separate Application Note: Power Dissipation for LVCMOS Buffer. 8701CY www.icst.com/products/hiperclocks.html 8 REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 48 LEAD LQFP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W 200 500 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8701 is: 1743 8701CY www.icst.com/products/hiperclocks.html 9 REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC 0.60 0.75 L 0.45 0 -- 7 ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 8701CY www.icst.com/products/hiperclocks.html 10 REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8701CY ICS8701CY 48 Lead LQFP tray 0C to 70C ICS8701CYT ICS8701CY 48 Lead LQFP 1000 tape & reel 0C to 70C ICS8701CYLF ICS8701CYLF 48 Lead "Lead-Free" LQFP tray 0C to 70C ICS8701CYLFT ICS8701CYLF 48 Lead "Lead-Free" LQFP 1000 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8701CY www.icst.com/products/hiperclocks.html 11 REV. D FEBRUARY 27, 2006 ICS8701 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR REVISION HISTORY SHEET Rev B Table 5A 5B C 4B 4D C 1 T2 D T8 8701CY Page 5 7 8 - 10 4 6 11 2 9 1 3 7 8 11 Description of Change Updated notes. Updated notes. Updated drawings. Revised VIH rows from 3.8 Maximum to VDD + 0.3 Maximum. Revised VIH rows from 3.8 Maximum to VDD + 0.3 Maximum. Added Power Dissipation and Driver Termination notes. Pin Description Table, revised nMR/OE description. Date 10/4/01 11/28/01 Updated Output Rise/Fall Time Diagram. Features Section - added lead-free bullet. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Parameter Measurement Information - added Bank Skew diagram. Application Information - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free par t number, marking and note. Updated format throughout the data sheet. www.icst.com/products/hiperclocks.html 12 8/19/02 2/27/06 REV. D FEBRUARY 27, 2006