a ADSP-21000 Family Development Tools ADDS-210xx-TOOLS FEATURES FEATURES DEVELOPMENT SOFTWARE TOOLS DEVELOPMENT HARDWARE TOOLS ASSEMBLER Easy-to-Use Algebraic Syntax EZ-LAB(R) DEVELOPMENT BOARD Enables Evaluation, Prototyping, and Development of ADSP-21000 Family-Based Systems 16-Bit IBM-AT Compatible Plug-In Board LINKER Combines Object and Library Files ASSEMBLY LIBRARY/LIBRARIAN Includes Set of Arithmetic and DSP Functions EZ-KIT Includes the EZ-LAB Development Board, Development Software Tools, and C Compiler and Runtime Library SIMULATOR Reconfigurable, MS Windows GUI Interface Full Symbolic Disassembly and On-Line Assembly Simulates Memory and Port Configurations Plots Memory Graphically EZ-ICE(R) EMULATOR Full Speed, In-Circuit Emulation 8-Bit IBM-PC/AT Compatible Plug-In Board with Small 11-Pin JTAG In-Circuit Probe PROM SPLITTER ICEPACTM EMBEDDABLE IN-CIRCUIT EMULATOR Incorporates Embedded Emulation Functionality in a Plug-In Target Board (ADSP-2106x Only) OPTIMIZING G21K ANSI C COMPILER Includes C-Callable Library of ANSI Standard and DSP Functions Supports In-Line Assembly Code CBUGTM C SOURCE LEVEL DEBUGGER Integrated with Simulator and Emulator; Uses Same GUI Interface C RUNTIME LIBRARY Includes Over 150 DSP and Mathematical Functions CBUG and ICEPAC are trademarks of Analog Devices, Inc. EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc. SYSTEM DEVELOPMENT DIAGRAM STEP 1: DESCRIBE ARCHITECTURE STEP 2: GENERATE CODE SYSTEM ARCHITECTURE FILE ANSI C COMPILER C SOURCE FILES ASSEMBLER SOURCE FILES STEP 3: DEBUG SOFTWARE STEP 4: DEBUG IN TARGET SYSTEM STEP 5: MANUFACTURE FINAL SYSTEM = USER FILE OR HARDWARE LINKER LIBRARIES EXECUTABLE FILE ASSEMBLER EZ-LAB DEVELOPMENT BOARD OR THIRD-PARTY PC PLUG-IN CARDS SOFTWARE SIMULATOR TARGET BOARD EZ-ICE EMULATOR TESTED & DEBUGGED DSP BOARD PROM SPLITTER = SOFTWARE DEVELOPMENT TOOL = HARDWARE DEVELOPMENT TOOL REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 ADDS-210xx-TOOLS The ADSP-21000 Family Simulator runs the program on a software model of the DSP, reproducing the execution of the program by the processor in hardware. The simulator displays different portions of the virtual hardware environment through a reconfigurable windows interface identical to the emulator software interface. INTRODUCTION TO DEVELOPMENT TOOLS The ADSP-21000 Family Development Tools let you design applications for the ADSP-21000 family of Floating-Point DSP processors, including the ADSP-2106x SHARC. These tools enable you to develop hardware architectures together with creating and debugging code for your applications throughout the research, design, development, and test stages. The System Development Diagram illustrates how the tools work together. These tools are compatible with IBM-AT or Sun4 host platforms. Development Hardware Tools * * * * Components of the ADSP-21000 Family Development Tools fall into one of two broad categories: Software Tools and Hardware Tools. EZ-LAB Development Board EZ-ICE In-Circuit Emulator ICEPAC Embeddable In-Circuit Emulator (SHARC only) EZ-KIT and EZ-KIT Plus The ADSP-2106x and ADSP-21020 EZ-LAB Development Boards are ready-to-run target system and evaluation platforms. They let you download and execute your ADSP-21000 family programs in real time. EZ-ICE, an in-circuit emulator, provides a controlled environment for observing, debugging, and testing by directly connecting to the target processor through its (IEEE 1149.1) JTAG interface. The ICEPAC, a small daughter card, incorporates embedded emulation functionality that effectively adds all of the capabilities of the EZ-ICE to your PC plug-in target board. Development Software Tools * * * * * * Assembler Linker Simulator PROM Splitter Assembly Library/Librarian Optimizing G21K ANSI C Compiler with Numeric C Extensions * CBUG C Source-Level Debugger * C Runtime Library The EZ-KIT for the ADSP-2106x SHARC and the EZ-KIT Plus for the ADSP-21020 include the EZ-LAB Development Board, the ADSP-21000 Family Development Software, the C Compiler, C Runtime Library, and the CBUG Source Level Debugger. The Assembler translates ADSP-21000 Family assembly language source files into object code. The G21K C Compiler compiles C source files into object files or, optionally, into assembly language source files. The Linker then links the multiple object files together with various library files to form an executable program. Minimum Host Platform Requirements* IBM-AT Sun4 * * * * * * SunOS 4.1.1 for UNIX software; Windows version software compatible in Windows emulation mode * High resolution color monitor * 3.5" HD Floppy Disk Drive * Minimum 19 MB free hard disk drive space 386-based or greater AT with 4 MB DRAM DOS 3.1 or higher; Windows 3.1 or higher EGA or VGA Monitor and color video card 3.5" HD Floppy Disk Drive Minimum 11 MB free hard disk drive space *Some tools may vary. -2- REV. B ADDS-210xx-TOOLS SOFTWARE TOOLS Assembler Simulator The Simulator, a software model of the DSP, provides instructionlevel simulation of program execution. It models system memory and I/O according to the contents of the system architecture file, and displays hardware registers and memory in separate data windows (see Figure 1). The standard Windows Graphical User Interface (GUI) provides additional reconfigurable windows that display and let you alter register and memory contents, making a powerful debugging environment. The Simulator also reads symbols to perform symbolic debugging. A separate Simulator is provided for ADSP-2106x class DSPs and for ADSP-21020 class DSPs. The Assembler reads ADSP-21000 Family assembly language source files and generates a relocatable object file. It includes a preprocessor that lets you use the C preprocessor directives #define, #include, #if, #ifdef, and #else in assembly code. Assembler directives define code modules, data buffers, data variables, and memory mapped I/O ports. Both the assembler and C preprocessor have directives to define macros. Programming in assembly language is eased by the highly readable algebraic syntax of the ADSP-21000 Family instruction set. An add instruction, for example, is written in the same manner as the actual equation: The algebraic statement r = x + y is coded in assembly language as (f0 = f1 + f2). Features of the ADSP-21000 Family Simulators: * * * * * * * Linker The Linker processes separately assembled object and library files to create a single executable program. It assigns memory locations to code and data according to user defined architecture files--text files that describe the memory configuration of the target system. The Linker generates symbols (variable names and program labels) in the processed files that are used by the simulator and emulator to perform symbolic debugging. Display of all registers, caches, and stacks Integration with CBUG C Source-Level Debugger Single step execution Interrupt simulation Plotting memory Break points and break conditions Simulation of program and data memory. G21K ANSI C COMPILER Known for its efficiency and reliability, the GNU-based Optimizing G21K C Compiler supports in-line assembly code, using the asm( ) construct, and generates COFF (Common Object Format Files), an industry standard file format for object, library, and executable files. Assembly Library/Librarian The Assembly Library contains standard arithmetic and DSP routines accessible to your programs. You can create libraries of your own functions using the Librarian tool. Figure 1. ADSP-21000 Family Simulator and Emulator User Interface REV. B -3- ADDS-210xx-TOOLS For code portability and development platform flexibility, the G21K C Compiler conforms to ANSI Standard X3J11. Its optimizing features include the following: * Constant folding * Common subexpression elimination * Loop unrolling and strength reduction * Global and local register allocation * Flow Analysis * Pattern combining * Instruction scheduling * Global and local register allocation * Parallelization CBUG C Source-Level Debugger NUMERICAL C C Runtime Library CBUG, a full-featured C source-level debugger, is fully integrated with the ADSP-21000 Family Simulator and EZ-ICE Emulator. It performs the following functions: * Displays Variables and Expressions (Automatically Updated) * Evaluates Standard ANSI C Expressions * Stepping and Various other Program Execution Commands * Breakpoints and Conditional Breaks Based on Expression Evaluation * Displays Symbol Definition and Values * Displays Function Calling Tree * Uses Same Friendly User Interface as the EZ-ICE Simulator The C Compiler has a set of ANSI-standard functions that ease program development. These library routines include ANSIstandard functions commonly used in digital signal processing. The table below contains all the C Runtime Library functions and macros that perform digital signal processing operations. Numerical C--extensions to the G21K ANSI C compiler-- requires fewer lines of code to perform vector and matrix operations. Developed with the ANSI Numerical C Extensions Group (NCEG), a working committee reporting to ANSI X3J11, Numerical C lets the compiler perform more powerful optimizations. These Numerical C extensions have been adapted by the Free Software Foundation for GNU C compilers (version 2.4). The ADSP-21000 Family Runtime Library includes the following ANSI-standard function categories: * Standard Library * Mathematics * Signal, Variable and Character Handling Numerical C supports iterators used for generating one or more loops out of a single statement. This Numerical C code fragment for DSP application: int i,_ilimit_I = N; The library also includes signal processing functions in the following categories developed by Analog Devices: * DSP Filters * Fast Fourier Transforms * Matrix Operations * Interrupt Servicing for (i=0; i<_ilimit_I; i++) PROM Splitter iter i = N; A [i] = sin (2 x PI x i/N); is equivalent to this C Code: The PROM splitter translates an ADSP-21000 Family executable program into one of several formats for different PROM configurations or to be downloaded to the target system. The PROM Splitter's output file is generated as a Motorola S Record, Intel Hex Record format, or a stacked format used by the emulators. { A[i] = sin(2*PI*i/N); } A FIR filter with k taps on the array of n numbers notated as follows: k yi = x - a i j j j =0 is coded as this equation: iter I = n, j = k; y[i] = sum (x [i-j] * a [j]); -4- REV. B ADDS-210xx-TOOLS Table I. Library Functions a_compress a_expand abort abs acos, acosf asin, asinf atan, atanf atan2, atan2f atexit atoi atof autocoh autocorr bsearch biquad cabsf calloc ceil, ceilf cexpf cos, cosf cosh, coshf cot, cotf crosscoh crosscorr div exit exp, expf fabs, fabsf fir floor, floorf fmod, fmodf free frexp, frexpf getenv histo idle ifftN iir interrupt isalnum isalpha iscntrl isdigit isgraph islower isprint ispunct isspace isupper isxdigit labs ldexp, ldexpf ldiv localeconv log, logf log10, log10f longjmp malloc matadd matmul matscalmut matsub mean memchr REV. B A-law compression A-law expansion abnormal program end absolute value arc cosine arc sine arc tangent arc tangent of quotient register a function to call at program termination convert string to integer convert string to long integer autocoherence autocorrelation perform binary search in sorted array biquad filter section complex absolute value allocate and initialize memory ceiling complex exponential cosine hyperbolic cosine cotangent cross-coherence cross-correlation division normal program termination exponential absolute value finite impulse response (FIR) filter floor floating-point modulus deallocate memory separate fraction and exponent get string definition from operating system histogram execute ADSP-21020 IDLE instruction N-point inverse fast Fourier transform (IFFT) infinite impulse response (IIR) filter define interrupt handling detect alphanumeric character detect alphabetic character detect control character detect decimal digit detect printable character, not including whitespace detect lowercase character detect printable character detect punctuation character detect whitespace character detect uppercase character detect hexadecimal digit absolute value multiply by power of 2 division get pointer for formatting to current locale natural logarithm base 10 logarithm second return from setjmp allocate memory matrix addition matrix multiplication multiply matrix by scalar matrix subtraction computes mean find first occurrence of character -5- memcmp memcpy memmove memset modf, modff mu_compress mu_expand poll_flag_in pow, powf raise rand realloc rfftN set_semaphore set_alloc_type set_flag setjmp setlocale sgu signal signalf signals sin, sinf sinh, sinhf sqrt, sqrtf srand strcat strchr strcmp strcoll strcpy strcspn strerror strlen strncat strncmp strncpy strpbrk strrchr strspn strstr strtod strtok strtol strtoul strxfrm system tan, tanf tanh, tanhf test_and_set_semaphore timer_off timer_on timer_set tolower toupper var zero_cross compare objects copy characters from one object to another copy characters from one object to another set range of memory to a character separate integral and fractional parts -law compression -law expansion test input flag raise to a power force a signal random number generator change memory allocation N-point fast Fourier transform sets semaphore value for ADSP-2106x change memory allocation interface to the input flags of the ADSP-21020 label for external linkage set the current locale performs a stochastic gradient update on its input (ADSP-2106x) define signal handling (regular) define signal handling (fast dispatchr) (ADSP-2106x) define signal handling (super dispatchr) (ADSP-2106x) sine hyperbolic sine square root random number seed concatenate strings find first occurrence of character in string compare strings compare strings copy from one string to another length of character segment in one string but not the other get string containing error message string length concatenate characters from one string to another compare characters in strings copy characters from one string to another find character match in two strings find last occurrence of character in string length of segment of characters in both strings find string within string converts an ASCII string to floating point value (ADSP-2106x) convert string to tokens convert string to long integer convert string to unsigned long integer transform string using LC_COLLATE send string to operating system tangent hyperbolic tangent tests a value and sets a semaphore for the ADSP-2106x disable timer enable timer initialize timer convert from uppercase to lowercase convert from lowercase to uppercase variance count zero crossings ADDS-210xx-TOOLS Table II. Library Macros MIN(X,Y) MAX(X,Y) ABS(X) SWAP(X,Y) HARDWARE DEVELOPMENT TOOLS Hardware tools for developing ADSP-21000 Family based products are divided into two categories: 1) for the ADSP2106x SHARC, and 2) for the ADSP-21020 floating-point digital signal processors. Returns the minimum of X and Y Returns the maximum of X and Y Returns the absolute value of X and Y Swaps the values of X and Y ADSP-2106x SHARC Development Tools n SUM(var, n, expr) Returns exp r EZ-LAB Development Board Overview: The EZ-LAB Development Board is a 16-bit AT compatible plug-in board that lets you control and observe ADSP-2106x executable programs operating in real-time from on-board RAM. Optional processor and memory expansion modules from third parties let you customize the EZ-LAB. Several demonstration programs accompany EZ-LAB for you to familiarize yourself with and evaluate the ADSP-2106x floatingpoint DSPs. Figure 2 shows the EZ-LAB Board. var =0 FORALL(var, n, body) Does body n times FOREVER( ) ADSP-21020 idling CIRCULAR_BUFFER(TYPE, DAGREG, name) Circular buffer declaration macro BASE(name) Circular buffer register initialization macro LENGTH(name) Circular buffer register initialization macro CIRC_READ(ptr, step, variable, memory) Circular buffer access macro CIRC_WRITE(ptr, step, variable, memory) Circular buffer access macro CIRC_MODIFY(ptr, step) Circular buffer access macro CLIP(X,Y) Clip Y by Z: |Rx| < |Ry| then Rx, else if Rx < 0 then -Ry, else Ry AVG(X,Y) Returns (x+y)/2 Platform Requirements: The ADSP-2106x EZ-LAB can draw power from the host PC or from an external power source when used in a stand-alone mode. The EZ-LAB's power requirements are: +5 V dc @ 1 A, +12 V dc @ 400 mA, and -12 V dc @ 400 mA. (Note: The use of any SHARCPAC or ICEPAC module will add to the power requirements.) Memory: The ADSP-2106x EX-LAB is equipped with up to 512Kx8 of Boot PROM for program storage and up to 4 Mbits of SRAM on the DSP itself. This can be supplemented with additional memory through a memory expansion SHARCPACTM module. The following provide direct access to actual assembly instructions in the ADSP-210xx Family SCALB(X,Y) MANT(X) LOGB(X) FIXBY(X,Y) FLOATBY(X,Y) RECIPS(X) RSQRTS(X) COPYSIGN(X,Y) BCLR(X,Y) BTGL(X,Y) BTST(X,Y) EXP(X) LEFTZ(X) LEFTO(X) LOG2I(a) Returns a value which is a scaled exponent of X added to the fixedpoint twos-complement integer Y Returns the mantissa from the float X Returns the conversion of the exponent of the float in X to an unbiased twos-complement fixed point integer Returns the conversion of a floating point operand in X to a twoscomplement 32-bit fixed point integer Returns the conversion of a fixedpoint integer in X to a floating point; Y is a scaling factor which is added to the exponent of the result Returns an 8-bit accurate seed for 1/X Returns a 4-bit accurate seed for 1/sqrt(X) Returns the sign of the floating point value in Y copied to the floating point value in X without changing the exponent Returns a fixed point integer equal to X with the Y bits cleared Returns a fixed point integer equal to X with the Y bits toggled Returns a fixed point integer equal to X with the Y bits set Returns an exponent of a fixed point integer Returns the number of leading zeroes from the fixed point value X Returns the number of leading ones from the fixed point value X Calculate log base 2 of a number (int) Expansion Connectors: The EZ-LAB has several expansion connectors. These include the MAFETM expansion connector, the SHARCPAC module connectors, the SHARCNETTM connectors, and the JTAG in-circuit emulator connector. The Modular Analog Front End (MAFE) connector provides a standard interface for real world analog interface I/O daughterboards. The SHARCPAC connectors provide an interface for optional SHARCPAC modules that may take on a multitude of special functions, including memory expansion and multiprocessing applications. The SHARCNET connectors let you access two link ports from the on-board DSP and to two link ports from the SHARCPAC module connectors. The JTAG connector provides an interface for an in-circuit emulator probe such as the EZ-ICE or the ICEPAC In-Circuit Emulator module. MAFE Daughtercard: A sample analog interface MAFE daughtercard is supplied with the EZ-LAB. This card contains an Analog Devices AD1847-based sound codec and supporting hardware for audio input and output. PC Interface: The EZ-LAB can be interfaced to a host PC by plugging the board into a 16-bit ISA expansion slot within the PC. The host PC has access to the on-board resources and the SHARCPAC expansion port through the ISA bus. Jumpers are used for address and interrupt selection, thus minimizing potential conflicts. -6- REV. B ADDS-210xx-TOOLS ICEPAC (OPTIONAL) EZ-ICE (OPTIONAL) LEDs JTAG HEADER 16-BIT PC/AT I/O BUS CONNECTOR PUSHBUTTON SWITCHES ISA BUS ICEPAC INTERFACE LINK PORTS LINK CONNECTOR LINK PORTS LINK CONNECTOR M.A.F.E. SITE SERIAL PORTS BOOT ROM (4MB) SHARC PROCESSOR BUS ISA INTERFACE LINK PORTS SHARCPACTM MODULE SITE CONTROL I/F Figure 2. ADSP-2106x EZ-LAB Board EZ-ICE Emulator Overview Nonintrusive In-Circuit Emulation The EZ-ICE emulator does not affect target loading or timing. Nonintrusive, in-circuit emulation is assured because EZ-ICE controls the target system's processor through its IEEE 1149.1 (JTAG) Test Access Port. The ADSP-2106x SHARC EZ-ICE in-circuit emulator provides a controlled environment for observing, debugging and testing real-time activities in a target hardware environment by connecting directly to the target processor through its JTAG interface. The emulator monitors system behavior while running at full speed. It lets you examine and alter memory locations, including processor registers and stacks. EZ-ICE Target System Requirements The ADSP-2106x SHARC EZ-ICE Emulators use the IEEE 1149.1 JTAG test access port of the processors to monitor and control the target board processor during emulation. The EZICE TAP probe requires the CLKIN, EMU, TMS, TCK, TRST, TDI, TDO, and GND signals to be accessible on the target system via a 14-pin connector (pin strip header) such as that shown in Figure 3. System Configuration Requirements The EZ-ICE Emulator board is a half-size card that installs in an IBM PC's 8-bit expansion slot. The ICEPAC module is mounted as a daughter card to the EZ-ICE board. And the Test Access Port (TAP) probe is connected to EZ-ICE board through a ribbon cable, and to the target processor through its JTAG interface connector. 1 The following minimum PC configuration is required for the EZ-ICE: * 386-based or greater AT with 4 MB DRAM * EGA or VGA graphic card * Hard disk with 2.5 MB available * DOS 3.1 or higher; Windows 3.1 or higher * An available slot for an 8-bit half-size card * Mouse or other pointing device EMU 3 4 5 6 7 8 9 10 11 12 CLKIN KEY (NO PIN) TMS BTMS TCK BTCK BTRST TRST BTDI Graphical User Interface TDI 13 The EZ-ICE interface software uses the same GUI interface design as the simulator software. This same software works with the fully configured EZ-ICE board or with the ICEPAC installed in the EZ-LAB Development Board. REV. B 2 GND 14 GND TDO TOP VIEW Figure 3. Target Board Connector for ADSP-2106x EZ-ICE (Jumpers in Place) -7- ADDS-210xx-TOOLS The EZ-ICE probes plug directly onto these connectors for chip-on-board emulation. You must add a JTAG connector to your target board design if you intend to use the EZ-ICE. It is possible to support multiprocessor SHARC systems using a single JTAG connector and EZ-ICE. Figure 4 shows the dimensions of the ADSP-21060 SHARC EZ-ICE TAP probe. Be sure to allow enough room in your system to fit the probe's cable connector onto the target's JTAG connector. Together, EZ-LAB and ICEPAC combine to form a high speed DSP workstation with an interactive, window-based debugging interface. This setup lets you develop and test your application without any additional time investment in hardware prototyping. ADSP-2106x Emulator Connector Specification In addition to the EZ-LAB Development Board, ADSP-2106x EZ-KIT contains the ADSP-2106x EZ-LAB and the ADSP21000 Family Development Software: Simulator, Assembler, G21K C Compiler, C Source Level Debugger, Linker, Librarian, and PROM Splitter. Also included are abridged versions of software from SHARC Third Party developers. This package creates a complete development environment for programming applications in assembly language. Combined Software and Hardware Packages EZ-KIT Packages for the ADSP-21000 Family processors offer complete development tools sets at an affordable price. SHARC EZ-KIT The 2-row, 14-pin ADSP-2106x pin strip header is keyed at the Pin 3 location--you must remove Pin 3 from the header. The pins must be 0.025 inch square and at least 0.20 inch long. Pin spacing should be 0.100 x 0.100 inches. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. The length of the traces between the EZ-ICE probe connector and the processor's test access port pins should be as short as possible. Note that the EZ-ICE probe adds two TTL loads to the CLKIN pin. 3.187 (80.9) ADSP-21020 Development Tools ADSP-21020 EZ-LAB Evaluation Board Similar to the EZ-LAB SHARC Development Board, the ADSP-21020 EZ-LAB lets you control and observe ADSP21020 programs executing in real-time from on-board RAM. The large memory space--up to 4 Mbits of SRAM--lets you develop high performance floating-point DSP applications. Unlike the EZ-LAB SHARC Development Board, the ADSP21020 EZ-LAB is a stand-alone board that interfaces to the host computer through an RS-232 serial link. Several demonstration programs accompany EZ-LAB for you to familiarize yourself with and evaluate the ADSP-21020 floating-point DSPs. 9.5 (241.3) 0.577 (14.7) RIBBON CABLE LENGTH = 59.2 INCHES (1503.7 mm) 1.893 (48.1) BOTTOM VIEW RIBBON CABLE RIBBON CABLE Platform Requirements ALL DIMENSIONS IN INCHES AND (mm) The ADSP-21020 EZ-LAB requires a power supply that can deliver +5 V dc @ 1 amp and 12 V dc @ 200 mA. Figure 4. ADSP-2106x SHARC EZ-ICE TAP Probe Memory The BMTS, BTCK, BTRST, and BTDI signals are provided so that the test access port can also be used for board-level testing. When the connector is not being used for emulation, place jumpers between the BXXX pins and the XXX pins as shown in Figure 5. If you are not going to use the test access port for board test, tie BTRST to GND and tie or pull up BTCK to VDD. The TRST pin must be asserted (pulsed low) after power up (through BTRST on the connector) or held low for proper operation of the processor. The ADSP-21020 EZ-LAB contains 32K x 48-bit words of zero-wait state program memory and 32K x 48-bit words of zero-wait state data memory. Expansion Connectors Two expansion connectors let you add additional program memory, data memory, and I/O devices to customize the system. The 96-pin expansion connectors accept standard Eurocard prototyping boards (6U or 3U form factor). PC Control ICEPAC Embeddable In-Circuit Emulator A host PC controls the ADSP-21020 EZ-LAB board through an RS-232 link. With this connection, you can download and run ADSP-21000 Family programs using interface software that runs on the PC. Program results may be uploaded from EZLAB's on-board memory to the host PC. For code debug, plug the ADSP-21020 EZ-ICE Emulator probe into the EZ-LAB's JTAG emulation connection. The ICEPAC is a small (business card size) daughter card that contains emulator-specific hardware that incorporates emulation functionality into a plug-in target board. With ICEPAC, you can use standard ADSP-2106x EZ-ICE software for full incircuit emulation capability. The ICEPAC interfaces to the PC Host through an 8-bit data bus, and to the target system through its (IEEE 1149.1) JTAG test access port. The ICEPAC connector is a superset of the standard EZ-ICE target board connector. Analog Interface A basic analog interface is provided on-board, based on an AD1849 SoundPort Stereo Codec, for developing speech and audio processing applications. A 16-bit sigma-delta audio codec, the AD1849 integrates two sigma-delta DACs, two sigma-delta ADCs, anti-aliasing filters, digital interpolation filters, attenuators, and analog anti-imaging filters in a single package. It handles multiple channels of stereo input and output, and allows sampling rates from 8 kHz to 48 kHz. Using EZ-LAB and EZ-ICE Together For the ADSP-2106x SHARC EZ-LAB Development System, the only additional component required to have in-circuit emulation is an ICEPAC module. The EZ-ICE board's interface and probe functions are built into the EZ-LAB System. -8- REV. B ADDS-210xx-TOOLS The input signal to the AD1849 can come from a microphone (for speech processing), a signal generator, or any other highimpedance source. The processed signal is output through the standard on-board audio amplifier and a small speaker. Linelevel I/O is also provided. 1 2 3 4 5 6 7 8 9 10 11 12 CLKIN KEY (NO PIN 1) TMS BTMS TCK BTCK A 2-channel, 8-bit AD7769 general purpose analog interface lets the ADSP-21020 processor work with sampled analog signals. The AD7769 interfaces to the ADSP-21020 processor through four memory-mapped I/O ports (two for input, two for output). BTRST TRST BTDI EZ-ICE Emulator TDI GND The ADSP-21020 EZ-ICE provides a controlled environment for observing, debugging and testing activities in a target system by connecting directly to the target processor through its JTAG interface. The emulator monitors system behavior while running at full speed; it lets you examine and alter memory locations, including processor registers and stacks. TDO TOP VIEW Figure 5. Target Board Connector for ADSP-21020 EZ-ICE (Jumpers in Place) Nonintrusive In-Circuit Emulation 2.435 (61.9) The emulator does not affect target loading or timing. Nonintrusive, in-circuit emulation is assured because EZ-ICE controls the target system's processor through its IEEE 1149.1 (JTAG) Test Access Port. 0.590 (15.0) RIBBON CABLE LENGTH = 60.0 INCHES (1524 mm) 0.128 (3.25) 0.128 (3.25) 0.408 (10.4) Graphical User Interface The software provides a graphical user interface identical to the simulator's. The emulator connects to an IBM PC host computer through an 8-bit ISA bus plug-in board. Note: This EZ-ICE ISA bus interface board is not compatible with the ADSP2106x SHARC class of DSPs. 0.92 (23.4) BOTTOM VIEW System Configuration Requirements To operate the ADSP-21020 EZ-ICE, you need the following minimum PC configuration: * * * * * * * 2.435 (61.9) RIBBON CABLE 386- or 486-based PC with 2 MB RAM (total) 2.5 MB free hard disk space graphics card DOS 3.1 or higher MS-Windows 3.1 or higher an available slot for an 8-bit half-size plug-in board mouse ALL DIMENSIONS IN INCHES AND (mm) Figure 6. ADSP-21020 EZ-ICE Probe ADSP-21020 EZ-ICE Probe Connector Specifications The 2-row, 12-pin ADSP-21020/ADSP-21010 pin strip header is keyed at the Pin 1 location--you must remove Pin 1 from the header. Pin dimensions and availability are similar to those for the ADSP-2106x EZ-ICE TAP probe compatible header. However, the tip of the pins must be at least 0.10 inch higher than the tallest component under the ADSP-21020 emulator's probe to allow clearance for the bottom of the probe. EZ-ICE Target System Requirements The ADSP-21020 EZ-ICE Emulator use the IEEE 1149.1 JTAG test access port of the processors to monitor and control the target board processor during emulation. The ADSP-21020/ ADSP-21010 EZ-ICE probe requires the CLKIN, TMS, TCK, TRST, TDI, TDO, and GND signals to be accessible on the target system via a 12-pin connector (pin strip header) such as that shown in Figure 5. The length of the traces between the EZ-ICE probe connector and the processor's test access port pins should be as short as possible. Note that the ADSP-21020 EZ-ICE probe adds two TTL loads to the CLKIN pin. Target system boards must have the JTAG connector to interface to EZ-ICE's in-circuit probe. The EZ-ICE probe plugs directly onto this connector for chip-on-board emulation. The BMTS, BTCK, BTRST, and BTDI signals are provided so that the test access port can also be used for board-level testing. When the connector is not being used for emulation, place jumpers between the BXXX pins and the XXX pins as shown in Figures 6. If you are not going to use the test access port for board test, tie BTRST to GND and tie or pull up BTCK to VDD. The TRST pin must be asserted (pulsed low) after power up (through BTRST) on the connector) or held low for proper operation of the processor. Figure 6 shows the dimensions of the ADSP-21020/ADSP21010 EZ-ICE probe. Be sure to allow enough room in your system to fit the probe onto the connector. REV. B 0.6 (15.2) -9- ADDS-210xx-TOOLS Using EZ-LAB and EZ-ICE Together Combined Software and Hardware Packages Together, EZ-LAB and EZ-ICE combine to form a high-speed DSP workstation with an interactive, window-based debugging interface. In this configuration, EZ-LAB becomes the target system for EZ-ICE. From the EZ-ICE, you can download and execute programs, set breakpoints, and observe and change register and memory contents. The "Emulator port" on EZLAB lets EZ-ICE control the lab board's processor through its JTAG (IEEE 1149.1) interface. The EZ-KIT Plus Package for the ADSP-21020 offers a complete development tool set. EZ-KIT Plus EZ-KIT Plus contains the ADSP-21000 Family Development Software, EZ-LAB Evaluation Board, the G21K ANSI C Compiler, the C Runtime Library, and the CBUG C SourceLevel Debugger for a comprehensive set of tools for developing applications in C or in mixed C and assembly. -10- REV. B ADDS-210xx-TOOLS ORDERING INFORMATION The ADSP-21000 Family Development Software is available for IBM-compatible PCs, and SUN4 platforms. Analog Devices offers a sales package: the SW package includes the ADSP-21000 Family simulator, systems builder, assembler, linker, C Compiler, C Runtime Library, CBUG C Source-Level Debugger and PROM splitter. ADSP-2100 Family Ordering Guide ADI Part Number Description1, 2 ADDS-210xx-SW-PC Assembler Tools, Simulator, and C Tools for the IBM-PC/AT ADDS-210xx-SW-SUN Assembler Tools, Simulator, and C Tools for the Sun4 Platform ADDS-21020-EZ-LAB ADSP-21020 EZ-LAB Evaluation Board ADDS-21020-EZ-ICE ADSP-21020 EZ-ICE Emulator ADDS-21020-EZKITPL ADSP-21020 EZ-LAB, Assembler Package, Simulator, and C Tools ADDS-2106x-EZ-LAB ADSP-2106x SHARC EZ-LAB Evaluation Board ADDS-2106x-EZ-ICE ADSP-2106x SHARC EZ-ICE Emulator ADDS-2106x-ICEPAC ADSP-2106x SHARC ICEPAC Embeddable In-Circuit Emulator3 ADDS-2106x-EZ-KIT ADSP-2106x SHARC EZ-LAB, Assembler Package, Simulator, and C Tools NOTES 1 Assembler Tools = Assembler, Assembly Library/Librarian, Linker, PROM Splitter and Simulator. 2 C TOOLS = G21K C Compiler, C Runtime Library, and CBUG C Source-Level Debugger. 3 Available Fall 1995. REV. B -11- -12- PRINTED IN U.S.A. C1855a-10-7/95