AD5321BRMZ-REEL - Analog Devices, Inc.

2.5 V to 5.5 V, 120 μA, 2-Wire Interface,

Voltage-Output 8-/10-/12-Bit DACs

AD5301/AD5311/AD5321

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

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FEATURES

AD5301: buffered voltage output 8-bit DAC

AD5311: buffered voltage output 10-bit DAC

AD5321: buffered voltage output 12-bit DAC

6-lead SOT-23 and 8-lead MSOP packages

Micropower operation: 120 μA @ 3 V

2-wire (I2C®-compatible) serial interface

Data readback capability

2.5 V to 5.5 V power supply

Guaranteed monotonic by design over all codes

Power-down to 50 nA @ 3 V

Reference derived from power supply

Power-on reset to 0 V

On-chip rail-to-rail output buffer amplifier

3 power-down functions

APPLICATIONS

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

GENERAL DESCRIPTION

The AD5301/AD5311/AD53211 are single 8-/10-/12-bit, buff-

ered, voltage-output DACs that operate from a single 2.5 V to

5.5 V supply, consuming 120 μA at 3 V. The on-chip output

amplifier allows rail-to-rail output swing with a slew rate of

0.7 V/μs. It uses a 2-wire (I2C-compatible) serial interface that

operates at clock rates up to 400 kHz. Multiple devices can share

the same bus.

The reference for the DAC is derived from the power supply

inputs and thus gives the widest dynamic output range. These

parts incorporate a power-on reset circuit, which ensures that

the DAC output powers up to 0 V and remains there until a

valid write takes place. The parts contain a power-down feature

that reduces the current consumption of the device to 50 nA at

3 V and provides software-selectable output loads while in

power-down mode.

The low power consumption in normal operation makes these

DACs ideally suited to portable battery-operated equipment. The

power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,

reducing to 1 μW in all power-down modes.

1 Protected by U.S. Patent No. 5684481.

FUNCTIONAL BLOCK DIAGRAM

RESISTOR

NETWORK

BUFFER

DAC

POWER-DOWN

LOGIC

AD5301/AD5311/AD5321

SCL

GND

A1*

REF

POWER-ON

RESET

PD*

*AVAILABLE ON 8-LEAD VE RS IO N ONLY

INTERFACE

LOGIC 8-/10-/12-BIT

DAC V

OUT

00927-001

Figure 1.

AD5301/AD5311/AD5321

Rev. B | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 5

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Terminology ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 13

Digital-to-Analog ....................................................................... 13

Resistor String............................................................................. 13

Output Amplifier........................................................................ 13

Power-On Reset.......................................................................... 13

Serial Interface ................................................................................ 14

2-Wire Serial Bus........................................................................ 14

Input Shift Register .................................................................... 14

Write Operation.......................................................................... 15

Read Operation........................................................................... 16

Power-Down Modes .................................................................. 17

Application Notes ........................................................................... 18

Using REF19x as a Power Supply ............................................. 18

Bipolar Operation Using the AD5301/AD5311/AD5321..... 18

Multiple Devices on One Bus ................................................... 18

CMOS Driven SCL and SDA Lines.......................................... 18

Power Supply Decoupling ......................................................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 21

REVISION HISTORY

3/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Table 4............................................................................ 6

Changes to Figure 4 Caption........................................................... 7

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide .......................................................... 21

11/03—Rev. 0 to Rev. A

Changes to Ordering Guide ............................................................ 4

Updated Outline Dimensions....................................................... 15

7/99—Revision 0: Initial Version

AD5301/AD5311/AD5321

Rev. B | Page 3 of 24

SPECIFICATIONS

VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.

Table 1.

B Version1

Parameter2Min Typ Max Unit Conditions/Comments

DC PERFORMANCE3, 4

AD5301

Resolution 8 Bits

Relative Accuracy ±0.15 ±1 LSB

Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes.

AD5311

Resolution 10 Bits

Relative Accuracy ±0.5 ±4 LSB

Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes.

AD5321

Resolution 12 Bits

Relative Accuracy ±2 ±16 LSB

Differential Nonlinearity ±0.3 ±0.8 LSB Guaranteed monotonic by design over all codes.

Zero-Code Error 5 20 mV All zeros loaded to DAC, see Figure 12.

Full-Scale Error ±0.15 ±1.25 % of FSR All ones loaded to DAC, see Figure 12.

Gain Error ±0.15 ±1 % of FSR

Zero-Code Error Drift5 –20 μV/°C

Gain Error Drift5 −5 ppm of FSR/°C

OUTPUT CHARACTERISTICS5

Minimum Output Voltage 0.001 V

Maximum Output Voltage VDD − 0.001 V

This is a measure of the minimum and maximum

drive capability of the output amplifier.

DC Output Impedance 1 Ω

Short-Circuit Current 50 mA VDD = 5 V.

20 mA VDD = 3 V.

Power-Up Time 2.5 μs Coming out of power-down mode. VDD = 5 V.

6 μs Coming out of power-down mode. VDD = 3 V.

LOGIC INPUTS (A0, A1, PD)5

Input Current ±1 μA

Input Low Voltage, VIL 0.8 V VDD = 5 V ± 10%.

0.6 V VDD = 3 V ± 10%.

0.5 V VDD = 2.5 V.

Input High Voltage, VIH 2.4 V VDD = 5 V ± 10%.

2.1 V VDD = 3 V ± 10%.

2.0 V VDD = 2.5 V.

Pin Capacitance 3 pF

LOGIC INPUTS (SCL, SDA)5

Input High Voltage, VIH 0.7 × VDD V

DD + 0.3 V

Input Low Voltage, VIL −0.3 +0.3 × VDD V

Input Leakage Current, IIN ±1 μA VIN = 0 V to VDD.

Input Hysteresis, VHYST 0.05 × VDD V

Input Capacitance, CIN 6 pF

Glitch Rejection6 50 ns Pulse width of spike suppressed.

AD5301/AD5311/AD5321

Rev. B | Page 4 of 24

B Version1

Parameter2Min Typ Max Unit Conditions/Comments

LOGIC OUTPUT (SDA)5

Output Low Voltage, VOL 0.4 V ISINK = 3 mA.

0.6 V ISINK = 6 mA.

Three-State Leakage

Current

±1 μA

Three-State Output

Capacitance

6 pF

POWER REQUIREMENTS

VDD 2.5 5.5 V IDD specification is valid for all DAC codes.

IDD (Normal Mode) DAC active and excluding load current.

VDD = 4.5 V to 5.5 V 150 250 μA VIH = VDD and VIL = GND.

VDD = 2.5 V to 3.6 V 120 220 μA VIH = VDD and VIL = GND.

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.2 1 μA VIH = VDD and VIL = GND.

VDD = 2.5 V to 3.6 V 0.05 1 μA VIH = VDD and VIL = GND.

1 Temperature range is as follows: B Version: −40°C to +105°C.

2 See the Terminology section.

3 DC specifications tested with the outputs unloaded.

4 Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); and AD5321 (Code 112 to 4000).

5 Guaranteed by design and characterization, not production tested.

6 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

AD5301/AD5311/AD5321

Rev. B | Page 5 of 24

AC CHARACTERISTICS1

VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

B Version2

Parameter3Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time VDD = 5 V

AD5301 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0)

AD5311 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300)

AD5321 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)

Slew Rate 0.7 V/μs

Major-Code Change Glitch Impulse 12 nV-s 1 LSB change around major carry

Digital Feedthrough 0.3 nV-s

1 See the Terminology section.

2 Temperature range for the B Version is as follows: –40°C to +105°C.

3 Guaranteed by design and characterization, not production tested.

TIMING CHARACTERISTICS1

VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Limit at TMIN, TMAX

Parameter2(B Version) Unit Conditions/Comments

fSCL 400 kHz max SCL clock frequency

t1 2.5 μs min SCL cycle time

t2 0.6 μs min tHIGH, SCL high time

t3 1.3 μs min tLOW, SCL low time

t4 0.6 μs min tHD,STA, start/repeated start condition hold time

t5 100 ns min tSU,DAT, data setup time

t630.9 μs max tHD,DAT, data hold time

0 μs min

t7 0.6 μs min tSU,STA, setup time for repeated start

t8 0.6 μs min tSU,STO, stop condition setup time

t9 1.3 μs min tBUF, bus free time between a stop condition and a start condition

t10 300 ns max tR, rise time of both SCL and SDA when receiving4

0 ns min May be CMOS driven

t11 250 ns max tF, fall time of SDA when receiving4

300 ns max tF, fall time of both SCL and SDA when transmitting4

20 + 0.1Cb5ns min

Cb 400 pF max Capacitive load for each bus line

1 See Figure 2.

2 Guaranteed by design and characterization, not production tested.

3 A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the VIH MIN of the SCL signal) in order to bridge the undefined region of SCL’s

falling edge.

4 tR and tF measured between 0.3 VDD and 0.7 VDD.

5 Cb is the total capacitance of one bus line in picofarads.

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

SDA

SCL

t9t3t10

t4t6t5

t11

t1t8

00927-002

Figure 2. 2-Wire Serial Interface Timing Diagram

AD5301/AD5311/AD5321

Rev. B | Page 6 of 24

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.1

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V

SCL, SDA to GND −0.3 V to VDD + 0.3 V

PD, A1, A0 to GND −0.3 V to VDD + 0.3 V

VOUT to GND −0.3 V to VDD + 0.3 V

Operating Temperature Range

Industrial (B Version) −40°C to +105°C

Storage Temperature Range −65°C to +150°C

Junction Temperature (TJ max) 150°C

SOT-23 Package

Power Dissipation (TJ max − TA)/θJA

θJA Thermal Impedance 229.6°C/W

MSOP Package

Power Dissipation (TJ max – TA)/θJA

θJA Thermal Impedance 206°C/W

Lead Temperature JEDEC Industry Standard

Soldering J-STD-020

1 Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

AD5301/AD5311/AD5321

Rev. B | Page 7 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OUT

GND

SCL

SDA

AD5301/

AD5311/

AD5321

00927-004

TOP VIEW

(Not to Scale)

GND

SDA

SCL

OUT

AD5301/

AD5311/

AD5321

0927-003

TOP VIEW

(Not to Scale)

Figure 3. 8-Lead MSOP

(RM-8) Pin Configuration

Figure 4. 6-Lead SOT-23

(RJ-6) Pin Configuration

Table 5. Pin Function Descriptions

MSOP

Pin No.

SOT-23

Pin No. Mnemonic Description

1 6 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled

with a 10 μF in parallel with a 0.1 μF capacitor to GND.

2 5 A0 Address Input. Sets the least significant bit of the 7-bit slave address.

3 N/A A1 Address Input. Sets the second least significant bit of the 7-bit slave address.

4 4 VOUT Buffered Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

5 N/A PD Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software

power-down option. The DAC output goes three-state and the current consumption of the part

drops to 50 nA @ 3 V (200 nA @ 5 V).

6 3 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift

be CMOS/TTL driven.

7 2 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift

two bytes for the AD5311/AD5321) during the read cycle. It is a bidirectional open-drain data line that

should be pulled to the supply with an external pull-up resistor. If not used in readback mode, SDA may

be CMOS/TTL driven.

8 1 GND Ground Reference Point for All Circuitry on the Part.

AD5301/AD5311/AD5321

Rev. B | Page 8 of 24

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSBs, from a straight

line passing through the actual endpoints of the DAC transfer

function. Typical INL vs. code plots can be seen in Figure 5 to

Figure 7.

Differential Nonlinearity (DNL)

DNL is the difference between the measured change and the

ideal 1 LSB change between any two adjacent codes. A specified

differential nonlinearity of ±1 LSB maximum ensures monotonic-

ity. These DACs are guaranteed monotonic by design over all

codes. Typical DNL vs. code plots can be seen in Figure 8 to

Figure 10.

Zero-Code Error

Zero-code error is a measure of the output error when zero

code (0x00) is loaded to the DAC register. Ideally, the output

should be 0 V. The zero-code error of the AD5301/AD5311/

AD5321 is always positive because the output of the DAC

cannot go below 0 V, due to a combination of the offset errors

in the DAC and output amplifier. It is expressed in millivolts,

see Figure 12.

Full-Scale Error (FSR)

Full-scale error is a measure of the output error when full

scale is loaded to the DAC register. Ideally, the output should

be VDD – 1 LSB. Full-scale error is expressed in percent of FSR.

A plot can be seen in Figure 12.

Gain Error

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the actual DAC transfer characteristic from

the ideal expressed as a percentage of the full-scale range.

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code

error with a change in temperature. It is expressed in μV/°C.

Gain Error Drift

Gain error drift is a measure of the change in gain error with

changes in temperature. It is expressed in (ppm of full-scale

range)/°C.

Major Code Transition Glitch Energy

Major code transition glitch energy is the energy of the impulse

injected into the analog output when the code in the DAC register

changes state. It is normally specified as the area of the glitch in

nV-s and is measured when the digital code is changed by 1 LSB

at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00

to 011 . . . 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital input pins of the

device, but is measured when the DAC is not being written to. It

is specified in nV-s and is measured with a full-scale change on

the digital input pins, that is, from all 0s to all 1s and vice versa.

AD5301/AD5311/AD5321

Rev. B | Page 9 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.5

–0.5

–1.0 0 50 100 150 200 255

INL ERROR (LSB)

CODE

= 25°C

= 5V

0927-005

Figure 5. AD5301 Typical INL Plot

–2

–3 0 200 400 600 800 1023

INL ERROR (LSB)

CODE

= 25°C

= 5V

–1

7-00

–8

–12 0 1000 2000 3000 4095

INL ERROR (LSB)

CODE

–4

0092 6

Figure 6. AD5311 Typical INL Plot

= 25°C

= 5V

00927-007

Figure 7. AD5321 Typical INL Plot

0.3

0.1

–0.2

–0.3 0 50 100 150 255

DNL ERROR (LSB)

CODE

–0.1

0.2

200

7-00

= 25°C

= 5V

0092 8

Figure 8. AD5301 Typical DNL Plot

0.6

0.2

–0.4

–0.6 0 200 400 600 800 1023

DNL ERROR (LSB)

CODE

–0.2

0.4

= 25°C

= 5V

0092 97-00

1.0

0.5

–0.5

–1.0 0 1000 2000 3000 4095

DNL ERROR (LSB)

CODE

Figure 9. AD5311 Typical DNL Plot

= 25°C

= 5V

00927-010

Figure 10. AD5321 Typical DNL Plot

AD5301/AD5311/AD5321

Rev. B | Page 10 of 24

= 5V

MAX INL

1.00

0.75

0.50

–0.50

0.25

–0.25

–0.75

–1.00

–40 0 40 80 120

ERROR (LSB)

TEMPERATURE (°C)

MAX DNL

MIN INL

MIN DNL

00927-011

Figure 11. AD5301 INL Error and DNL Error vs. Temperature

–2

–4

–6

–8

–10

–40 0 40 806020–20 100

ERROR (mV)

TEMPERATURE (°C)

ZERO CODE

FULL SCALE

= 5V

0927-012

Figure 12. Zero-Code Error and Full-Scale Error vs. Temperature

80 120 160 190140100 200

FREQUENCY (Hz)

(µA)

= 5V

= 3V

00927-013

Figure 13. IDD Histogram with VDD = 3 V and VDD = 5 V

–00369121

OUT

(V)

I (mA)

5V SINK

3V SINK

5V SOURCE

3V SOURCE

0927-014

Figure 14. Source and Sink Current Capability

(µA)

CODE

200

ZERO SCALE FULL SCALE

180

160

140

120

100

= 5V

= 25°C

= 5V

= 3V

0927-015

Figure 15. Supply Current vs. Code

(µA)

(V)

200

2.7 3.2 3.7 4.2 4.7 5.2

150

100

+25°C

–40°C

+105°C

00927-016

Figure 16. Supply Current vs. Supply Voltage

AD5301/AD5311/AD5321

Rev. B | Page 11 of 24

(µA)

(V)

1.0

2.7 3.2 3.7 4.2 4.7 5.2

0.8

0.6

0.4

0.2

+25°C

–40°C

+105°C

00927-017

Figure 17. Power-Down Current vs. Supply Voltage

(µA)

LOGIC

(V)

300

0 1.0 2.0 3.0 4.0 5.0

250

200

150

100

DECREASING

= 25°C

= 5V

= 3V

INCREASING

00927-018

Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage

Increasing and Decreasing

CH1 1V, TIME BASE = 5µs/DIV

= 5V

= 25°C

LOAD = 2kΩ AND

200pF TO GND

OUT

00927-019

Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Charge)

CH2

CH1 1V, CH2 1V, TIME BASE = 20µs/DIV

CH1

OUT

= 25°C

00927-020

Figure 20. Power-On Reset to 0 V

AD5301/AD5311/AD5321

Rev. B | Page 12 of 24

CH1 1V, CH2 5V, TIME BASE = 1µs/DIV

= 25°C V

= 5V

OUT

CLK

00927-021

Figure 21. Exiting Power-Down to Midscale

2.48

2.47

OUT

(V)

2.49

2.50

1µs/DIV

00927-022

Figure 22. Major-Code Transition

2.440

2.445

2.450

2.455

OUT

(V)

1ns/DIV

00927-023

Figure 23. Digital Feedthrough

AD5301/AD5311/AD5321

Rev. B | Page 13 of 24

THEORY OF OPERATION

The AD5301/AD5311/AD5321 are single resistor-string DACs

fabricated on a CMOS process with resolutions of 8/10/12 bits,

respectively. Data is written via a 2-wire serial interface. The

devices operate from single supplies of 2.5 V to 5.5 V and the

output buffer amplifiers provide rail-to-rail output swing with

a slew rate of 0.7 V/μs. The power supply (VDD) acts as the

reference to the DAC. The AD5301/AD5311/AD5321 have

three programmable power-down modes, in which the DAC

can be turned off completely with a high impedance output,

or the output can be pulled low by an on-chip resistor (see the

Power-Down Modes section).

DIGITAL-TO-ANALOG

The architecture of the DAC channel consists of a resistor string

DAC followed by an output buffer amplifier. The voltage at the

VDD pin provides the reference voltage for the DAC. Figure 24

shows a block diagram of the DAC architecture. Since the input

coding to the DAC is straight binary, the ideal output voltage is

given by

OUT

where:

N = DAC resolution

D = decimal equivalent of the binary code that is loaded to the

DAC register:

0–255 for AD5301 (8 bits)

0–1023 for AD5311 (10 bits)

0–4095 for AD5321 (12 bits)

DAC

RESISTOR

STRING

OUTPUT BUFFER

AMPLIFIER

REF(+)

REF(–)

GND

OUT

00927-024

Figure 24. DAC Channel Architecture

RESISTOR STRING

The resistor string section is shown in Figure 25. It is simply

a string of resistors, each with a value of R. The digital code

loaded to the DAC register determines at what node on the

string the voltage is tapped off to be fed into the output ampli-

fier. The voltage is tapped off by closing one of the switches

connecting the string to the amplifier. Because it is a string

of resistors, it is guaranteed monotonic over all codes.

RTO OUTPUT

AMPLIFIER

00927-025

Figure 25. Resistor String

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating output volt-

ages to within 1 mV from either rail, which gives an output range

of 0.001 V to VDD − 0.001 V. It is capable of driving a load of

2 kΩ to GND and VDD, in parallel with 500 pF to GND. The

source and sink capabilities of the output amplifier can be seen

in Figure 14.

The slew rate is 0.7 V/μs with a half-scale settling time to

±0.5 LSB (at 8 bits) of 6 μs with the output unloaded.

POWER-ON RESET

The AD5301/AD5311/AD5321 are provided with a power-on

reset function, ensuring that they power up in a defined state.

The DAC register is filled with zeros and remains so until a

valid write sequence is made to the device. This is particularly

useful in applications where it is important to know the state

of the DAC output while the device is powering up.

AD5301/AD5311/AD5321

Rev. B | Page 14 of 24

SERIAL INTERFACE

2-WIRE SERIAL BUS

The AD5301/AD5311/AD5321 are controlled via an I2C-

compatible serial bus. The DACs are connected to this bus

as slave devices (no clock is generated by the AD5301/AD5311/

AD5321 DACs).

The AD5301/AD5311/AD5321 has a 7-bit slave address. In

the case of the 6-lead device, the six MSBs are 000110 and the

LSB is determined by the state of the A0 pin. In the case of the

8-lead device, the five MSBs are 00011 and the two LSBs are

determined by the state of the A0 and A1 pins. A1 and A0

allow the user to use up to four of these DACs on one bus.

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high. The following byte is

the address byte that consists of the 7-bit slave address

followed by an R/W bit (this bit determines whether data

is read from or written to the slave device).

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

its serial register. If the R/W bit is high, the master reads

from the slave device. However, if the R/W bit is low, the

master writes to the slave device.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during

the low period of SCL and remain stable during the high

period of SCL.

3. When all data bits have been read or written, a stop con-

dition is established by the master. A stop condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master pulls the SDA line

high during the 10th clock pulse to establish a stop condi-

tion. In read mode, the master issues a no acknowledge for

the ninth clock pulse (that is, the SDA line remains high).

The master then brings the SDA line low before the 10th

clock pulse and then high during the 10th clock pulse to

establish a stop condition.

In the case of the AD5301/AD5311/AD5321, a write operation

contains two bytes whereas a read operation may contain one or

two bytes. See Figure 29 to Figure 34 for a graphical explanation

of the serial interface.

A repeated write function gives the user flexibility to update the

DAC output a number of times after addressing the part only

once. During the write cycle, each multiple of two data bytes

updates the DAC output. For example, after the DAC acknowl-

edges its address byte, and receives two data bytes; the DAC

output updates after the two data bytes, if another two data

bytes are written to the DAC while it is still the addressed slave

device. These data bytes also cause an output update. A repeat

read of the DAC is also allowed.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide. Figure 26, Figure 27,

and Figure 28 illustrate the contents of the input shift register

for each part. Data is loaded into the device as a 16-bit word

under the control of a serial clock input, SCL. The timing

diagram for this operation is shown in Figure 2. The 16-bit

word consists of four control bits followed by 8/10/12 bits of

data, depending on the device type. MSB (Bit 15) is loaded first.

The first two bits are don’t cares. The next two are control bits

that control the mode of operation of the device (normal mode

or any one of three power-down modes). See the Power-Down

Modes section for a complete description. The remaining bits

are left justified DAC data bits, starting with the MSB and

ending with the LSB.

XX XXXX

DB0 (LS B)DB15 (MS B)

DAT A BITS

PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0

0927-026

Figure 26. AD5301 Input Shift Register Contents

DB0 (LS B)DB15 (MS B)

D7D8 D6 D5X X D1 D0 X XPD1 PD0 D9 D4 D3 D2

DATA BI TS

0927-037

Figure 27. AD5311 Input Shift Register Contents

DAT A B IT S

DB0 (LS B)DB15 ( M SB)

X X PD1 PD0 D11 D10 D9 D8 D7 D6 D4D5 D3 D2 D1 D0

00927-038

Figure 28. AD5321 Input Shift Register Contents

AD5301/AD5311/AD5321

Rev. B | Page 15 of 24

WRITE OPERATION

When writing to the AD5301/AD5311/AD5321 DACs, the

user must begin with an address byte, after which the DAC

acknowledges that it is prepared to receive data by pulling

SDA low. This address byte is followed by the 16-bit word in the

form of two control bytes. The write operations for the three

DACs are shown in Figure 29 to Figure 31.

SCL

LEAST SIGNIFICANT CONTROL BYTE

ACK

AD5301

ACK

AD5301

START

COND

MASTER

*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.

ACK

AD5301

STOP

COND

MASTER

PD1XX PD0 D7 D6 D5 D4

MOST SIGNIFICANT CONTROL BYTEADDRESS BYTE

0A1*A00011 R/W

D3 D2 D1 D0 X X X X

0927-027

Figure 29. AD5301 Write Sequence

SCL

LEAST SIGNIFICANT CONTROL BYTE

ACK

AD5311

ACK

AD5311

START

COND

MASTER

*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.

ACK

AD5311

STOP

COND

MASTER

PD1XX PD0 D9 D8 D7 D6

MOST SIGNIFICANT CONTROL BYTEADDRESS BYTE

0A1*A00011 R/W

D5 D4 D3 D2 D1 D0 X X

00927-028

Figure 30. AD5311 Write Sequence

SCL

SDA

SCL

SDA

LEAST SIGNIFICANT CONTROL BYTE

ACK

AD5321

ACK

AD5321

START

COND

MASTER

*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.

ACK

AD5321

STOP

COND

MASTER

PD1XX PD0 D11 D10 D9 D8

MOST SIGNIFICANT CONTROL BYTEADDRESS BYTE

0A1*A00011 R/W

D7 D6 D5 D4 D3 D2 D1 D0

00927-029

Figure 31. AD5321 Write Sequence

AD5301/AD5311/AD5321

Rev. B | Page 16 of 24

READ OPERATION

When reading data back from the AD5301/AD5311/AD5321

DACs, the user must begin with an address byte after which

the DAC acknowledges that it is prepared to transmit data by

pulling SDA low. There are two different read operations. In the

case of the AD5301, the readback is a single byte that consists of

the eight data bits in the DAC register. However, in the case

of the AD5311 and AD5321, the readback consists of two bytes

that contain both the data and the power-down mode bits. The

read operations for the three DACs are shown in Figure 32 to

Figure 34.

SCL

SDA

ACK

AD5301

NO ACK

MASTER

START

COND

MASTER

*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.

ADDRESS BYTE

00011

A1* A0 R/W

STOP

COND

MASTER

DATA BYTE

D7 D6 D5 D4 D3 D2 D1 D0

00927-030

Figure 32. AD5301 Readback Sequence

SCL

SDA

SCL

SDA

LEAST SIGNIFICANT CONTROL BYTE

*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.

NO ACK

MASTER

STOP

COND

MASTER

PD1XX PD0 D9 D8 D7 D60A1*A00011 R/W

D5 D4 D3 D2 D1 D0 X X

ACK

AD5311

ACK

AD5311

START

COND

MASTER

MOST SIGNIFICANT BYTEADDRESS BYTE

00927-031

Figure 33. AD5311 Readback Sequence

LEAST SIGNIFICANT BYTE

SCL

ACK

AD5321

NO ACK

MASTER

START

COND

MASTER

STOP

COND

MASTER

*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.

ADDRESS BYTE

STOP

COND

MASTER

MOST SIIGNIFICANT BYTE

D7 D6 D5 D4 D3 D2 D1 D0

0011

A1* A0 R/W X X PD1 PD0 D11 D10 D9 D8

00927-032

Figure 34. AD5321 Readback Sequence

AD5301/AD5311/AD5321

Rev. B | Page 17 of 24

POWER-DOWN MODES

The AD5301/AD5311/AD5321 have very low power consump-

tion, dissipating typically 0.36 mW with a 3 V supply and 0.75 mW

with a 5 V supply. Power consumption can be further reduced

when the DAC is not in use by putting it into one of three

power-down modes, which are selected by Bit 13 and Bit 12 (PD1

and PD0) of the control word. Table 6 shows how the state of

the bits corresponds to the mode of operation of the DAC.

Table 6. PD1 and PD0 Operating Modes

PD1 PD0 Operating Mode

0 0 Normal operation

0 1 Power-down (1 kΩ load to GND)

1 0 Power-down (100 kΩ load to GND)

1 1 Power-down (three-state output)

The software power-down modes programmed by PD1 and

PD0 may be overridden by the PD pin on the 8-lead version.

Taking this pin low puts the DAC into three-state power-down

mode. If PD is not used, tie it high.

When both bits are set to 0, the DAC works normally with its

normal power consumption of 150 μA at 5 V, while for the three

power-down modes, the supply current falls to 200 nA at 5 V

(50 nA at 3 V). Not only does the supply current drop, but the

output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode and provides a defined input

condition for whatever is connected to the output of the DAC

amplifier. There are three different options. The output is con-

nected internally to GND through a 1 kΩ resistor, a 100 kΩ

resistor, or it is left three-stated. Resistor tolerance = ±20%.

The output stage is illustrated in Figure 35.

STRING DAC

AMPLIFIER

OUT

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

00927-033

Figure 35. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and

all other associated linear circuitry are shut down when the

power-down mode is activated. However, the contents of the

DAC register are unchanged when in power-down. The time to

exit power-down is typically 2.5 μs for VDD = 5 V and 6 μs when

VDD = 3 V (see Figure 21).

AD5301/AD5311/AD5321

Rev. B | Page 18 of 24

APPLICATIONS NOTES

USING REF19x AS A POWER SUPPLY

Because the supply current required by the AD5301/AD5311/

AD5321 is extremely low, the user has an alternative option to

employ a REF195 voltage reference (for 5 V) or a REF193 voltage

reference (for 3 V) to supply the required voltage to the part

(see Figure 36).

SDA

SCL

150µA TYP

REF195

2-WIRE

SERIAL

INTERFACE

AD5301/

AD5311/

AD5321

OUT

= 0V TO 5V

00927-034

Figure 36. REF195 as Power Supply to AD5301/AD5311/AD5321

This is especially useful if the power supply is quite noisy or if

the system supply voltages are at some value other than 5 V or

3 V (for example, 15 V). The REF193/REF195 output a steady

supply voltage for the AD5301/AD5311/AD5321. If the low

dropout REF195 is used, it needs to supply a current of 150 μA

to the AD5301/AD5311/AD5321. This is with no load on the

output of the DAC. When the DAC output is loaded, the REF195

also needs to supply the current to the load.

The total current required (with a 2 kΩ load on the DAC output

and full scale loaded to the DAC) is

150 μA + (5 V/2 kΩ) = 2.65 mA

The load regulation of the REF195 is typically 2 ppm/mA,

which results in an error of 5.3 ppm (26.5 μV) for the 2.65 mA

current drawn from it. This corresponds to a 0.00136 LSB error.

BIPOLAR OPERATION USING THE AD5301/

AD5311/AD5321

The AD5301/AD5311/AD5321 has been designed for single-

supply operation, but a bipolar output range is also possible

using the circuit in Figure 37. The circuit below gives an output

voltage range of ±5 V. Rail-to-rail operation at the amplifier

output is achievable using an AD820 or an OP295 as the output

amplifier.

AD5301/

AD5311/

AD5321

2-WIRE SERIAL

INTERFACE

VOUT

VDD

10µF 0.1µF

+5V

–5V

10kΩ

AD820/

OP295

10kΩ

±5V

00927-035

Figure 37. Bipolar Operation with the AD5301/AD5311/AD5321

The output voltage for any input code can be calculated as

VOUT = [(VDD × (D/2N) × R1 + R2)/R1) − VDD × (R2/R1)]

where:

D is the decimal equivalent of the code loaded to the DAC.

N is the DAC resolution.

With VDD = 5 V, R1 = R2 = 10 kΩ,

VOUT = (10 × D/2N) − 5 V

MULTIPLE DEVICES ON ONE BUS

Figure 38 shows four AD5301 devices on the same serial bus.

Each has a different slave address since the state of their A0

and A1 pins is different. This allows each DAC to be written to

or read from independently. The master device output bus line

drivers are open-drain, pull-downs in a fully I2C-compatible

interface.

CMOS DRIVEN SCL AND SDA LINES

For single or multisupply systems where the minimum SCL

swing requirements allow it, a CMOS SCL driver may be used,

and the SCL pull-up resistor can be removed, making the SCL

bus line fully CMOS compatible. This reduces power consump-

tion in both the SCL driver and receiver devices. The SDA line

remains open-drain, I2C compatible.

Further changes, in the SDA line driver, may be made to make

the system more CMOS compatible and save more power. As

the SDA line is bidirectional, it cannot be made fully CMOS

compatible. A switched pull-up resistor can be combined with

a CMOS device with an open-circuit (three-state) input such

that the CMOS SDA driver is enabled during write cycles and

I2C mode is enabled during shared cycles, that is, readback,

acknowledge bit cycles, start conditions, and stop conditions.

AD5301/AD5311/AD5321

Rev. B | Page 19 of 24

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera-

tion of the power supply and ground return layout helps to

ensure the rated performance. The AD5301/AD5311/AD5321

should be decoupled to GND with 10 μF in parallel with a

0.1 μF capacitor, located as close to the package as possible.

The 10 μF capacitor should be the tantalum bead type, while

a ceramic 0.1 μF capacitor provides a sufficient low impedance

path to ground at high frequencies. The power supply lines of

the AD5301/AD5311/AD5321 should use as large a trace as

possible to provide low impedance paths. A ground line routed

between the SDA and SCL lines helps reduce crosstalk between

them. This is not required on a multilayer board as there is a

ground plane layer, but separating the lines helps.

AD5301

OUT

AD5301

SCL

SDA

SDASCLSDASCLSDASCLSDA

MASTER

OUT

00927-036

Figure 38. Multiple AD5301 Devices on One Bus

AD5301/AD5311/AD5321

Rev. B | Page 20 of 24

OUTLINE DIMENSIONS

1 3

2.90 BSC

1.60 BSC 2.80 BSC

1.90

BSC

0.95 BSC

0.22

0.08

10°

4°

0°

0.50

0.30

0.15 MAX

1.30

1.15

0.90

SEATING

PLANE

1.45 MAX

0.60

0.45

0.30

PIN 1

INDICATOR

COMPLIANT TO JEDEC STANDARDS MO-178-AB

Figure 39. 6-Lead Small Outline Transistor Package [SOT-23]

(RJ-6)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-187-AA

0.80

0.60

0.40

8°

0°

PIN 1

0.65 BSC

SEATING

PLANE

0.38

0.22

1.10 MAX

3.20

3.00

2.80

COPLANARITY

0.10

0.23

0.08

3.20

3.00

2.80

5.15

4.90

4.65

0.15

0.00

0.95

0.85

0.75

Figure 40. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

AD5301/AD5311/AD5321

Rev. B | Page 21 of 24

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD5301BRM –40°C to +105°C 8-Lead MSOP RM-8 D8B

AD5301BRM-REEL –40°C to +105°C 8-Lead MSOP RM-8 D8B

AD5301BRM-REEL7 –40°C to +105°C 8-Lead MSOP RM-8 D8B

AD5301BRMZ1–40°C to +105°C 8-Lead MSOP RM-8 D8B#

AD5301BRMZ-REEL1–40°C to +105°C 8-Lead MSOP RM-8 D8B#

AD5301BRMZ-REEL71–40°C to +105°C 8-Lead MSOP RM-8 D8B#

AD5301BRT-500RL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D8B

AD5301BRT-REEL –40°C to +105°C 6-Lead SOT-23 RJ-6 D8B

AD5301BRT-REEL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D8B

AD5301BRTZ-500RL71–40°C to +105°C 6-Lead SOT-23 RJ-6 D8B#

AD5301BRTZ-REEL1–40°C to +105°C 6-Lead SOT-23 RJ-6 D8B#

AD5301BRTZ-REEL71–40°C to +105°C 6-Lead SOT-23 RJ-6 D8B#

AD5311BRM –40°C to +105°C 8-Lead MSOP RM-8 D9B

AD5311BRM-REEL –40°C to +105°C 8-Lead MSOP RM-8 D9B

AD5311BRM-REEL7 –40°C to +105°C 8-Lead MSOP RM-8 D9B

AD5311BRMZ1–40°C to +105°C 8-Lead MSOP RM-8 D9B#

AD5311BRMZ-REEL1–40°C to +105°C 8-Lead MSOP RM-8 D9B#

AD5311BRMZ-REEL71–40°C to +105°C 8-Lead MSOP RM-8 D9B#

AD5311BRT-500RL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D9B

AD5311BRT-REEL –40°C to +105°C 6-Lead SOT-23 RJ-6 D9B

AD5311BRT-REEL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D9B

AD5311BRTZ-500RL71–40°C to +105°C 6-Lead SOT-23 RJ-6 D9B#

AD5311BRTZ-REEL1–40°C to +105°C 6-Lead SOT-23 RJ-6 D9B#

AD5311BRTZ-REEL71–40°C to +105°C 6-Lead SOT-23 RJ-6 D9B#

AD5321BRM –40°C to +105°C 8-Lead MSOP RM-8 DAB

AD5321BRM-REEL –40°C to +105°C 8-Lead MSOP RM-8 DAB

AD5321BRM-REEL7 –40°C to +105°C 8-Lead MSOP RM-8 DAB

AD5321BRMZ1–40°C to +105°C 8-Lead MSOP RM-8 DAB#

AD5321BRMZ-REEL1–40°C to +105°C 8-Lead MSOP RM-8 DAB#

AD5321BRMZ-REEL71–40°C to +105°C 8-Lead MSOP RM-8 DAB#

AD5321BRT-500RL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 DAB

AD5321BRT-REEL –40°C to +105°C 6-Lead SOT-23 RJ-6 DAB

AD5321BRT-REEL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 DAB

AD5321BRTZ-500RL71–40°C to +105°C 6-Lead SOT-23 RJ-6 DAB#

AD5321BRTZ-REEL1–40°C to +105°C 6-Lead SOT-23 RJ-6 DAB#

AD5321BRTZ-REEL71–40°C to +105°C 6-Lead SOT-23 RJ-6 DAB#

1 Z = RoHS Compliant Part; # denotes RoHS Compliant product, may be top or bottom marked.

AD5301/AD5311/AD5321

Rev. B | Page 22 of 24

NOTES

AD5301/AD5311/AD5321

Rev. B | Page 23 of 24

NOTES

AD5301/AD5311/AD5321

Rev. B | Page 24 of 24

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent

Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D00927-0-3/07(B)