CapSense® Applications
CY8C20X36/46/66/96
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-12696 Rev. *E Revised April 24, 2009
Features
■1.71V to 5.5V Operating Range
■Low Power CapSense™ Block
❐Configurable Capacitive Sensing Elements
❐Supports Combination of CapSense Buttons, Sliders, Touch-
pads, Touch Screens, and Proximity Sensor
■Powerful Harvard Architecture Processor
❐M8C Processor Speeds Running to 24 MHz
❐Low Power at High Speed
❐Interrupt Controller
❐Temperature Range: -40°C to +85°C
■Flexible On-Chip Memory
❐Three Program/Data Storage Size Options:
• CY8C20x36: 8K Flash / 1K SRAM
• CY8C20x46, CY8C20x96: 16K Flash / 2K SRAM
• CY8C20x66: 32K Flash / 2K SRAM
❐50,000 Flash Erase/Write Cycles
❐Partial Flash Updates
❐Flexible Protection Modes
❐In-System Serial Programming (ISSP)
■Full Speed USB
❐Available on CY8C20646, CY8C20666, CY8C20x96 Only
❐12 Mbps USB 2.0 Compliant
❐Eight Unidirectional Endpoints
❐One Bidirectional Control Endpoint
❐Dedicated 512 Byte Buffer
❐Internally Regulated at 3.3V
■Precision, Programmable Clocking
❐Internal Main Oscillator: 6/12/24 MHz ± 5%
❐Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep Timers
❐Precision 32 kHz Oscillator for Optional External Crystal
❐0.25% Accuracy for USB with No External Components
(CY8C20646, CY8C20666, CY8C20x96 only)
■Programmable Pin Configurations
❐Up to 36 GPIO (Depending on Package)
❐Dual Mode GPIO: All GPIO Support Digital I/O and Analog
Input
❐25 mA Sink Current on All GPIO
❐Pull up, High Z, Open Drain Modes on All GPIO
❐CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1:
• 20 mA (at 3.0V) Total Source Current on Port 0
• 20 mA (at 3.0V) Total Source Current on Port 1
❐Selectable, Regulated Digital I/O on Port 1
❐Configurable Input Threshold on Port 1
❐Hot Swap Capability on all Port 1 GPIO
■Versatile Analog Mux
❐Common Internal Analog Bus
❐Simultaneous Connection of I/O
❐High PSRR Comparator
❐Low Dropout Voltage Regulator for All Analog Resources
■Additional System Resources
❐I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No Clock Stretching Required (under most conditions)
• Implementation During Sleep Modes with Less Than
100 µA
• Hardware Address Validation
❐SPI™ Master and Slave: Configurable 46.9 kHz to 12 MHz
❐Three 16-Bit Timers
❐Watchdog and Sleep Timers
❐Internal Voltage Reference
❐Integrated Supervisory Circuit
❐8-bit Delta-Sigma Analog-to-Digital Converter
❐Two General Purpose High Speed, Low Power Analog Com-
parators
■Complete Development Tools
❐Free Development Tool (PSoC Designer™)
❐Full Featured, In-Circuit Emulator and Programmer
❐Full Speed Emulation
❐Complex Breakpoint Structure
❐128K Trace Memory
■Package Options
❐CY8C20x36:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN
❐CY8C20x46:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
❐CY8C20x96:
• 24-Pin 4 x 4 x 0.6 mm QFN (with USB)
• 32-Pin 5 x 5 x 0.6 mm QFN (with USB)
❐CY8C20x66:
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
• 48-Pin SSOP
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Document Number: 001-12696 Rev. *E Page 2 of 39
Logic Block Diagram
CAPSENSE
SYSTEM
1K/2K
SRAM
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
Internal Low Speed Oscillator (ILO)
6/12/24 MHz Internal Main Oscillator
(IMO)
PSoC CORE
CPU Core (M8C)
Supervisory ROM (SROM) 8K/16K/32K Flash
Nonvolatile Memory
SYSTEM RESOURCES
SYSTEM BUS
Analog
Reference
SYSTEM BUS
Port 3 Port 2 Port 1 Port 0
CapSense
Module
Global Analog Interconnect
1.8/2.5/3V
LDO
Analog
Mux
Two
Comparators
I2C
Slave
SPI
Master/
Slave
POR
and
LVD
USB System
Resets
Internal
Voltage
References
Three 16-Bit
Programmable
Timers
PWRSYS
(Regulator)
Port 4
Digital
Clocks
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PSoC® Functional Overview
The PSoC family consists of on-chip Controller devices. These
devices are designed to replace multiple traditional MCU-based
components with one, low cost single-chip programmable
component. A PSoC device includes configurable analog and
digital blocks, and programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, is comprised of three main areas: the
Core, the CapSense Analog System, and the System Resources
(including a full speed USB port). A common, versatile bus allows
connection between I/O and the analog system. Each
CY8C20x36/46/66/96 PSoC Device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 36 general purpose IO (GPIO) are also
included. The GPIO provides access to the MCU and analog
mux.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard archi-
tecture microprocessor.
System Resources provide additional capability, such as
configurable USB and I2C slave/SPI master-slave
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.2V analog reference, which together support
capacitive sensing of up to 36 inputs.
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
Figure 1. Analog System Block Diagram
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■Complex capacitive sensing interfaces, such as sliders and
touchpads.
■Chip-wide mux that allows analog input from any I/O pin.
■Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under http://www.cypress.com >
Documentation > Application Notes. In general, and unless
otherwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
IDAC
Reference
Buffer
Vr
Cinternal
Analog Global Bus
Cap Sense Counters
Comparator
Mux
Mux Refs
CapSense
Clock Select Oscillator
CSCLK
IMO
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Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include low voltage detection and
power on reset. The merits of each system resource are listed
here:
■The I2C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
■The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
■Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power-On-Reset) circuit eliminates the need for a system
supervisor.
■An internal reference provides an absolute reference for capac-
itive sensing.
■A register-controlled bypass mode allows the user to disable
the LDO.
■Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36/46/66/96 family of parts. However, the
additional trace length and a minimal ground plane in the Flex-
Pod can create noise problems that make it difficult to debug
the design. A custom bonded On-Chip Debug (OCD) device is
available in an 48-pin QFN package. The OCD device is
recommended for debugging designs that have high current
and/or high analog accuracy requirements. The QFN package
is compact and is connected to the ICE through a high density
connector.
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip™
Technical Reference Manual for CY8C20x36/46/66/96 PSoC
Devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet, Digi-
Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at 1-800-
541-4736.
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Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assem-
blers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC devices that match your system
requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over on-
chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
pre-built, pre-tested hardware peripheral components. In the
system-level view these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces (I2C-
bus, for example), and the logic to control how they interact with
one another (called valuators).
In the chip-level view the components are called “user modules.”
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and programmable
system-on-chip varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to corre-
spond to your chosen application. Enter values directly or by
selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions.
In the system-level view selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog-to-
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, you perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high-level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabil-
ities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 11 on page 17 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Table 1. Acronyms
Acronym Description
AC alternating current
API application programming interface
CPU central processing unit
DC direct current
FSR full scale range
GPIO general purpose I/O
GUI graphical user interface
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
I/O input/output
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
POR power on reset
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
SLIMO slow IMO
SRAM static random access memory
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Pinouts
The CY8C20x36/46/66/96 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, Vss, Vdd, and XRES
are not capable of Digital I/O.
16-Pin QFN (No E-Pad)
Table 2. Pin Definitions - CY8C20236, CY8C20246 PSoC Device [2]
Pin
No.
Type Name Description Figure 2. CY8C20236, CY8C20246 PSoC Device
Digital Analog
1I/O IP2[5] Crystal output (XOut)
2I/O IP2[3] Crystal input (XIn)
3IOHR IP1[7] I2C SCL, SPI SS
4IOHR IP1[5] I2C SDA, SPI MISO
5IOHR IP1[3] SPI CLK
6IOHR IP1[1] ISSP CLK[1], I2C SCL, SPI
MOSI
7Power Vss Ground connection
8IOHR IP1[0] ISSP DATA[1], I2C SDA, SPI
CLK
9IOHR IP1[2]
10 IOHR IP1[4] Optional external clock
(EXTCLK)
11 Input XRES Active high external reset with
internal pull down
12 IOH IP0[4]
13 Power Vdd Supply voltage
14 IOH IP0[7]
15 IOH IP0[3] Integrating input
16 IOH IP0[1] Integrating input
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
QFN
(Top View)
AI, XOut, P2[5]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
11
10
9
16
15
14
13
P0[3], AI
P0[7], AI
Vdd
P0[4], AI
AI, CLK1, SPI MOSI, P1[1]
AI, DATA1, I2C SDA, SPI CLK, P1[0]
P1[2], AI
AI, XIn, P2[3]
P1[4], EXTCLK, AI
XRES
P0[1], AI
Vss
12
5
6
7
8
Notes
1. These are the ISSP pins, which are not High Z at POR (Power On Reset).
2. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.
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24-Pin QFN
Note
3. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Table 3. Pin Definitions - CY8C20336, CY8C20346 [2, 3]
Pin
No.
Type Name Description Figure 3. CY8C20336, CY8C20346 PSoC Device
Digital Analog
1I/O IP2[5] Crystal output (XOut)
2I/O IP2[3] Crystal input (XIn)
3I/O IP2[1]
4IOHR IP1[7] I2C SCL, SPI SS
5IOHR IP1[5] I2C SDA, SPI MISO
6IOHR IP1[3] SPI CLK
7IOHR IP1[1] ISSP CLK[1], I2C SCL, SPI
MOSI
8NC No connection
9Power Vss Ground connection
10 IOHR IP1[0] ISSP DATA[1], I2C SDA, SPI
CLK
11 IOHR IP1[2]
12 IOHR IP1[4] Optional external clock input
(EXTCLK)
13 IOHR IP1[6]
14 Input XRES Active high external reset with
internal pull down
15 I/O IP2[0]
16 IOH IP0[0]
17 IOH IP0[2]
18 IOH IP0[4]
19 IOH IP0[6]
20 Power Vdd Supply voltage
21 IOH IP0[7]
22 IOH IP0[5]
23 IOH IP0[3] Integrating input
24 IOH IP0[1] Integrating input
CP Power Vss Center pad must be connected
to ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
AI, DATA2, I2C SDA, SPI CLK, P1[0]
QFN
(Top View)
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[2], AI
P0[0], AI
24
23
22
21
20
19
P0[3], AI
P0[5], AI
P0[7], AI
Vdd
P0[4], AI
7
8
9
10
11
12
SPI MOSI, P1[1]
AI, P1[2]
AI, P2[1]
NC
P1[6], AI
AI, EXTCLK, P1[4]
XRES
P2[0], AI
P0[6], AI
AI, CLK2, I2C SCL
P0[1], AI
Vss
AI, XOut, P2[5]
AI, XIn, P2[3]
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24-Pin QFN with USB
Table 4. Pin Definitions - CY8C20396 PSoC Device [2, 3]
Pin No. Type Name Description
Digital Analog
1I/O IP2[5]
2I/O IP2[3]
3I/O IP2[1]
4IOHR IP1[7] I2C SCL, SPI SS
5IOHR IP1[5] I2C SDA, SPI MISO
6IOHR IP1[3] SPI CLK
7IOHR IP1[1] ISSP CLK, I2C SCL, SPI MOSI
8 Power VSS Ground
9I/O ID+ USB D+
10 I/O ID- USB D-
11 Power VDD Supply
12 IOHR IP1[0] ISSP DATA, I2C SDA
13 IOHR IP1[2]
14 IOHR IP1[4] Optional external clock input
(EXTCLK)
15 IOHR IP1[6]
16 RESET INPUT XRES Active high external reset with
internal pull down
17 IOH IP0[0]
18 IOH IP0[2]
19 IOH IP0[4]
20 IOH IP0[6]
21 IOH IP0[7]
22 IOH IP0[5]
23 IOH IP0[3] Integrating input
24 IOH IP0[1] Integrating input
CP Power VSS Thermal pad must be
connected to Ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Figure 4. CY8C20396 PSoC Device
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 11 of 39
32-Pin QFN
Table 5. Pin Definitions - CY8C20436, CY8C20446,
CY8C20466 PSoC Device [2, 3]
Pin
No.
Type Name Description Figure 5. CY8C20436, CY8C20446, CY8C20466 PSoC Device
Digital Analog
1IOH IP0[1] Integrating input
2I/O I P2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O IP2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O I P3[3]
7I/O IP3[1]
8IOHR IP1[7] I2C SCL, SPI SS
9IOHR IP1[5] I2C SDA, SPI MISO
10 IOHR IP1[3] SPI CLK.
11 IOHR IP1[1] ISSP CLK[1], I2C SCL, SPI MOSI.
12 Power Vss Ground connection.
13 IOHR IP1[0] ISSP DATA[1], I2C SDA., SPI CLK
14 IOHR IP1[2]
15 IOHR IP1[4] Optional external clock input
(EXTCLK)
16 IOHR IP1[6]
17 Input XRES Active high external reset with
internal pull down
18 I/O I P3[0]
19 I/O I P3[2]
20 I/O I P2[0]
21 I/O IP2[2]
22 I/O IP2[4]
23 I/O IP2[6]
24 IOH IP0[0]
25 IOH IP0[2]
26 IOH IP0[4]
27 IOH IP0[6]
28 Power Vdd Supply voltage
29 IOH IP0[7]
30 IOH IP0[5]
31 IOH IP0[3] Integrating input
32 Power Vss Ground connection
CP Power Vss Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
AI, P0[1]
AI, P2[7]
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
AI, P3[3]
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0 [3 ], AI
P0 [7 ], AI
Vd d
P0 [6 ], AI
P0 [4 ], AI
P0 [2 ], AI
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
P0[0], AI
P2[6], AI
P3[0], AI
XRES
AI, I2C SDA, SP I MISO , P1[5]
AI, SPI CLK, P1[3]
Vss
AI, P1[2]
AI, EXTCLK, P 1[4]
AI, P1[6]
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P0 [5 ], AI
AI, CLK4, I2C SCL, SPI MOSI, P1[1]
AI, DATA1, I2C SDA, SPI CLK, P1[0]
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 12 of 39
32-Pin QFN (with USB)
Table 6. Pin Definitions - CY8C20496 PSoC Device [2, 3]
Pin
No.
Type Name Description Figure 5. CY8C20496 PSoC Device
Digital Analog
1IOH IP0[1]
2I/O I P2[5] XTAL Out
3I/O I P2[3] XTAL In
4I/O IP2[1]
5IOHR IP1[7] I2C SCL, SPI SS
6IOHR I P1[5] I2C SDA, SPI MISO
7IOHR IP1[3] SPI CLK
8IOHR IP1[1] TC CLK, I2C SCL, SPI MOSI
9Power VSS Ground Pin
10 I
I
D+ USB PHY
11 D- USB PHY
12 Power Vdd Power pin
13 IOHR I P1[0] TC DATA*, I2C SDA, SPI CLKI
14 IOHR IP1[2]
15 IOHR IP1[4] EXTCLK
16 IOHR IP1[6]
17 Input XRES Active high external reset with
internal pull down
18 I/O I P3[0]
19 I/O I P3[2]
20 I/O I P2[0]
21 I/O IP2[2]
22 I/O IP2[4]
23 I/O IP2[6]
24 IOH IP0[0]
25 IOH IP0[2]
26 IOH IP0[4]
27 IOH IP0[6]
28 Power Vdd Power Pin
29 IOH IP0[7]
30 IOH IP0[5]
31 IOH IP0[3]
32 Power Vss Ground Pin
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
AI , P0[1]
XTAL OUT, P2[5]
XTAL IN , P2[3]
AI, P2[1]
I2C SCL, SPI SS, P1[7]
I2C SDA, SPI MISO, P1[5]
QFN
( Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0[3], AI
P0[7], AI
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
SPI CLK , P1[3]
TC CLK, I2C SCL, SPI MOSI,P1[1]
P0[0] , AI
P2[6] , AI
P3[0] , AI
XRES
Vss
USB PHY, D+
Vdd
AI, P 1[2]
AI , E X TC LK , P 1[ 4]
AI, P 1[6]
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P0[5], AI
USB PHY D-
TC, DATA1, I2C SDA, SPI CLK, P1[0]
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 13 of 39
48-Pin SSOP
Table 7. Pin Definitions - CY8C20536, CY8C20546,
and CY8C20566 PSoC Device[2]
Pin No.
Digital
Analog
Name Description
Figure 6. CY8C20536, CY8C20546, and CY8C20566 PSoC Device
1IOH IP0[7]
2IOH IP0[5]
3IOH IP0[3]
4IOH IP0[1]
5I/O IP2[7]
6I/O IP2[5] XTAL Out
7I/O I P2[3] XTAL In
8I/O IP2[1]
9NC No connection
10 NC No connection
11 I/O IP4[3]
12 I/O IP4[1]
13 NC No connection
14 I/O IP3[7]
15 I/O IP3[5]
16 I/O IP3[3]
17 I/O IP3[1]
18 NC No connection
19 NC No connection
20 IOHR IP1[7] I2C SCL, SPI SS
21 IOHR IP1[5] I2C SDA, SPI MISO
22 IOHR IP1[3] SPI CLK
23 IOHR IP1[1] TC CLK[1], I2C SCL, SPI MOSI
24 VSS Ground Pin
25 IOHR IP1[0] TC DATA[1], I2C SDA, SPI CLK
26 IOHR IP1[2]
27 IOHR IP1[4] EXT CLK
28 IOHR IP1[6]
29 NC No connection
30 NC No connection
31 NC No connection
32 NC No connection
Pin No.
Digital
Analog
Name Description
33 NC No connection 41 I/O IP2[2]
34 NC No connection 42 I/O IP2[4]
35 XRES Active high external reset with internal
pull down
43 I/O IP2[6]
36 I/O IP3[0] 44 IOH IP0[0]
37 I/O IP3[2] 45 IOH IP0[2]
38 I/O I P3[4] 46 IOH IP0[4]
39 I/O I P3[6] 47 IOH IP0[6]
40 I/O IP2[0] 48 Power Vdd Power Pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
SSOP
AI, P0[7] VDD
AI, P0[5] P0[6], AI
AI, P0[3] P0[4], AI
AI P0[1] P0[2], AI
AI, P2[7] P0[0], AI
XTALOUT, P2[5] P2[6], AI
XTALIN, P2[3] P2[4], AI
AI, P2[1] P2[2], AI
NC P2[0], AI
NC P3[6], AI
AI, P4[3] P3[4], AI
AI, P4[1] P3[2], AI
NC P3[0], AI
AI, P3[7] XRES
AI, P3[5] NC
AI, P3[3] NC
AI, P3[1] NC
NC NC
NC NC
I2C SCL, SPI SS, P1[7] NC
I2C SDA, SPI MISO, P1[5] P1[6], AI
SPI CLK, P1[3] P1[4], EXT CLK
TC CLK, I2C SCL, SPI MOSI, P1[1] P1[2], AI
VSS P1[0], TC DATA, I2C SDA, SPI CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
43
44
42
40
41
39
38
37
36
35
33
34
32
31
30
29
28
27
26
25
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 14 of 39
48-Pin QFN
Table 8. Pin Definitions - CY8C20636 PSoC Device [2, 3]
Pin
No.
Digital
Analog
Name Description
Figure 7. CY8C20636 PSoC Device
1NC No connection
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O I P2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP4[3]
7I/O IP4[1]
8I/O IP3[7]
9I/O IP3[5]
10 I/O IP3[3]
11 I/O IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14 NC No connection
15 NC No connection
16 IOHR IP1[3] SPI CLK
17 IOHR IP1[1] ISSP CLK[1], I2C SCL, SPI MOSI
18 Power Vss Ground connection
19 DNU
20 DNU
21 Power Vdd Supply voltage
22 IOHR IP1[0] ISSP DATA[1], I2C SDA, SPI CLK
23 IOHR IP1[2]
24 IOHR IP1[4] Optional external clock input
(EXTCLK)
25 IOHR IP1[6]
26 Input XRES Active high external reset with
internal pull down
27 I/O IP3[0]
28 I/O IP3[2]
29 I/O IP3[4] Pin
No.
Digital
Analog
Name Description
30 I/O IP3[6] 40 IOH IP0[6]
31 I/O IP4[0] 41 Power Vdd Supply voltage
32 I/O IP4[2] 42 NC No connection
33 I/O IP2[0] 43 NC No connection
34 I/O IP2[2] 44 IOH IP0[7]
35 I/O IP2[4] 45 IOH IP0[5]
36 I/O IP2[6] 46 IOH IP0[3] Integrating input
37 IOH IP0[0] 47 Power Vss Ground connection
38 IOH IP0[2] 48 IOH IP0[1]
39 IOH IP0[4] CP Power Vss Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
(Top View)
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
Vdd
P0[6], AI
P0[2], AI
P0[0], AI
10
11
12
AI , P2[7]
NC
AI, XOut, P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI P3[1]
AI, I2 C SCL, SPI SS, P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0], AI
XRES
P1[6] , AI
P2[6] , AI
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C SDA, SPI MISO, A I, P1[5]
NC
SPICLK,AI,P1[3]
AI, CLK6, I2C SCL, SPI MOSI, P1[1]
Vss
DNU
DNU
Vdd
AI, DATA1,I2CSDA,SPICLK,P1[0]
AI, P 1[ 2]
AI, EXTCLK, P1[4]
NC
NC
NC
P0[4], AI
P0[1], AI
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 15 of 39
48-Pin QFN with USB
Table 9. Pin Definitions - CY8C20646, CY8C20666 PSoC Device [2, 3]
Pin
No.
Digital
Analog
Name Description
Figure 8. CY8C20646, CY8C20666 PSoC Device
1NC No connection
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O I P2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP4[3]
7I/O IP4[1]
8I/O IP3[7]
9I/O IP3[5]
10 I/O IP3[3]
11 I/O IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14 NC No connection
15 NC No connection
16 IOHR IP1[3] SPI CLK
17 IOHR IP1[1] ISSP CLK[1], I2C SCL, SPI MOSI
18 Power Vss Ground connection
19 I/O D+ USB D+
20 I/O D- USB D-
21 Power Vdd Supply voltage
22 IOHR IP1[0] ISSP DATA[1], I2C SDA, SPI CLK
23 IOHR IP1[2]
24 IOHR IP1[4] Optional external clock input
(EXTCLK)
25 IOHR IP1[6]
26 Input XRES Active high external reset with
internal pull down
27 I/O IP3[0]
28 I/O IP3[2]
29 I/O IP3[4] Pin
No.
Digital
Analog
Name Description
30 I/O IP3[6] 40 IOH IP0[6]
31 I/O IP4[0] 41 Power Vdd Supply voltage
32 I/O IP4[2] 42 NC No connection
33 I/O IP2[0] 43 NC No connection
34 I/O IP2[2] 44 IOH IP0[7]
35 I/O IP2[4] 45 IOH IP0[5]
36 I/O IP2[6] 46 IOH IP0[3] Integrating input
37 IOH IP0[0] 47 Power Vss Ground connection
38 IOH IP0[2] 48 IOH IP0[1]
39 IOH IP0[4] CP Power Vss Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
(Top View)
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
Vdd
P0[6], AI
P0[2], AI
P0[0], AI
10
11
12
AI , P2[7]
NC
AI, XOut, P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI, P4[3]
AI, P4[1]
AI, P3[7]
AI, P3[5]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[4], AI
P2[2], AI
P2[0], AI
P4[2], AI
P4[0], AI
P3[6], AI
P3[4], AI
P3[2], AI
P3[0], AI
XRES
P1[6], AI
P2[6], AI
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C SDA, SPI MISO, A I, P1[5]
NC
SPI CLK, AI, P1[3]
AI, CLK6, I2C SCL, SPI MOSI, P1[1]
Vss
D+
D-
Vdd
AI, DATA1, I2C SDA, SPI CLK, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
NC
NC
NC
P0[4], AI
P0[1], AI
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 16 of 39
48-Pin QFN OCD
The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit
debugging.[4]
Table 10. Pin Definitions - CY8C20066 PSoC Device [2, 3]
Pin
No.
Digital
Analog
Name Description
Figure 9. CY8C20066 PSoC Device
1OCDOE OCD mode direction pin
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O I P2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP4[3]
7I/O IP4[1]
8I/O IP3[7]
9I/O IP3[5]
10 I/O IP3[3]
11 I/O IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14 CCLK OCD CPU clock output
15 HCLK OCD high speed clock output
16 IOHR IP1[3] SPI CLK.
17 IOHR IP1[1] ISSP CLK[1], I2C SCL, SPI MOSI
18 Power Vss Ground connection
19 I/O D+ USB D+
20 I/O D- USB D-
21 Power Vdd Supply voltage
22 IOHR IP1[0] ISSP DATA(1), I2C SDA, SPI CLK
23 IOHR IP1[2] Pin
No.
Digital
Analog
Name Description
24 IOHR IP1[4] Optional external clock input
(EXTCLK)
37 IOH IP0[0]
25 IOHR IP1[6] 38 IOH IP0[2]
26 Input XRES Active high external reset with
internal pull down
39 IOH IP0[4]
27 I/O IP3[0] 40 IOH IP0[6]
28 I/O IP3[2] 41 Power Vdd Supply voltage
29 I/O IP3[4] 42 OCDO OCD even data I/O
30 I/O IP3[6] 43 OCDE OCD odd data output
31 I/O IP4[0] 44 IOH IP0[7]
32 I/O IP4[2] 45 IOH IP0[5]
33 I/O IP2[0] 46 IOH IP0[3] Integrating input
34 I/O IP2[2] 47 Power Vss Ground connection
35 I/O IP2[4] 48 IOH IP0[1]
36 I/O IP2[6] CP Power Vss Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
(Top View)
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
Vdd
P0[6], AI
P0[2], AI
P0[0], AI
10
11
12
A
I, P2[7]
AI, XOut, P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI, P3[7]
AI, P3[5]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[4], AI
P2[2], AI
P2[0], AI
P4[2], AI
P4[0], AI
P3[6], AI
P3[4], AI
P3[2], AI
P3[0], AI
XRES
P1[6], AI
P2[6], AI
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C SDA, SPI MISO, AI, P1[5]
SPI CLK, AI, P1[3]
AI, CLK6, I2C SCL, SPI MOSI, P1[1]
Vss
D+
D-
Vdd
AI, DATA1, I2C SDA, SPI CLK, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
P0[4], AI
P0[1], AI
OCDO
E
CCLK
HCLK
OCDE
OCDO
Note
4. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 17 of 39
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20x36/46/66/96 PSoC devices. For the latest electrical
specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc.
F ig u r e 1 0. Vo lt ag e v e rs u s C P U F r eq u en c y F i gu r e 11 . I MO F r eq u en c y Tr i m O p t i o n s
The following table lists the units of measure that are used in this section.
Table 11. Units of Measure
Symbol Unit of Measure Symbol Unit of Measure
°C degree Celsius mA milli-ampere
dB decibels ms milli-second
fF femto farad mV milli-volts
Hz hertz nA nanoampere
KB 1024 bytes ns nanosecond
Kbit 1024 bits nV nanovolts
kHz kilohertz Ωohm
ksps kilo samples per second pA picoampere
kΩkilohm pF picofarad
MHz megahertz pp peak-to-peak
MΩmegaohm ppm parts per million
μAmicroampere ps picosecond
μFmicrofarad sps samples per second
μHmicrohenry ssigma: one standard deviation
μsmicrosecond Vvolts
μWmicrowatts
5.5V
750 kHz 24 MHz
CPU Freque ncy
Vd d Vo lt ag e
5.5V
750 kHz 6 MHz 24 MHz
IMO Frequency
Vd d Vol t ag e
3 MHz
1.71V1.71V
3 MHz
Valid
Operating
Region
SLIMO
Mode
= 01
12 MHz
SLIMO
Mode
= 00
SLIMO
Mode
= 10
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 18 of 39
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Operating Temperature
Table 12. Absolute Maximum Ratings
Symbol Description Conditions Min Typ Max Units
TSTG Storage Temperature Higher storage temperatures reduces data
retention time. Recommended Storage
Temperature is +25°C ± 25°C. Extended
duration storage temperatures above 85oC
degrades reliability.
–55 +25 +125 °C
Vdd Supply Voltage Relative to Vss –0.5 –+6.0 V
VIO DC Input Voltage Vss – 0.5 –Vdd + 0.5 V
VIOZ DC Voltage Applied to Tri-state Vss –0.5 –Vdd + 0.5 V
IMIO Maximum Current into any Port Pin –25 –+50 mA
ESD Electro Static Discharge Voltage Human Body Model ESD 2000 – – V
LU Latch up Current In accordance with JESD78 standard – – 200 mA
Table 13. Operating Temperature
Symbol Description Conditions Min Typ Max Units
TAAmbient Temperature –40 –+85 °C
TJOperational Die Temperature The temperature rise from ambient to junction
is package specific. Refer the table Thermal
Impedances per Package on page 34. The
user must limit the power consumption to
comply with this requirement.
–40 –+100 °C
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 19 of 39
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and
–40°C ≤ TA ≤ 85°C, 2.4V to 3.0V and –40°C ≤ TA ≤ 85°C, or 1.71V to 2.4V and –40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V and 3.3V at 25°C and are for design guidance only.
Table 14. DC Chip-Level Specifications
Symbol Description Conditions Min Typ Max Units
Vdd Supply Voltage Refer the table DC POR and LVD
Specifications on page 24
1.71 –5.5 V
IDD24 Supply Current, IMO = 24 MHz Conditions are Vdd = 3.0V, TA = 25°C,
CPU = 24 MHz. CapSense running at 12
MHz, no I/O sourcing current
–2.88 4.0 mA
IDD12 Supply Current, IMO = 12 MHz Conditions are Vdd = 3.0V, TA = 25°C,
CPU = 12 MHz. CapSense running at 12
MHz, no I/O sourcing current
–1.71 2.6 mA
IDD6 Supply Current, IMO = 6 MHz Conditions are Vdd = 3.0V, TA = 25°C,
CPU = 6 MHz. CapSense running at 6 MHz,
no I/O sourcing current
–1.16 1.8 mA
ISB0 Deep Sleep Current Vdd = 3.0V, TA = 25°C, I/O regulator turned
off
–0.1 –μA
ISB1 Standby Current with POR, LVD and
Sleep Timer
Vdd = 3.0V, TA = 25°C, I/O regulator turned
off
–1.07 1.5 μA
Table 15. 3.0V to 5.5V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull up Resistor 4 5.6 8 kΩ
VOH1 High Output Voltage
Port 2 or 3 Pins
IOH < 10 μA, maximum of 10 mA source
current in all IOs
Vdd - 0.2 – – V
VOH2 High Output Voltage
Port 2 or 3 Pins
IOH = 1 mA, maximum of 20 mA source
current in all IOs
Vdd - 0.9 – – V
VOH3 High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH < 10 μA, maximum of 10 mA source
current in all IOs
Vdd - 0.2 – – V
VOH4 High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 5 mA, maximum of 20 mA source
current in all IOs
Vdd - 0.9 – – V
VOH5 High Output Voltage
Port 1 Pins with LDO Regulator
Enabled for 3V Out
IOH < 10 μA, Vdd > 3.1V, maximum of
4 IOs all sourcing 5 mA
2.85 3.00 3.3 V
VOH6 High Output Voltage
Port 1 Pins with LDO Regulator
Enabled for 3V Out
IOH = 5 mA, Vdd > 3.1V, maximum of
20 mA source current in all IOs
2.20 – – V
VOH7 High Output Voltage
Port 1 Pins with LDO Enabled for 2.5V
Out
IOH < 10 μA, Vdd > 2.7V, maximum of
20 mA source current in all IOs
2.35 2.50 2.75 V
VOH8 High Output Voltage
Port 1 Pins with LDO Enabled for 2.5V
Out
IOH = 2 mA, Vdd > 2.7V, maximum of
20 mA source current in all IOs
1.90 – – V
VOH9 High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V
Out
IOH < 10 μA, Vdd > 2.7V, maximum of
20 mA source current in all IOs
1.60 1.80 2.1 V
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 20 of 39
VOH10 High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V
Out
IOH = 1 mA, Vdd > 2.7V, maximum of
20 mA source current in all IOs
1.20 – – V
VOL Low Output Voltage IOL = 25 mA, Vdd > 3.3V, maximum of
60 mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example, P0[3]
and P1[5])
––0.75V
VIL Input Low Voltage – – 0.80 V
VIH Input High Voltage 2.00 – V
VHInput Hysteresis Voltage –80 –mV
IIL Input Leakage (Absolute Value) –0.001 1μA
CPIN Pin Capacitance Package and pin dependent
Tem p = 25 °C
0.5 1.7 5pF
Table 15. 3.0V to 5.5V DC GPIO Specifications (continued)
Symbol Description Conditions Min Typ Max Units
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 21 of 39
Table 16. 2.4V to 3.0V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull up Resistor 4 5.6 8 kΩ
VOH1 High Output Voltage
Port 2 or 3 Pins
IOH < 10 μA, maximum of 10 mA
source current in all IOs
Vdd - 0.2 – – V
VOH2 High Output Voltage
Port 2 or 3 Pins
IOH = 0.2 mA, maximum of 10 mA
source current in all IOs
Vdd - 0.4 – – V
VOH3 High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH < 10 μA, maximum of 10 mA
source current in all IOs
Vdd - 0.2 – – V
VOH4 High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all IOs
Vdd - 0.5 – – V
VOH5A High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V
Out
IOH < 10 μA, Vdd > 2.4V, maximum of
20 mA source current in all IOs
1.50 1.80 2.1 V
VOH6A High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V
Out
IOH = 1 mA, Vdd > 2.4V, maximum of
20 mA source current in all IOs
1.20 – – V
VOL Low Output Voltage IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
– – 0.75 V
VIL Input Low Voltage – – 0.72 V
VIH Input High Voltage 1.4 – V
VHInput Hysteresis Voltage –80 –mV
IIL Input Leakage (Absolute Value) –0.001 1μA
CPIN Capacitive Load on Pins Package and pin dependent
Tem p = 25 oC
0.5 1.7 5pF
Table 17. 1.71V to 2.4V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull up Resistor 4 5.6 8 kΩ
VOH1 High Output Voltage
Port 2 or 3 Pins
IOH = 10 μA, maximum of 10 mA
source current in all I/Os
Vdd - 0.2 – – V
VOH2 High Output Voltage
Port 2 or 3 Pins
IOH = 0.5 mA, maximum of 10 mA
source current in all I/Os
Vdd - 0.5 – – V
VOH3 High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 100 μA, maximum of 10 mA
source current in all I/Os
Vdd - 0.2 – – V
VOH4 High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all I/Os
Vdd - 0.5 – – V
VOL Low Output Voltage IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
––0.4V
VIL Input Low Voltage – – 0.3 x Vdd V
VIH Input High Voltage 0.65 x Vdd – V
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 22 of 39
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
VHInput Hysteresis Voltage –80 –mV
IIL Input Leakage (Absolute Value) –0.001 1μA
CPIN Capacitive Load on Pins Package and pin dependent
Te mp = 2 5 oC
0.5 1.7 5pF
Table 17. 1.71V to 2.4V DC GPIO Specifications (continued)
Symbol Description Conditions Min Typ Max Units
Table 18.DC Characteristics – USB Interface
Symbol Description Conditions Min Typ Max Units
Rusbi USB D+ Pull Up Resistance With idle bus 0.900 - 1.575 kΩ
Rusba USB D+ Pull Up Resistance While receiving traffic 1.425 - 3.090 kΩ
Vohusb Static Output High 2.8 - 3.6 V
Volusb Static Output Low -0.3V
Vdi Differential Input Sensitivity 0.2 - V
Vcm Differential Input Common Mode
Range
0.8 - 2.5 V
Vse Single Ended Receiver Threshold 0.8 - 2.0 V
Cin Transceiver Capacitance - 50 pF
Iio Hi-Z State Data Line Leakage On D+ or D- line -10 - +10 μA
Rps2 PS/2 Pull Up Resistance 3 5 7 kΩ
Rext External USB Series Resistor In series with each USB pin 21.78 22.0 22.22 Ω
Table 19. DC Analog Mux Bus Specifications
Symbol Description Conditions Min Typ Max Units
RSW Switch Resistance to Common Analog
Bus
– – 800 Ω
RGND Resistance of Initialization Switch to
Vss
– – 800 Ω
The maximum pin voltage for measuring RSW and RGND is 1.8V
Table 20. DC Comparator Specifications
Symbol Description Conditions Min Typ Max Units
VLPC Low Power Comparator (LPC)
common mode
Maximum voltage limited to Vdd 0.0 – 1.8 V
ILPC LPC supply current – 10 40 μA
VOSLPC LPC voltage offset – 2.5 30 mV
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 23 of 39
Comparator User Module Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V.
ADC Electrical Specifications
Table 21. Comparator User Module Electrical Specifications
Symbol Description Conditions Min Typ Max Units
TCOMP Comparator Response Time 50 mV overdrive 70 100 ns
Offset 2.5 30 mV
Current Average DC current, 50 mV
overdrive
20 80 µA
PSRR Supply voltage >2V Power Supply Rejection Ratio 80 dB
Supply voltage <2V Power Supply Rejection Ratio 40 dB
Input
Range
01.5 V
Note
5. Monotonicity is not guaranteed.
Table 22. ADC User Module Electrical Specifications
Symbol Description Conditions Min Typ Max Units
Input
VIN Input Voltage Range This gives 72% of maximum
code
Vss 1.3 V
CIN Input Capacitance 5pF
RES Resolution Settings 8, 9, or 10 8 10 Bits
S8 8-Bit Sample Rate Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data clock)
23.4375 ksps
S10 10-Bit Sample Rate Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data clock)
5.859 ksps
DC Accuracy
DNL[5] Differential Nonlinearity For any configuration -1 +2 LSB
INL Integral Nonlinearity For any configuration -2 +2 LSB
Eoffset Offset Error 0 15 90 mV
IADC Operating Current 275 350 μA
FCLK Data Clock Source is chip’s internal main
oscillator. See device data
sheet for accuracy.
2.25 12 MHz
PSRR Power Supply Rejection Ration
PSRR (Vdd>3.0V) 24 dB
PSRR (2.2 < Vdd < 3.0) 30 dB
PSRR (2.0 < Vdd < 2.2) 12 dB
PSRR (Vdd < 2.0) 0 dB
Egain Gain Error For any resolution 1 5 %FSR
RIN Input Resistance Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution.
1/(500fF*
Data-Clock)
1/(400fF*
Data-Clock)
1/(300fF*
Data-Clock)
Ω
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 24 of 39
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 23. DC POR and LVD Specifications
Symbol Description Conditions Min Typ Max Units
VPPOR0
VPPOR1
VPPOR2
VPPOR3
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b, HPOR = 0
PORLEV[1:0] = 00b, HPOR = 1
PORLEV[1:0] = 01b, HPOR = 1
PORLEV[1:0] = 10b, HPOR = 1
Vdd must be greater than or equal to
1.71V during startup, reset from the XRES
pin, or reset from watchdog.
1.61
–
1.66
2.36
2.60
2.82
1.71
2.41
2.66
2.95
V
V
V
V
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40[6]
2.64[7]
2.85[8]
2.95
3.06
1.84
1.75[9]
4.62
2.45
2.71
2.92
3.02
3.13
1.90
1.80
4.73
2.51
2.78
2.99
3.09
3.20
2.32
1.84
4.83
V
V
V
V
V
V
V
V
Notes
6. Always greater than 50 mV above VPPOR1 voltage for falling supply.
7. Always greater than 50 mV above VPPOR2 voltage for falling supply.
8. Always greater than 50 mV above VPPOR3 voltage for falling supply.
9. Always greater than 50 mV above VPPOR0 voltage for falling supply.
Table 24. DC Programming Specifications
Symbol Description Conditions Min Typ Max Units
VddIWRITE Supply Voltage for Flash Write
Operations
1.71 –5.25 V
IDDP Supply Current During
Programming or Verify
– 5 25 mA
VILP Input Low Voltage During
Programming or Verify
See the appropriate DC General Purpose
IO Specifications on page 19
– – VIL V
VIHP Input High Voltage During
Programming or Verify
See appropriate DC General Purpose IO
Specifications on page 19 table on pages
15 or 16
VIH – – V
IILP Input Current when Applying Vilp
to P1[0] or P1[1] During
Programming or Verify
Driving internal pull down resistor – – 0.2 mA
IIHP Input Current when Applying Vihp
to P1[0] or P1[1] During
Programming or Verify
Driving internal pull down resistor – – 1.5 mA
VOLP Output Low Voltage During
Programming or Verify
– – Vss + 0.75 V
VOHP Output High Voltage During
Programming or Verify
See appropriate DC General Purpose IO
Specifications on page 19 table on page
16. For Vdd > 3V use VOH4 in Table 13 on
page 18.
VOH –Vdd V
FlashENPB Flash Write Endurance Erase/write cycles per block 50,000 – – -
FlashDR Flash Data Retention Following maximum Flash write cycles;
ambient temperature of 55°C
10 20 –Years
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 25 of 39
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 25. AC Chip-Level Specifications
Symbol Description Conditions Min Typ Max Units
FCPU CPU Frequency 5.7 –25.2 MHz
F32K1 Internal Low Speed Oscillator Frequency 19 32 50 kHz
FIMO24 Internal Main Oscillator Frequency at 24
MHz Setting
22.8 24 25.2 MHz
FIMO12 Internal Main Oscillator Frequency at 12
MHz Setting
11.4 12 12.6 MHz
FIMO6 Internal Main Oscillator Frequency at 6
MHz Setting
5.7 6.0 6.3 MHz
DCIMO Duty Cycle of IMO 40 50 60 %
TRAMP Supply Ramp Time 20 – – μs
TXRST External Reset Pulse Width at Power Up After supply voltage is valid 1ms
TXRST2 External Reset Pulse Width after Power
Up[10] Applies after part has booted 10 μs
Note
10. The minimum required XRES pulse length is longer when programming the device (see Table 32 on page 28).
[+] Feedback
CY8C20X36/46/66/96
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AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 12. GPIO Timing Diagram
Table 26. AC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
FGPIO GPIO Operating Frequency Normal Strong Mode Port 0, 1 0
0
–
–
6 MHz for
1.71V<Vdd<2.4V
12 MHz for
2.4V<Vdd<5.5V
MHz
TRise23 Rise Time, Strong Mode, Cload = 50 pF
Ports 2 or 3
Vdd = 3.0 to 3.6V, 10% – 90% 15 – 80 ns
TRise23L Rise Time, Strong Mode Low Supply,
Cload = 50 pF, Ports 2 or 3
Vdd = 1.71 to 3.0V, 10% – 90% 15 – 80 ns
TRise01 Rise Time, Strong Mode, Cload = 50 pF
Ports 0 or 1
Vdd = 3.0 to 3.6V, 10% – 90%
LDO enabled or disabled
10 – 50 ns
TRise01L Rise Time, Strong Mode Low Supply,
Cload = 50 pF, Ports 0 or 1
Vdd = 1.71 to 3.0V, 10% – 90%
LDO enabled or disabled
10 – 80 ns
TFall Fall Time, Strong Mode, Cload = 50 pF
All Ports
Vdd = 3.0 to 3.6V, 10% – 90% 10 – 50 ns
TFallL Fall Time, Strong Mode Low Supply,
Cload = 50 pF, All Ports
Vdd = 1.71 to 3.0V, 10% – 90% 10 – 70 ns
TFall
TRise23
TRise01
90%
10%
GPIO Pin
Output
Voltage
TRise23L
TRise01L
TFallL
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 27 of 39
AC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
AC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 27.AC Characteristics – USB Data Timings
Symbol Description Conditions Min Typ Max Units
Tdrate Full speed data rate Average bit rate 12–0.25% 12 12 + 0.25% MHz
Tdjr1 Receiver data jitter tolerance To next transition -18.5 – 18.5 ns
Tdjr2 Receiver data jitter tolerance To pair transition -9 – 9 ns
Tudj1 Driver differential jitter To next transition -3.5 – 3.5 ns
Tudj2 Driver differential jitter To pair transition -4.0 – 4.0 ns
Tfdeop Source jitter for differential
transition
To SE0 transition -2 – 5 ns
Tfeopt Source SE0 interval of EOP 160 – 175 ns
Tfeopr Receiver SE0 interval of EOP 82 – ns
Tfst Width of SE0 interval during
differential transition
–14ns
Table 28.AC Characteristics – USB Driver
Symbol Description Conditions Min Typ Max Units
Tr Transition rise time 50 pF 4 – 20 ns
Tf Transition fall time 50 pF 4 – 20 ns
TR Rise/fall time matching 90.00 – 111.1 %
Vcrs Output signal crossover voltage 1.3 – 2.0 V
Table 29. AC Low Power Comparator Specifications
Symbol Description Conditions Min Typ Max Units
TLPC Comparator Response Time, 50
mV Overdrive
50 mV overdrive does not include
offset voltage.
100 ns
Table 30. AC Analog Mux Bus Specifications
Symbol Description Conditions Min Typ Max Units
FSW Switch Rate Maximum pin voltage when measuring
switch rate is 1.8Vp-p
––6.3MHz
Table 31. AC External Clock Specifications
Symbol Description Conditions Min Typ Max Units
FOSCEXT Frequency 0.750 –25.2MHz
– High Period 20.6 –5300 ns
– Low Period 20.6 ––ns
– Power Up IMO to Switch 150 – – μs
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 28 of 39
AC Programming Specifications
Figure 13. AC Waveform
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 32. AC Programming Specifications
Symbol Description Conditions Min Typ Max Units
TRSCLK Rise Time of SCLK 1 – 20 ns
TFSCLK Fall Time of SCLK 1 – 20 ns
TSSCLK Data Set up Time to Falling Edge of SCLK 40 – – ns
THSCLK Data Hold Time from Falling Edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
TERASEB Flash Erase Time (Block) – – 18 ms
TWRITE Flash Block Write Time – – 25 ms
TDSCLK Data Out Delay from Falling Edge of SCLK 3.6 < Vdd – – 60 ns
TDSCLK3 Data Out Delay from Falling Edge of SCLK 3.0 ≤ Vdd ≤ 3.6 – – 85 ns
TDSCLK2 Data Out Delay from Falling Edge of SCLK 1.71 ≤ Vdd ≤ 3.0 – – 130 ns
TXRST3 External Reset Pulse Width after Power Up Required to enter programming mode
when coming out of sleep
263 – – μs
SCLK (P1[1])
TRSCLK TFSCLK
SDATA (P1[0])
TSSCLK THSCLK TDSCLK
[+] Feedback
CY8C20X36/46/66/96
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AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 33. AC Characteristics of the I2C SDA and SCL Pins
Symbol Description
Standard
Mode Fast Mode Units
Min Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHz
THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is
generated.
4.0 –0.6–μs
TLOWI2C LOW Period of the SCL Clock 4.7 –1.3–μs
THIGHI2C HIGH Period of the SCL Clock 4.0 –0.6–μs
TSUSTAI2C Setup Time for a Repeated START Condition 4.7 –0.6–μs
THDDATI2C Data Hold Time 0 –0–μs
TSUDATI2C Data Setup Time 250 –100
[11] –ns
TSUSTOI2C Setup Time for STOP Condition 4.0 –0.6–μs
TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 –1.3–μs
TSPI2C Pulse Width of spikes are suppressed by the input filter. ––050ns
SDA
SCL
SSr SP
TBUFI2C
TSPI2C
THDSTAI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
Note
11. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This automatically be the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
[+] Feedback
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Table 34. SPI Master AC Specifications
Symbol Description Conditions Min Typ Max Units
FSCLK SCLK clock frequency VDD ≥ 2.4V
VDD < 2.4V
6
3
MHz
DC SCLK duty cycle 50 %
TSETUP MISO to SCLK setup time VDD ≥ 2.4V
VDD < 2.4V
60
100
ns
THOLD SCLK to MISO hold time 40 ns
TOUT_VAL SCLK to MOSI valid time 40 ns
TOUT_HIGH MOSI high time 40 ns
Table 35. SPI Slave AC Specifications
Symbol Description Conditions Min Typ Max Units
FSCLK SCLK clock frequency
VDD ≥ 2.4V
VDD < 2.4V
12
6
MHz
TLOW SCLK low time 41.67 ns
THIGH SCLK high time 41.67 ns
TSETUP MOSI to SCLK setup time 30 ns
THOLD SCLK to MOSI hold time 50 ns
TSS_MISO SS high to MISO valid 153 ns
TSCLK_MISO SCLK to MISO valid 125 ns
TSS_HIGH SS high time 50 ns
TSS_CLK Time from SS low to first SCLK 2/SCLK ns
TCLK_SS Time from last SCLK to SS high 2/SCLK ns
[+] Feedback
CY8C20X36/46/66/96
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Packaging Information
This section illustrates the packaging specifications for the CY8C20x36/46/66/96 PSoC device, along with the thermal impedances
for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 15. 16-pin QFN No E-pad 3x3mm Package Outline (Sawn)
001-09116 *D
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 32 of 39
Figure 16. 24-Pin (4x4 x 0.6 mm) QFN
Figure 17. 32-Pin (5x5 x 0.6 mm) QFN
001-13937 *B
001-42168 *C
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 33 of 39
Figure 18. 48-Pin (300 MIL) SSOP
Figure 19. 48-Pin (7x7 mm) QFN
Important Notes
■For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■Pinned vias for thermal conduction are not required for the low power PSoC device.
51-85061 *C
0.095
0.025
0.008
SEATING PLANE
0.420
0.088
.020
0.292
0.299
0.395
0.092
BSC
0.110
0.016
0.620
0.008
0.0135
0.630
DIMENSIONS IN INCHES MIN.
MAX.
0.040
0.024
0°-8°
GAUGE PLANE
.010
124
25 48
0.004
0.005
0.010
001-13191 *C
[+] Feedback
CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 34 of 39
Thermal Impedances
Solder Reflow Peak Temperature
This table lists the minimum solder reflow peak temperature to achieve good solderability.
Table 36. Thermal Impedances per Package
Package Typical θJA [12]
16 QFN 32.69oC/W
24 QFN[13] 20.90oC/W
32 QFN[13] 19.51oC/W
48 SSOP 69oC/W
48 QFN[13] 17.68oC/W
Table 37. Solder Reflow Peak Temperature
Package Minimum Peak Temperature[14] Maximum Peak Temperature
16 QFN 240oC260oC
24 QFN 240oC260oC
32 QFN 240oC260oC
48 SSOP 220oC260oC
48 QFN 240oC260oC
Notes
12. TJ = TA + Power x θJA.
13. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
14. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
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CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 35 of 39
Development Tool Selection
Software
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at
http://www.cypress.com/psocdesigner and includes a free C
compiler.
PSoC Programmer
PSoC Programmer is flexible enough and is used on the bench
in development and is also suitable for factory programming.
PSoC Programmer works either as a standalone programming
application or operates directly from PSoC Designer or PSoC
Express. PSoC Programmer software is compatible with both
PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC
programmer is available free of cost at
http://www.cypress.com/psocprogrammer.
Development Kits
All development kits are sold at the Cypress Online Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■PSoC Designer Software CD
■ICE-Cube In-Circuit Emulator
■ICE Flex-Pod for CY8C29x66 Family
■Cat-5 Adapter
■Mini-Eval Programming Board
■110 ~ 240V Power Supply, Euro-Plug Adapter
■iMAGEcraft C Compiler (Registration Required)
■ISSP Cable
■USB 2.0 Cable and Blue Cat-5 Cable
■2 CY8C29466-24PXI 28-PDIP Chip Samples
Evaluation Tools
All evaluation tools are sold at the Cypress Online Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■MiniProg Programming Unit
■MiniEval Socket Programming and Evaluation Board
■28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■PSoC Designer Software CD
■Getting Started Guide
■USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■Evaluation Board with LCD Module
■MiniProg Programming Unit
■28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■PSoC Designer Software CD
■Getting Started Guide
■USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
■PSoCEvalUSB Board
■LCD Module
■MIniProg Programming Unit
■Mini USB Cable
■PSoC Designer and Example Projects CD
■Getting Started Guide
■Wire Pack
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CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 36 of 39
Device Programmers
All device programmers are purchased from the Cypress Online
Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■Modular Programmer Base
■Three Programming Module Cards
■MiniProg Programming Unit
■PSoC Designer Software CD
■Getting Started Guide
■USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■CY3207 Programmer Unit
■PSoC ISSP Software CD
■110 ~ 240V Power Supply, Euro-Plug Adapter
■USB 2.0 Cable
Accessories (Emulation and Programming)
Third-Party Tools
Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and
production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC
device, refer Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/?rID2748.
Table 38. Emulation and Programming Accessories
Part Number Pin Package Flex-Pod Kit[15] Foot Kit[16] Adapter[17]
CY8C20236-24LKXI 16 QFN CY3250-20266QFN CY3250-16QFN-RK See note 15
CY8C20246-24LKXI 16 QFN CY3250-20266QFN CY3250-16QFN-FK See note 17
CY8C20336-24LQXI 24 QFN CY3250-20366QFN CY3250-24QFN-FK See note 15
CY8C20346-24LQXI 24 QFN CY3250-20366QFN CY3250-24QFN-FK See note 17
CY8C20396-24LQXI 24 QFN Not Available
CY8C20436-24LQXI 32 QFN CY3250-20466QFN CY3250-32QFN-RK See note 15
CY8C20446-24LQXI 32 QFN CY3250-20466QFN CY3250-32QFN-FK See note 17
CY8C20466-24LQXI 32 QFN CY3250-20466QFN CY3250-32QFN-FK See note 17
CY8C20496-24LQXI 32 QFN Not Available
CY8C20536-24PVXI 48 SSOP CY3250-20X66 CY3250-48SSOP-FK See note 17
CY8C20546-24PVXI 48 SSOP CY3250-20X66 CY3250-48SSOP-FK See note 17
CY8C20566-24PVXI 48 SSOP CY3250-20X66 CY3250-48SSOP-FK See note 17
CY8C20636-24LTXI 48 QFN CY3250-20666QFN CY3250-48QFN-FK See note 17
CY8C20646-24LTXI 48 QFN CY3250-20666QFN CY3250-48QFN-FK See note 17
CY8C20666-24LTXI 48 QFN CY3250-20666QFN CY3250-48QFN-FK See note 17
Notes
15. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
16. Foot kit includes surface mount feet that can be soldered to the target PCB.
17. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
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CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 37 of 39
Ordering Information
The following table lists the CY8C20x36/46/66/96 PSoC devices' key package features and ordering codes.
Table 39. PSoC Device Key Features and Ordering Information
Package Ordering Code Flash
(Bytes)
SRAM
(Bytes)
CapSense
Blocks
Digital I/O
Pins
Analog
Inputs[18] XRES
Pin USB
16-Pin (3x3x0.6mm) QFN CY8C20236-24LKXI 8K 1K 113 13 Yes No
16-Pin (3x3x0.6mm) QFN
(Tape and Reel)
CY8C20236-24LKXIT 8K 1K 113 13 Ye s No
16 Pin (3x3 x 0.6 mm) QFN CY8C20246-24LKXI 16K 2K 113 13 Yes No
16 Pin (3x3 x 0.6 mm) QFN
(Tape and Reel)
CY8C20246-24LKXIT 16K 2K 113 13 Ye s No
24-Pin (4x4x0.6mm) QFN CY8C20336-24LQXI 8K 1K 120 20 Yes No
24-Pin (4x4x0.6mm) QFN
(Tape and Reel)
CY8C20336-24LQXIT 8K 1K 120 20 Ye s No
24 Pin (4x4 x 0.6 mm) QFN CY8C20346-24LQXI 16K 2K 120 20 Yes No
24 Pin (4x4 x 0.6 mm) QFN
(Tape and Reel)
CY8C20346-24LQXIT 16K 2K 120 20 Ye s No
24-Pin (4x4x0.6mm) QFN CY8C20396-24LQXI 16K 2K 119 19 Ye s Yes
24-Pin (4x4x0.6mm) QFN
(Tape and Reel)
CY8C20396-24LQXIT 16K 2K 119 19 Ye s Yes
32-Pin (5x5x0.6mm) QFN CY8C20436-24LQXI 8K 1K 128 28 Yes No
32-Pin (5x5x0.6mm) QFN
(Tape and Reel)
CY8C20436-24LQXIT 8K 1K 128 28 Ye s No
32 Pin (5x5 x 0.6 mm) QFN CY8C20446-24LQXI 16K 2K 128 28 Yes No
32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)
CY8C20446-24LQXIT 16K 2K 128 28 Ye s No
32 Pin (5x5 x 0.6 mm) QFN CY8C20466-24LQXI 32K 2K 128 28 Yes No
32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)
CY8C20466-24LQXIT 32K 2K 128 28 Ye s No
32 Pin (5x5 x 0.6 mm) QFN CY8C20496-24LQXI 16K 2K 125 25 Yes No
32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)
CY8C20496-24LQXIT 16K 2K 125 25 Ye s No
48-Pin SSOP CY8C20536-24PVXI 8K 1K 136 36 Ye s No
48-Pin SSOP
(Tape and Reel)
CY8C20536-24PVXIT 8K 1K 136 36 Ye s No
48-Pin SSOP CY8C20546-24PVXI 16K 2K 136 36 Ye s No
48-Pin SSOP
(Tape and Reel)
CY8C20546-24PVXIT 16K 2K 136 36 Ye s No
48-Pin SSOP CY8C20566-24PVXI 32K 2K 136 36 Yes No
48-Pin SSOP
(Tape and Reel)
CY8C20566-24PVXIT 32K 2K 136 36 Ye s No
48 Pin (7x7 mm) QFN CY8C20636-24LTXI 8K 1K 136 36 Ye s No
48 Pin (7x7 mm) QFN
(Tape and Reel)
CY8C20636-24LTXIT 8K 1K 136 36 Ye s No
48 Pin (7x7 mm) QFN CY8C20646-24LTXI 16K 2K 136 36 Ye s Yes
48 Pin (7x7 mm) QFN
(Tape and Reel)
CY8C20646-24LTXIT 16K 2K 136 36 Yes Yes
48 Pin (7x7 mm) QFN CY8C20666-24LTXI 32K 2K 136 36 Ye s Yes
48 Pin (7x7 mm) QFN
(Tape and Reel)
CY8C20666-24LTXIT 32K 2K 136 36 Yes Yes
48 Pin (7x7 mm) QFN (OCD)[4] CY8C20066-24LTXI 32K 2K 136 36 Yes Yes
Notes
18. Dual-function Digital I/O Pins also connect to the common analog mux.
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CY8C20X36/46/66/96
Document Number: 001-12696 Rev. *E Page 38 of 39
Document History Page
Document Title: CY8C20x36/46/66/96 CapSense® Applications
Document Number: 001-12696
Revision ECN Origin of Change Submission Date Description of Change
** 766857 HMT See ECN New silicon and document (Revision **).
*A 1242866 HMT See ECN Add features. Update all applicable sections. Update specs.
Fix 24-pin QFN pinout moving pins inside. Update package
revisions. Update and add to Emulation and Programming
Accessories table.
*B 2174006 AESA See ECN Added 48-Pin SSOP Part Pinout
Modified symbol RVDD to RGND in Table DC Analog Mux Bus
Specification
Added footnote in Table DC Analog Mux Bus Specification
Added 16K FLASH Parts. Updated Notes, Package Diagrams
and Ordering Information table. Updated Thermal Impedance
and Solder Reflow tables
*C 2587518 TOF/JASM/MNU/
HMT
10/13/08 Converted from Preliminary to Final
Fixed broken links. Updated data sheet template.
Added operating voltage ranges with USB
ADC resolution changed from 10-bit to 8-bit
Included ADC specifications table
Included Comparator specification table
Included Voh7, Voh8, Voh9, Voh10 specs
Flash data retention – condition added to Note
Input leakage spec changed to 1 μA max
GPIO rise time for ports 0,1 and ports 2,3 made common
AC Programming specifications updated
Included AC Programming cycle timing diagram
AC SPI specification updated
The VIH for 3.0<Vdd<2.4 changed to 1.6 from 2.0
Added USB specification
Added SPI CLK to P1[0]
Updated package diagrams
Updated thermal impedances for QFN packages
Updated FGPIO parameter in Table 23
Updated voltage ranges for FSPIM and FSPIS in Table 30
Update Development Tools, add Designing with PSoC
Designer. Edit, fix links, notes and table format. Update RIN
formula, fix TRise parameter names in GPIO figure, fix Switch
Rate note. Update maximum data in Table 20. DC POR and
LVD Specifications.
*D 2649637 SNV/AESA 03/17/2009 Changed title to “CY8C20x36/46/66, CY8C20396
CapSense™ Applications”. Updated data sheet Features, pin
information, and ordering information sections. Updated
package diagram 001-42168 to *C.
*E 2700196 SNV/PYRS 04/30/2009 Added part numbers CY8C20496, CY8C20536, CY8C20546,
CY8C20636, CY8C20646
Updated Features on page 1
Added 48-Pin QFN without USB pin Diagram and Pin Definition
table
Added 32-Pin QFN (with USB) package
Added SPI Master and Slave AC Specificatons
Updated Emulations and Programming Accessories Table on
page 33
Updated Ordering Information on page 37
Removed reference to Hi-Tech C Compiler in Development
Tool Selection on page 35
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Document Number: 001-12696 Rev. *E Revised April 24, 2009 Page 39 of 39
PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are
property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the
trademarks of their respective holders.
CY8C20X36/46/66/96
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com
PSoC Solutions
General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb
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