LTM2883 SPI/Digital or I2C Module Isolator with Adjustable 12.5V and 5V Regulated Power DESCRIPTION FEATURES n 2500VRMS for One Minute per UL1577 UL Recognized File #E151738 Isolated Adjustable DC Power: 3V to 5V at Up to 30mA 12.5V at Up to 20mA No External Components Required SPI (LTM2883-S) or I2C (LTM2883-I) Options High Common Mode Transient Immunity: 30kV/s High Speed Operation: 10MHz Digital Isolation 4MHz/8MHz SPI Isolation 400kHz I2C Isolation 3.3V (LTM2883-3) or 5V (LTM2883-5) Operation 1.62V to 5.5V Logic Supply 10kV ESD HBM Across the Isolation Barrier Maximum Continuous Working Voltage: 560VPEAK Low Current Shutdown Mode (<10A) Low Profile (15mm x 11.25mm x 3.42mm) BGA Package (R) n n n n n n n n n n n APPLICATIONS n n n n The LTM(R)2883 is a complete galvanic 6-channel digital Module(R) (micromodule) isolator. No external components are required. A single 3.3V or 5V supply powers both sides of the interface through an integrated, isolated DC/ DC converter. A logic supply pin allows easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply. Available options are compliant with SPI and I2C (master mode only) specifications. The isolated side includes 12.5V and 5V nominal power supplies, each capable of providing more than 20mA of load current. Each supply may be adjusted from its nominal value using a single external resistor. Coupled inductors and an isolation power transformer provide 2500VRMS of isolation between the input and output logic interface. This device is ideal for systems where the ground loop is broken, allowing for a large common mode voltage range. Communication is uninterrupted for common mode transients greater than 30kV/s. All registered trademarks and trademarks are the property of their respective owners. Isolated SPI or I2C Interfaces Industrial Systems Test and Measurement Equipment Breaking Ground Loops TYPICAL APPLICATION Isolated 4MHz SPI Interface LTM2883-5S 5V VCC2 VCC AVCC2 V+ VL AV+ ON SDI SCK SDO CS SDI SCK ISOLATION BARRIER SDOE CS V- AV- CS2 SDI2 SCK2 DO2 I2 SDO SDO2 DO1 I1 GND GND2 5V AT 20mA LTM2883 Operating Through 35kV/s CM Transient SCK SD0 SCK2 = SD02 12.5V AT 20mA -12.5V AT 15mA 2V/DIV 2V/DIV REPETITIVE COMMON MODE TRANSIENTS CS SDI SCK SDO 200V/DIV 20ns/DIV 2883 TA01b 2883 TA01a 2883fd For more information www.linear.com/LTM2883 1 LTM2883 ABSOLUTE MAXIMUM RATINGS (Note 1) VCC to GND................................................... -0.3V to 6V VL to GND..................................................... -0.3V to 6V VCC2, AVCC2, AV+ to GND2............................ -0.3V to 6V V+ to GND2................................................. -0.3V to 16V V-, AV- to GND2..........................................0.3V to -16V Logic Inputs DI1, SCK, SDI, CS, SCL, SDA, SDOE, ON to GND...................................-0.3V to (VL + 0.3V) I1, I2, SDA2, SDO2 to GND2......................... -0.3V to (VCC2 + 0.3V) Logic Outputs DO1, DO2, SDO to GND...............-0.3V to (VL + 0.3V) O1, SCK2, SDI2, CS2, SCL2 to GND2......................... -0.3V to (VCC2 + 0.3V) Operating Temperature Range (Note 4) LTM2883C..........................................0C TA 70C LTM2883I...................................... -40C TA 85C LTM2883H....................................-40C TA 105C Maximum Internal Operating Temperature............. 125C Storage Temperature Range................... -40C to 125C Peak Body Reflow Temperature............................. 245C PIN CONFIGURATION LTM2883-I LTM2883-S TOP VIEW 1 2 3 4 DO2 DNC SCL SDA 5 6 7 8 DI1 GND ON VL TOP VIEW 1 A A B B C DO1 VCC GND C D D E E F F G G H J 2 3 4 SDO DO2 SCK SDI DO1 GND 5 6 7 8 CS SDOE ON VL VCC H I1 GND2 AVCC2 AV- AV+ K J I1 GND2 AVCC2 AV- AV+ V- V+ K L I2 DNC SCL2 SDA2 O1 VCC2 V- V+ BGA PACKAGE 32-PIN (15mm x 11.25mm x 3.42mm) TJMAX = 125C, JA = 30C/W, JC(BOTTOM) = 15.7C/W, JC(TOP) = 25C/W, JBOARD = 14.5C/W VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g L SDO2 I2 SCK2 SDI2 CS2 VCC2 BGA PACKAGE 32-PIN (15mm x 11.25mm x 3.42mm) TJMAX = 125C, JA = 30C/W, JC(BOTTOM) = 15.7C/W, JC(TOP) = 25C/W, JBOARD = 14.5C/W VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g 2883fd 2 For more information www.linear.com/LTM2883 LTM2883 ORDER INFORMATION PART NUMBER http://www.linear.com/product/LTM2883#orderinfo INPUT VOLTAGE PAD OR BALL FINISH PART MARKING DEVICE FINISH CODE PACKAGE TYPE MSL RATING LTM2883CY-3S#PBF LTM2883IY-3S#PBF TEMPERATURE RANGE 0C TO 70C 3V TO 3.6V LTM2883Y-3S -40C TO 85C LTM2883HY-3S#PBF -40C TO 105C LTM2883CY-5S#PBF 0C TO 70C LTM2883IY-5S#PBF 4.5V TO 5.5V LTM2883Y-5S LTM2883HY-5S#PBF SAC305 LTM2883CY-3I#PBF (RoHS) LTM2883IY-3I#PBF 3V TO 3.6V -40C TO 85C e1 BGA 4 LTM2883Y-3I -40C TO 105C 0C TO 70C -40C TO 85C LTM2883HY-3I#PBF -40C TO 105C LTM2883CY-5I#PBF 0C TO 70C LTM2883IY-5I#PBF 4.5V TO 5.5V LTM2883Y-5I -40C TO 85C LTM2883HY-5I#PBF -40C TO 105C * Device temperature grade is indicated by a label on the shipping container. * Pad or ball finish code is per IPC/JEDEC J-STD-609. * Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/BGA-assy * Terminal Finish Part Marking: www.linear.com/leadfree * This product is moisture sensitive. For more information, go to: www.linear.com/BGA-assy * This product is not recommended for second side reflow. For more information, go to: www.linear.com/BGA-assy * BGA Package and Tray Drawings: www.linear.com/packaging ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supplies VCC Input Supply Range LTM2883-3 LTM2883-5 l l 3 4.5 3.3 5 3.6 5.5 V V VL Logic Supply Range LTM2883-S LTM2883-I l l 1.62 3 5 5.5 5.5 V V ICC Input Supply Current ON = 0V LTM2883-3, ON = VL, No Load LTM2883-5, ON = VL, No Load l l l 0 25 19 10 35 28 A mA mA IL Logic Supply Current ON = 0V LTM2883-S, ON = VL LTM2883-I, ON = VL l 0 10 10 A A A 150 2883fd For more information www.linear.com/LTM2883 3 LTM2883 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 4.75 5 5.25 V 5.5 V 25 100 mV 8 80 mV 600 615 mV Output Supplies VCC2 ICC2 V+ I+ V- Regulated Output Voltage No Load l Output Voltage Operating Range (Note 2) Line Regulation ILOAD = 1mA, MIN VCC MAX l 3 Load Regulation ILOAD = 100A to 20mA l ADJ Pin Voltage ILOAD = 100A to 20mA l Voltage Ripple ILOAD = 20mA (Note 2) Efficiency ILOAD = 20mA (Note 2) 45 % Output Short Circuit Current VCC2 = 0V 45 mA Current Limit VCC2 = -5% l 20 Regulated Output Voltage No Load l 12 Line Regulation ILOAD = 1mA, MIN VCC MAX l 585 1 mVRMS mA 12.5 13 V 5 30 mV 200 mV 1.220 1.260 mV Load Regulation ILOAD = 100A to 20mA l ADJ Pin Voltage ILOAD = 100A to 20mA l Voltage Ripple ILOAD = 20mA (Note 2) Efficiency ILOAD = 20mA (Note 2) 45 % Output Short Circuit Current V+ = 0V 70 mA Current Limit V+ = -0.5V l 20 Regulated Output Voltage No Load l -12 Line Regulation ILOAD = -1mA, MIN VCC MAX l Load Regulation ILOAD = 100A to 15mA, V+ ADJ Pin Voltage ILOAD = 100A to 15mA, V+LOAD = 1.5mA 1.170 3 mA -12.5 -13 V 4 15 mV 35 mV -1.220 -1.256 mV LOAD = 1.5mA l -1.184 mVRMS Voltage Ripple ILOAD = 15mA, V+ 2 mVRMS Efficiency ILOAD = 15mA (Note 2) 45 % Output Short-Circuit Current V- = 0V 30 mA Current Limit V- = 0.5V, V+ = 1.5mA l 15 mA VITH Input Threshold Voltage ON, DI1, SDOE, SCK, SDI, CS 1.62V VL < 2.35V ON, DI1, SDOE, SCK, SDI, CS 2.35V VL I1, I2, SDO2 l 0.25 * VL l 0.33 * VL l 0.33 * VCC2 IINL Input Current VHYS Input Hysteresis (Note 2) VOH Output High Voltage DO1, DO2, SDO ILOAD = -1mA, 1.62V VL < 3V ILOAD = -4mA, 3V VL 5.5V l VL - 0.4 V O1, SCK2, SDI2, CS2, ILOAD = -4mA l VCC2 - 0.4 V I- LOAD = 1.5mA (Note 2) 10 Logic/SPI 0.75 * VL 0.67 * VL 0.67 * VCC2 1 l 150 V V V A mV VOL Output Low Voltage DO1, DO2, SDO ILOAD = 1mA, 1.62V VL < 3V ILOAD = 4mA, 3V VL 5.5V l 0.4 O1, SCK2, SDI2, CS2, ILOAD = 4mA l 0.4 V ISC Short-Circuit Current 0V (DO1, DO2, SDO) VL 0V (O1, SCK2, SDI2, CS2) VCC2 l 85 mA mA 60 V 2883fd 4 For more information www.linear.com/LTM2883 LTM2883 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I2C VIL Low Level Input Voltage SCL, SDA SDA2 l l VIH High Level Input Voltage SCL, SDA SDA2 l l IINL Input Current SCL, SDA = VL or 0V l VHYS Input Hysteresis SCL, SDA SDA2 VOH Output High Voltage SCL2, ILOAD = -2mA DO2, ILOAD = -2mA l l VOL Output Low Voltage SDA, VL = 3V, ILOAD = 3mA DO2, VL = 3V, ILOAD = 2mA SCL2, ILOAD = 2mA SDA2, No Load, SDA = 0V, 4.5V VCC2 < 5.5V SDA2, No Load, SDA = 0V, 3V < VCC2 < 4.5V l l l l l 0.3 * VL 0.3 * VCC2 V V 0.7 * VL 0.7 * VCC2 V V 1 A mV mV 0.05 * VL 0.05 * VCC2 VCC2 - 0.4 VL - 0.4 V V 0.3 0.4 0.4 0.4 0.45 0.55 V V V V V CIN Input Pin Capacitance SCL, SDA, SDA2 (Note 2) l 10 pF CB Bus Capacitive Load SCL2, Standard Speed (Note 2) SCL2, Fast Speed SDA, SDA2, SR 1V/s, Standard Speed (Note 2) SDA, SDA2, SR 1V/s, Fast Speed l l l l 400 200 400 200 pF pF pF pF Minimum Bus Slew Rate SDA, SDA2 l Short-Circuit Current SDA2 = 0, SDA = VL 0V SCL2 VCC2 0V DO2 VL SDA = 0, SDA2 = VCC2 SDA = VL, SDA2 = 0 l ISC 1 V/s 30 30 6 -1.8 100 mA mA mA mA mA ESD (HBM) (Note 2) Isolation Boundary (VCC2, V+, V-, GND2) to (VCC, VL, GND) 10 kV SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Maximum Data Rate tPHL, tPLH Propagation Delay Ix DOx, CL = 15pF (Note 3) l 10 35 MHz CL = 15pF (Figure 1) l 60 100 ns tR Rise Time CL = 15pF (Figure 1) LTM2883-I, DO2, CL = 15pF (Figure 1) l l 3 20 12.5 35 ns ns tF Fall Time CL = 15pF (Figure 1) LTM2883-I, DO2, CL = 15pF (Figure 1) l l 3 20 12.5 35 ns ns Maximum Data Rate Bidirectional Communication (Note 3) Unidirectional Communication (Note 3) l l 4 8 CL = 15pF (Figure 1) l 35 SPI tPHL, tPLH Propagation Delay tPWU Output Pulse Width Uncertainty SDI2, CS2 (Note 2) -20 MHz MHz 60 100 ns 50 ns 2883fd For more information www.linear.com/LTM2883 5 LTM2883 SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN tR Rise Time CL = 15pF (Figure 1) l tF Fall Time CL = 15pF (Figure 1) l TYP MAX UNITS 3 12.5 ns 3 12.5 ns tPZH, tPZL Output Enable Time SDOE = , RL = 1k, CL = 15pF (Figure 2) l 50 ns tPHZ, tPLZ Output Disable Time SDOE = , RL = 1k, CL = 15pF (Figure 2) l 50 ns I2C Maximum Data Rate (Note 3) l tPHL, tPLH Propagation Delay SCL SCL2, CL = 15pF (Figure 1) SDA SDA2, RL = Open, CL = 15pF (Figure 3) SDA2 SDA, RL = 1.1k, CL = 15pF (Figure 3) l l l tPWU Output Pulse Width Uncertainty SDA, SDA2 (Note 2) tHD;DAT Data Hold Time (Note 2) tR Rise Time SDA2, CL = 200pF (Figure 3) SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1k, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1) l l l SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1k, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1) tF Fall Time tSP Pulse Width of Spikes Suppressed by Input Filter 400 kHz 150 150 200 225 250 350 ns ns ns 50 ns 40 40 40 250 300 250 250 ns ns ns ns l l l 40 40 250 250 250 ns ns ns l 0 50 ns 0.6 0.6 0.6 2 2 2.5 ms ms ms TYP MAX -20 600 ns Power Supply Power-Up Time ON = to VCC2 (Min) ON = to V+ (Min) ON = to V- (Min) ISOLATION CHARACTERISTICS l l l TA = 25C. SYMBOL PARAMETER CONDITIONS MIN VISO Rated Dielectric Insulation Voltage (Notes 5, 6, 7) 1 Minute, Derived from 1 Second Test 2500 1 Second 4400 Common Mode Transient Immunity LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = ON = 3.3V, VCM = 1kV, t = 33ns (Note 2) 30 kV/s Maximum Continuous Working Voltage (Notes 2, 5) 560 400 VPEAK VRMS Partial Discharge VPD = 1050VPEAK (Notes 2, 5) Comparative Tracking Index IEC 60112 (Note 2) Depth of Erosion IEC 60112 (Note 2) Distance Through Insulation (Note 2) Input to Output Resistance (Notes 2, 5) Input to Output Capacitance (Notes 2, 5) Creepage Distance (Note 2) VIORM CTI DTI UNITS VRMS V 5 600 pC VRMS 0.017 mm 0.06 mm 109 6 pF 9.48 mm 2883fd 6 For more information www.linear.com/LTM2883 LTM2883 ISOLATION CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design and not subject to production test. Note 3: Maximum data rate is guaranteed by other measured parameters and is not tested directly. Note 4: This module includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Note 5: Device considered a 2-terminal device. Pin group A1 through B8 shorted together and pin group K1 through L8 shorted together. Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating. Note 7: In accordance with UL1577, each device is proof tested for the 2500VRMS rating by applying the equivalent positive and negative peak voltage multiplied by an acceleration factor of 1.2 for one second. 2883fd For more information www.linear.com/LTM2883 7 LTM2883 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. VCC Supply Current vs Temperature 30 Isolated Supplies vs Equal Load Current Isolated Supplies vs Equal Load Current 14 NO LOAD, REFRESH DATA ONLY 20 LTM2883-5 VCC = 5V 15 10 8 6 4 VCC2 V+ V- 2 10 -50 0 50 25 75 TEMPERATURE (C) -25 100 0 125 0 5 3.5 11.5 11.0 10.5 9.5 9.0 40 0 10 20 30 40 LOAD CURRENT (mA) -12.5 50 4.5 4.0 3.5 2.5 10 20 30 LOAD CURRENT (mA) 2883 G07 10 20 LOAD CURRENT (mA) 12.0 -10.0 LTM2883-5 + -9.5 ICC2 = I = 0A 11.5 11.0 10.5 9.0 10 20 30 40 LOAD CURRENT (mA) -10.5 VCC = 4.5V VCC = 4.75V VCC = 5V VCC = 5.5V -11.0 -11.5 -12.0 VCC = 4.5V VCC = 4.75V VCC = 5V VCC = 5.5V 0 30 V- Line Regulation vs Load Current -9.0 9.5 40 0 2883 G06 13.0 10.0 VCC = 4.5V VCC = 5V VCC = 5.5V 0 -13.0 60 V- VOLTAGE (V) 5.0 3.0 -11.5 -12.0 LTM2883-5 - 12.5 ICC2 = I = 0A V+ VOLTAGE (V) VCC2 VOLTAGE (V) 5.5 -11.0 V+ Line Regulation vs Load Current LTM2883-5 I+ = I- = 0A 30 VCC = 3V VCC = 3.15V VCC = 3.3V VCC = 3.6V -10.5 2883 G05 VCC2 Line Regulation vs Load Current 25 LTM2883-3 + -9.5 ICC2 = I = 0A VCC = 3V VCC = 3.15V VCC = 3.3V VCC = 3.6V 2883 G04 6.0 10 15 20 LOAD CURRENT (mA) -10.0 10.0 VCC = 3V VCC = 3.3V VCC = 3.6V 10 20 30 LOAD CURRENT (mA) 5 -9.0 V- VOLTAGE (V) V+ VOLTAGE (V) VCC2 VOLTAGE (V) 4.0 0 V- Line Regulation vs Load Current LTM2883-3 ICC2 = I- = 0A 12.5 4.5 VCC2 V+ V- 2883 G03 12.0 0 4 0 25 10 15 20 LOAD CURRENT (mA) 13.0 5.0 2.5 6 V+ Line Regulation vs Load Current LTM2883-3 I+ = I- = 0A 3.0 8 2883 G02 VCC2 Line Regulation vs Load Current 5.5 10 2 2883 G01 6.0 LTM2883-5 VCC = 5V 12 VCC2, V+, |V-| VOLTAGE (V) LTM2883-3 VCC = 3.3V VCC2, V+, |V-| VOLTAGE (V) SUPPLY CURRENT (mA) 12 25 14 LTM2883-3 VCC = 3.3V -12.5 50 60 2883 G08 -13.0 0 10 20 30 LOAD CURRENT (mA) 40 2883 G09 2883fd 8 For more information www.linear.com/LTM2883 LTM2883 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. V+ Load Regulation vs Temperature VCC2 Load Regulation vs Temperature 12.8 5.20 5.05 5.00 4.95 4.90 -50 12.5 12.4 LTM2883-3 VCC = 3.3V ICC2 = I- = 0A 12.3 ICC2 = 1mA ICC2 = 20mA -25 12.6 25 75 0 50 TEMPERATURE (C) 100 12.2 -50 125 -25 25 75 0 50 TEMPERATURE (C) 100 -12.5 -12.6 -12.7 -12.8 -50 125 -25 25 75 0 50 TEMPERATURE (C) 12.7 5.20 LTM2883-5 VCC = 5V 5.15 I+ = I- = 0A 5.05 5.00 -12.2 12.5 I- = 1mA I- = 20mA LTM2883-5 VCC = 5V ICC2 = I+ = 0A -12.3 V- VOLTAGE (V) V+ VOLTAGE (V) 5.10 125 V- Load Regulation vs Temperature I+ = 1mA I+ = 5mA I+ = 10mA I+ = 15mA I+ = 20mA 12.6 100 2883 G14 V+ Load Regulation vs Temperature VCC2 Load Regulation vs Temperature LTM2883-3 VCC = 3.3V ICC2 = I+ = 0A -12.4 2883 G12 2883 G10 12.4 12.3 -12.4 -12.5 4.90 -50 ICC2 = 1mA ICC2 = 20mA -25 LTM2883-5 VCC = 5V ICC2 = I- = 0A 12.2 25 75 0 50 TEMPERATURE (C) 100 125 12.1 -50 -25 0 50 25 75 TEMPERATURE (C) 100 60 LTM2883-3, VCC = 3.3V LTM2883-5, VCC = 5V 6 0.5 5 0.4 4 EFFICIENCY 30 0.3 20 0.2 0 POWER LOSS I+ = I- = 0A 0 25 75 0 50 TEMPERATURE (C) 100 125 2883 G15 10 20 30 LOAD CURRENT (mA) 40 150 I+ = I- = 0A 125 VOLTAGE 100 3 75 ICC CURRENT 2 0.1 1 0 0 50 LTM2883-3, VCC = 3.3V LTM2883-5, VCC = 5V 0 2883 G16 10 20 30 LOAD CURRENT (mA) 40 ICC CURRENT (mA) 0.6 POWER LOSS (W) 40 10 -25 VCC2 Voltage and ICC Current vs Load Current VCC2 Efficiency 50 -12.6 -50 125 2883 G13 2883 G11 VCC2 VOLTAGE (V) 4.95 EFFICIENCY (%) VCC2 VOLTAGE (V) I- = 1mA I- = 15mA -12.3 V- VOLTAGE (V) 5.10 -12.2 I+ = 1mA I+ = 5mA I+ = 10mA I+ = 15mA I+ = 20mA 12.7 V+ VOLTAGE (V) VCC2 VOLTAGE (V) LTM2883-3 VCC = 3.3V 5.15 I+ = I- = 0A V- Load Regulation vs Temperature 25 0 2883 G17 2883fd For more information www.linear.com/LTM2883 9 LTM2883 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. V+ Voltage and ICC Current vs Load Current V+ Efficiency LTM2883-3, VCC = 3.3V LTM2883-5, VCC = 5V 1.0 12 300 10 250 0.8 EFFICIENCY 30 0.6 20 0.4 POWER LOSS 10 0 ICC2 = I- = 0A 0 10 40 20 30 LOAD CURRENT (mA) 50 ICC2 = I- = 0A VOLTAGE 8 6 150 4 100 0.2 2 0 0 LTM2883-3, VCC = 3.3V LTM2883-5, VCC = 5V 0 10 20 30 40 LOAD CURRENT (mA) V- VOLTAGE (V) EFFICIENCY (%) 0.2 POWER LOSS 0.1 10 0 30 10 20 LOAD CURRENT (mA) -10.0 240 -10.5 200 ICC CURRENT -11.0 120 -12.0 80 -13.0 40 VOLTAGE 10 20 LOAD CURRENT (mA) 0 2883 G20 30 0 2883 G21 V+ Transient Response 20mA Load Step VCC2 Transient Response 20mA Load Step 160 -11.5 -12.5 0 280 ICC CURRENT (mA) 0.3 POWER LOSS (W) 0.4 320 LTM2883-3, VCC = 3.3V LTM2883-5, VCC = 5V -9.5 0.5 30 0 -9.0 0.6 EFFICIENCY 20 0 V- Voltage and ICC Current vs Load Current LTM2883-3, VCC = 3.3V LTM2883-5, VCC = 5V 40 50 50 2883 G19 V- Efficiency 50 200 ICC CURRENT 2883 G18 60 350 ICC CURRENT (mA) 40 14 POWER LOSS (W) EFFICIENCY (%) 50 1.2 V+ VOLTAGE (V) 60 V- Transient Response 20mA Load Step I+ = 1.5mA VCC2 100mV/DIV V+ 200mV/DIV V- 200mV/DIV ICC2 10mA/DIV I+ 10mA/DIV I- 10mA/DIV 100s/DIV 2883 G22 100s/DIV 2883 G23 100s/DIV 2883 G24 2883fd 10 For more information www.linear.com/LTM2883 LTM2883 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. V+ Ripple VCC2 Ripple 2mV/DIV I+ = 1mA I- = 1mA 5mV/DIV 5mV/DIV I+ = 20mA I- = 20mA 2883 G25 500ns/DIV 500ns/DIV 2mV/DIV 1ms/DIV VCC Supply Current vs Single Channel Data Rate CL = 1nF CL = 330pF CL = 100pF CL = 20pF 60 3.5 VCC = 5V ICC2 = I+ = I- = 0 50 40 30 20 2883 G29 Logic Input Threshold vs VL Supply Voltage 10k 100k 1M DATA RATE (Hz) 10M 100M 5.0 2.5 INPUT RISING 2.0 INPUT FALLING 1.5 1.0 2883 G31 0 2883 G30 6.0 VL = 5.5V VL = 3.3V VL = 1.62V 4.0 3.0 2.0 1.0 0.5 1k 1ms/DIV Logic Output Voltage vs Load Current 3.0 THRESHOLD VOLTAGE (V) 70 2883 G27 2mV/DIV 2883 G28 1ms/DIV 500ns/DIV V- Noise OUTPUT VOLTAGE (V) 2mV/DIV VCC CURRENT (mA) 2883 G26 V+ Noise VCC2 Noise 10 V- Ripple 1 2 3 4 5 VL SUPPLY VOLTAGE (V) 6 2883 G32 0 0 1 2 3 4 5 6 7 LOAD CURRENT (mA) 8 9 10 2883 G33 2883fd For more information www.linear.com/LTM2883 11 LTM2883 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. VCC2 Cross Regulation vs V+, V- Load Power On Sequence ON 5V/DIV 5.1 12 11 10 5.0 9 4.9 V- 4.8 2883 G34 200s/DIV 14 LTM2883-3 VCC = 3.3V 13 ICC2 = 15mA 8 VCC2 V+ V- 0 V+, |V-| VOLTAGE (V) VCC2 VCC2 VOLTAGE (V) V+ 5.2 7 40 10 20 30 LOAD CURRENT (mA) 6 2883 G35 VCC2 Cross Regulation vs V+, V- Load 5.2 Isolated Supply Efficiency with Equal Load Current 9 8 4.9 VCC2 V+ V- 0 EFFICIENCY (%) VCC2 VOLTAGE (V) 10 5.0 0.9 40 0.7 40 EFFICIENCY 0.6 30 0.5 0.4 20 0.3 POWER LOSS 10 7 10 20 30 LOAD CURRENT (mA) 0.8 6 0 0.2 LTM2883-3, VCC = 3.3V 0.1 LTM2883-5, VCC = 5V 0 5 15 25 10 20 LOAD CURRENT (mA) 0 2883 G36 2883 G37 V+ Cross Regulation vs V- Load 14 12 11 10 9 8 V+, I+ = 10mA V-, I+ = 10mA V+, I+ = 15mA V-, I+ = 15mA 7 6 14 0 5 LTM2883-5 VCC = 5V 13 V+, |V-| VOLTAGE (V) V+, |V-| VOLTAGE (V) V+ Cross Regulation vs V- Load LTM2883-3 VCC = 3.3V 13 12 11 10 9 8 V+, I+ = 10mA V-, I+ = 10mA V+, I+ = 15mA V-, I+ = 15mA 7 10 15 20 LOAD CURRENT (mA) POWER LOSS (W) 11 1.0 50 V+, |V-| VOLTAGE (V) 12 5.1 4.8 60 14 LTM2883-5 VCC = 5V 13 ICC2 = 15mA 25 6 0 2883 G38 5 10 15 20 25 LOAD CURRENT (mA) 30 35 2883 G39 2883fd 12 For more information www.linear.com/LTM2883 LTM2883 PIN FUNCTIONS (LTM2883-I) Logic Side DO2 (A1): Digital Output, Referenced to VL and GND. Logic output connected to I2 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. DNC (A2): Do Not Connect Pin. Pin connected internally. SCL (A3): Serial I2C Clock Input, Referenced to VL and GND. Logic input connected to isolated side SCL2 pin through isolation barrier. Clock is unidirectional from logic to isolated side. Do not float. The logic state on I2 translates to the same logic state on DO2. Do not float. DNC (L2): Do Not Connect Pin. Pin connected internally. SCL2 (L3): Serial I2C Clock Output, Referenced to VCC2 and GND2. Logic output connected to logic side SCL pin through isolation barrier. Clock is unidirectional from logic to isolated side. SCL2 has a push-pull output stage, do not connect an external pull-up device. Under the condition of an isolation communication failure this output defaults to a high state. SDA (A4): Serial I2C Data Pin, Referenced to VL and GND. Bidirectional logic pin connected to isolated side SDA2 pin through isolation barrier. Under the condition of an isolation communication failure this pin is in a high impedance state. Do not float. SDA2 (L4): Serial I2C Data Pin, Referenced to VCC2 and GND2. Bidirectional logic pin connected to logic side SDA pin through isolation barrier. Output is biased high by a 1.8mA current source. Do not connect an external pullup device to SDA2. Under the condition of an isolation communication failure this output defaults to a high state. DI1 (A5): Digital Input, Referenced to VL and GND. Logic input connected to O1 through isolation barrier. The logic state on DI1 translates to the same logic state on O1. Do not float. O1 (L5): Digital Output, Referenced to VCC2 and GND2. Logic output connected to DI1 through isolation barrier. Under the condition of an isolation communication failure O1 defaults to a high state. GND (A6, B2 to B6): Circuit Ground. VCC2 (L6): 5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V. Internally bypassed with 2.2F. ON (A7): Enable. Enables power and data communication through the isolation barrier. If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float. VL (A8): Logic Supply. Interface supply voltage for pins DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is 3V to 5.5V. Internally bypassed with 2.2F. DO1 (B1): Digital Output, Referenced to VL and GND. Logic output connected to I1 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. VCC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5. Internally bypassed with 2.2F. V- (L7): -12.5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to -12.5V. Internally bypassed with 1F. V+ (L8): 12.5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 12.5V. Internally bypassed with 1F. I1 (K1): Digital Input, Referenced to VCC2 and GND2. Logic input connected to DO1 through isolation barrier. The logic state on I1 translates to the same logic state on DO1. Do not float. GND2 (K2 to K5): Isolated Ground. AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV referenced to GND2. Isolated Side AV- (K7): -12.5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is -1.22V referenced to GND2. I2 (L1): Digital Input, Referenced to VCC2 and GND2. Logic input connected to DO2 through isolation barrier. AV+ (K8): 12.5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 1.22V referenced to GND2. 2883fd For more information www.linear.com/LTM2883 13 LTM2883 PIN FUNCTIONS (LTM2883-S) Logic Side Isolated Side SDO (A1): Serial SPI Digital Output, Referenced to VL and GND. Logic output connected to isolated side SDO2 pin through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. SDO2 (L1): Serial SPI Digital Input, Referenced to VCC2 and GND2. Logic input connected to logic side SDO pin through isolation barrier. Do not float. DO2 (A2): Digital Output, Referenced to VL and GND. Logic output connected to I2 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. SCK (A3): Serial SPI Clock Input, Referenced to VL and GND. Logic input connected to isolated side SCK2 pin through isolation barrier. Do not float. SDI (A4): Serial SPI Data Input, Referenced to VL and GND. Logic input connected to isolated side SDI2 pin through isolation barrier. Do not float. CS (A5): Serial SPI Chip Select, Referenced to VL and GND. Logic input connected to isolated side CS2 pin through isolation barrier. Do not float. SDOE (A6): Serial SPI Data Output Enable, Referenced to VL and GND. A logic high on SDOE places the logic side SDO pin in a high impedance state, a logic low enables the output. Do not float. ON (A7): Enable. Enables power and data communication through the isolation barrier. If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float. VL (A8): Logic Supply. Interface supply voltage for pins SDI, SCK, SDO, DO1, DO2, CS, and ON. Operating voltage is 1.62V to 5.5V. Internally bypassed with 2.2F. DO1 (B1): Digital Output, Referenced to VL and GND. Logic output connected to I1 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. GND (B2 to B6): Circuit Ground. VCC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5. Internally bypassed with 2.2F. I2 (L2): Digital Input, Referenced to VCC2 and GND2. Logic input connected to DO2 through isolation barrier. The logic state on I2 translates to the same logic state on DO2. Do not float. SCK2 (L3): Serial SPI Clock Output, Referenced to VCC2 and GND2. Logic output connected to logic side SCK pin through isolation barrier. Under the condition of an isolation communication failure this output defaults to a low state. SDI2 (L4): Serial SPI Data Output, Referenced to VCC2 and GND2. Logic output connected to logic side SDI pin through isolation barrier. Under the condition of an isolation communication failure this output defaults to a low state. CS2 (L5): Serial SPI Chip Select, Referenced to VCC2 and GND2. Logic output connected to logic side CS pin through isolation barrier. Under the condition of an isolation communication failure this output defaults to a high state. VCC2 (L6): 5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V. Internally bypassed with 2.2F. V- (L7): -12.5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to -12.5V. Internally bypassed with 1F. V+ (L8): 12.5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 12.5V. Internally bypassed with 1F. I1 (K1): Digital Input, Referenced to VCC2 and GND2. Logic input connected to DO1 through isolation barrier. The logic state on I1 translates to the same logic state on DO1. Do not float. GND2 (K2 to K5): Isolated Ground. AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV Referenced to GND2. AV- (K7): -12.5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is -1.22V Referenced to GND2. AV+ (K8): 12.5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 1.22V Referenced to GND2. 2883fd 14 For more information www.linear.com/LTM2883 LTM2883 BLOCK DIAGRAM REG VCC VL 110k 2.2F 2.2F 2.2F VCC2 AVCC2 15k GND2 GND REG 150k 1F AV+ 16.2k REG DC/DC CONVERTER 16.2k 150k ON 1F REG ISOLATED COMMUNICATIONS INTERFACE DI1 SDA V+ AV- V- ISOLATED COMMUNICATIONS INTERFACE O1 SDA2 SCL SCL2 DO2 I2 DO1 I1 2882 BDa LTM2883-I REG VCC VL 110k 2.2F 2.2F 2.2F AVCC2 15k GND2 GND REG 150k 1F REG DC/DC CONVERTER 16.2k 150k ON REG SDOE SDI SCK ISOLATED COMMUNICATIONS INTERFACE V+ AV+ 16.2k CS VCC2 ISOLATED COMMUNICATIONS INTERFACE 1F AV- V- CS2 SDI2 SCK2 DO2 I2 SDO SDO2 DO1 I1 2883 BDb LTM2883-S 2883fd For more information www.linear.com/LTM2883 15 LTM2883 TEST CIRCUITS INPUT 0V OUTPUT CL INPUT VL OUTPUT CL INPUT OUTPUT 90% tPHL 10% 1/2VCC2 10% 90% tR tF VCC2 0V OUTPUT tPLH VOH VOL INPUT 1/2VL 1/2VCC2 tPLH VOH VOL 90% tPHL 10% 1/2VL 10% 90% tR tF 2883 F01 Figure 1. Logic Timing Measurements VL OR 0V VL SDOE RL 0V SDO2 OR VCC2 SDO CL 1/2VL 0V SDO SDOE SDO tPZH VOH tPHZ VOH - 0.5V 1/2VL 0V VL tPLZ tPZL 1/2VL VOL VOL + 0.5V 2883 F02 Figure 2. Logic Enable/Disable Time VL RL SDA 0V SDA2 CL SDA VL SDA2 1/2VL tPHL VOH VOL 1/2VCC2 tPLH 30% 70% 70% 30% tF tR VL RL SDA2 0V SDA CL VCC2 SDA2 SDA 1/2VCC2 tPHL VOH VOL 1/2VL tPLH 70% 30% 70% tF 30% tR 2883 F03 Figure 3. I2C Timing Measurements 2883fd 16 For more information www.linear.com/LTM2883 LTM2883 APPLICATIONS INFORMATION Overview The LTM2883 digital Module isolator provides a galvanically-isolated robust logic interface, powered by an integrated, regulated DC/DC converter, complete with decoupling capacitors. The LTM2883 is ideal for use in networks where grounds can take on different voltages. Isolation in the LTM2883 blocks high voltage differences, eliminates ground loops and is extremely tolerant of common mode transients between ground planes. Error-free operation is maintained through common mode events greater than 30kV/s providing excellent noise isolation. Isolator Module Technology The LTM2883 utilizes isolator Module technology to translate signals and power across an isolation barrier. Signals on either side of the barrier are encoded into pulses and translated across the isolation boundary using coreless transformers formed in the Module substrate. This system, complete with data refresh, error checking, safe shutdown on fail, and extremely high common mode immunity, provides a robust solution for bidirectional signal isolation. The Module technology provides the means to combine the isolated signaling with multiple regulators and a powerful isolated DC/DC converter in one small package. the 12.5V supply. A load current of 1.5mA is sufficient to improve static and dynamic load regulation characteristics of the -12.5V output. The increased load allows the boost regulator to operate continuously and in turn improves the regulation of the inverting charge pump. The internal power solution is sufficient to provide a minimum of 20mA of current from VCC2 and V+, and 15mA from V-. VCC and VCC2 are each bypassed with 2.2F ceramic capacitors, and V+ and V- are bypassed with 1F ceramic capacitors. VL Logic Supply A separate logic supply pin VL allows the LTM2883 to interface with any logic signal from 1.62V to 5.5V as shown in Figure 4. Simply connect the desired logic supply to VL. There is no interdependency between VCC and VL; they may simultaneously operate at any voltage within their specified operating ranges and sequence in any order. VL is bypassed internally by a 2.2F capacitor. 3V TO 3.6V LTM2883-3 4.5V TO 5.5V LTM2883-5 LTM2883-S VCC2 VCC AVCC2 V+ ANY VOLTAGE FROM 1.62V TO 5.5V The LTM2883 contains a fully integrated DC/DC converter, including the transformer, so that no external components are necessary. The logic side contains a full-bridge driver, running at 2MHz, and is AC-coupled to a single transformer primary. A series DC blocking capacitor prevents transformer saturation due to driver duty cycle imbalance. The transformer scales the primary voltage, and is rectified by a full-wave voltage doubler. This topology allows for a single diode drop, as in a center tapped full-wave bridge, and eliminates transformer saturation caused by secondary imbalances. The DC/DC converter is connected to a low dropout regulator (LDO) to provide a regulated 5V output. An integrated boost converter generates a regulated 14V supply and a charge pumped -14V supply. These rails are regulated to 12.5V respectively by low dropout regulators. Performance of the -12.5V supply is enhanced by loading AV+ VL ON SDOE CS SDI EXTERNAL DEVICE SCK V- ISOLATION BARRIER DC/DC Converter AV- CS2 SDI2 SCK2 DO2 I2 SDO SDO2 DO1 I1 GND GND2 2883 F04 Figure 4. VCC and VL Are Independent Hot-Plugging Safely Caution must be exercised in applications where power is plugged into the LTM2883's power supplies, VCC or VL, due to the integrated ceramic decoupling capacitors. The For more information www.linear.com/LTM2883 2883fd 17 LTM2883 APPLICATIONS INFORMATION parasitic cable inductance along with the high Q characteristics of ceramic capacitors can cause substantial ringing which could exceed the maximum voltage ratings and damage the LTM2883. Refer to Analog Devices Application Note 88, entitled Ceramic Input Capacitors Can Cause Overvoltage Transients for a detailed discussion and mitigation of this phenomenon. Isolated Supply Adjustable Operation The three isolated power rails may be adjusted by connection of a single resistor from the adjust pin of each output to its associated output voltage or to GND2. The pre-configured voltages represent the maximums for guaranteed performance. Figure 5 illustrates configuration of the output power rails for VCC2 = 3.3V, V+ = 10V, and V- = -10V. LTM2883-5S 5V VCC2 VCC AVCC2 V+ VL AV+ ON CS SDI SCK AV- 530k 3.3V 10V -10V CS2 SDI2 SCK2 DO2 I2 SDO SDO2 DO1 I1 GND 530k V- ISOLATION BARRIER SDOE 174k GND2 2883 F05 Figure 5. Adjustable Voltage Rails To decrease the output voltage a resistor must be connected from the output voltage pin to the associated adjust pin. To increase the output voltage connect a resistor to the adjust pin to GND2. Use the equations listed in Table 1 to calculate the resistances required to adjust each output. The output voltage adjustment range for VCC2 is 3V to 5.5V. Adjustment range for V+ and V- is 1.22V to approximately 13.5V. Operation at low output voltages for V+ or V- may result in thermal shutdown due to low dropout regulator power dissipation. Table 1. Voltage Adjustment Formula OUTPUT VOLTAGE RESISTOR (Ax TO Vx) TO REDUCE OUTPUT RESISTOR (Ax TO GND2) TO INCREASE OUTPUT VCC2 110k * ( VCC2 - 0.6 ) 66k VCC2 - 5 V+, V- 150k * V + ,V - - 1.22 5 - VCC2 ( ) 12.5 - V + ,V - 183k + V ,V - - 12.5 Channel Timing Uncertainty Multiple channels are supported across the isolation boundary by encoding and decoding of the inputs and outputs. Up to three signals in each direction are assembled as a serial packet and transferred across the isolation barrier. The time required to transfer all 3 bits is 100ns maximum, and sets the limit for how often a signal can change on the opposite side of the barrier. Encoding transmission is independent for each data direction. The technique used assigns SCK or SCL on the logic side, and SDO2 or I2 on the isolated side, the highest priority such that there is no jitter on the associated output channels, only delay. This preemptive scheme will produce a certain amount of uncertainty on the other isolation channels. The resulting pulse width uncertainty on these low priority channels is typically 6ns, but may vary up to 44ns if the low priority channels are not encoded within the same high priority serial packet. Serial Peripheral Interface (SPI) Bus The LTM2883-S provides a SPI compatible isolated interface. The maximum data rate is a function of the inherent channel propagation delays, channel to channel pulse width uncertainty, and data direction requirements. Channel timing is detailed in Figures 5 through 8 and Tables 3 and 4. The SPI protocol supports four unique timing configurations defined by the clock polarity (CPOL) and clock phase (CPHA) summarized in Table 2. Table 2. SPI Mode CPOL CPHA 0 0 DATA TO (CLOCK) RELATIONSHIP Sample (Rising) Set-Up (Falling) 0 1 Set-Up (Rising) Sample (Falling) 1 0 Sample (Falling) Set-Up (Rising) 1 1 Set-Up (Falling) Sample (Rising) 2883fd 18 For more information www.linear.com/LTM2883 LTM2883 APPLICATIONS INFORMATION The maximum data rate for bidirectional communication is 4MHz, based on a synchronous system, as detailed in the timing waveforms. Slightly higher data rates may be achieved by skewing the clock duty cycle and minimizing the SDO to SCK set-up time, however the clock rate is still dominated by the system propagation delays. A discussion of the critical timing paths relative to Figure 6 and 7 follows. * CS to SCK (master sample SDO, 1st SDO valid) t0 t1 50ns, CS to CS2 propagation delay t1 t1+ Isolated slave device propagation (response time), asserts SDO2 t1 t3 50ns, SDO2 to SDO propagation delay t3 t5 Set-up time for master SDO to SCK CPHA = 0 CS = SDOE CS2 SDI SDI2 SCK (CPOL = 0) SCK2 (CPOL = 0) SCK (CPOL = 1) SCK2 (CPOL = 1) INVALID SDO SDO2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t17 t18 2883 F06 Figure 6. SPI Timing, Bidirectional, CPHA = 0 CPHA = 1 CS = SDOE CS2 SDI SDI2 SCK (CPOL = 0) SCK2 (CPOL = 0) SCK (CPOL = 1) SCK2 (CPOL = 1) INVALID SDO SDO2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 2883 F07 Figure 7. SPI Timing, Bidirectional, CPHA = 1 2883fd For more information www.linear.com/LTM2883 19 LTM2883 APPLICATIONS INFORMATION * SDI to SCK (master data write to slave) t2 t4 50ns, SDI to SDI2 propagation delay t5 t6 50ns, SCK to SCK2 propagation delay t2 t5 50ns, SDI to SCK, separate packet non-zero set-up time t4 t6 50ns, SDI2 to SCK2, separate packet non-zero set-up time * SDO to SCK (master sample SDO, subsequent SDO valid) t8 set-up data transition SDI and SCK t8 t10 50ns, SDI to SDI2 and SCK to SCK2 propagation delay t10 SDO2 data transition in response to SCK2 t10 t11 50ns, SDO2 to SDO propagation delay t11 t12 Set-up time for master SDO to SCK Table 3. Bidirectional SPI Timing Event Description TIME CPHA EVENT DESCRIPTION t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output enabled, initial data is not equivalent to slave device data output t0 to t1, t17 to t18 0, 1 Propagation delay chip select, logic to isolated side, 50ns typical t1 0, 1 Slave device chip select output data enable t2 0 Start of data transmission, data set-up 1 Start of transmission, data and clock set-up. Data transition must be within -13ns to 3ns of clock edge t1 to t3 0, 1 Propagation delay of slave data, isolated to logic side, 50ns typical t3 0, 1 Slave data output valid, logic side t2 to t4 0 Propagation delay of data, logic side to isolated side 1 Propagation delay of data and clock, logic side to isolated side t5 0, 1 Logic side data sample time, half clock period delay from data set-up transition t5 to t6 0, 1 Propagation delay of clock, logic to isolated side t6 0, 1 Isolated side data sample time t8 0, 1 Synchronous data and clock transition, logic side t7 to t8 0, 1 Data to clock delay, must be 13ns t8 to t9 0, 1 Clock to data delay, must be 3ns t8 to t10 0, 1 Propagation delay clock and data, logic to isolated side t10, t14 0, 1 Slave device data transition t10 to t11, t14 to t15 0, 1 Propagation delay slave data, isolated to logic side t11 to t12 0, 1 Slave data output to sample clock set-up time t13 t13 to t14 t15 t15 to t16 0 Last data and clock transition logic side 1 Last sample clock transition logic side 0 Propagation delay data and clock, logic to isolated side 1 Propagation delay clock, logic to isolated side 0 Last slave data output transition logic side 1 Last slave data output and data transition, logic side 1 Propagation delay data, logic to isolated side t17 0, 1 Asynchronous chip select transition, end of transmission. Disable slave data output logic side t18 0, 1 Chip select transition isolated side, slave data output disabled 2883fd 20 For more information www.linear.com/LTM2883 LTM2883 APPLICATIONS INFORMATION Maximum data rate for single direction communication, master to slave, is 8MHz, limited by the systems encoding/decoding scheme or propagation delay. Timing details for both variations of clock phase are shown in Figures 8 and 9 and Table 4. * SDI and SCK set-up data transition occur within the same data packet. Referencing Figure 6, SDI can precede SCK by up to 13ns (t7 t8) or lag SCK by 3ns (t8 t9) and not violate this requirement. Similarly in Figure 8, SDI can precede SCK by up to 13ns (t4 t5) or lag SCK by 3ns (t5 t6). Additional requirements to insure maximum data rate are: Inter-IC Communication (I2C) Bus * CS is transmitted prior to (asynchronous) or within the same (synchronous) data packet as SDI The LTM2883-I provides an I2C compatible isolated interface, Clock (SCL) is unidirectional, supporting master mode only, and data (SDA) is bidirectional. The maximum CPHA = 0 CS = SDOE CS2 SDI SDI2 SCK (CPOL = 0) SCK2 (CPOL = 0) SCK (CPOL = 1) SCK2 (CPOL = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t11 t12 2883 F08 Figure 8. SPI Timing, Unidirectional, CPHA = 0 CPHA = 1 CS = SDOE CS2 SDI SDI2 SCK (CPOL = 0) SCK2 (CPOL = 0) SCK (CPOL = 1) SCK2 (CPOL = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 2883 F09 Figure 9. SPI Timing, Unidirectional, CPHA = 1 2883fd For more information www.linear.com/LTM2883 21 LTM2883 APPLICATIONS INFORMATION Table 4. Unidirectional SPI Timing Event Description TIME CPHA EVENT DESCRIPTION t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns t0 to t1 0, 1 Propagation delay chip select, logic to isolated side t2 t2 to t3 0 Start of data transmission, data set-up 1 Start of transmission, data and clock set-up. Data transition must be within -13ns to 3ns of clock edge 0 Propagation delay of data, logic side to isolated side 1 Propagation delay of data and clock, logic side to isolated side t3 0, 1 Logic side data sample time, half clock period delay from data set-up transition t3 to t5 0, 1 Clock propagation delay, clock and data transition t4 to t5 0, 1 Data to clock delay, must be 13ns t5 to t6 0, 1 Clock to data delay, must be 3ns t5 to t7 0, 1 Data and clock propagation delay t8 t8 to t9 t9 to t10 0 Last clock and data transition 1 Last clock transition 0 Clock and data propagation delay 1 Clock propagation delay 1 Data propagation delay t11 0, 1 Asynchronous chip select transition, end of transmission t12 0, 1 Chip select transition isolated side data rate is 400kHz which supports fast-mode I2C. Timing is detailed in Figure 10. The data rate is limited by the slave acknowledge setup time (tSU;ACK), consisting of the I2C standard minimum setup time (tSU;DAT) of 100ns, maximum clock propagation delay of 225ns, glitch filter and isolated data delay of 350ns maximum, and the combined isolated and logic data fall time of 500ns at maximum bus loading. The total setup time reduces the I2C data hold time (tHD;DAT) to a maximum of 125ns, guaranteeing sufficient data setup time (tSU;ACK). The isolated side bidirectional serial data pin, SDA2, simplified schematic is shown in Figure 11. An internal 1.8mA current source provides a pull-up for SDA2. Do not connect any other pull-up device to SDA2. This current source is sufficient to satisfy the system requirements for bus capacitances greater than 200pF in FAST mode and greater than 400pF in STANDARD mode. Additional proprietary circuitry monitors the slew rate on the SDA and SDA2 signals to manage directional control across the isolation barrier. Slew rates on both pins must be greater than 1V/s for proper operation. The logic side bidirectional serial data pin, SDA, requires a pull-up resistor or current source connected to VL. Follow SLAVE ACK SDA SDA2 SCL 1 8 9 SCL2 START tPROP tSU;DAT tHD;DAT tSU;ACK STOP 2883 F10 Figure 10. I2C Timing Diagram 2883fd 22 For more information www.linear.com/LTM2883 LTM2883 APPLICATIONS INFORMATION TO LOGIC SIDE GLITCH FILTER 1.8mA SDA2 FROM LOGIC SIDE 2883 F11 Figure 11. Isolated SDA2 Pin Schematic the requirements in Figures 12 and 13 for the appropriate pull-up resistor on SDA that satisfies the desired rise time specifications and VOL maximum limits for FAST and STANDARD modes. The resistance curves represent the maximum resistance boundary; any value may be used to the left of the appropriate curve. 30 RPULL_UP (k) The isolator Module technology used within the LTM2883 has been independently evaluated, and successfully passed the RF and magnetic field immunity testing requirements per European Standard EN 55024, in accordance with the following test standards: 20 15 10 5 0 10 100 CBUS (pF) 1000 2883 F12 Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA 10 8 Radiated, Radio-Frequency, Electromagnetic Field Immunity EN 61000-4-8 Power Frequency Magnetic Field Immunity EN 61000-4-9 Pulsed Magnetic Field Immunity Table 5. 7 RPULL_UP (k) EN 61000-4-3 Tests were performed using an unshielded test card designed per the data sheet PCB layout recommendations. Specific limits per test are detailed in Table 5. V = 3V V = 3.3V V = 3.6V V = 4.5V TO 5.5V 9 Some consideration must be given to signal coupling between SCL2 and SDA2. Separate these signals on a printed circuit board or route with ground between. If these signals are wired off board, twist SCL2 with VCC2 and/or GND2 and SDA2 with GND2 and/or VCC2, do not twist SCL2 and SDA2 together. If coupling between SCL2 and SDA2 is unavoidable, place the aforementioned RC filter at the SCL2 pin to reduce noise injection onto SDA2. RF, Magnetic Field Immunity V = 3V V = 3.3V V = 3.6V V = 4.5V TO 5.5V 25 The isolated side clock pin, SCL2, has a weak push-pull output driver; do not connect an external pull-up device. SCL2 is compatible with I2C devices without clock stretching. On lightly loaded connections, a 100pF capacitor from SCL2 to GND2 or RC low-pass filter (R = 500 C = 100pF) can be used to increase the rise and fall times and minimize noise. 6 TEST 5 EN 61000-4-3 Annex D 4 3 2 1 0 10 100 CBUS (pF) 1000 2883 F13 FREQUENCY FIELD STRENGTH 80MHz to 1GHz 10V/m 1.4MHz to 2GHz 3V/m 2GHz to 2.7GHz 1V/m EN 61000-4-8 Level 4 50Hz and 60Hz 30A/m EN 61000-4-8 Level 5 60Hz 100A/m* EN 61000-4-9 Level 5 Pulse 1000A/m *non IEC method Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA 2883fd For more information www.linear.com/LTM2883 23 LTM2883 APPLICATIONS INFORMATION PCB Layout The high integration of the LTM2883 makes PCB layout very simple. However, to optimize its electrical isolation characteristics, EMI, and thermal performance, some layout considerations are necessary. * Under heavily loaded conditions VCC and GND current can exceed 300mA. Sufficient copper must be used on the PCB to insure resistive losses do not cause the supply voltage to drop below the minimum allowed level. Similarly, the VCC2 and GND2 conductors must be sized to support any external load current. These heavy copper traces will also help to reduce thermal stress and improve the thermal conductivity. * Input and output decoupling is not required, since these components are integrated within the package. An additional bulk capacitor with a value of 6.8F to 22F is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1F to 4.7F, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance. any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, voltage rating, leakage, and clearance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates component selection issues; however, the PCB must be 4 layers. Care must be exercised in applying either technique to insure the voltage rating of the barrier is not compromised. The PCB layout in Figures 14a and 14b shows the low EMI demo board for the LTM2883. The demo board uses a combination of EMI mitigation techniques, including both embedded PCB bridge capacitance and discrete GND to GND2 capacitors. Two safety rated type Y2 capacitors are used in series, manufactured by MuRata, part number GA342QR7GF471KW01L. The embedded capacitor effectively suppresses emissions above 400MHz, whereas the discrete capacitors are more effective below 400MHz. EMI performance is shown in Figure 15, measured using a Gigahertz Transverse Electromagnetic (GTEM) cell and method detailed in IEC 61000-4-20, Testing and Measurement Techniques - Emission and Immunity Testing in Transverse Electromagnetic Waveguides. * Do not place copper on the PCB between the inner columns of pads. This area must remain open to withstand the rated isolation voltage. * The use of solid ground planes for GND and GND2 is recommended for non-EMI critical applications to optimize signal fidelity, thermal performance, and to minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes, where EMI is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between GND and GND2. If ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate RF emissions. * For large ground planes a small capacitance (330pF) from GND to GND2, either discrete or embedded within the substrate, provides a low impedance current return path for the module parasitic capacitance, minimizing TECHNOLOGY Figure 14a. LTM2883 Low EMI Demo Board Layout 2883fd 24 For more information www.linear.com/LTM2883 LTM2883 APPLICATIONS INFORMATION Top Layer Inner Layer 2 Inner Layer 1 Bottom Layer Figure 14b. LTM2883 Low EMI Demo Board Layout (DC1748A) 2883fd For more information www.linear.com/LTM2883 25 LTM2883 APPLICATIONS INFORMATION 60 50 CISPR 22 CLASS B LIMIT 40 dBV/m 30 DC1748A-B 20 10 DC1748A-A 0 DETECTOR = QuasiPeak RBW = 120kHz VBW = 300kHz SWEEP TIME = 17s # OF POINTS = 501 -10 -20 -30 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) 2883 F15 Figure 15. LTM2883 Low EMI Demo Board Emissions TYPICAL APPLICATIONS 0.1F B8 5V A8 1F LTM2883-5I VCC VL 1.7k A7 1.7k VCC A5 SDA C A6 SCL GND A4 A3 A2 A1 B1 B2 ON GND DI1 SDA SCL DNC DO2 DO1 GND 12.5V L8 V+ K8 AV+ L7 - V K7 - AV L6 VCC2 K6 AVCC2 L5 O1 L4 SDA2 L3 SCL2 L2 DNC L1 I2 K1 I1 K2 GND2 1F 12.5V 3 -12.5V 2 5V + 8 1/2 LTC2055 - 1 7 8 9 - 10 4 1.25V 2 5 6 2883 F16 0.1F 10 11 12 1 2 3 VDD GND AD0 REFC AD1 VREF GND IN- SDA IN+ SCL GND + 5 4 10V OUT 0.1F -12.5V + 1/2 LTC2055 7 - 0.1F 2.5V LTC2301, ADC 0.1F 3 2.5V F.S. 6 LT1991 G=8 1 LTC2631A-LM12, DAC 1 8 CA0 R_SEL 2 7 VOUT SCL 3 6 SDA REF 4 5 V GND CC 0.1F 12.5V 9 8 7 6 7 10F 0.1F 4 - 6 5 1F 4V F.S. 8 LT1991 G = 0.2 0.1F 5 9 10 1 + 2 10V IN 3 4 -12.5V Figure 16. Isolated I2C 12-Bit, 10V Analog Input and Output 2883fd 26 For more information www.linear.com/LTM2883 LTM2883 TYPICAL APPLICATIONS B8 3.3V A8 10k 1nF V+ AV VL Cx A7 CLR A6 A B A5 Q A4 A3 A2 VCC A1 CSA B1 CSB B2 C MOSI L8 + K8 V- 74VC1G123 Rx/Cx 1F LTM2883-3S VCC L7 K7 AV- VCC2 ON AVCC2 SDOE CS CS2 SDI SDI2 SCK SCK2 DO2 I2 SDO SDO2 DO1 I1 GND GND2 L6 CSB K6 L5 CSA L4 MOSI L3 SCK L2 L1 MISO K1 K2 2883 F17 SCK MISO GND CSA CSB MOSI SCK Figure 17. Isolated SPI Device Expansion B8 5V A8 10k 10k A7 A6 ENABLE SDA SCLIN A5 A4 A3 A2 A1 B1 B2 LTM2883-5I VCC VL V+ AV V- AV- ON GND DI1 L8 + K8 VCC2 AVCC2 O1 SDA SDA2 SCL SCL2 DNC DNC DO2 I2 DO1 I1 GND GND2 L7 K7 L6 K6 L5 8.66k 10k L4 1 L3 2 L2 3 L1 4 K1 5 K2 137 SDAIN SDAOUT SCLIN SCLOUT CONN LTC4302-1 VCC ADDR GPIO2 GND GPIO1 10 9 8 7 6 10k SDA SCLOUT GPIO2 GPIO1 2883 F18 Figure 18. Isolated I2C Buffer with Programmable Outputs 2883fd For more information www.linear.com/LTM2883 27 LTM2883 TYPICAL APPLICATIONS B8 5V A8 1F A7 A6 VCC A5 Oz A4 Oy C A3 Ox A2 A1 Iy B1 GND Ix B2 LTM2883-5S V+ VCC AV VL L8 + K8 V- L7 K7 AV- VCC2 ON SDOE AVCC2 CS CS2 SDI SDI2 SCK SCK2 DO2 I2 SDO SDO2 DO1 I1 GND GND2 NTC THERMISTORS, MURATA NTSD1WD104, 100k L6 K6 L3 L2 LTC1799 5 L1 K1 4 K2 OUT V+ GND DIV SET 1 2 3 1M 3.01k 3 11 10 6 7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 1.23 1.46 1.87 2.58 3.77 5.67 8.64 13.09 19.53 28.47 40.65 55.87 74.45 96.08 119.83 144.73 169.36 -t DG4051A 16 9 FREQUENCY (kHz) -t -t L4 2883 F19 TEMPERATURE (C) -t -t L5 8 VCC X0 X X1 A X2 B X3 C X4 ENABLE X5 VEE X6 GND X7 -t -t -t 13 14 15 12 1 5 2 4 -t -t -t -t LTC1799 5 4 OUT V+ GND DIV SET 1 2 3 1M 3.01k DG4051A 16 3 11 10 9 6 7 8 VCC X0 X X1 A X2 B X3 C X4 ENABLE X5 VEE X6 GND X7 13 -t -t -t -t 14 15 12 1 5 2 4 Figure 19. 16-Channel Isolated Temperature to Frequency Converter 2883fd 28 For more information www.linear.com/LTM2883 LTM2883 TYPICAL APPLICATIONS IRF7509 100k 5V B8 A8 A7 A6 -12.5V ENABLE 12.5V ENABLE 5V ENABLE 12.5V UV -12.5V UV 5V UV A5 A4 A3 A2 A1 B1 B2 SWITCHED 12.5V LTM2883-5S VCC VL V+ AV V- AV- ON SDOE CS L8 IRF7509 + K8 VCC2 AVCC2 CS2 SDI SDI2 SCK SCK2 DO2 I2 SDO SDO2 DO1 I1 GND GND2 100k L7 SWITCHED -12.5V K7 L6 IRF7509 K6 L5 100k IRLML2402 100k L4 SWITCHED 5V L3 L2 226k L1 K1 K2 LTC2902 2883 F20 1 2 3 0.1F 4 10k 5 6 7 8 COMP3 COMP2 COMP1 COMP4 V3 V2 V1 V4 CRT VREF RST VPG T0 GND RDIS T1 16 15 196k 14 13 12 11 10 9 20k 93.1k 9.53k Figure 20. Digitally Switched Triple Power Supply with Undervoltage Monitor 2883fd For more information www.linear.com/LTM2883 29 LTM2883 TYPICAL APPLICATIONS 0.1F 12.5V 7 8 9 10 - LT1991 G=8 1 2 3 + 4 5 6 10V OUTA 0.1F -12.5V 0.1F 5V B8 3.3V 1F A8 A7 A6 VCC CS MOSI C SCK MISO GND A5 A4 A3 A2 A1 B1 B2 0.1F LTM2883-3S VCC VL V+ AV + K8 V- AV- ON SDOE CS L8 VCC2 AVCC2 CS2 SDI SDI2 SCK SCK2 DO2 I2 SDO SDO2 DO1 I1 GND GND2 L7 K7 12.5V LTC2654-L16 L6 15 K6 6 L5 7 L4 9 L3 8 L2 11 L1 10 K1 12 K2 1.25V -12.5V VCC LDAC CS REFOUT REFC VOUTA SDI VOUTB SCK VOUTC CLR VOUTD SDO REFLO PORSEL GND 5 3 4 + 5 LTC2054 - 0.1F 12.5V 7 8 1 2 9 10 3 2 LT1991 G=8 1 2 3 - + 4 4 5 6 10V OUTB 0.1F -12.5V 13 14 1 16 0.1F 0.1F 12.5V 7 8 2883 F21 9 10 - LT1991 G=8 1 2 3 + 4 5 6 10V OUTC 0.1F -12.5V 0.1F 12.5V 7 8 9 10 - LT1991 G=8 1 2 3 + 4 5 6 10V OUTD 0.1F -12.5V Figure 21. Quad 16-Bit 10V Output Range DAC 2883fd 30 For more information www.linear.com/LTM2883 LTM2883 TYPICAL APPLICATIONS B8 5V A8 1F LTM2883-5I AV VL A7 10k A6 A5 Ox C A4 SDA A3 SCL A2 Ix A1 GND B1 B2 + K8 L7 V- K7 AV- 10k VCC L8 V+ VCC L6 VCC2 ON K6 AVCC2 GND L5 O1 DI1 SDA SDA2 SCL SCL2 DNC DNC DO2 I2 DO1 I1 GND GND2 L4 L3 10k L2 L1 K1 K2 VEE -48V RTN 1k, x4 IN SERIES 1/4W EACH 453k 8 9 16.9k 10 11 19 20 26 1 25 24 11.8k 7 1F 47nF -48V INPUT VEE 10k FLTIN SCL ADIN2 SDAI SDAO OV ALERT SS LTC4261CGN TMR ON EN PGI PGI0 ADR1 PG ADR0 ADIN VEE SENSE GATE DRAIN RAMP 14 15 16 220nF 0.1F VIN UVH 13 100nF 21 INTVCC UVL 0.1F 47nF 0.008 1% 10 22 6 5 4 3 2 28 PWRGD2 27 PWRGD1 23 18 1M + 1k 10nF 100V IRF1310NS 330F 100V VOUT 402k 2883 F22 Figure 22. -48V, 200W Hot Swap Controller with Isolated I2C Interface 2883fd For more information www.linear.com/LTM2883 31 LTM2883 TYPICAL APPLICATIONS 3.3V B8 1F A8 A7 A6 VCC A5 CS C A4 MOSI A3 SCK A2 MISO GND A1 B1 B2 LTM2883-3S V+ VCC AV VL + K8 3.3k 44 43 42 K7 AV- 41 VCC2 AVCC2 SDOE 3.3k 3.3k L7 V- ON 3.3k L8 CS CS2 SDI SDI2 SCK SCK2 DO2 I2 SDO SDO2 DO1 I1 GND GND2 L6 40 K6 39 L5 1F 38 1F L4 37 L3 36 L2 35 L1 34 K1 K2 100k 74LVC3G07 100k 33 32 31 2883 F23 30 100k 29 100k 28 27 26 25 24 23 LTC6803-1 CSO CSI SDO SDOI SDI SCKO 1 2 3 + 4 V SCKI VMODE C12 GPIO2 S12 GPIO1 C11 WDT S11 MM C10 TOS S10 VREG C9 VREF S9 VTEMP2 C8 VTEMP1 S8 NC C7 V- S7 S1 C6 C1 S6 S2 C5 C2 S5 S3 C4 C3 S4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Figure 23. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown B8 3.3V A8 1F LTM2883-3I VCC VL 10k A7 10k VCC A6 A5 C SDA SCL GND A4 A3 A2 A1 B1 B2 ON GND DI1 SDA SCL DNC DO2 DO1 GND V+ AV L8 + K8 L7 V- K7 - AV L6 VCC2 K6 AVCC2 L5 O1 L4 SDA2 L3 SCL2 L2 DNC L1 I2 K1 I1 K2 GND2 0.02 48V VOUT SENSE+ SENSE- VIN SHDN SDA SCL 100k AT 25C, 1% VISHAY 2381 6154.104 LTC4151 ADIN ADR0 ADR1 1.37k 1% GND 2883 F24 T(C) = 3950 - 273, -40C < T < 150C 1000 8.965 + LN - 1 N ADIN NADIN IS THE DIGITAL CODE MEASURED BY THE ADC AT THE ADIN PIN Figure 24. Isolated I2C Voltage, Current and Temperature Power Supply Monitor 2883fd 32 For more information www.linear.com/LTM2883 LTM2883 TYPICAL APPLICATIONS B8 5V A8 10k LTM2883-5I VCC VL ENABLE SDA SCLIN A7 A6 A5 A4 A3 A2 A1 INTERRUPT B1 B2 AV L8 + K8 V- L7 0.1F K7 AV- 10k SHUTDOWN V+ ON GND DI1 VCC2 AVCC2 O1 SDA SDA2 SCL SCL2 DNC DNC DO2 I2 DO1 I1 GND GND2 L6 174k K6 100k L5 0.1F SHDN1 VDD RESET L4 BYP SDAIN L3 SCL L2 SDAOUT L1 AUTO K1 DETECT 1/4 LTC4266 INT K2 AD0 AD1 AD2 AD3 Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T FB1, FB2: TDK MPZ2012S601A T1: PULSE H609NL OR COILCRAFT ETH1-230LD CMPD3003 VEE DGND AGND SMAJ58A 1F SENSE GATE OUT 0.25 Q1 -48V S1B S1B 0.22F FB1 * * RJ45 CONNECTOR 1 * 10nF * * T1 75 75 2 10nF 3 * 4 5 PHY 6 7 * * * 8 * 10nF * (NETWORK PHYSICAL LAYER CHIP) FB2 75 75 10nF * 2883 F25 1nF Figure 25. One Complete Isolated Powered Ethernet Port 2883fd For more information www.linear.com/LTM2883 33 3.175 SUGGESTED PCB LAYOUT TOP VIEW 1.905 aaa Z 0.630 0.025 O 32x E 0.000 PACKAGE TOP VIEW 0.635 4 0.635 PIN "A1" CORNER 1.905 Y X D For more information www.linear.com/LTM2883 6.350 5.080 0.000 5.080 6.350 aaa Z SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee b1 DETAIL A NOM 3.42 0.60 2.82 0.75 0.63 15.0 11.25 1.27 12.70 8.89 0.32 2.50 MAX 3.62 0.70 2.92 0.90 0.66 DIMENSIONS BALL DIMENSION PAD DIMENSION BALL HT NOTES DETAIL B PACKAGE SIDE VIEW A2 A SUBSTRATE THK 0.37 MOLD CAP HT 2.55 0.15 0.10 0.20 0.30 0.15 TOTAL NUMBER OF BALLS: 32 0.27 2.45 MIN 3.22 0.50 2.72 0.60 0.60 H1 SUBSTRATE A1 ddd M Z X Y eee M Z DETAIL B H2 MOLD CAP ccc Z Ob (32 PLACES) // bbb Z (Reference LTC DWG # 05-08-1851 Rev E) Z 34 Z BGA Package 32-Lead (15mm x 11.25mm x 3.42mm) e b 7 5 G 4 e 3 PACKAGE BOTTOM VIEW 6 2 1 L K J H G F E D C B A DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE BALL DESIGNATION PER JESD MS-028 AND JEP95 TRAY PIN 1 BEVEL COMPONENT PIN "A1" 6 ! 3 BGA 32 0517 REV E PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX Module PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG Module PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS 6 SEE NOTES PIN 1 SEE NOTES NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 F b 8 DETAIL A LTM2883 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM2883#packaging for the most recent package drawings. 2883fd 3.175 4.445 4.445 LTM2883 REVISION HISTORY REV DATE DESCRIPTION A 11/12 Storage temperature range updated. B 8/13 Added CTI/DTI parameters and Notes 6, 7 to Isolation Characteristics table. 6, 7 C 5/14 Removed H-grade throughout data sheet. 1-36 Changed Depth of Erosion parameter. Changed overtemperature protection threshold. D 11/17 Added H-Grade; removed Obsolete mark from H-Grade. Raised Maximum Internal Operating Temperature, Storage Temperature Range, and package TJMAX. Updated graphs showing performance characteristics vs temperature. PAGE NUMBER 2 6 7 2, 3 2 8, 9 2883fd Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. For more information www.linear.com/LTM2883 35 LTM2883 TYPICAL APPLICATION Precision 4mA to 20mA Sink/Source with Current Monitor B8 3.3V A8 LTM2883-3S VCC VL 1F A7 A6 VCC CS C MOSI SCK MISO GND A5 A4 A3 A2 A1 B1 B2 V+ AV+ V- AV- ON SDOE VCC2 AVCC2 CS CS2 SDI SDI2 SCK SCK2 DO2 I2 SDO SDO2 DO1 I1 GND GND2 L8 12.5V K8 1F L7 K7 75k LTC2641, DAC 1 2 L6 3 K6 4 L5 REF GND CS VDD SCK VOUT DIN CLR 8 7 SINK 3 + 6 5 2 7 - L4 4 1k 6 LTC1050 Si1555DL_N 0.1F 0.01F L3 5V L2 10 L1 14 K1 K2 2883 TA02 3 0.1F 100k 3V LT6660-3 IN OUT 1 GND 2 LTC2452, ADC 3 7 1 8 REF VCC CS IN+ SCK IN- SDO GND 15 3 + LTC1100 G = 10 4 2 - 11 6 15 0.1% 7 6 5 2 SOURCE 0.1F RETURN -5V RELATED PARTS PART NUMBER LTM2881 LTM2882 LTC4310 LTC6803 DESCRIPTION Isolated RS485/RS422 Module Transceiver Plus Power Dual Isolated RS232 Module Transceiver Plus Power Hot-Swappable I2C Isolators Multistack Battery Monitor LTC2309/ 12-Bit, 8-/2-/1-Channel, 14ksps SAR ADCs with I2C LTC2305/LTC2301 LTC2631/LTC2630 Single 12-/10-/8-Bit I2C or SPI VOUT DACs with 10ppm/C Reference LTC2641/LTC2642 16-/14-/12-Bit VOUT DACs LTC2452/LTC2453 Ultra-Tiny 16-Bit Differential 5.5V ADCs, SPI/I2C LTC1859/ 8-Channel 16-/14-/12-Bit, 100ksps, 10V SoftSpanTM LTC1858/LTC1857 SAR ADCs with SPI LTC2487/LTC2486 16-Bit 2- or 4-Channel ADCs with Easy DriveTM Inputs and I2C/SPI Interface LTC4303/LTC4304 Hot Swappable I2C Bus Buffers LTC1100 LT1991 LTC2054/LTC2055 LTC4151 LTC4261 LTC1799 LTC6990 LTM2892 Zero-Drift Instrumentation Amplifier Precision, Pin Configurable Gain Difference Amplifier Micropower Zero-Drift Op Amps High Voltage I2C Current and Voltage Monitor Negative Voltage Hot Swap Controller with ADC and I2C Monitoring Wide Frequency Range Silicon Oscillator TimerBloxTM Voltage Controlled Oscillator SPI/Digital or I2C Isolated Module COMMENTS 20Mbps 2500VRMS Isolation with Power in LGA/BGA Package 20Mbps 2500VRMS Isolation with Power in LGA/BGA Package Bidirectional I2C Communication, Low Voltage Level Shifting Individual Battery Cell Monitoring of High Voltage Battery Stacks, Multiple Devices Interconnected via SPI 5V, Internal Reference, Software Compatible Family 180A per DAC, 2.7V to 5.5V Supply Range, 10ppm/C Reference, Rail-to-Rail Output 1LSB INL/DNL, 0.5nV * s Glitch, 1s Settling, 3mm x 3mm DFN 2LSB INL, 50nA Sleep Current, Tiny 3mm x 2mm DFN-8 or TSOT Packages 5V Supply, Up to 10V Configurable Unipolar/Bipolar Input Range, Pin Compatible Family in SSOP-28 package 16-Bit and 24-Bit ADC Family, Up to 16 Input Channels and Integrated Temperature Sensor 2.7V to 5.5V Supply, Rise Time Acceleration, Stuck Bus Protection, 15kV ESD Fixed Gain of 10 or 100 Gain Range -13 to +14 3V/5V/5V Supply Wide Operating Range: 7V to 80V Floating Topology Allows Very High Voltage Operation 1kHz to 30MHz 488Hz to 2MHz 3500VRMS Isolation, 6 Channels 2883fd 36 LT 1117 REV D * PRINTED IN USA www.linear.com/LTM2883 For more information www.linear.com/LTM2883 ANALOG DEVICES, INC. 2012