AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
2
ISO9001
ISO9001ISO9001
ISO9001
FS6158-01
FS6158-01FS6158-01
FS6158-01
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er ICTwo-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN TYPE NAME DESCRIPTION SUPPLY
47 DI APICON Enables (logic-high) or disables (logic-low) the optional 1.8V APIC clocks VDD_R
APIC_0 One of three optional APIC clocks, enabled or disabled by APICON VDD_A
21 DIO SEL_A One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
VDD_A,
VDD_H
APIC_1 One of three optional APIC clocks, enabled or disabled by APICON VDD_A
22 DIO SEL_B One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
VDD_A,
VDD_H
APIC_2 One of three optional APIC clocks, enabled or disabled by APICON VDD_A
23 DIO SS_EN# Active-low spread spectrum enable turns on spread spectrum modulation of PLL clocks. Input
levels are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
VDD_A,
VDD_H
2 DO 14REF One 14.318MHz clock output, provided as a reference clock to the companion clock device VDD_R
14 DO 66REF One 66.67MHz clock output, provided as a reference clock to the companion clock device VDD_66
27 AI IREF A fixed precision resistor from this pin to ground provides a reference current used for the
differential current-mode HOST clock outputs VDD_I
17, 18 DI ISEL_0
ISEL_1
The logic setting on these two pins selects the multiplying factor of the IREF reference current
for the HOST pair outputs VDD_66
45, 44 AO HOST_P1
HOST_N1
Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1 VDD_H
42, 41 AO HOST_P2
HOST_N2 Host clock pair #2; one of six pairs of current-steering differential current-mode outputs VDD_H
39, 38 AO HOST_P3
HOST_N3 Host clock pair #3; one of six pairs of current-steering differential current-mode outputs VDD_H
36, 35 AO HOST_P4
HOST_N4 Host clock pair #4; one of six pairs of current-steering differential current-mode outputs VDD_H
33, 32 AO HOST_P5
HOST_N5 Host clock pair #5; one of six pairs of current-steering differential current-mode outputs VDD_H
30, 29 AO HOST_P6
HOST_N6 Host clock pair #6; one of six pairs of current-steering differential current-mode outputs VDD_H
8 DO MREF_P One clock in a pair of outputs provided as a reference clock to a memory clock driver VDD_M
9DOMREF_N
One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver VDD_M
24 DI PWR_DWN# Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins. VDD_I
16 DI SEL133/100# Selects 133MHz or 100MHz Host clock frequency VDD_66
11 P VDD 3.3V core power supply -
19 P VDD_A 1.8V power supply for optional APIC clocks or a 3.3V supply to pins 21-23 -
13 P VDD_66 3.3V power supply for 66REF clock output -
28, 34, 40, 46 P VDD_H 3.3V power supply for the differential HOST clock outputs -
25 P VDD_I 3.3V power supply for IREF current reference input -
7 P VDD_M 3.3V power supply for MREF clock outputs -
3, 48 P VDD_R 3.3V power supply for the 14REF clock output and the crystal oscillator -
12 P VSS Core Ground -
15 P VSS_66 Ground for the 66REF clock output -
20 VSS_A Ground for the APIC clock outputs
31, 37, 43 P VSS_H Ground for the differential HOST clock outputs -
26 P VSS_I Ground for IREF current reference input -
10 P VSS_M Ground for the MREF clock outputs -
1, 6 P VSS_R Ground for the 14REF clock output and the crystal oscillator -
4 AI XIN 14.318MHz crystal oscillator input VDD_R
5 AO XOUT 14.318MHz crystal oscillator output VDD_R