LMC6044
www.ti.com
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
LMC6044 CMOS Quad Micropower Operational Amplifier
Check for Samples: LMC6044
1FEATURES APPLICATIONS
2• Low Supply Current: 10 μA/Amp (Typ) • Battery Monitoring and Power Conditioning
• Operates from 4.5V to 15.5V Single Supply • Photodiode and Infrared Detector Preamplifier
• Ultra Low Input Current: 2 fA (Typ) • Silicon Based Transducer Systems
• Rail-to-Rail Output Swing • Hand-Held Analytic Instruments
• Input Common-Mode Range Includes Ground • pH Probe Buffer Amplifier
• Fire and Smoke Detection Systems
• Charge Amplifier for Piezoelectric Transducers
DESCRIPTION
Ultra-low power consumption and low input-leakage current are the hallmarks of the LMC6044. Providing input
currents of only 2 fA typical, the LMC6044 can operate from a single supply, has output swing extending to each
supply rail, and an input voltage range that includes ground.
The LMC6044 is ideal for use in systems requiring ultra-low power consumption. In addition, the insensitivity to
latch-up, high output drive, and output swing to ground without requiring external pull-down resistors make it
ideal for single-supply battery-powered systems.
Other applications for the LMC6044 include bar code reader amplifiers, magnetic and electric field detectors, and
hand-held electrometers.
This device is built with National's advanced Double-Poly Silicon-Gate CMOS process.
See the LMC6041 for a single, and the LMC6042 for a dual amplifier with these features.
Connection Diagram
14-Pin PDIP/SOIC Instrumentation Amplifier
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1994–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMC6044
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
Absolute Maximum Ratings(1)(2)
Differential Input Voltage ±Supply Voltage
Supply Voltage (V+−V−) 16V
Output Short Circuit to V+See(3)
Output Short Circuit to V−See(4)
Lead Temperature (Soldering, 10 sec.) 260°C
Current at Input Pin ±5 mA
Current at Output Pin ±18 mA
Current at Power Supply Pin 35 mA
Power Dissipation See(5)
Storage Temperature Range −65°C to +150°C
Junction Temperature(5) 110°C
ESD Tolerance(6) 500V
Voltage at I/O Pin (V+) +0.3V, (V−)−0.3V
(1) Absolute Maximum Ratings indicate limts beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Do not connect output to V+when V+is greater than 13V or reliability may be adversely affected.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 110°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
(5) The maximum power dissipation is a function of TJ(max),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(max) −TA)/θJA.
(6) Human body model, 1.5 kΩin series with 100 pF.
Operating Ratings LMC6044AI, LMC6044I −40°C ≤TJ≤+85°C
Temperature Range Supply Voltage 4.5V ≤V+ ≤15.5V
14-Pin PDIP 85°C/W
Thermal Resistance (θJA)(1) 14-Pin SOIC 115°C/W
Power Dissipation See(2)
(1) All numbers apply for packages soldered directly into a PC poard.
(2) For operating at elevated temperatures, the device must be derated based on the thermal resistance θJA with PD= (TJ−TA)/θJA.
2Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated
Product Folder Links: LMC6044
LMC6044
www.ti.com
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TA= TJ= 25°C. Boldface limits apply at the temperature extremes. V+=
5V, V−= 0V, VCM = 1.5V, VO= V+/2, and RL> 1M unless otherwise specified.
Symbol Parameter Conditions LMC6044AI LMC6044I Units
Typical(1) Limit(2) Limit(2) (Limit)
VOS 1 3 6 mV
Input Offset Voltage 3.3 6.3 max
TCVOS Input Offset Voltage 1.3 μV/°C
Average Drift
IBInput Bias Current 0.002 4 4 pA max
IOS Input Offset Current 0.001 2 2
RIN Input Resistance >10 TeraΩ
CMRR 75 68 62 dB
Common Mode Rejection 0V ≤VCM ≤12.0V
Ratio V+= 15V 66 60 min
+PSRR 75 68 62 dB
Positive Power Supply 5V ≤V+≤15V
Rejection Ratio VO= 2.5V 66 60 min
−PSRR 94 84 74 dB
Negative Power Supply 0V ≤V−≤ −10V
Rejection Ratio VO= 2.5V 83 73 min
CMR −0.4 −0.1 −0.1 V
0 0 max
Input Common-Mode V+= 5V & 15V
Voltage Range For CMRR ≥50 dB V+−1.9V V+−2.3V V+−2.3V V
V+−2.5V V+−2.4V min
AV1000 400 300 V/mV
Sourcing 300 200 min
RL= 100 kΩ(3) 500 180 90 V/mV
Sinking 120 70 min
Large Signal Voltage Gain 1000 200 100 V/mV
Sourcing 160 80 min
RL= 25 kΩ(3) 250 100 50 V/mV
Sinking 60 40 min
VO4.987 4.970 4.940 V
4.950 4.910 min
V+= 5V
RL= 100 kΩto 2.5V 0.004 0.030 0.060 V
0.050 0.090 max
4.980 4.920 4.870 V
4.870 4.820 min
V+= 5V
RL= 25 kΩto 2.5V 0.010 0.080 0.130 V
0.130 0.180 max
Output Swing 14.970 14.920 14.880 V
14.880 14.820 min
V+= 15V
RL= 100 kΩto V+/2 0.007 0.030 0.060 V
0.050 0.090 max
14.950 14.900 14.850 V
14.850 14.800 min
V+= 15V
RL= 25 kΩto V+/2 0.022 0.100 0.150 V
0.150 0.200 max
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed at room temperature (standard type face) or at operating temperature extremes (bold face type).
(3) V+= 15V, VCM = 7.5V and RLconnected to 7.5V. For Sourcing tests, 7.5V ≤VO≤11.5V. For Sinking tests, 2.5V ≤VO≤7.5V.
Copyright © 1994–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMC6044
LMC6044
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TA= TJ= 25°C. Boldface limits apply at the temperature extremes. V+=
5V, V−= 0V, VCM = 1.5V, VO= V+/2, and RL> 1M unless otherwise specified.
Symbol Parameter Conditions LMC6044AI LMC6044I Units
Typical(1) Limit(2) Limit(2) (Limit)
ISC 22 16 13 mA
Sourcing, VO= 0V 10 8 min
Output Current
V+= 5V 21 16 13 mA
Sinking, VO= 5V 8 8 min
ISC 40 15 15 mA
Sourcing, VO= 0V 10 10 min
Output Current
V+= 15V 39 24 21 mA
Sinking, VO= 13V(4) 8 8 min
IS40 65 75 μA
Four Amplifiers
VO= 1.5V 72 82 max
Supply Current 52 85 98 μA
Four Amplifiers
V+= 15V 94 107 max
(4) Do not connect output to V+when V+is greater than 13V or reliability may be adversely affected.
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TA= TJ= 25°C. Boldface limits apply at the temperature extremes. V+=
5V, V−= 0V, VCM = 1.5V, VO= V+/2, and RL> 1M unless otherwise specified.
Symbol Parameter Conditions LMC6044AI LMC6044I Units
Typical(1) Limit(2) Limit(2) (Limit)
SR 0.02 0.015 0.010 V/μs
Slew Rate See(3) 0.010 0.007 min
GBW Gain-Bandwidth Product 0.10 MHz
φmPhase Margin 60 Deg
Amp-to-Amp Isolation See(4) 115 dB
enInput-Referred Voltage Noise F = 1 kHz 83 nV/√Hz
inInput-Referred Current Noise F = 1 kHz 0.0002 pA/√Hz
F = 1 kHz, AV=−5
T.H.D. Total Harmonic Distortion RL= 100 kΩ, VO= 2 Vpp 0.01 %
±5V Supply
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed at room temperature (standard type face) or at operating temperature extremes (bold face type).
(3) V+= 15V. Connected as Voltage Follower with 10V step input. Number specified in the slower of the positive and negative slew rates.
(4) Input referred V+= 15V and RL= 100 kΩconnected to V+/2. Each amp excited in turn with 100 Hz to produce VO= 12 VPP.
4Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated
Product Folder Links: LMC6044
LMC6044
www.ti.com
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
Typical Performance Characteristics
VS= ±7.5V, TA= 25°C unless otherwise specified
Offset Voltage vs
Supply Current vs Temperature of Five
Supply Voltage Representative Units
Figure 1. Figure 2.
Input Bias Current vs
Input Bias Current Input Common-Mode
vs Temperature Voltage
Figure 3. Figure 4.
Input Common-Mode
Voltage Range vs Output Characteristics
Temperature Current Sinking
Figure 5. Figure 6.
Copyright © 1994–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMC6044
LMC6044
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
VS= ±7.5V, TA= 25°C unless otherwise specified
Output Characteristics Output Characteristics
Current Sourcing vs Frequency
Figure 7. Figure 8.
CMRR
Crosstalk Rejection vs vs
Frequency Frequency
Figure 9. Figure 10.
Power Supply Rejection
CMRR Ratio
vs vs
Temperature Frequency
Figure 11. Figure 12.
6Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated
Product Folder Links: LMC6044
LMC6044
www.ti.com
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
Typical Performance Characteristics (continued)
VS= ±7.5V, TA= 25°C unless otherwise specified
Open-Loop Voltage Gain Open-Loop
vs Temperature Frequency Response
Figure 13. Figure 14.
Gain and Phase
Responses
vs Gain and Phase
Load Responses vs
Capacitance Temperature
Figure 15. Figure 16.
Gain Error
(VOS Common-Mode Error vs
vs Common-Mode Voltage of
VOUT) Three Representative Units
Figure 17. Figure 18.
Copyright © 1994–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LMC6044
LMC6044
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
VS= ±7.5V, TA= 25°C unless otherwise specified
Non-Inverting Slew
Rate
vs Inverting Slew Rate
Temperature vs Temperature
Figure 19. Figure 20.
Non-Inverting Large
Signal Pulse Response Non-Inverting Small
(AV= +1) Signal Pulse Response
Figure 21. Figure 22.
Inverting Large-Signal Inverting Small Signal
Pulse Response Pulse Response
Figure 23. Figure 24.
8Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated
Product Folder Links: LMC6044
LMC6044
www.ti.com
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
Typical Performance Characteristics (continued)
VS= ±7.5V, TA= 25°C unless otherwise specified
Stability Stability
vs vs
Capacitive Load Capacitive Load
Figure 25. Figure 26.
Copyright © 1994–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LMC6044
LMC6044
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
APPLICATION HINTS
AMPLIFIER TOPOLOGY
The LMC6044 incorporates a novel op-amp design topology that enables it to maintain rail to rail output swing
even when driving a large load. Instead of relying on a push-pull unity gain outupt buffer stage, the output stage
is taken directly from the internal integrator, which provides both low output impedance and large gain. Special
feed-forward compensation design techniques are incorporated to maintain stability over a wider range of
operating conditions than traditional micropower op-amps. These features make the LMC6044 both easier to
design with, and provide higher speed than products typically found in this ultra-low power class.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance with amplifiers with ultra-low input current, like the
LMC6044.
Although the LMC6044 is highly stable over a wide range of operating conditions, certain precautions must be
met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and
even small values of input capacitance, due to transducers, photodiodes, and circuits board parasitics, reduce
phase margins.
When high input impedance are demanded, guarding of the LMC6044 is suggested. Guarding input lines will not
only reduce leakage, but lowers stray input capacitance as well. (See PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK.)
Figure 27. Canceling the Effect of Input Capacitance
The effect of input capacitance can be compensated for by adding a capacitor. Adding a capacitor, Cf, around
the feedback resistor (as in Figure 27) such that:
(1)
or R1CIN ≤R2Cf(2)
Since it is often difficult to know the exact value of CIN, Cfcan be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on
compensating for input capacitance.
CAPACITIVE LOAD TOLERANCE
Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created
by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the
unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.
With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 28.
10 Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated
Product Folder Links: LMC6044
LMC6044
www.ti.com
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
Figure 28. LMC6044 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 28, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the
overall feedback loop.
Capacitive load driving capability is enhanced by using a pull up resistor to V+(Figure 29). Typically, a pull up
resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).
Figure 29. Compensating for Large Capacitive Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6044, typically less than 2 fA, it is essential to have an excellent layout. Fortunately, the techniques of
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
Copyright © 1994–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LMC6044
LMC6044
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
Figure 30. Example of Guard Ring in P.C. Board Layout
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6044's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs, as in Figure 30. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifer
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the
LMC6044's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ωwould cause only 0.05 pA of leakage current. See Figure 33 for typical connections of guard
rings for standard op-amp configurations.
Figure 31. Inverting Amplifier Typical Connections of Guard Rings
Figure 32. Non-Inverting Amplifier Typical Connections of Guard Rings
Figure 33. Follower Typical Connections of Guard Rings
12 Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated
Product Folder Links: LMC6044
LMC6044
www.ti.com
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 34.
Typical Single-Supply Applications
(V+ = 5.0 VDC)
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 34. Air Wiring
The extremely high input impedance, and low power consumption, of the LMC6044 make it ideal for applications
that require battery-powered instrumentation amplifiers. Examples of these type of applications are hand-held pH
probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure
transducers.
The circuit in Figure 35 is recommended for applications where the common-mode input range is relatively low
and the differential gain will be in the range of 10 to 1000. This two op-amp instrumentation amplifier features an
independent adjustment of the gain and common-mode rejection trim, and a total quiescent supply current of less
than 40 μA. To maintain ultra-high input impedance, it is advisable to use ground rings and consider PC board
layout an important part of the overall system design (see PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-
IMPEDANCE WORK). Referring to Figure 35, the input voltages are represented as a common-mode input VCM
plus a differential input VD. Rejection of the common-mode component of the input is accomplished by making
the ratio of R1/R2 equal to R3/R4. So that where,
(3)
A suggested design guideline is to minimize the difference of value between R1 through R4. This will often result
in improved resistor tempco, amplifier gain, and CMRR over temperature. If RN = R1 = R2 = R3 = R4 then the
gain equation can be simplified:
(4)
Due to the “zero-in, zero-out” performance of the LMC6044, and output swing rail-rail, the dynamic range is only
limited to the input common-mode range of 0V to VS–2.3V, worst case at room temperature. This feature of the
LMC6044 makes it an ideal choice for low-power instrumentation systems.
A complete instrumentation amplifier designed for a gain of 100 is shown in Figure 36. Provisions have been
made for low sensitivity trimming of CMRR and gain.
Copyright © 1994–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMC6044
LMC6044
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
(V+ = 5.0 VDC)
Figure 35. Two Op-Amp Instrumentation Amplifier
Figure 36. Low-Power Two-Op-Amp Instrumentation Amplifier
Figure 37. Low-Leakage Sample-and-Hold
Figure 38. Instrumentation Amplifier
14 Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated
Product Folder Links: LMC6044
LMC6044
SNOS612D –NOVEMBER 1994–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 15
16 Submit Documentation Feedback Copyright © 1994–2013, Texas Instruments Incorporated
Product Folder Links: LMC6044
PACKAGE OPTION ADDENDUM
www.ti.com 17-Mar-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMC6044-MDC ACTIVE DIESALE Y 0 100 Green (RoHS
& no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85
LMC6044AIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LMC6044
AIM
LMC6044AIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6044
AIM
LMC6044AIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6044
AIM
LMC6044IM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LMC6044IM
LMC6044IM/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6044IM
LMC6044IMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6044IM
LMC6044IN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS
& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LMC6044IN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Mar-2017
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMC6044AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMC6044IMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMC6044AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMC6044IMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 2
MECHANICAL DATA
N0014A
www.ti.com
N14A (Rev G)
NFF0014A
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
