ANALOG DEVICES - Dual 8-Bit CMOS D/A Converter with Voltage Output DAC8229 FEATURES Two 8-Bit DACs In A Single Chip Adjustment-Free Internal CMOS Amplifiers Single or Dual Supply Operation TTL Compatible Over Full V,,, Range 5 Microsecond Settling Time Fast Interface Timing ............ccscsessesessserenereenee t Improved Resistance to ESD Fits AD/PM-7528 And AD/PM-7628 Sockets Available In Small Outline Package 40C to +85C for the Extended Industrial Temperature Range e Available In Die Form APPLICATIONS Automatic Test Equipment Process/Industrial Controls Energy Controls Programmable instrumentation Disk Drive Systems Multi-Channel Microprocessor-Controlled Systems GENERAL DESCRIPTION The DAC-8229 is a dual 8-bit, voltage output, multiplying CMOS D/A converter. Its reference input accepts a +2.5V signal, in- verts and delivers it to the output with an internal amplifier. Itcan also accept10V atV,,_, with a corresponding +10V output (the maximum positive input signal that it can accept is +2.5V). The DAC-8229 was designed to operate with dual supplies; however, it can be operated with a single supply by connecting Continued FUNCTIONAL DIAGRAM Yop DAC-8229 DB; INPUT BUFFER DB, WR os ToGIe DAC A/DAC B REV.A DGND Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ORDERING INFORMATIONt PACKAGE: 20-PIN DIP/SOL EXTENDED" MILITARY* INDUSTRIAL RELATIVE GAIN TEMPERATURE TEMPERATURE ACCURACY ERROR -55C to +125C 40C to +85C 1/2LSB #2LSB DAC8229AR DAC8229ER #1/2LSB +2LSB DAC8229FP 21/2LSB +2LSB DAC8229FS * For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. t Allcommercial and industrial temperature range parts are available with burn- in. tt Cerdip and epoxy packaged devices available in the extended industrial tem- perature range. PIN CONNECTIONS AGNDA [4] Ves [2 20-PIN VourA [3] 0.3"CERDIP VaerA [a] (R-Suffix) DGND [5] BaGAwace [GI 20-PiN SOL (NSB) 0B, (S-Suffix) DBs 20-PIN EPOXY DIP DBs (P-Suffix) DB, VaerA VourA AGNDA Vss AGND B Your B Vaer8 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Telex: 924491 Fax: 617/326-8703 Twx: 710/394-6577 Cable: ANALOG NORWOODMASSDAC8229 GENERAL DESCRIPTION Continued Veg, AGND A, and AGND B to ground. Its operating character- istics will then be similar to that of the DAC-8228 (whose pin-out allows it to drop into the AD/PM-7528 and AD/PM-7628 sock- ets). An internal regulator provides TTL logic compatibility and fast microprocessor interface timing over the full V,,, range. Also, each DAC input latch is addressable for easy microprocessor interfacing. The DAC-8229 dissipates less than 109mW in the space-saving 20-pin 0.3" DIP or the 20-lead SO surface-mount package. Its compact size, low power, and economical cost per channel, make it attractive for applications requiring multiple D/A convert- ers without sacrificing circuit-board space. Reduced parts count also improves system reliability. PMls advanced oxide-isolated, silicon-gate CMOS process, coupled with PMIs highly-stable thin-film R-2R resistor ladder, offers superior matching and temperature tracking between DACs. The DAC-8229 offers cerdip or epoxy packaged devices in the extended industrial temperature range of 40C to +85C. ELECTRICAL CHARACTERISTICS at V,,, = +11.4V or +15.75V; V, ABSOLUTE MAXIMUM RATINGS (T, = +25C, unless oth- erwise noted.) Vp to AGND or DGND ..... eee eeteeeeeeeeteseeeseeeetenee VV,, to AGND or DGND Vig 10 Vag csieeerecettereseeerents ve AGND to DGND 1... eee eset seetceteceesecerereeanteeeneees Digital Input Voltage to GND ....... ccc reecseneneres 0.3V, Vio Vee to AGND Vou 10 AGND (Note 1)... eeeceseeeeteseeteaeensseersneacenens Vee, Vi Operating Temperature Range DAC-8229AR Version ......ccesesecssseesessenenees DAC-8229ER/FP/FS Versions Junction Temperature ........cseseceeees Storage Temperature 0.0... eccsesssseessrenesees Lead Temperature (Soldering, 60 S@C) oe. cesses +300C PACKAGE TYPE 6,, (NOTE 3) Bic UNITS 20-Pin Hermetic DIP (R) 76 14 CW 20-Pin Plastic DIP (P) 69 27 CW 20-Pin SOL (S) 88 25 C NOTES: 1. Outputs may be shorted to any terminal provided the package power dissipa- tion is not exceeded. Typical output short-circuit current to AGND is 50mA. 2. Use proper antistatic handling procedures when handling these devices. 3. @,, is specified for worst case mounting conditions, i.e., @,, is specified for device in socket for CerDIP and P-DIP packages; @,, is specified for device soldered to printed circuit board for SOL package. 5g = ~BV 210%; Va. = #2.5V; AGND = OV; T, = Full Tem- perature Range specified under Absolute Maximum Ratings, unless otherwise noted. DAC-8229 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (Nate 1) Resolution N 8 - - Bits Relative Accuracy INL _ _ 1/2 LsB (Note 2,10) Differential Nonlinearity DNL _ _ *t LSB (Note 3, 10) Gain Error - - +2 LSB (Note 10) Srse Gain Error / Temperature Coefficient TCGeg - +0.0008 20.002 %PC (Note 4, 10) Zero Gain Error ~ ~ 10 mV (Note 10) Vase * Zero Code Error Temperature Coefficient TCVz5 - +5 - uVPC (Nate 4, 10) REFERENCE INPUT (Note 8) Input Resistance R 7 _ 15 ka (Note 5) IN Input Resistance Match AR _ #0.1 1 % VrerAVeer5) Rin Input Capacitance - 9 20 F Note 4) Cy p REV. AELECTRICAL CHARACTERISTICS at V,,, = +11.4V or +15.75V; V., = -5V 10%; V,-, = 2.5V; AGND = OV; T, = Full Tem- perature Range specified under Absolute Maximum Ratings, unless otherwise noted. Continued DAC-8229 PARAMETER SYMBOL CONDITIONS MIN TYP UNITS DIGITAL INPUTS Digital Input High Vink 2.4 - - Digital Input Low INL - ~ 0.8 Vv Input Current Vin Vin = OV oF Von - - 21 pA Input Capacitance (Note 4) C, N - 4 8 pF POWER SUPPLIES Positive Supply Current (Note 6) bp - - 6 mA Negative Supply Current {Note 6) 'gs - - 5 mA DC Power Supply Rejection Ratio PSRR AVpp = 25% - - 0.04 %/% (A Gain/AV,,,) (Note 10) DYNAMIC PERFORMANCE T,=25C lewR (Neto 4) our) sR Vaer=-25V - 25 - Vius Digital Inputs = OV to +5V Settling Time our) Voce =-2.5V Positive or Negative t REF _ 2 5 us $ igi t = VV (Notes 4,7) Digital Inputs = OV to +5V Channel-to-Channel cel VaerB to Vays oF Vere to Voy),B . 80 _ de Isolation (Note 4) Veer8 = VeerA= 20V,.5 @ f=10kHz Dici a igital Crosstalk Q For Code Transition _ 4 10 nVs (Notes 4, 9) 0000 0000 to 11411111 AC Feedthrough F Ty = 25C - - ~70 cB (Notes 4, 11) T T, = Full Temp. Range - - 65 SWITCHING CHARACTERISTICS (Note 4) Chip Select to t 60 - - ns Write Set-Up Time cs Chip Select to Write Hold Time on 10 - 7 ns DAC Select to { 60 - - ns Write Set-Up Time AS DAC Select to - - ns Write Hold Time an Data Valid to 60 . ns Write Set-Up Time bs Data Valid to t 10 _ ns Write Hold Time DH Write Pulse Width twr 50 - - ns NOTES: 8. V, EF voltage range is +3V to -10V; the absolute maximum negative value is: 1. Specifications apply to both DAC A and DAC B. Vaerl= Vpp4V. 2. This is an endpoint linearity specification. 9. Digital crosstalk is a measure of the amount of digital input pulse appearing at the 3. Alldevices are guaranteed to be monotonic over the full operating temperature range. analog output of the unselected DAC while applying it to the digital inputs of the 4. These characteristics are for design guidance only and are not subject to production other DAC. test. 10. Voge = +2.5V, ReuLLDOWN = 20k (a pulldown resistor to V,, is used for these 5. Input resistance temperature coefficient = +300 ppm/C. tests). : 6. Vin = Vine or Vinn! outputs unloaded. 11. Veer Vaer8 =20V.__ Sinewave @ f = 10kHz; 7.Ve EF +2.5V; to where output settles to +1/2 LSB. VappAto Vi egB or Veer to VaerA REV. A -3-DAC8229 DICE CHARACTERISTICS 1. ANALOG GROUND (AGND A) 11. DIGITAL INPUT DB, 2. NEGATIVE POWER SUPPLY (V,.) 12. DIGITAL INPUT DB, 3. VOLTAGE OUTPUT (V,,,, A) 13. DIGITALINPUT DB, 4. DAC A REFERENCE INPUT (V__,A) 14. DIGITAL INPUT DB, (LSB) 5. DIGITAL GROUND (DGND) 15. CHIP SELECT (CS) 6. DIGITAL SELECTION (DAC A/DAC B) 16. WRITE (WR) 7. DIGITAL INPUT OB, (MSB) 17. POSITIVE POWER SUPPLY (V,,,) 8 DIGITAL INPUT DB, 18. DAC B REFERENCE INPUT (V__, B) 9. DIGITAL INPUT DB, 19. VOLTAGE OUTPUT (V>,,, B) 10. DIGITAL INPUT DB, 20. ANALOG GROUND (AGND B) Substrate (die backside) is internally connected to V,,. DIE SIZE 0.082 x 0.111 inch, 9,102 sq. mifs (2.08 x 2.82 mm, 5.87 sq. mm) WAFER TEST LIMITS at Vop = 111.4V or +15.75V; Vo, = -5V + 10%; Vp, = #2.5V; AGND = OV; T, = +25C. DAC-8229GBC PARAMETER SYMBOL CONDITIONS LIMIT UNITS Relative Accuracy INL E int Linearity E. 412 LSB MAX (Note 3) ndpoint Linearity Error +1/ Differential Nonlinearity 4 BMAX (Notes 4, 3) DNL * LS Gain Error . (Note 3) Gege DAC Latches Loaded with 1111 11114 +2 LSB MAX Zero Code Error Vv. 10 mV MAX (Note 3) ZSE + Input Resistance Rin Pad 4and 18 75 kQ MIN/koS2 MAX Veer AVaecB Input AR RE REF N MAX Resistance Match Rin ' % Digital Input High Vin 2.4 VMIN Digital Input Vv 0.8 VMAX Low IL Input Current ly Vin = OVOrVon #1 pA MAX DC Supply Rejection (aGain/AV,, ,.) PSRR Vpp =#5% 0.01 %/% MAX (Note 3) Positive Supply Current | 6 mA MAX (Note 2) pb Negative Supply Current 5 mA MAX (Note 2) ss NOTES: 1. Alldice guaranteed monotonic over the full operating temperature range. 2. Vin = Vine OF Yip) Output unloaded. 3. Voer = +2-5V, Rous i pown = 20k (a pulldown resistor to V.,., is used for these tests). Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. -4- REV. ADAC8229 TYPICAL PERFORMANCE CHARACTERTISTICS RELATIVE ACCURACY (LSB) RELATIVE ACCURACY (LSB) FULL-SCALE GAIN ERROR (LSB) 0.4 DAC A-TO-DAC B MATCHING (DACs A & B ARE SUPERIMPOSED) Ta = 425C Vpp = +15V Veg = -5V VREF = 0 32 64 96 128 160 192 224 256 DIGITAL INPUT CODE (DECIMAL) RELATIVE ACCURACY vs REFERENCE VOLTAGE MAXIMUM we 428C 0.8 POSITIVE Vpp= +5 7 ERROR Vgg = -5V 0.6 AGND = 0V 7 Reyttpown=" | 02 \ 0.2 v 7 0.4 V/ MAXIMUM 38 ERROR | -3 -2 -1 0 1 2 3 REFERENCE VOLTAGE - Vper (VOLTS) FULL-SCALE GAIN ERROR vs TEMPERATURE Vpp= +15 = -5.5V Vrer = +2.5V Q -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) REV. A RELATIVE ACCURACY (LSB) RELATIVE ACCURACY (LSB) ZERO CODE ERROR (mV) RELATIVE ACCURACY (DAC A) vs CODE AT Ty =-55C, +25C, 0 +125C (SUPERIMPOSED) Vpp= +15V Vgg = -5V \, pene +2.5V 32 64 96 128 160 192 224 256 DIGITAL INPUT CODE (DECIMAL) RELATIVE ACCURACY vs REFERENCE VOLTAGE 10 o8 06 04 N_ posmrve 0.2 ERROR 0 y \ 0.2 / MAXIMUM 0.4 NEGATIVE ] Taz +25C ERROR -0.6 | Vpo=+5V BEND = ov oer Fputt-pown = 2k -1.0 L t 3 -2 -1 0 1 2 3 REFERENCE VOLTAGE - Veer (VOLTS) ZERO CODE ERROR vs TEMPERATURE 2.00 Vpp= +15V 1.75 L Veg =-5.5V Veer = +2.5V 1.50 1.25 1.00 0.75 0.50 0.25 o -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) DIFFERENTIAL NONLINEARITY (LSB) POWER SUPPLY REJECTION (%/%) 1.0 0.5 1.0 -12 -10 SUPPLY CURRENT - | pp (mA) 0.004 0,003 0.002 0.001 DIFFERENTIAL NONLINEARITY VS Vier Ty = +25C Vpp = +15V Vgg = -5V 4 6 +4 2 oO 2 4 Veer (VOLTS) SUPPLY CURRENT vs DIGITAL INPUT VOLTAGE Vpp = +15V Vsgs = -5V Ta = 425C Vper=2.5V Vaer= +2.5V 5 10 15 DIGITAL INPUT VOLTAGE V,, (VOLTS) POWER SUPPLY REJECTION vs TEMPERATURE Vpp= +15 Vgg = -8V 0 -75 -500~25 Q 25 50 75 100 125 TEMPERATURE (C)DAC8229 TYPICAL PERFORMANCE CHARACTERISTICS Continued POWER SUPPLY CURRENT . TOTAL HARMONIC vs TEMPERATURE DISTORTION vs FREQUENCY Vpp= +124 Vgg = -5V -20 | Vper = 200mv,, Ta = +25C Vpp= +15V =-5.5V = +2.5V 60 TOTAL HARMONIC DISTORTION (dB) -100 POWER SUPPLY CURRENT Ipp (MA) -120 10 100 1k 10k 100k FREQUENCY (Hz) Qo ~75 -50 -25 0 25 50 75 8100 125 TEMPERATURE (C) MULTIPLYING MODE, FREQUENCY RESPONSE OUTPUT VOLTAGE vs vs DIGITAL CODE OUTPUT SOURCE CURRENT 0 Vv, AN(MSE) By Ty = 425C ac DBs -12 A ov S DB, 24 Yoo? rd DBs 3 2 DB, 36 z DB a (LSB) DB, 48 3 = Yoo"4 = oo & # Vpp = +18V 9 35 3 v6 Pe 4 3 S$ bo d a 3 SE Von-8 e a " E Vpp=+15V -96 * Veg = -5V ALL BITS OFF rer cave fl 108 Vpp-t0 tk 10k 100k 1M 10M 0 1 2 30 40 SO 60 70 80 FREQUENCY (Hz) OUTPUT SOURCE CURRENT (ma) WRITE CYCLE TIMING DIAGRAM }<_-..--. teg- _____}- toy aN +5V CHIP SELECT iN 3 tas tan _N!| +5V DAC A/DAC B Ky 0 fo +5V twR> WRITE /) NOTES: 0 1, ALLINPUT SIGNAL RISE AND FALL |. tog ton TIMES MEASURED FROM 10% TO 90% AREt,=t, =20ns. Vin +5V 2. TIMING MEASUREMENT REFERENCE DATA IN (DB, - DB,) vy, DATAIN STABLE LEVELIS Ys Me: 0 -6- REV. ADAC8229 BURN-IN CIRCUIT 102 -5V C2 ~5V C, +t5V DAC-8229 Cc 2 NOTES: 1. Cy = 10nF 2. Cz = O.1pF PARAMETER DEFINITIONS RESOLUTION (N) The resolution of a DAC is the number of states (2") that the full- scale range (FSR) is divided (or resolved) into; where n is equal to the number of bits. RELATIVE ACCURACY (INL) Relative accuracy, or integral nonlinearity, is the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. It is expressed in terms of least significant bit (LSB), or as a percent of full scale. DIFFERENTIAL NONLINEARITY (DNL) Differential nonlinearity is the worst case deviation of any adja- cent analog output from the ideal 1 LSB step size. The deviation of the actual step size from the ideal step size of 1 LSBis called the differential nonlinearity error or DNL. DACs with DNL greater than +1 LSB may be non-monotonic. +1/2 LSB INL guarantees monotonicity and +1 LSB maximum DNL. GAIN ERROR (G_.,-) Gain error is the difference between the actual and the ideal analog output range, expressed as a percent of full-scale or in terms of LSB value. It is the deviation in slope of the DAC trans- fer characteristic from ideal. Zero code error is not included in this measurement. See Orientation in Digital-to-Analog Converters Section of the current data book, for additional parameter definitions. GENERAL CIRCUIT DESCRIPTION The DAC-8229 consists of two voltage output amplifiers, two high accuracy R-2R resistor ladder networks, an 8-bit input buffer, two 8-bit DAC registers, and interface control logic cir- cuitry. Also included are 16 single-pole, double-throw NMOS transis- tor switches. These switches, which are controlled by the digital input code, were designed to switch each R-2R resistor leg between the amplifier inverting input and AGND. A simplified circuit of the R-2R resistor ladder and output ampli- fier is illustrated in Figure 1. The signal is inverted from the V,-- input to the output. Note that analog ground (AGND) is acces- sible and can be biased above digital ground (DGND) for some applications; more on this in the applications section under Single Supply Operation. REFERENCE INPUT The DAC-8229s internal output amplifier has a maximum volt- age swing in the negative direction of 2.5V (limited by V.,.). In >O Your | a ! | ~ ~ OB, Leet re$<{) AGND (LSB) FIGURE 1: Simplified single DAC configuration (switches shown for all digital inputs at logic "0"). REV. A _7-DAC8229 the positive direction, the voltage swing is limited to 4V less than Vop. These limitations set the maximum levels that the refer- ence input (V,.-) can accept. Note that the positive Veer limitis set by the negative supply voltage, V..., and the negative VaerE limit is set by (V,, -4V). For example, maximum V, input in the positive direction is +2.5V and11V with Vp p=t15V. The equation for the absolute value in the negative direction takes the form of: I-Vaer Max| = V,, 4V. ss D The equation shows that ~8V is the maximum voltage that can be applied in the negative direction at V.... with V,, = +12V. The DAC-8229's output voltage equation is: Vour = Vrer X D/256 where D is the digital inout code number that is between 0 and 255. BUFFER AMPLIFIER SECTION The DAC-8229s amplifier output stage is an NPN bipolar tran- sistor. This transistor provides a low-impedance high-output current capability. The emitter of the NPN transistor is loaded with a 450,A NMOS current source that is connected to V,.; (see Figure 2). This current is sunk into the negative supply al- lowing the amplifier's output to go to 2.5V. Figure 3 depicts a typical output current-sink versus voltage graph for the DAC-8229. It shows the output amplifiers current sink capability with Vg = ~5V and OV. With Vo, = -5V, the amplifier still operates in the saturation region as the output goes to zero; however, with V. . = OV, the amplifier comes out of its saturation region and starts appearing resistive as the output approaches zero. The DAC-8229s internal amplifiers can each drive +10 volts across a 2kQ load, sourcing 5mA. In fact, they can drive up to 65mA, but with a reduced output amplitude. See the Output Source Current graph under the typical electrical characteristic curves. The user must use caution that the package power dissipation is not exeeded when driving low impedances and high currents. However, as seen in Figure 3, the amplifier has limited current sink capability. Signal waveforms can be im- proved considerably by adding a pull-down resistor at each amplifier output. For example, pulling a2kQ load down to2.5V requires a 1kQ pull-down resister (connected to-5V) The ac- companying scope photographs show the effects of operating 700 600 500 400 300 200 OUTPUT CURRENT SINK (pA) 100 0 1 2 3 4 6 6 7 Vout (VOLTS) FIGURE 3: DAC Output Current Sink OUTPUT Bl) Bama Vgs FIGURE 2: Amplifier Output Stage PHOTO B: Multiplying Mode (f = 1kHZ, with 1k Q Pull-down) REV.DAC8229 the DAC-8229 with and without a 1kQ pull-down resistor. Photo Ais that without the pull-down resistor, and B with the 1k pull- down resistor. Note signal improvement using the pull-down resistor. Figure 4 shows this circuit configuration and the table - lists other resistor values. PULL-DOWN RESISTOR vs LOAD RESISTOR VALUES (Vpp = +15V; V,,=-5V) LOAD PULL-DOWN 2kQ 1kQ 5kQ 4kQ 10kQ 10kQ 15kQ 12kQ 20kQ 16kQ 25kQ 400kQ >30kQ None Required r t 1/2 DAC-B229 pac PN Yo a oo ra Rep SRL AGND e Ves = -5V FIGURE 4: Fy gap 89d Rous pown Circuit Configuration with the DAC-8229 The DAC-8229 can also operate with +5V supplies, V,,, = +5V and V.., = 5V. See the Relative Accuracy vs. Reference Volt- age graphs under the typical characteristics curves. The graphs are shown with and without a 2kQ pull-down resistor. Note how the DAC stays within the specified limit except when V,,... = -2V and without the pull-down resistor. The amplifiers internal gain stages were designed to maintain sufficient gain over its common mode range. This results in good offset performance over the specified voltage range. In addition, the amplifiers offset voltage is laser-trimmed during manufacturing. This eliminates user offset trimming in many applications. DIGITAL SECTION Figure 5 shows one digital input structure of the DAC-8229. A built-in 5V regulator and level shifter converts TTL digital input signals into CMOS levels to drive the internal circuitry. This provides full TTL compatibility over a V,,,, range of 5 to 15V. As shown in Figure 5, each digital input is protected from elec- trostatic-discharge with two internal diodes connected between Vpp and DGND. Each input has a typical input current of less than 1nA. INTERFACE CONTROL INFORMATION DAC SELECTION DAC A and DAC B both share a common 8-bit input port. The control input, DAC A/DAC B, selects which DAC can accept data from the input port. A logic low selects DAC A and a logic high selects DAC B. DAC OPERATION Inputs CS and WR control the operation of the selected DAC. See Mode Selection Table below. WRITE MODE When GS and WR are both low, the selected DAC is in the write mode. The input buffer and DAC register of the selected DAC are transparent and its analog output responds to the codes on the digital input pins. VEL TER OGND TO R-2R LADDER _> } NMOS SWITCHES o+[So-+ FIGURE 5: Simplified Digital Input Structure REV.ADAC8229 HOLD MODE The selected DAC register latches the data present on the digi- tal input pins just prior to CS and WR assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective registers. MODE SELECTION TABLE DAC A/ __ _ DAC B cs WR DACA DAC B L L L WRITE HOLD H L L HOLD WRITE X H x HOLD HOLD X Xx H HOLD HOLD L=Low State H-=HighState X =Don't Care APPLICATIONS INFORMATION UNIPOLAR OPERATION Figure 6 shows the DAC-8229 configured to operate in the unipolar mode, and Table 1 shows the corresponding code table. The equation for 1 LSB and the analog output voltage is: 8 1 LSB = VaeeX 2, OF Veer x 1/256 and Vout = Ver X D/256 where D is the digital input number between 0 and 255. VrerA pp PN 3 YourA Dac + 1 AGNDA _{} 5 DGND 1/2 DAC-8229* Vss *DIGITAL CIRCUITRY OMITTED FOR SIMPLICITY FIGURE 6: Unipolar Operation 10 TABLE 1: Unipolar Code Table (Refer to Figure 6) DAC DATA INPUT MSB LSB ANALOG OUTPUT 1144 44144 ~Vrer (255) 256 1000 0001 ~Vrer (122) 256 1000 0000 ~Vrer (128) - VRE 256/ 2 o1t1 44114 ~Vaer (122) 256 0000 0001 ~Vrer (1) 256 0000 0000 ov BIPOLAR OPERATION Figure 7 shows the DAC-8229 configured in the bipolar mode o1 operation. This configuration requires an external amplifier anc four resistors. To keep gain and offset errors at a minimum, the external resistors should be matched to +0.1% and track over the operating temperature range of interest. Table 2 shows the corresponding code table. TABLE 2: Bipolar (Offset Binary) Code Table (Refer to Figure 7) DAC DATA INPUT MSB LSB ANALOG OUTPUT 11444 44141 +Vner (122) 128 1000 0001 +Vner(1_} 128 1000 0000 ov 01417 41411 ~Vrer(_} 128 0000 0001 ~Vrer (127) 128 0000 0000 Vrer (128. = VReF 128 REV. ADAC8229 Veer A Yoo ? 9 4 17 < 20k. > 20k v PN 3 YourA 10k DAC O- YA + O VourA a 1 AGNDA m o + 1/2 DAG-8229* 5 DGND 5kQ y OO 2 => = Veg DIGITAL CIRCUITRY OMITTED FOR SIMPLICITY FIGURE 7: Bipolar Operation SINGLE SUPPLY OPERATION Some applications require the AGND pin to be biased above ground for single supply operation. A popular scheme is shown in Figure 8. It consists of connecting a +2.5 volt reference (such as PMIs REF-03) to the AGND pin, V,,, and Vg, pins grounded, and +12V to V,,. Both DAC A and DAC B AGND pins are separate and can be independently biased. The resulting transfer equation is: Voyr(D) = 2-5(1 + D/256) where D is the whole number binary digital input. Voyt for the circuit of Figure 8 results in: Voyr(255) = 2.5(1 + 255/256) = +5V Voyr(0) = +2.5V. +12V I Yop Vout Veer 1/2 DAC-8229* AGND Vout = 2.5V $ Voy $5V pO +2.5V | Vout + +120- Vin REF-03 i-o ie tr IK GND I * DIGITAL CIRCUITRY OMITTED FOR SIMPLICITY. FIGURE 8: Single Supply Configuration Figure 9 shows a typical plot of the DAC-8229 in the single- supply configuration of Figure 8. It is plotted for various values of AGND voltage biased above ground. It shows relative accu- racy degrading as AGND is taken above +4V; however, it con- tributes only 1 LSB error at +5V. MAXIMUM POSITIVE ERROR MAXIMUM NEGATIVE ERROR RELATIVE ACCURACY (LSB) 1 2 3 4 5 AGND (VOLTS) FIGURE 9: Relative Accuracy vs. AGND REV. A -11-DAC8229 MICROPROCESSOR INTERFACE CIRCUITS The DAC-8229s versatile input structure allows direct interface to 8- or 16-bit microprocessors. Its simplicity reduces the num- ber of required glue logic components. Figures 10 and 11 show the DAC-8229 interface configurations with the 6800 and 8085 microprocessors. AQ-AI15 SZ ADDRESS BUS ADDRESS DAC A/DAC B VMA -e3m] DECODE _ LOGIC cs ceu Atl _g999* 6800 _ DAC-8229) wea 2 DAC B OB, DB, DO-D7 DATA BUS \ *ANALOG CIRCUITRY OMITTED FOR SIMPLICITY FIGURE 10: DAC-8229 Interface to 6800 Microprocessor A8-A15 cPU . 8085 ALE ADO-AD7 h ADDRESS BUS a5 y A i ADDRESS DAC A/DAC B DECODE _ Ce <7 an DAGC-B229" . an DAC B pe} LATCH 0 8212 DB, ADDR/DATA BUS "\ v *ANALOG CIRCUITRY OMITTED FOR SIMPLICITY NOTE: 8085 INSTRUCTION SHLD (STORE H & L DIRECT) CAN UPDATE BOTH DACs WITH DATA FROMH AND L REGISTERS. FIGURE 11: DAC-8229 Interface to 8085 Microprocessor 12- REV. A