General Description The MAX1003 is a dual, 6-bit analog-to-digital converter (ADC) that combines high-speed, low-power operation with a user-selectable input range, an internal refer- ence, and a clock oscillator. The dual paraliel ADCs are designed to convert in-phase (I) and quadrature (Q) analog signals into two 6-bit, offset-binary-coded digital outputs at sampling rates up to 90Msps. The ability to directly interface with baseband | and Q signals makes the MAX1003 ideal for use in direct-broadcast satellite, VSAT, and QAM16 demodulation applications. The MAX1003 input amplifiers feature true differential inputs, a -0.5dB analog bandwidth of 55MHz, and user- programmable input full-scale ranges of 125mVp-p, 250mVp-p, or 500mVp-p. With an AC-coupled input signal, matching performance between input channels is typically better than 0.1dB gain, 1/4LSB offset, and 0.5 phase. Dynamic performance is 5.85 effective number of bits (ENOB) with a 20MHz anatog input sig- nal, or .7 ENOB with a 50MHz signal. The MAX1003 operates with +5V analog and +3.3V digi- tal supplies for easy interfacing to +3.3V-logic-compati- ble digital signal processors and microprocessors. It comes in a 36-pin SSOP package. Applications Direct Broadcast Satellite (DBS) Receivers VSAT Receivers Wide Local Area Networks (WLANs) Cable Television Set-Top Boxes MAXUM Low-Power, 90Msps, Dual 6-Bit ADC Features * Two Matched 6-Bit ADCs # High Sampling Rate: 90Msps per ADC @ Low Power Dissipation: 350mW @ Excellent Dynamic Performance: 5.85 ENOB with 20MHz Analog Input 5.7 ENOB with SOMHz Anatog Input # +1/4LSB INL and DNL (typ) # Internal Bandgap Voltage Reference # Internal Oscillator with Overdrive Capability @ 55MHz (-0.5d8) Bandwidth Input Amplifiers with True Differential inputs User-Selectable Input Full-Scale Range (125mVp-p, 250mVp-p, or 500mVp-p) * 1/4LSB Channel-to-Channel Offset Matching (typ) * 0.1dB Gain and 0.5 Phase Matching (typ) Single-Ended or Differential input Drive * Flexible, 3.3V, CMOS-Compatible Digital Outputs = 3 Sd Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX1003CAX OC to +70C 36 SSOP Pin Configuration appears at end of data sheet. Functional Diagram 7 BANDGAP REFERENCE DATA BUFFER | MA AXLAA Maxim Integrated Products 7-73 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 For small orders, phone 408-737-7600 ext. 3468.MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC ABSOLUTE MAXIMUM RATINGS Ver to GND icc cecceccecerrereenesterteaserene -0.3V to 6.5V Vcco to OGND... -0.3V to 6.5V GND to OGND .... -0.3V to 0.3V Digital and Clock Output Pins to OGND...-0.3V to Veco (10sec) AU Other Pins to GND cc ceeseccntecrereptereneee -0.3V to Veco Continuous Power Dissipation (Ta = +70C) SSOP (derate 11.8mWPC above +70C) oo. 941mW Operating Temperature Range Storage Temperature Range... Lead Temperature (soldering, < 10sec) , Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functionaf operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended penods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voc = +5V +5%, Voro = 3.3V +300mV, Ta = Tain to Tax. unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS DC ACCURACY (Note 1) Resolution RES 6 Bits Integral Noniinearity INL -0.5 40.25 05 LSB Differential Nontinearity DNL No missing codes over temperature 0.6 0.25 0.5 LSB VESH GAIN = Voc (high gain) 118.75 125 131.25 Full-Scale input Range VFSM GAIN = open (mid gain} 237.6 250 262.5 | mVp-p VESL GAIN = GND (low gain) 475 500 525 INVERTING AND NONINVERTING ANALOG INPUTS Input Open-Circuit Voltage Vaoc 2.25 2.35 2.45 v input Resistance Rin 13 20 29 kQ Input Capacitance Cin Guaranteed by design 3 5 pF Common-Mode Voitage Range Vo oe ne input driven with external source 1.75 275 Vv OSCILLATOR INPUTS i Oscillator Input Resistance [ Rosc [ Other oscillator input tied to Vec + 0.3V | 48 8 121; kQ | DIGITAL OUTPUTS (DI0-DI5, DQ0~DQ5) Digital Outputs Logic-High _ Voltage VOH IsouRCcE = SOA 0.7Vceco v Digital Outputs Logic-Low _ Voltage VoL IgINK = 400A 0.5 V POWER SUPPLY Supply Current icc 63 104 mA Power-Supply Rejection Ratio PSRR_ | Voc = 4.75V te .25V (Note 3) 75 -40 dB a 20MHz, full-scale | and Q analog inputs. Digital Outputs Supply Current Icco Ci = 15pF (Note 4) 21 mA Power Dissipation PD 350 mW 7-74 MAAXLAALow-Power, 90Msps, Dual 6-Bit ADC AC ELECTRICAL CHARACTERISTICS (Voc = +5V +5%, Veco = 3.3V 4300mvV, Ta = +25C, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), Vini = VINQ = 20MHz sine, amplitude -1dB below full scale, unless atherwise noted.) = : 9 o Maximum Sample Rate fMAX 90 Msps Analog Input -0.5dB Bandwidth BW GAIN = GND, open, Voc 65 MHz GAIN = open (mid gain} 56 5.85 ENOBm | GAIN = open (mid gain), fin = SOMHz, 57 Effective Number of Bits -1dB below full scale ~ Bits ENOBy | GAIN = Vcc (high gain) 5.8 ENOB, | GAIN = GND (low gain) 5.85 Signalto-Noise plus Distortion 1 sinap | GAIN = open (mid gain) 355 37 dB | channel -0.5 0.5 Input Offset (Note 5 OFF nput Offset (Note 5) Q channel 05 os | 8 Crosstalk Between ADCs XTLK -55 dB Offset Mismatch Between ADCs | OMM (Note 5) ~0.5 0.25 0.5 CSB Amplitude Match Setween ADCs AM -0.2 +0.4 0.2 dB Phase Match Between ADCs PM -2 20.5 2 degrees TIMING CHARACTERISTICS (Data outputs: RL = 1MQ, Cy = 15pF) Clock to Data Propagation Delay tpD (Note 6) 3.6 as Data Valid Skew tskew | (Note 6) 15 ns input to DCLK Delay toctk | TNK+ to DCLK (Note 6) 5.3 ns Aperture Delay taD Figure 8 . 75 ns oe : clock Pipeline Delay PD Figure 8 1 cycle Note 1: Best-fit straight-line linearity method. Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V). However, it is also possibile to OC couple the analog input (using differential or single-ended drive) within this common- mode input range (Figures 4 and 5). Note 3: PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in Vcc supply voltage, expressed in decibels. Note 4: The current in the Veco supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran- sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig- ital outputs to @ minimum. Note 5: Offset-correction compensation enabled, 0.22uF at Q and | compensation inputs (Figures 2 and 3). Note 6: tpp and tskew are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a data bit. tocik is measured from the 50% ievel of the clock-averdrive signal on TNK+ to the 7.4V level of DCLK. The capac- itive load on the outputs is 15pF. MAXIM 7-75MAX1003 EFFECTIVE NUMBER OF BITS Low-Power, 90Msps, Dual 6-Bit ADC Typical Operating Characteristics (Voc = +5V 45%, Voco = 3.3V +300mvV, foLk = 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, Ta = +25C, unless otherwise noted.) 60 5.8 56 54 5.2 5.0 7-76 EFFECTIVE HUMBER OF BITS s. ANALOG INPUT FREQUENCY 5 : 0 ee 0.2 rT & 94 = S S05 G8 { ferx = 90Msps | 1.0 10 100 1 ANALOG INPUT FREQUENCY (MHz) OSCHLLATOR GPEN-LOOP PHASE NOISE vs. FREQUENCY OFFSET PHASE NOISE (dBc) INL (LSB) -50 110 130 0.50 B 2 1 -0.50 tk 10k 100k FREQUENCY OFFSET FROM CARRIER (Hz) INTEGRAL NONLINEARITY vs. CODE 1M MAX IO0S-05 ad 20 30 CODE 40 = 50 6064 ANALOG INPUT BANOWIDTH 10 ANALOG INPUT FREQUENCY (MHz} AMPLITUDE (dB) DNL (LSB) 100 -20 a 0.50 0.25 08 EFFECTIVE NUMBER OF BITS vs. SAMPLING/CLOCK FREQUENCY 60 59 5.8 57 EFFECTIVE NUMBER OF BITS 56 {iy = 20MHz 56 1 10 100 CLOCK FREQUENCY (MHz) FFY PLOT fin = 19.9512MHz fork = 90.000Miz 1024 POINTS AC COUPLED SINGLE ENDED AVERAGED WG-05 0 9 18 27 36 45 FREQUENCY (MHz) DIFFERENTIAL NONLINEARITY vs, CODE MAK1O02-07 oe = wd vf 0 0 8% 4 SO 8064 CODE MAAXLAALow-Power, 90Msps, Dual 6-Bit ADC Pin Description = PIN NAME FUNCTION 1 GAIN Gain-Select Input. Sets input full-scale range: 125/250/S00mVp-p (Table 1). 2 liOCC+ Positive -Channel Offset-Correction Compensation. Connect a 0.22uF capacitor for AC-coupied mh, inputs. Ground for DC-coupied inputs. Se 3 jocc- Negative |-Channel Offset-Correction Compensation. Connect a 0.22uF capacitor for AC-coupled 8 inputs. Ground for DC-coupled inputs. 4 {IN+ 1-Channe! Noninverting Analog input lIN- |-Channel inverting Analgg Input 6 Veco +5V +5% Supply. Bypass with a 0.01uF capacitor to GND (pin 7). 7, 8 a GND Analog Ground 8 Veco +5V +5% Supply. Bypass with a 0.01uF capacitor to GND (pin 14). 9 TNK+ Positive Gscillatar/Clock Input 10 TNK- Negative Oscillator/Clack Input 13 Vec +5V +5% Supply. Bypass with a O.01pF capacitor to GND (pin 12). 14 QIN- Q-Channel Inverting Analog Input 15 QIN+ Q-Channel Noninverting Analog input 16 aocc. Negative Q-Chanrel Offset-Correction Campensation. Connect a 0.22uF capacitor for AC-coupled inputs. Ground for DC-coupied inputs. 17 aocc:. Positive Q-Channel Offset-Correction Compensation. Connect a 0.22uF capacitor for AC-coupled inputs. Ground for DC-coupled inputs 20-25 DQ5-NO0 | O-Channel Digital Outputs 0-5. DQS5 is the most significant bit (MSB). 26, 28 Veco Digital Output Supply, +3.3V 2300mV. Bypass each with a 47pF capacitor to OGND {pin 27). 27 OGND Digital Output Ground 29 DCLK Digital Clock Output. Frames the output data. 30-35 DIO-DIS -Channet Digital Outputs 0-5, DI5 is the most significant bit (MSB). 36 Vee +5V +5% Supply. Bypass with a 0.01,F capacitor to GND (pin 19). Detailed Description Programmable Input Amplifiers The MAX1003 has two (1 and Q) programmable-gain Converter Operation input amplifiers with a -0.5dB bandwidth of 55MHz and The MAX1003 contains two 6-bit analog-to-digital con- _ true differential inputs. To maximize performance in verters (ADCs), a buffered voltage reference, and oscil- iator circuitry. The ADCs use a flash conversion technique to convert an analog input signal into a 6-bit parallel digital output code. The MAX1003s unique design includes 63 fully differential comparators and a proprietary enceding scheme that ensures no more than 1LSB dynamic encoding error. The control logic interfaces easily to most digital signal processors (DSPs) and microprocessors (uPs) with +3.3V CMOS- compatible logic interfaces. Figure 1 shows the MAX 1003 in a typical application. MAAXIAA high-speed systems, each amplifier has less than 5pF of input capacitance. The input amplifier gain is pro- grammed, via the GAIN pin, to provide three possible input full-scale ranges (FSRs) as shown in Tabie 1. Table 1. Input Amplifier Programming INPUT FULL-SCALE RANGE N Gal (mVp-p) GND 500 Open 250 Voc 125 7-77MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC Single-ended and differential AC-coupied input circuits compensation capacitor is required to set the dominant are shown in Figures 2 and 3. Each of the amplifier pole of the offset-correction amplifiers frequency inputs is internally biased to a 2.35V reference through response (Figures 2 and 3). The compensation capaci- @ 20kQ resistor, eliminating external DC bias circuits. A tor will determine the low-frequency corner of the ana- series O.1pF capacitor is required at each amplifier log input response according to the following formula: input for AC-coupled signals. fo=1/(0.1xC) When operating with AC-coupled inputs, the input amplifiers OC offset voltage is nulled to within +1/2LSB by an on-chip offset-correction amplifier. An external where C is the value of the compensation capacitor in uF, and fe is the corner frequency in Hz. Ty rc ca - 950MHz TO 2150MHz F-CONNECTOR KUBAND INPUT =] sms mene oem mses meen tes oem ) ee mk at x ' 1 i i i ' i VARACTOR-TUNED I 1 PRESELECTION FILTER i \ A ~< L- { I \ FROM TANK VOLTAGE t i ! AGCY Vec - ! i AGC ! ' RFIN| a I ' x mt IN ' I FEN (QUT I I { 1 ie CLKIN 1 1 i { OSP i ! BE | OWN t 1 EXTERNAL gout | I 1 vco Lo t ~) | ape cLock Tp fe AAA] ! ; wurvesizen | | 1 Mane SYNTHESIZER | 1c rMODCTL FIN CAR! 4 po MOD|GND re a ' 1 TSASO5S 1 [ or EQUIV. I 1 I { Figure 1. Commercial Satellite Receiver System 7-78 MAAXLAALow-Power, 90Msps, Dual 6-Bit ADC 0.22uF O.1pF if _INe ie i ! Vv Vsounce SOURCE LL _IN- _IN- = 0.1pF AAAXLAA Op AMAAXIAA Lo 20k Sak MAX1003 20k 20k MAX1003 2.35V INTERNAL REFERENCE 2.38 INTERNAL REFERENCE Figure 2. Single-Ended AC-Caupled Input Figure 3. Differential AC-Coupled Input OFFSET CORRECTION DISABLED OFFSET CORRECTION DISABLED + 00+ OCC- _OCC+ Del, Lefeser Lefrser CORREC-| CORREC- ON 10N _IN+ _IN+ + + INPUT Q Vsquace AMP 8 Vsquace ir = IN- 7 nm | TL PAAXIIA ~ AAAXIMA 20k 20k MAX7003 20k 20k MAX1003 Var 3 DIFFERENTIAL SOURCE WITH COMMON MODE VIBVTO2 780 Ny 2.35V INTERNAL REFERENCE FROM 1 7SVT02.75V 2.35V INTERNAL REFERENCE Figure 4. Single-Ended DC-Coupled input For applications where a DC component of the input signal is present, Figures 4 and 5 show single-ended and differential DC-coupled input circuits. The ampli- fiers input common-mode voitage range extends from 1.75V to 2.75V. To prevent attenuation of the input signal's DC component in this mode, disable the offset- correction amplifier by grounding the _OCC+ and _OCC- pins for the | and Q blocks (Figures 4 and 5). MAAKLAA Figure 5. Differential DC-Coupled Input ADCs The | and Q ADC biocks receive the analog signals from the respective | and Q input amplifiers. The ADCs use flash conversion with 63 fully differential compara- tors to digitize the analog input signal into a 6-bit output in offset binary format. 7-79 = : oMAX1003 Low-Power, 90Msps, Dual 6-Bit ADC The MAX1003 features a proprietary encoding scheme that ensures no more than 1LSB dynamic encoding error, Dynamic encoding errors resulting from metastable states may occur when the analog input voltage, at the time the sample is taken, falls close to the decision point for any one of the input comparators. The resulting output code for typical converters can be incorrect, including false full- or zero-scale outputs. The MAX1003s unique design reduces the magnitude of this tyoe of error to 1LSB. Internal Voltage Reference An internal buffered bandgap reference is included on the MAX1003 to drive the ADCs reference ladders. The on-chip reference and buffer eliminate any external (high-impedance) connections to the reference ladder, minimizing the potential for noise coupling from exter- nal circuitry while ensuring that the voltage reference, input amplifier, and reference ladder track well with variations of temperature and power supplies. Oscillator Circuit The MAX1003 includes a differential oscillator, which is controlled by an external parallel resonant (tank) net- work as shown in Figure 6. Alternatively, the oscillator may be overdriven with an external clock source as shown in Figure 7. Internal Clock Operation (Tank) lf the tank circuit is used, the resonant inductor should have a sufficiently high Q and a self-resonant frequen- cy (SRF) of at least twice the intended oscillator fre- quency. Coilcrafts 1908HS-221, with an SRF of 700MHz and a Q of 45, works well for this application. Generate different clock frequency ranges by adjusting varactor and tank elements. An internal clock-driver buffer is included to provide sharp clock edges to the internal flash comparators. The buffer ensures that the comparators are simuitane- ously clocked, maximizing the ADCs effective number of bits (ENOB) performance. 47k : i 10k} Vrune fi + ' 4 ' TNK+ LY 5pF 220nH CS) TNK- -~---4 Vouk = 300MVp 9 10 1.25Vp-p TNK+ MAAXLN 47pF MAX1003 TNK- 47k ' MAAXLM MAX1003 = 500 Viune = OV TO 8V fose = TOMH2 TO 110MHZ 1 VARACTOA DIODE PAIR IS M/A-COM MA4STO79CK-287 (S0123 PACKAGE) INDUCTOR COILCRAFT 1008HS-221. Figure 6. Tank Resonator Oscillator Figure 7. External Clock Drive Circuit 7-80 MAAXIMALow-Power, 90Msps, Dual 6-Bit ADC ANALOG INPUT DCLK 14v DATA VALID N - 1 Y 2 DATA VALID N Figure 8. MAX 1003 Timing Diagram \S External Clock Operation To accommodate designs that use an external clock, the MAX1003s interna! oscillator can be overdriven by an external clack source as shown in Figure 7. The wii exiernal clock source should be a sinusoid to minimize 1tttt0 clock phase noise and jitter, which can degrade the +1108 ADCs ENOB performance. AC couple the clock source (recommended voltage level is approximately 1Vp-p) to ' I the oscillator inputs as shown in Figure 7. 100001 { Q Output Data Format 5 am The conversion results are output on a dual, 6-bit-wide 5 ' data bus. Data is latched into the ADC output latch fol- > otto lowing a pipeline delay of one clock cycle, as shown in q ' Figure 8. Output data is clocked out of the respective 00011 s ' ADC's data output pins (D_O through D_5) on the rising ovate ' edge of the clock output (DCLK), with a DCLK-to-data ' propagation delay (tep) of 3.6ns. The MAX1003 outputs 000001 : are +3.3V CMOS-lagic compatible. 100000 C4 ee 1ts8 a Transfer Function INPUT VOLTAGE (_IN+ TO _IN-) Figure 9 shows the MAX1003s nominal transfer function. Output coding is offset binary with 1LSB = FSR / 63. Figure 9. ideal Transfer Function MAAXIAA 7-61 = x 8MAX1003 Low-Power, 90Msps, Dual 6-Bit ADC Applications Information The MAX1003 is designed with separate analog and digita! power-supply and ground connections to isolate high-current digital noise spikes from the more sensi- tive analog circuilry. The high-current digital output ground (OGND) and analog ground (GND) should be at the same DC level, connected at only one location on the board. This will provide best noise immunity and improved conversion accuracy. Use of separate ground planes is strongly recommended. The entire board needs good DC bypassing for both analog and digital supplies. Place the power-supply bypass capacitors close to where the power is routed onto the board, i.e, close to the connector. 10uUF elec- trolytic capacitors with low-ESR ratings are recom- mended. For best effective bits performance, minimize capacitive loading at the digital outputs. Keep the digi- tal output traces as short as possible. The MAX1003 requires a +5V +5% power supply for the analog supply (Vcc) and a +3.3V 4300mV power supply connected to Vcco for the logic outputs. Bypass each of the Vcc_ supply pins to its respective GND with high-quality ceramic capacitors located as close to the package as possible (Table 2). Consult the evaluation kit manual for a suggested layout and bypassing scheme. Table 2. Bypassing BYPASS SUPPLY Vec/ TO CAPACITOR FUNCTION Veco GND/ VALUE OGND Analog inputs 6 7 0.01pF Oscillator/Clock 8 11 0.01yF Converter 13 12 0.01UF Digital Q-Output 26 a7 47pF Digital |-Output 28 27 47pF Buffer 36 19 0.01 uF 7-82 Dynamic Performance Signal-to-noise and distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to all other ADC output signals. The output spectrum is limit- ed to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADCs resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a per- fect 6-bit ADC can do no better than 38dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 20MHz sinusoid at a 90MHz clock rate. This FFT plot of the output shows the output level in various spectral bands. The plot has been averaged to reduce the quantization noise floor and reveal the low-amplitude spurs. This emphasizes the excellent spurious-free dynamic range of the MAX1003. The effective resolution (or effective number of bits) the ADC provides can be measured by transposing the equation that converts resolution to SINAD: N = (SINAD - 1.76) / 6.02 (see Typical Operating Characteristics). MAAXISAALow-Power, 90Msps, Dual 6-Bit ADC Pin Configuration = > TOP VIEW x nal, GaN [1] 38] Voc S toces [| 35} D6 wocc- [3] 34] 014 wns [4] eS 13 un- [5 MAXIMA 32] D2 MAX1003 vec [6] 31] O11 eno [7 : Die Yoo [8] 29] DCLK Tike [3 [28] Veco ma 27] OGND GND {a 26] Veco Guo [12] j25] Dao Vee fai 24} Doi ain- [4] [za] poz ais [15] 22] 003 aoce- [16] 21] 004 aocts [17] [26] bas eno [19] 1g] GND SSOP __Chip Information TRANSISTOR COUNT: 6097 MAAXLAA 7-83