1
®
FN9098.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Dynamic VID™ is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6561
Multi-Phase PWM Controller with
Precision rDS(ON) or DCR Differential
Current Sensing for VR10.X Application
The ISL6561 controls micropro cessor core v ol tage regulation
by driving up to 4 synchronous-recti fied b uck channels in
parallel. Multi-phase buc k converter architecture uses
interleav ed timing to m ultip ly channel ripple frequency and
reduce input and output ripple currents . Low er ripple results in
f ewer compone nts , lower compo nent cost, re duced po w e r
dissipation, and smaller impleme ntation area.
Microprocessor loads can generate load transients with
extremely fast edge rates. The ISL6561 features a high
bandwidth control loop an d ripple frequencies of >4MHz to
provide optimal response to the transients.
Today’s microprocessors require a tightly regulated output
voltage position versus load current (droop). The ISL6561
senses current by utilizing patented techniques to measure
the voltage across the on resistance, rDS(ON), of the lower
MOSFETs or DCR of the output inductor during the low er
MOSFET conduction intervals . Current sensing provides the
needed signals for precision droop, channel-current
balancing, and overcurrent protection.
The accuracy of the current-sensing method is enhanced by
the ISL6561’s temperature compensation function. Droop
accuracy can be aff ected b y increasing rDS(ON) or DCR with
eleva ted temperature. The ISL6561 uses an internal
temperature-sensing element to provide programmable
temperature compensation. Correctly applied, temperature
compensation can completely nullify the effect of rDS(ON) or
DCR temperature sensitivity.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be completely eliminated using the
remote-sense amplifier. Eliminating ground differences
improves regulation and protection accuracy. The threshold-
sensitive enable input is available to accurately coordinate
the start up of the ISL6561 with any other voltage rail.
Dynamic-VID™ technology allows seamless on-the-fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting. The ISL6561
uses 5V bias and has a built-in shunt regulator to allow 12V
bias using only a small external limiting resisto r.
Features
• Precision Multi-Phase Core Voltage Regulation
- Differential Remote Voltage Sensing
-±0.5% System Accuracy Over Life, Load, Line and
Temperature
- Adjustable Reference-Vo ltage Offset
• Precision rDS(ON) or DCR Current Sensing
- Integrated Programmable Temperature Compensation
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Differential Current Sense
- Low-Cost, Lossless Current Sensing
• Internal Shunt Regulator for 5V or 12V Biasing
• Microprocessor Voltage Identification Input
- Dynamic VID™ technolog y
- 6-Bit VID Input
- 0.8375V to 1.600V in 12.5mV Steps
• Threshold-Sensitive Enable Function for synchronizing
with driver POR
• Overcurrent Protection
• Overvoltage Protection
- No Additional External Components Needed
- OVP Pin to dr ive opitional Crowbar Device
• 2, 3, or 4 Phase Operation
• Greater Than 1MHz Operation (> 4MHz Ripple)
• Pb-free Available (RoHS Compliant)
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QF N - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in P r of il e
Data Sheet May 12, 2005
2FN9098.5
May 12, 2005
ISL6561
Pinout
ISL6561 (40-PIN QFN)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
(°C) PACKAGE
PKG.
DWG #
ISL6561CR 0 to 70 40 Ld 6x6 QFN L40.6x6
ISL6561CR-T 40 Ld 6x6 QFN Tape and Reel L40.6x6
ISL6561CRZ (Note) 0 to 70 40 Ld 6x6 QFN (Pb-free) L40.6x6
ISL6561CRZ-T (Note) 40 Ld 6x6 QFN Tape and Reel
(Pb-free)
L40.6x6
ISL6561CRZA (Note) 0 to 70 40 Ld 6x6 QFN (Pb-free) L40.6x6
ISL6561CRZA-T
(Note)
40 Ld 6x6 QFN Tape and Reel
(Pb-free)
L40.6x6
ISL6561IR -40 to 85 40 Ld 6x6 QFN L40.6x6
ISL6561IR-T 40 Ld 6x6 QFN Tape and Reel L40.6x6
ISL6561IRZ (Note) -40 to 85 40 Ld 6x6 QFN (Pb-free) L40.6x6
ISL6561IRZ-T (Note) 40 Ld 6x6 QFN Tape and Reel
(Pb-free)
L40.6x6
NO TE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Ordering Information (Continued)
PART NUMBER
TEMP.
(°C) PACKAGE
PKG.
DWG #
VID3
VID2
VID1
VID0
VID12.5
OFS
DAC
GND
GND
PGOOD
OVP
GND
FS
GND
ENLL
EN
TCOMP
VID4
REF
VCC
PWM4
ISEN4+
ISEN4-
ISEN2-
ISEN2+
PWM2
PWM1
ISEN1+
ISEN1-
ISEN3-
ISEN3+
VSEN
RGND
VDIFF
COMP
GND
FB
IDROOP
GND
PWM3
1
40
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
39 38 37 36 35 34 33 32 31
11 12 13 14 15 16 17 18 19 20
3FN9098.5
May 12, 2005
ISL6561CR Block Diagram
I_TRIP
OVP
LATCH
∑
∑
∑
∑
∑
CHANNEL
POWER-ON
RESET (POR)
PWM1
PWM2
PWM3
PWM4
GND
VCC
FB
FS
S
CLOCK AND
VID4
VID3
VID2
VID1
COMP
VSEN
GENERATOR
SAWTOOTH
ISEN3-
ISEN4+
VID0
RGND
VDIFF PGOOD
OVP
EN
1.24V
I_TOT
DYNAMIC
VID
D/A
SAMPLE
HOLD
&
∑
CURRENT
BALANCE
CHANNEL
DETECT
OFS
THREE-STATE
ISEN1+
ISEN2-
CHANNEL
CURRENT
SENSE
OVP
VID12.5
SOFT START
AND
FAULT LOGIC
OFFSET
REF
+200mV
R
x1
E/A
OC
PWM
PWM
PWM
PWM
Q
TCOMP
T
ENLL
DAC
ISEN4-
ISEN3+
ISEN2+
ISEN1-
IDROOP
ISL6561
4FN9098.5
May 12, 2005
ISL6561
Typical Application - 4-Phase Buck Converter with Rds,on Sensing and External NTC
VID3
+5V
PWM
VCC
BOOT
UGATE
PHASE
LGATE
GND
+12V
VIN
PWM
VCC BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
VID4
PGOOD
VID2
VID1
VID0
VSEN
VDIFF
FB COMP
VCC
GND
RGND
EN
ISEN1+
PWM1
PWM2
ISEN2+
PWM3
ISEN3+
PWM4
ISEN4+
ISL6561
µP
LOAD
VID12.5
ISEN1-
ISEN2-
ISEN3-
ISEN4-
TCOMP
REF
DAC
OVP
NTC
THERMISTOR
FS
OFS
HIP6601B
PVCC
ENLL
VIDPGOOD
IDROOP
HIP6601B
DRIVER
DRIVER
+12V
RT
5FN9098.5
May 12, 2005
Typical Application - 4-Phase Buck Converter with rDS(ON) Sensing and Internal PTC
VID3
+5V
PWM
VCC BOOT
UGATE
PHASE
LGATE
GND
+12V
DRIVER
VIN
PWM
VCC BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
VID4
PGOOD
VID2
VID1
VID0
VSEN
VDIFF
FB
COMP
VCC
GND
RGND
EN
ISEN1+
PWM1
PWM2
ISEN2+
PWM3
ISEN3+
PWM4
ISEN4+
ISL6561
µP
LOAD
VID12.5
ISEN1-
ISEN2-
ISEN3-
ISEN4-
TCOMP
REF
DAC
OVP
FS
OFS
DRIVER
HIP6601B
PVCC
ENLL
VIDPGOOD
IDROOP
HIP6601B
+12V
RT
ISL6561
6FN9098.5
May 12, 2005
Typical Application - 4-Phase Buck Converter with DCR Sensing and External NTC
VID3
+5V
PWM
VCC
BOOT
UGATE
PHASE
LGATE
GND
+12V
VIN
PWM
VCC BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
VID4
PGOOD
VID2
VID1
VID0
VSEN
VDIFF
FB COMP
VCC
GND
RGND
EN
ISEN1+
PWM1
PWM2
ISEN2+
PWM3
ISEN3+
PWM4
ISEN4+
ISL6561
µP
LOAD
VID12.5
ISEN1-
ISEN2-
ISEN3-
ISEN4-
TCOMP
REF
DAC
OVP
NTC
THERMISTOR
FS
OFS
DRIVER
HIP6601B
PVCC
ENLL
VIDPGOOD
IDROOP
HIP6601B
DRIVER
+12V
RT
ISL6561
7FN9098.5
May 12, 2005
ISL6561
Typical Application - 4-Phase Buck Converter with DCR Sensing and Internal PTC
VID3
+5V
PWM
VCC BOOT
UGATE
PHASE
LGATE
GND
+12V
DRIVER
VIN
PWM
VCC BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
PWM
VCC
BOOT
UGATE
PHASE
LGATE
PVCC
GND
+12V
HIP6601B
DRIVER
VIN
VID4
PGOOD
VID2
VID1
VID0
VSEN
VDIFF
FB
COMP
VCC
GND
RGND
EN
ISEN1+
PWM1
PWM2
ISEN2+
PWM3
ISEN3+
PWM4
ISEN4+
ISL6561
µP
LOAD
VID12.5
ISEN1-
ISEN2-
ISEN3-
ISEN4-
TCOMP
REF
DAC
OVP
FS
OFS
DRIVER
HIP6601B
PVCC
ENLL
VIDPGOOD
IDROOP
HIP6601B
+12V
RT
8FN9098.5
May 12, 2005
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Input, Output, or I/O Voltage (except OVP)GND -0.3V to VCC + 0.3V
OVP Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V
SD (Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV
ESD (Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300V
ESD (Charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV
Operating Conditions
Supply Voltage, VCC (5V bias mode, Note 3) . . . . . . . . . . +5V ±5%
Ambient Temperature (ISL6561CR, ISL6561CRZ). . . . . 0°C to 70°C
Ambient Temperature (ISL6561IR, ISL6561IRZ) . . . . -40°C to 85°C
Thermal Information
Thermal Resistance θJA (°C/W) θJC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . . 32 3.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150°C
Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stress abo ve those listed in “A bsolute Maxim u m Ratings” may cause permanent damage to the de vice. This is a stress only ratin g and o per ati on of th e device
at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Operating Conditi ons: VCC = 5V or I CC < 25mA (Not e 3). Unless Oth erwise Specif ied
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply VCC = 5VDC; EN = 5VDC; RT = 100 kΩ,
ISEN1 = ISEN2 = ISEN3 = ISEN4 = -70µA-1418mA
Shutdown Supply VCC = 5VDC; EN = 0VDC; RT = 100 kΩ-1014mA
SHUNT REGULATOR
VCC Voltage VCC tied to 12VDC thru 300Ω resistor, , RT = 100kΩ5.6 5.9 6.3 V
VCC Sink Current VCC tied to 12VDC thru 300Ω resistor, RT = 100kΩ--25mA
POWER-ON RESET AND ENABLE
POR Threshold VCC Rising 4.15 4.31 4.51 V
VCC Falling 3.68 3.82 4.05 V
ENABLE Threshold EN Rising 1.22 1.24 1.26 V
Hysteresis 100 mV
Fault Reset 1.10 1.14 1.18 V
ENLL Input Logic Low Level --0.4V
ENLL input Logic High Level 0.8 - - V
ENLL Leakage Current ENLL=5V 1µA
REFERENCE VOLTAGE AND DAC
System Accuracy (VID = 1.2V-1.6V) (0°C to
85°C)
(Note 4) -0.5 - 0.5 %VID
System Accuracy (VID = 1.2V-1.6V) (-
40°C)
(Note 4) -0.8 - 0.8 %VID
System Accuracy (VID = 0.8375V-
1.1875V) (0°C to 85°C)
(Note 4) -0.8 - 0.8 %VID
System Accuracy (VID = 0.8375V-
1.1875V) (-40°C)
(Note 4) -1.1 - 1.1 %VID
VID Pull Up -65 -50 -35 µA
VID Input Low Level --0.4V
VID Input High Level 0.8 - - V
DAC Source/Sink Current VID = 010100 -200 - 200 µA
REF Source/Sink Current -50 - 50 µA
ISL6561
9FN9098.5
May 12, 2005
PIN-ADJUSTABLE OFFSET
Voltage at OFS pin Offset resistor connected to ground 485 500 515 mV
VCC = 5.00V, offset resistor connected to VCC 2.91 3.00 3.09 V
OSCILLATOR
Accuracy RT = 100 kΩ-10 - 10 %
Adjustment Range 0.08 - 1.5 MHz
Sawtooth Amplitude -1.5- V
Max Duty Cycle - 66.7 - %
ERROR AMPLIFIER
Open-Loop Gain RL = 10kΩ to ground - 80 - dB
Open-Loop Bandwidth CL = 100pF, RL = 10kΩ to ground - 18 - MHz
Slew Rate CL = 100pF 4.4 6.0 7.5 V/µs
Maximum Output Voltage 4.0 4.3 - V
Output High Voltage @ 2mA 3.7 - - V
Output Low Voltage @ 2mA - - 1.40 V
REMOTE-SENSE AMPLIFIER
Bandwidth -20-MHz
Output High Current VSEN - RGND = 2.5V -500 - 500 µA
Output High Current VSEN - RGND = 0.6 -500 - 500 µA
PWM OUTPUT
PWM Output Voltage LOW Threshold Iload = ±500µA--0.3V
PWM Output Voltage HIGH Threshold Iload = ±500µA4.3 - - V
TEMPERATURE COMPENSATION
Temperature Compensation Current @
40°C and Tcomp = 0.5V 10 15 20 µA
Temperature Compensation
Transconductance -1-1µA/V/
°C
SENSE CURRENT
Sensed Current Tolerance (0°C to 85°C) ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA74 81 91 µA
Sensed Current Tolerance (-40°C) ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA74 81 92 µA
Overcurrent Trip Level (0°C to 85°C) 98 110 122 µA
Overcurrent Trip Level (-40°C) 98 110 127 µA
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage IPGOOD = 4mA - - 0.4 V
Under-Voltage Offset From VID (0°C to
85°C)
VSEN Falling 72 74 76 %VID
Under-Voltage Offset From VID (-40°C) VSEN Falling 71 74 82 %VID
Overvoltage Threshold Voltage above VID, After Soft Start (Note 5) 180 200 220 mV
Before Enable 1.63 V
VCC < POR Threshold 1.67 1.80 1.87 V
Overvoltage Reset Voltage VCC ≥ POR Threshold, VSEN Falling - 0.6 - V
VCC < POR Threshold - 1.5 - V
OVP Drive Voltage IOVP = -100mA, VCC = 5V - 1.9 - V
Minimum VCC for OVP 1.4 - - V
NOTES:
3. When using the internal shunt regulator, VCC is clamped to 6.02V (max). Current must be limited to 25mA or less.
4. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
5. During soft start, VDAC rises from 0 to VID. The overvoltage trip level is the higher of 1.7V and VDAC + 0.2V.
Electrical Specifications Operating Conditi ons: VCC = 5V or I CC < 25mA (Not e 3). Unless Oth erwise Specif ied (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ISL6561
10 FN9098.5
May 12, 2005
Functional Pin Description
VCC - Supplies all the power necessary to operate the chip.
The controller starts to operate when the v oltage on this pin
ex ceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply or through a series
300Ω resistor to a +12V supply.
GND - Bias and reference ground for the IC.
EN - This pin is a threshold-sensitive enable input for the
controller. Connecting the 12V supply to EN through an
appropriate resistor divider provides a means to synchronize
power-up of the controller and the MOSFET driver ICs.
When EN is driven above 1.24V, the ISL6561 is activ e
depending on status of ENLL, the internal POR, and pending
fault states. Driving EN below 1.14V will clear all fault states
and prime th e ISL6556 to soft start when re-enabled.
ENLL - This pin is implemented in QFN ISL6561 only. It’s a
logic-lev el enab le input for the controller . When asserted to a
logic high, the ISL6561 is active depending on status of EN,
the internal POR, VID inputs and pending fault states.
Deasserting ENLL will clear all fault states and prime the
ISL6561 to soft start when re-enabled.
FS - A resistor, placed from FS to ground will set the switch-
ing frequency. There is an inverse relationship between the
value of the resistor and the switching frequency. See Figure
15 and Equation 29.
VID4, VID3, VID2, VID1, VID0, and VID12.5 - These are the
inputs to the internal D AC that pro vides the reference voltage
for output regulation. Connect these pins either to open-drain
outputs with or without external pull-up resistors or to active-
pull-up outputs. VID4-VID12.5 have 50uA internal pull-up
current sources that diminish to zero as the voltage rises
above the logic-high level. These inputs can be pulled up as
high as VCC plus 0.3V.
VDIFF, VSEN, and RGND - VSEN and RGND form the
precision differential remote-sense amplifier. This amplifier
converts the differential voltage of the remote output to a
single-ended voltage referenced to local ground. VDIFF is
the amplifier’s output and the input to the regulation and
protection circuitry. Connect VSEN and RGND to the sense
pins of the remote load.
FB and COMP - Inverting input and output of the er ror
amplifier respectively. FB is connected to VDIFF through a
resistor. A negative current, proportional to output current is
present on the FB pin. A properly sized resistor between
VDIFF and FB sets the load line (droop). The droop scale
factor is set by the ratio of the ISEN resistors and the lower
MOSFET rDS(ON). COMP is tied back to FB through an
e x ternal R-C network to compensate the regula to r.
DAC and REF - The DAC output pin is the output of the
precision internal DAC reference. The REF input pin is the
positive input of the Error Amp . In typical applications, a 1kΩ,
1% resistor is used between DAC and REF to generate a
precise offset voltage. This voltage is proportional to the
offset current determined by the offset resistor from OFS to
ground or VCC. A capacitor is used between REF and
ground to smooth the voltage transition during Dynamic
VID™ operations.
PWM1, PWM2, PWM3, PWM4 - Pulse-width modulation
outputs. Connect these pins to the PWM input pins of the
Intersil driver IC. The number of active channels is
determined by the state of PWM3 and PWM4. Tie PWM3 to
VCC to configure for 2-phase operation. Tie PWM4 to VCC
to configure for 3-phase operation.
ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;
ISEN4+, ISEN4- - The ISEN+ and ISEN- pins are current
sense inputs to individual differential amplifiers.he sensed
current is used as a reference for channel balancing,
protection, and regulation. Inactive channels should have
their respective current sense inputs left open (for example,
for 3-phase operation open ISEN4+).
For DCR sensing, connect each ISEN- pin to the node
between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, RISEN.
The voltage across the sense capacitor is proportional to the
inductor current. The sense current is proportional to the
output current, and scaled by the DCR of the inductor,
divided by RISEN.
When configured for rDS(ON) current sensing, the ISEN1-,
ISEN2-, ISEN3-, and ISEN4- pins are grounded at the lo w er
MOSFET sources. The ISEN1+, ISEN2+, ISEN3+, and
ISEN4+ pins are then held at a virtual ground, such that a
resistor connected between them, and the drain terminal of
the associated lower MOSET, will carry a current
proportional to the current flowing through that channel. The
current is deter mined by the negative voltage developed
across the lower MOSFET’s rDS(ON), which is the channel
current scaled by rDS(ON).
PGOOD - PGOOD is used as an indication of the end of
soft-start per Intel VR10. It is an open-drain logic output that
is low impedance until the soft start is completed. It will be
pulled low again once the under-voltage point is reached.
OFS - The OFS pin provides a means to program a dc offset
current for generating a dc offset voltage at the REF input.
The offset current is generated via an external resistor and
precision internal voltage references. The polarity of the
offset is selected by connecting the resistor to GND or VCC.
For no offset, the OFS pin should be left unterminated.
TCOMP - Temperature compensation scalin g input. A
resistor from this pin to ground scales temperature
compensation of internal thermal sense circuitry. The
sensed temperature is utilized to modify the droop current
output to FB to adjust for MOSFET rDS(ON) or inductor DCR
variations with temperature.
ISL6561
11 FN9098.5
May 12, 2005
OVP - Ov ervoltage protection pin. This pin pulls to VCC and
is latched when an overvoltage condition is detected.
Connect this pin to the gate of an SCR or MOSFET tied from
VIN or VOUT to ground to prevent damage to the load. This
pin ma y be pulled above VCC as high as 15V to ground with
an external resistor . How e v er , it is only capab le of pulling low
when VCC is above 2V.
IDROOP - IDROOP is the ouput pin of sensed average
channel current which is propotional to load current. In the
application which does not require loadline, leave this pin
open. In the application which requires load line, connect this
pin to FB so that the sensed average current will flow
through the resistor between FB and VDIFF to create a
voltage drop which is propotional to load current.
Operation
Multi-Phase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multi-phase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase conv erter which is
both cost-effective and thermally viable have forced a
change to the cost-saving approach of multi-phase. The
ISL6561 controller helps simplifying the implementation by
integrating vital functions and requiring minimal output
components. The block diagrams on pages 2 and 3 provide
top level views of multi-phase power conversion using the
ISL65556ACB and ISL6561CR controllers.
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase conv erter , each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
f ollowing channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-to-
peak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
pre vious p hase . The pea k-to-peak current for each phase is
about 7A, and the dc components of the inductor currents
combine to f eed the lo ad.
To understand the reduction of ripple current amplitude in
the multi-phase circuit, examine the equation representing
an individual channel’s peak-to-peak inductor current.
In Equation 1, VIN and VOUT are th e input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase conv erters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
e xpression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output-
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
FIGURE 1. PWM AND INDUCT OR-CURRENT W A VEFORMS
FOR 3-PHASE CONVERTER
1µs/DIV
PWM2, 5V/DIV
PWM1, 5V/DIV
IL2, 7A/DIV
IL1, 7A/DIV
IL1 + IL2 + IL3, 7A/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
IPP
VIN VOUT
–()VOUT
LfSVIN
------------------------------------------------------= (EQ. 1)
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
INPUT-CAPACITOR CURRENT, 10A/DIV
1µs/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
ISL6561
12 FN9098.5
May 12, 2005
current. Reducing the inductor r ipple current allows the
designer to use fewer or less costly output capacitors.
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improv e ov erall system cost and size by lo wering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 36A to a 1.5V
load from a 12V input. The RMS input capacitor current is
5.9A. Compare this to a single-phase converter also
stepping down 12V to 1.5V at 36A. The single-phase
converter has 11.9A RMS input capacitor current. The
single-phase converter must use an input capacitor bank
with twice the RMS current capaci ty as the equivalent three-
phase converter.
Figures 16, 17 and 18 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution. Figure 19 shows the single
phase input-capacitor RMS current for comparison.
PWM Operation
The timing of each converter leg is set by the n u mb er of
active channels . The default channel setting for the ISL6561
is four. One switching cycle is defined as the time between
PWM1 pulse termination signals. The pulse termination
signal is the internally generated clock signal that triggers
the falling edge of PWM1. The cycle time of the pulse
ter m ination signal is the inverse of the switching frequency
set by the resistor between the FS pin and ground. Each
cycle begins when the clock signal commands the channel-1
PWM output to go low. The PWM1 transition signals the
channel-1 MOSFET driver to turn off the channel-1 upper
MOSFET and tur n on the channel-1 synchronous MOSFET.
In the default channel configuration, the PWM2 pulse
ter m inates 1/4 of a cycle after PWM1. The PWM3 output
f ollows another 1/4 of a cycle after PWM2. PWM4 terminates
another 1/4 of a cycle after PWM3.
If PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle later .
Connecting PWM4 to VCC selects three channel operation
and the pulse-termination times are spaced in 1/3 cycle
increments.
Once a PWM signal transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 4. When the modified
VCOMP voltage crosses the sawtooth r amp, the PWM output
transitions high. The MOSFET dr iver detects the change in
state of the PWM signal, turns off the synchronous MOSFET
and tur ns on the upper MOSFET. The PWM signal remains
high until the pulse termination signal commands the
beginning of the next cycle by triggering the PWM signal low.
Current Sensing
The ISL6561 supports inductor DCR sensing or MOSFET
rDS(ON) sensing. The internal circuitry, shown in Figures 3
and 5, represents channel n of an N-channel conv erter. This
circuitr y is repeated for each channel in the converter, but
may not be activ e depending on the status of the PWM3 and
PWM4 pins, as described in the PWM Operation section.
MOSFET rDS(ON) Sensing
The controller can sense the channel load current by
sampling the voltage across the lower MOSFET rDS(ON) as
in Figure 6. The amplifier is ground-reference by connecting
the ISEN- input to the source of the lower MOSFET. ISEN+
connects to the PHASE node through a resistor RISEN. The
voltage across RISEN is equivalent to the voltage drop
across the rDS(ON) of the lower MOSFET while it is
conducting. The resulting current into the ISEN+ pin is
proportional to the channel current IL. The ISEN current is
then sampled and held after sufficient settling time as
described in current sampling section. The sampled current
In, is used for channel-curre nt balance, load-line regulation,
and overcurrent protection. Fro m Figure 4, the following
equation for ISEN is derived
where IL is the channel curren t.
ILPP,
VIN NV
OUT
–()VOUT
LfSVIN
------------------------------------------------------------= (EQ. 2)
FIGURE 3. MOSFET rDS(ON) CURRENT-SENSING CIRCUIT
In
ISEN IL
rDS ON()
RISEN
--------------------------=
-
+
ISEN+(n)
RISEN
SAMPLE
&
HOLD
ISL6561 INTERNAL CIRCUIT EXTERNAL CIRCUIT
VIN
N-CHANNEL
MOSFETs
-
+
ILrDS ON()
IL
ISEN-(n)
(PTC)
ISEN IL
rDS ON()
RISEN
----------------------=(EQ. 3)
ISL6561
13 FN9098.5
May 12, 2005
INDUCTOR DCR Sensing
An inductor has a distr ibuted direct current winding
resistance (DCR). Consider the inductor DCR as a separate
lumped quantity as shown in Figure 4. The channel current,
IL, flowing through the inductor, also passes through the
DCR. Equation 4 sho ws the s-domain equivalent voltage,
VL, across the inductor.
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 5.
The voltage on the capacitor, VC, can be shown to be
proportional to the channel current IL(see Equation 5).
If the R-C network components are selected such that the R-
C time constant matches the inductor L/DCR time constant,
then VC is equal to the voltage drop across the DCR.
The capacitor voltage, VC, is replicated across the sense
resistor RISEN. so that the current flowing through the sense
resistor is proportional to the inductor current. Equation 6
shows that the relationship between the channel current and
the sensed current ISEN, is dr iven by the value of the sense
resistor and the inductor DCR.
Current Sampling
During the f orced off-time f ollowing a PWM transition low , the
associated channel current sense amplifier re produces a
signal , ISEN, proportional to the inductor current, IL.
Regardless of the current sense method, ISEN is simply a
scaled version of the inductor current. Coincident with the
f alling edge of the PWM signal, the sample and hold circuitry
samples ISEN. This is illustrated in Figure 5. The sample
time, tSAMP, is fix ed and equal to 1/3 of the switching period,
tSW. Therefore, the sample curre nt, In, is proportional to the
output current and held for one switching cycle. The sample
current is used for current balance, load-line regulation, and
overcurrent protection.
Channel-Current Balance
The sampled currents In, from each active channel are
summed together and divided by the number of active
channels. The resulting cycle average current, IAVG,
provides a measure of the total load current demand on the
converter during each switching cycle. Channel current
balance is achieved by comparing the sampled current of
each channel to the cycle average current, and making an
appropri ate adjustment to each channel pulse width base d
on the error. Intersil’s patented current-balance method is
illustrated in Figure 6, with error correction for channel 1
represented. In the figure, the cycle average current
combines with the channel 1 sample, I1, to create an error
signal IER. The filtered error sign al modifies the pulse width
commanded by VCOMP to correct any unbalance and force
IER tow ard zero . The same method for error signal correction
is applied to each active channel.
VLILsL DCR+⋅()⋅=(EQ. 4)
VC
sL
DCR
-------------
⋅1+
DCR IL
⋅()⋅
sRC 1+⋅()
---------------------------------------------------------------------
=
(EQ. 5)
FIGURE 4. DCR SENSING CONFIGURATION
In
ISEN ILDCR
RISEN
-------------------=
-
+
ISEN-
SAMPLE
&
HOLD
ISL6561 INTERNAL CIRCUIT
VIN
ISEN+
PWM(n)
ISL6561
RISEN
DCR
L
INDUCTOR
R
VOUT
COUT
-
+
VC(s)
C
ILs()
-
+
VL
ISEN ILDCR
RISEN
------------------
⋅=(EQ. 6)
tSAMP tSW
3
---------- 1
3f
SW
⋅
------------------
== (EQ. 7)
FIGURE 5. SAMPLE AND HOLD TIMING
TIME
PWM
IL
SWITCHING PERIOD
ISEN
SAMPLE CURRENT, In
t
SAMP
ISL6561
14 FN9098.5
May 12, 2005
Channel current balance is essential in realizing the thermal
advantage of multi-phase operation. The heat generated in
down converting is dissipated over multiple devices and a
greater area. The designer avoids the complexity of driving
multiple parallel MOSFETs, and the expense of using heat
sinks and nonstandard magnetic materials.
Voltage Regulation
The integrating compensation network sh own in Figure 7
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the D AC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6561 to include the
combined tolerances of each of these elements.
The output of the error amplifier, VCOMP, is compared to the
sawtooth w a v eform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET driv ers and
regulate the converter output to the spec ified reference
voltage. The internal and external circuitry that controls
voltage regulation is illustrated in Figure 7.
The ISL6561 incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measurin g the output
voltage relative to the local controller ground ref erence point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the non-
inver ting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, VDIFF, is
connected to the inverting input of the error amplifier through
an external resistor.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID12.5. The DAC decodes the a 6-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 50µA pull-up to an internal 2.5V
source for use with open-drain outputs. The pull-up current
diminishes to zero above the logic threshold to protect
voltage-sensitive output devices. External pull-up resistors
can augment the pull-up current sources in case leakage
into the driving device is greater than 50µA.
Load-Line Regulation
Some microprocessor manufacturers require a precisely-
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a
direction which wor ks to achieve the load-line regulation
required by these manufa cturers.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
÷ N
IAVG
I4 *
I3 *
I2
Σ
-
+
+
-
+
-
f(jω)
PWM1
I1
VCOMP
SAWTOOTH SIGNAL
IER
NOTE: *Channels 3 and 4 are optional.
FILTER
FIGURE 7. OUTPUT V OL TAGE AND LO AD-LINE
REGULATION WITH OFFSET ADUJUSTMENT
IAVG
EXTERNAL CIRCUIT ISL6561 INTERNAL CIRCUIT
COMP
RC
RFB
FB
VDIFF
VSEN
RGND
-
+
VDROOP
ERROR AMPLIFIER
-
+
VOUT+
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
VCOMP
C
C
REF
DAC
RREF
C
REF
-
+
VOUT-
IDROOP
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES
VID4 VID3 VID2 VID1 VID0 VID12.5 VDAC
0 1 0 1 0 0 0.8375V
0 1 0 0 1 1 0.8500V
0 1 0 0 1 0 0.8625V
0 1 0 0 0 1 0.8750V
0 1 0 0 0 0 0.8875V
0 0 1 1 1 1 0.9000V
0 0 1 1 1 0 0.9125V
0 0 1 1 0 1 0.9250V
0 0 1 1 0 0 0.9375V
0 0 1 0 1 1 0.9500V
0 0 1 0 1 0 0.9625V
0 0 1 0 0 1 0.975V0
0 0 1 0 0 0 0.9875V
0 0 0 1 1 1 1.0000V
0 0 0 1 1 0 1.0125V
0 0 0 1 0 1 1.0250v
0 0 0 1 0 0 1.0375V
0 0 0 0 1 1 1.0500V
ISL6561
15 FN9098.5
May 12, 2005
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to control the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, a current proportional to the average
current in all active channels, IAVG , flows from FB through a
load-line regulation resistor, RFB. The resulti ng voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
The regulated output voltage is reduced b y the droop v oltage
VDROOP. The output voltage as a function of load current is
derived by combining Equations 8 with the appropriate
sample current expression defined by the current sens e
method employed.
Where VREF is the reference voltage, VOFS is the
programmed offset voltage, VOUT is the total output current
of the conv erter , RISEN is the sense resistor in the ISEN line,
and RFB is the feedback resistor. RX has a value of DCR,
rDS(ON), or RSENSE depending on the sensing method.
Output-Voltage Offset Programming
The ISL6561 allows the designer to accurately adjust the
offset v oltage . When a resis tor , R OFS, is connected between
OFS and VCC, the voltage across it is regulated to 2.0V. This
causes a proportional current (IOFS) to flow into OFS. If
ROFS is connected to ground, the voltage across it is
regulated to 0.5V, and IOFS flows out of OFS. A resistor
0 0 0 0 1 0 1.0625V
0 0 0 0 0 1 1.0750V
0 0 0 0 0 0 1.0875V
11111 1 OFF
11111 0 OFF
1 1 1 1 0 1 1.1000V
1 1 1 1 0 0 1.1125V
1 1 1 0 1 1 1.1250V
1 1 1 0 1 0 1.1375V
1 1 1 0 0 1 1.1500V
1 1 1 0 0 0 1.1625V
1 1 0 1 1 1 1.1750V
1 1 0 1 1 0 1.1875V
1 1 0 1 0 1 1.2000V
1 1 0 1 0 0 1.2125V
1 1 0 0 1 1 1.2250V
1 1 0 0 1 0 1.2475V
1 1 0 0 0 1 1.2500V
1 1 0 0 0 0 1.2625V
1 0 1 1 1 1 1.2750V
1 0 1 1 1 0 1.2875V
1 0 1 1 0 1 1.3000V
1 0 1 1 0 0 1.3125V
1 0 1 0 1 1 1.3250V
1 0 1 0 1 0 1.3375V
1 0 1 0 0 1 1.3500V
1 0 1 0 0 0 1.3625V
1 0 0 1 1 1 1.3750V
1 0 0 1 1 0 1.3875V
1 0 0 1 0 1 1.4000V
1 0 0 1 0 0 1.4125V
1 0 0 0 1 1 1.4250V
1 0 0 0 1 0 1.4375V
1 0 0 0 0 1 1.4500V
1 0 0 0 0 0 1.4625V
0 1 1 1 1 1 1.4750V
0 1 1 1 1 0 1.4875V
0 1 1 1 0 1 1.5000V
0 1 1 1 0 0 1.5125V
0 1 1 0 1 1 1.5250V
TABLE 1. V OLTAGE IDENTIFICATION (VID) CODES (Contin ued)
VID4 VID3 VID2 VID1 VID0 VID12.5 VDAC
0 1 1 0 1 0 1.5375V
0 1 1 0 0 1 1.5500V
0 1 1 0 0 0 1.5625V
0 1 0 1 1 1 1.5750V
0 1 0 1 1 0 1.5875V
0 1 0 1 0 1 1.600V
TABLE 1. VOLTA GE IDENTI FICATION (VID) CODES (Continue d)
VID4 VID3 VID2 VID1 VID0 VID12.5 VDAC
VDROOP IAVG RFB
=(EQ. 8)
VOUT VREF VOFFSET
–IOUT
4
------------- RX
RISEN
------------------R
FB
–=(EQ. 9)
ISL6561
16 FN9098.5
May 12, 2005
between D AC and REF, RREF, is selected so that the product
(IOFS x RREF) is equal to the desired offset voltage. These
functions are shown in Figures 8.
As e vident in Figure 8, the OFSOUT pin must be connected
to the REF pin for this current injection to function in
ISL6561CR. The current flowing through RREF creates an
offset at the REF pin, which is ultimately duplicated at the
output of the regulator.
Once the desired output offset voltage has been determined,
use the following formulas to set ROFS:
For Positive Offset (connect ROFS to VCC):
For Negative Offset (connect ROFS to GND):
Dynamic VID
Moder n microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner . Supervising the saf e output voltage tr ansition within
the DAC range of the processor without discontinuity or
disr uption is a necessary function of the core-voltage
regulator.
The ISL6561 checks the VID inputs six times ev ery switching
cycle. If the VID code is found to have has changed, the
controller waits half of a complete cycle before executing a
12.5mV change. If during the half-cycle wait period, the
difference between DAC level and the new VID code
changes, no change is made. If the VID code is more than 1
bit higher or lower than the DAC (not recommended), the
controller will execute 12.5mV changes six times per cycle
until VID and DAC are equal. It is for this reason that it is
important to carefully control the rate of VID stepping in 1-bit
increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of RREF and CREF is required for an ISL6561
based voltage regulator. The selection of RREF is based on
the desired offset as detailed abov e in Output-Voltage Offset
Programming. The selection of CREF is based on the time
duration f or 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every TVID, the relationship between the time constant of
RREF and CREF network and TVID is given by Equation 12.
Typically RREF is selected to be 1kΩ, so with a VID step
change rate of 5µs per bit, the value of CREF is 22nF based
on Equation 12.
Temperature Compensation
Both the MOSFET rDS(ON) and inductor DCR of inductor
vary in proportion to v arying temperature. This means that a
circuit using rDS(ON) or DCR to sense channel current is
subject to a corresponding error in current measurement. In
order to compensate for this temperature-related error, a
temperature compensation circuit is provided within
ISL6561. This circuit senses the internal IC temperature and,
based on a resistor-selectable scaling factor, adjust the
droop current ouput to the IDROOP pin. When the TCOMP
resistor is properly selected, the droop current can
accurately represent the load current to achieve a linear,
temperature-independant load line.
The value of the Tcomp resistor can be determined using
Equation 13.
In Equation 13, KT is the te mperature coupling coefficient
between the ISL6561 and the low er MOSFET or output
inductor . It represents how closely the controller temperature
DYNAMIC
VID D/A
E/A
VCC
DAC
FB
REF
OFS
VCC GND
+
-
+
-
0.5V
2.0V
or
GND
ROFS
RREF
ISL6561CR
FIGURE 8. OUTPUT V OLTA GE OFFSET PR OGRAMMING
WITH ISL6561CR
ROFS 2R
REF
×
VOFFSET
--------------------------
=(EQ. 10)
ROFS 0.5 RREF
×
VOFFSET
------------------------------
=(EQ. 11)
CREF RREF4T
VID
=(EQ. 12)
(EQ. 13)
RTCOMP α
KTKTC
----------------------=
ISL6561
17 FN9098.5
May 12, 2005
tracks the lower MOSFET or inductor temperature. The
value of KT is typically between 75% and100%. KTC is the
temperature dependant transconductance of internal
compensation circuit. Its vaule is designed as 1µA/V/°C. The
temperature coefficient of MOSFET rDS(ON) or Inductor
DCR is given by . This is the ratio of the change in
resistance and the change in temp erature. Resistance is
nor malized to the value at 25°C and the value of is
typically between 0.35%/°C and 0.50 %/°C. For copper
wound inductors, is 0.39%/°C.
According to Equation 13, a voltage regulator with 80%
thermal coupling coefficient between the controller and lower
MOSFET and 0.4%/°C temperature coefficient of MOSFET
rDS(ON) requires a 5kΩ TCOMP resistor.
Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, PGOOD asserts
logic 1.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
f ollowing input conditions must be met before the ISL6561 is
released from shutdown mode.
1 - The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this threshold
is reached, proper operation of all aspects of the ISL6561 is
guaranteed. Hysteresis between the r ising and falling
thresholds assure that once enabled, the ISL6561 will not
inadvertentl y turn off unless the bias voltage drops
substantially (see Electrical Specifications).
2 - The ISL6561 features an enable input (EN) for power
sequencing between the controller bias voltage and another
voltage rail. The enable comparator holds the ISL6561 in
shutdown until the voltage at EN rises above 1.24V. The
enable comparator has about 100mV of hysteresis to
prevent bounce. It is important that the driver ICs reach their
POR level bef ore the ISL6561 becomes enab led. The
schematic in Figure 9 demonstrates sequencing the ISL6561
with the HIP660X family of Intersil MOSFET drivers, which
require 12V bias.
3 - The voltage on ENLL must be logic high to enable the
controller. This pin is typically connected to the
VID_PGOOD.
4 - The VID code must not be 111111 or 111110. These
codes signal the controller that no load is present. The
controller will enter shut-down mode after receiving either of
these codes and will execute soft start upon receiving any
other code. These codes can be used to enable or disable
the controller but it is not recommended. After receiving one
of these codes, the controller executes a 2-cycle delay
before changing the overvoltage trip level to the shut-down
level and disabling PWM. Overvoltage shutdown cannot be
reset using one of these codes.
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.24V; for
ISL6561CR, ENLL must be logic high; and VID cannot be
equal to 111111 or 111110. When each of th ese conditions
is true, the controller immediately begins the soft-start
sequence.
Soft-Start
During soft start, the D AC v oltage ramps linearly from zero to
the programmed VID le v el as shown in Figure 10. The PWM
signals remain in the high-impedance state until the
controller detects that the ramping DAC level has reached
the output-voltage le v el. This protects the system against the
large, negative inductor currents that would otherwise occur
when starting with a pre-existing charge on the output as the
controller attempted to regulate to z ero volts at the beginning
of the soft-start cycle. The soft-start time, tSS, begins with a
delay period equal to 64 s witching cycles followed b y a linear
ramp with a rate determined by the switching period, 1/fSW.
α
α
α
FIGURE 9. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
-
+
1.24V
EXTERNAL CIRCUITISL6561 INTERNAL CIRCUIT
EN
+12V
POR
CIRCUIT
10.7kΩ
1.40kΩ
ENABLE
COMPARATOR
SOFT START
AND
FAULT LOGIC
ENLL
VCC
tSS 64 1280 VID⋅+fSW
-----------------------------------------
=(EQ. 14)
ISL6561
18 FN9098.5
May 12, 2005
F or example , a regulator with 250kHz switching frequency
having VID set to 1.35V has tSS equal to 6.912ms.
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft start and ramps to zero during the first 640
cycles of soft start (704 cycles following enable). This
pre vents the large inrush current that would otherwise occur
should the output voltage start out with a slight negativ e
bias.
During the first 640 cycles of soft start (704 cycles following
enable) the DAC voltage increments the reference in 25mV
steps. The remainder of soft start sees the DAC ramping
with 12.5mV steps.
Fault Monitoring and Protection
The ISL6561 actively monitors o utput voltage and current to
detect fault conditions. Fault monitors trigger protectiv e
measures to prev ent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 11
outlines the inter action betw een the fault monitors and the
pow er g ood signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft start. PGOOD pulls low during shutdown and releases
high after a successful soft start. PGOOD only transitions
low when an under-voltage condition is detecte d or the
controller is disabled by a reset from EN, ENLL, POR, or one
of the no-CPU VID codes. After an under voltage event,
PGOOD will return high unless the controller has been
disabled. PGOOD does not automatically transition low upon
detection of an overvoltage condition.
Under -Voltage Detection
The under-voltage threshold is set at 75% of the VID code.
When the output voltage at VSEN is below the under-voltage
threshold, PGOOD gets pulled lo w.
Overvoltage Protection
When VCC is above 1.4V, but otherwise not valid as defined
under Power on Reset in Electrical Specifications, the
overvoltage trip circuit is active using auxiliary circuitry. In
this state, an overvoltage trip occurs if the voltage at VSEN
exceeds 1.8V.
With valid VCC, the overvoltage circuit is sensitive to the
voltage at VDIFF. In this state, the trip level is 1.7V prior to
v a li d en able conditions being met as de scribed in Enable
and Disable. The only exception to this is when the IC has
been disabled by an overvoltage trip. In that case the
overvoltage trip point is VID plus 200mV. During soft start,
the over voltage trip level is the higher of 1.7V or VID plus
200mV. Upon successful soft start, the overvoltage trip level
is 200mV above VID. Two actions are taken by the ISL6561
to protect the microprocessor load when an overvoltage
condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low until the voltage at VSEN falls below
0.6V with valid VCC or 1.5V otherwise. This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level that might cause damage to the
load. The PWM outputs remain low until VDIFF falls to the
programmed DAC level when they enter a high-impedance
state. The Intersil drivers respond to the high-impedance
input by turning off both upper and lower MOSFETs. If the
overvoltage condition reoccurs, the ISL6561 will again
FIGURE 10. SOFT-STAR T W A VEFORMS WITH AN UN-BIASED
OUTPUT. FSW = 500kHz
VOUT, 500mV/DIV
EN, 5V/DIV
500µs/DIV
FIGURE 11. POWER GOOD AND PROTECTION CIRCUITRY
OVP
-
+
VID + 0.2V
VDIFF
-
+
100µA
IAVG
-
+
DAC
REFERENCE
OV
OC
UV
PGOOD
75%
SOFT START, FAULT
AND CONTROL LOGIC
-
+
OC
I1
REPEAT FOR
EACH CHANNEL
100µA
ISL6561
19 FN9098.5
May 12, 2005
command the lower MOSFETs to tur n on. The ISL6561 will
continue to protect the load in this fashion as long as the
overvoltage condition recurs .
Simultaneous to the protective action of the PWM outputs,
the O VP pin pulls to VCC delivering up to 100mA to the gate
of a crowbar MOSFET or SCR placed either on the input rail
or the output rail. Turning on the MOSFET or SCR collapses
the power rail and causes a fuse placed further up stream to
blo w . The fuse m ust be sized such that the MOSFET or SCR
will not overheat before the fuse blows. The OVP pin is
tolerant to 12V (see Absolute Maximum Ratings), so an
exter nal resistor pull up can be used to augment the driving
capability. If using a pull up resistor in conjunction with the
internal overvoltage protection function, care must be taken
to avoid nuisance trips that could occur when VCC is below
2V. In that case, the controller is incapable of holding OVP
low.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6561 is reset. Cycling the
voltage on EN or ENLL or VCC below the POR-falling
threshold will reset the controller. Cycling the VID codes will
not reset the controller.
Overcurrent Protection
ISL6561 has two levels of overcurrent protection. Each
phase is protected from a sustained o vercurrent condition on
a delayed basis, while the combined phase currents are
protected on an instantaneous basis.
In instantaneous protection mode, the ISL6561 takes
advantage of the proportionality between the load current
and the av erage current, IAVG to detect an overcurrent
condition. See th e Channel-Current Balance section for
more detail on how the average current is measured. The
average current is continually compared with a constant
100µA ref e re nce current as shown in Figu re 11 . On ce th e
av erage current exceeds the ref erence current, a comparator
trigge rs the converter to shutdown.
In individual overcurrent protection mode, the ISL6561
continuously compares the current of each channel with the
same 100µA reference current. If any channel current
exceeds the reference current continuously for eight
consecutive cycles, the comparator triggers the converter to
shutdown.
At the beginning of overcurrent shutdown, the controller
places all PWM signals in a high-impedance sta te
commanding the Intersil MOSFET dr iver ICs to turn off both
upper and lower MOSFETs. The system remains in this
state a period of 4096 switching cycles. If the controller is still
enabled at the end of this wait period, it will attempt a soft
start. If the fault remains, trip-retry cycles continue
indefinitely (as shown in Figure 12) until either controller is
disabled or the fault is cleared. Note that the energy
delivered during tr ip-retry cycling is much less than during
full-load operation, so there, there is no therma l hazard
during this kind of operation.
General Design Guide
This design guide is intended to provide a high-level
e xplanati on of the steps ne cessary to create a multi-phase
pow er con verter . It is assumed that the reader i s familiar with
many of the basic skills and techn ique s referenced belo w. In
addition to this guide, Intersi l pro vides co mplete re ference
designs that include schema ti cs , bill s of materials, and
e xample board layouts f or all common microprocessor
applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the ne xt.
Princi pally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 15 and 20A. All
surface-mount designs will tend toward the lower end of this
current range. If through-hole MOSFETs and inductors can
be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current may be
pushed above 30A per phase, but these designs require
heat sinks and forced air to cool the MOSFETs, inductors
and heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the s witching frequency;
the capability of the MOSFETs to dissipate heat; and the
availability and nature of heat sinking and air flow.
0A
0V 2ms/DIV
OUTPUT CURRENT, 50A/DIV
FIGURE 12. O VERCURRENT BEHA VIOR IN HICCUP MODE.
FSW = 500kHz
OUTPUT VOLTAGE,
500mV/DIV
ISL6561
20 FN9098.5
May 12, 2005
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the ch annel
resistance (rDS(ON)). In Equation 15, IM is the max i mum
continuous output current; IPP is the peak-to-peak inductor
current (see Equation 1); d is the duty cycle (V OUT/VIN); and
L is the per-channel inductance.
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forw ard voltage at IM, VD(ON); the switching frequency,
fS; and the length of dead times, td1 and td2, at the
beginning and the end of the lower-MOSFET conduction
interval respectively.
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of PLOW,1 and
PLOW,2.
UPPER MOSFET POWER CALCULATION
In addition to rDS(ON) losses, a large portion of the upper-
MOSFET losses are due to currents conducted across the
input voltage (VIN) during switching. Since a substanti a l ly
higher portion of the upper-MOSFET losses are depende nt
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
recovery charge, Qrr; and the upper MOSFET rDS(ON)
conduction loss.
When the upper MOSFET turns off, the low er MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 17,
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 18, the
approximate power loss is PUP,2.
A third component involves the lower MOSFET’s reverse-
recovery charge, Qrr. Since the inductor current has fully
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can draw all of Qrr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is PUP,3 and is approximately
Finally, the resistive part of the upper MOSFET’s is given in
Equation 19 as PUP,4.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 17, 18, 19 and 20. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Current Sensing Resistor
The resistors connected between these pins and the
respective phase nodes determine the gains in the load-line
regulation loop and the channel-current balance loop as well
as setting the overcurrent trip point. Select values for these
resistors based on the room temperature rDS(ON) of the
lower MOSFETs, DCR of inductor or additional resistor; the
full-load operating current, IFL; and the number of phases, N
using Equation 21.
In certain circumstances , it may be necessary to adjust the
va lue of one or more ISEN resi stor. When the components of
one or more channels are inhibited from eff ectiv ely dissipating
their heat so that the affected channels run hotter than
desired, chose new, smaller values of RISEN for the affected
phases (see the section entitled Channe l-Curre nt Bal ance).
Choose RISEN,2 in proportion to the desired decrease in
temperature rise in order to cause proportionally less current
to flow in the hotter phase .
PLOW 1,rDS ON()
IM
N
------
2
1d–()
ILPP,21d–()
12
--------------------------------+= (EQ. 15)
PLOW 2,VDON()
fS
IM
N
------IPP
2
---------+
td1
IM
N
------IPP
2
---------
–
td2
+
=(EQ. 16)
PUP 1,VIN
IM
N
------IPP
2
---------+
t1
2
----
fS
≈(EQ. 17)
PUP 2,VIN
IM
N
------IPP
2
---------
–
t2
2
----
fS
≈(EQ. 18)
PUP 3,VIN Qrr fS
=(EQ. 19)
PUP 4,rDS ON()
IM
N
------
2
dIPP
2
12
----------
+≈(EQ. 20)
RISEN
RX
70 10 6
–
×
----------------------- IFL
N
--------= (EQ. 21)
RISEN 2,RISEN
∆T2
∆T1
----------=(EQ. 22)
ISL6561
21 FN9098.5
May 12, 2005
In Equation 22, make sure that ∆T2 is the desired temper ature
rise abov e the ambient temperature , and ∆T1 is the measured
temperature rise above the ambient temper ature . While a
single adjustment according to Eq uation 22 is usually
sufficient, it ma y occasionally be necessa ry to adjust RISEN
two or more times to achieve optimal thermal balance
between all channels.
Load-Line Regulation Resis tor
The load-line regulation resistor is labeled RFB in Figure 7.
Its value depends on the desired full-load droop voltage
(VDROOP in Figure 7). If Equation 21 is used to select each
ISEN resistor, the load-line regulation resistor is as shown
in Equation 23.
If one or more of the ISEN resistors is adjusted for thermal
balance, as in Equation 23, the load-line regulation resistor
should be selected according to Equation 24 where IFL is the
full-load operating current and RISEN(n) is the ISEN resistor
connected to the nth ISEN pin.
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loo p.
The final location of these poles is determined b y the system
function, the gain of the current si gnal, and the value of the
compensation components, RC and CC.
Since the system poles and zero are effected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
F ortunately there is a simple approximation that comes ve ry
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with v ery close to ideal
transient performance.
The feedback resistor, RFB, has already been chosen as
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the co mpensated system, f0. The target
bandwidth must be large enough to assure adequate
transient perfor m ance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
In Equations 25, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and VPP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 6 and Electrical Specifications.
RFB
VDROOP
70 10 6–
×
-------------------------= (EQ. 23)
RFB
VDROOP
IFL rDS ON()
-------------------------------- R ISEN n()
n
∑
=(EQ. 24)
FIGURE 13. COMPENSA TION CONFIGURA TION FOR
LOAD-LINE REGULATED ISL6561 CIRCUIT
ISL6561
COMP
CC
RC
RFB
FB
IDROOP
VDIFF
-
+
VDROOP
C2 (OPTIONAL)
1
2πLC
------------------- f 0
>
RCRFB
2πf0Vpp LC
0.75VIN
------------------------------------=
CC
0.75VIN
2πVPPRFBf0
------------------------------------=
Case 1:
1
2πLC
------------------- f0
1
2πC ESR()
------------------------------<≤
RCRFB
VPP 2π()
2f0
2LC
0.75 VIN
--------------------------------------------=
CC
0.75VIN
2π()
2f0
2VPPRFB LC
-------------------------------------------------------------=
Case 2:
(EQ. 25)
f0
1
2πC ESR()
------------------------------>
RCRFB
2πf0VppL
0.75 VIN ESR()
------------------------------------------=
CC
0.75VIN ESR()C
2πVPPRFBf0L
-------------------------------------------------=
Case 3:
ISL6561
22 FN9098.5
May 12, 2005
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 13). Keep
a position available for C2, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
nce selected, the compensation values in Equations 23
assure a stable converter with reasonable transient
perfor m ance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the v alue of CC from
Equations 23 unless some performance issue is noted.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 12). Keep
a position available for C2, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
trailing edge jitter problem is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated conv erter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A type
III controller, as shown in Figure 14, provides the necessary
compensation.
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
ex tra high-frequency pole, fHF. This pole can be used f or added
noise rejection or to assure adequate attenuation at the error-
amplifier high-order pole and zero frequencies. A good general
rule is to chose fHF = 10f0, b ut it can be higher if desired.
Choosing fHF to be lo we r than 10f0 can cause problems with
too much phase shift below the system bandwidth.
In the solutions to the compensation equations, there is a single
degree of freedom. For the solutions presented in Equations
26, RFB is selected arbitrarily. The remaining compensation
components are then selected according to Equations 26.
In Equations 26, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and VPP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 6 and Electrical Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
f orm a low-pass filter responsib le for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy until the regulator can respond.
Because it has a low bandwidth compared to the switching
frequency, the output filter necessarily limits the system
transient response. The output capacitor must supply or sink
load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often th e largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I; the load-current slew rate, di/dt; and the
maximum allow ab le output-v oltage de viation under transient
loading, ∆VMAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected m ust
have sufficiently low ESL and ESR so that the total output-
FIGURE 14. COMPENSA TION CIRCUIT FOR ISL6561 BASED
CONVERTER WITHOUT LOAD -LINE
REGULATION
ISL6561
COMP
CC
RC
RFB
FB
IDROOP
VDIFF
C2
C1
R1
CC
0.75VIN 2πfHF LC 1–
2π()
2f0fHF LCRFBVPP
-------------------------------------------------------------------=
RC
VPP 2π
2f0fHFLCRFB
0.75 VIN 2πfHF LC 1–
---------------------------------------------------------------------=
R1RFB
C ESR()
LC C ESR()–
-----------------------------------------=
C1
LC C ESR()–
RFB
-----------------------------------------=
C2
0.75VIN
2π()
2f0fHF LCRFBVPP
-------------------------------------------------------------------=
(EQ. 26)
ISL6561
23 FN9098.5
May 12, 2005
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
The filter capacitor must have sufficiently low ESL and ESR
so that ∆V < ∆VMAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the high-
frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also create s th e ma jo rity of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to IC,PP(ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
VPP(MAX), determines the lower limit on the inductance.
Since the capacitors are supplying a decreasing portio n of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
∆VMAX. This places an upper limit on inductance.
Equation 29 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 30
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
Input Supply Voltage Selection
The VCC input of the ISL6561 can be connected either
directly to a +5V supply or through a current limiting resistor
to a +12V supply. An integrated 5.8V shunt regulator
maintains the voltage on the VCC pin when a +12V supply is
used. A 300Ω resistor is suggested for limiting the current
into the VCC pin to a worst-case maximum of appro ximately
25mA.
Switching Frequency
There are a number of variables to consider when choosing
the s witching frequency, as there are considerab le eff ects on
the upper-MOSFET loss calculation. These effects are
outlined in MOSFETs, and they establish the upper limit for
the switching frequency. The lower limit is estab lished by the
requirement for fast transient response and small output-
v oltage ripple as outlined in Output Filter Design. Choose the
lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT (see th e fi gu re s la b ele d
Typical Application on pages 3 and 6). Figure 15 and
Equation 31 are provided to assist in selecting the correct
value for RT.
Input Capacitor Selection
The input capacitors are responsible for sourcing the ac
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the ac component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
∆V ESL()
di
dt
----- ESR()∆I+≈(EQ. 27)
L ESR()
VIN NV
OUT
–
VOUT
fSVINVPP MAX()
------------------------------------------------------------≥(EQ. 28)
L2NCV
O
∆I
()
2
--------------------- ∆VMAX ∆I ESR()–≤(EQ. 29)
L1.25
()
NC
∆I
()
2
--------------------------∆VMAX ∆IESR()–VIN VO
–
≤(EQ. 30)
FIGURE 15. RT vs SWITCHING FREQUENCY
100 1000 1000010
SWITCHING FREQUENCY (kHz)
10
100
1000
RT (kΩ)
RT1.0203 10()
10.6258- 1.03167()fS
()log[]
1200–
·
=(EQ. 31)
ISL6561
24 FN9098.5
May 12, 2005
For a two phase design, use Figure 16 to de termine the
input-capacitor RMS current requirement given the duty
cycle, maximum sustained output current (IO), and the ratio
of the per phase peak-to-peak inductor current (IL,PP) to IO.
Select a bulk capacitor with a ripple current rating which will
minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25 times greater
than the maximum input voltage.
Figures 17 and 18 provide the same input RMS current
infor m ation for three and four phase designs respectively.
Use the same approach to selecting the bulk capacitor type
and number as described above .
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes. The result from the high
current slew r ates produced b y the upper MOSFETs turn on
and off. Select low ESL cer amic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitic impedances and maximize suppression.
MULTI-PHASE RMS IMPROVEMENT
Figure 19 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multi-phase topology. For example,
compare the input r m s current requirements of a two-phase
converter versus that of a single phase. Assume both
converters have a duty cycle of 0.25, maximum sustained
output current of 40A, and a ratio of IC,PP to IO of 0.5. The
single phase converter would require 17.3 Arms current
capacity while the two-phase converter would only require
10.9 Arms. The adv antages become ev en more pronounced
when output current is increased and additional phases are
added to keep the component cost down relative to the
single phase approach.
0.3
0.1
0
0.2
INPUT-CAPACITOR CURRENT (IRMS / IO)
FIGURE 16. NORMALIZED INPUT-CAP A CITOR RMS CURRENT
vs DUTY CYCLE FOR 2-PHASE CONVE RTER
00.4 1.00.2 0.6 0.8
DUTY CYCLE (VO / VIN)
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.75 IO
DUTY CYCLE (VO / VIN)
FIGURE 17. NORMALIZED INPUT-CAP ACITOR RMS CURRENT
VS DUTY CYCLE FOR 3-PHASE CONVERTER
00.4 1.00.2 0.6 0.8
INPUT-CAPACITOR CURRENT (IRMS / IO)
0.3
0.1
0
0.2
IL,PP = 0
IL,PP = 0.25 IO
IL,PP = 0.5 IO
IL,PP = 0.75 IO
INPUT-CAPACITOR CURRENT (IRMS / IO)
FIGURE 18. NORMALIZED INPUT-CAP ACITOR RMS CURRENT
VS DUTY CYCLE FOR 4-PHASE CONVERTER
00.4 1.00.2 0.6 0.8
DUTY CYCLE (VO / VIN)
0.3
0.1
0
0.2
IL,PP = 0
IL,PP = 0.25 IO
IL,PP = 0.5 IO
IL,PP = 0.75 IO
FIGURE 19. NORMALIZED INPUT-CAP ACITOR RMS CURRENT
VS DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
00.4 1.00.2 0.6 0.8
DUTY CYCLE (VO / VIN)
INPUT-CAPACITOR CURRENT (IRMS / IO)
0.6
0.2
0
0.4
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.75 IO
ISL6561
25 FN9098.5
May 12, 2005
Layout Considerations
The f oll o wing layout strategies are intended to minimize the
impact of board parasitic impe dances on conv erter
performance and to optimize the heat-dissip ating capa bilities
of the printed-circuit board. These sections highlight some
important pra ctices which should not be o verlooked during the
la yout process .
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energ y and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that space
between the components is minimized while creating the
PHASE plane. Place the Intersil MOSFET driver IC as close
as possible to the MOSFETs they control to reduce the
parasitic impedances due to trace length between critical
driver input and output signals. If possible, duplicate the
same placement of these components for each phase.
Next, place the input and output capacitors. Position one
high-frequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to
the upper MOSFET drains as dictated by the component
size and dimensions. Long distances between input
capacitors and MOSFET drains results in too much trace
inductance and a reduction in capacitor perf ormance. Locate
the output capacitors between the inductors and the load,
while keeping them in close proximity to the microprocessor
socket.
The ISL6561 can be placed off to one side or centered
relative to the individual phase switching components.
Routing of sense lines and PWM signals will guide final
placement. Critic al small signal components to place close
to the controller include the ISEN resistors, RT resistor,
feedback resistor, and compensation components.
Bypass capacitors for the ISL6561 and HIP660X driver bias
supplies must be placed next to their respective pins. Trace
parasitic impedances will reduce their effectiveness.
Plane Allocation and Routing
Dedicate one solid laye r, usually a middle lay er, for a ground
plane. Make all critical component ground connection s with
vias to this plane. Dedicate one additional layer for power
planes; breaking the plane up into smalle r islands of
common voltage. Use the remaining layers for signal wiring.
Route phase planes of copper filled polygons on the top and
bottom once the switching component placement is set. Size
the trace width between the driver gate pins and the
MOSFET gates to carry 1A of current. When routing
components in the switching path, use short wide traces to
reduce the associated parasitic impedances.
ISL6561
26
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9098.5
May 12, 2005
ISL6561
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
INDEX
D1/2
D1
D/2
D
E1/2 E/2
E
A
2X 0.15 B
C
0.10 BAMC
A
N
SEATING PLANE
N
6
3
2
2
3
e
1
1
0.08
FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
CC
SECTION "C-C"
NX b A1
C
2X C
0.15
0.15
2X B
0
REF.
(Nd-1)Xe
(Ne-1)Xe
REF.
5
A1
4X P
A
C
C
4X P
B
2X AC0.15
A2
A3
D2
D2
E2
E2/2
TERMINAL TIP
SIDE VIEW
TOP VIEW
7
BOTTOM VIEW
7
5
C
LC
L
ee
E1
2
NX k
NX b
8
NX L
8
8
9
AREA
9
4X 0.10 C
/ /
9
(DATUM B)
(DATUM A)
AREA
INDEX
6
AREA
N9
CORNER
OPTION 4X
L1 L
10 L1 L
10
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJD-2 ISSUE C)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.18 0.23 0.30 5, 8
D 6.00 BSC -
D1 5.75 BSC 9
D2 3.95 4.10 4.25 7, 8
E 6.00 BSC -
E1 5.75 BSC 9
E2 3.95 4.10 4.25 7, 8
e 0.50 BSC -
k0.25 - - -
L 0.30 0.40 0.50 8
L1 - - 0.15 10
N402
Nd 10 3
Ne 10 3
P- -0.609
θ--129
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
