1-1 DS1006
Introduction_01.7
Data Sheet DS1006
© 2007 Lattice Semiconductor Corp.
Features
■
High Logic Density for System Integration
• 6K to 95K LUTs
• 90 to 583 I/Os
■
Embedded SERDES (LatticeECP2M Only)
• Data Rates 250 Mbps to 3.125 Gbps
• Up to 16 channels per device
PCI Express, Ethernet (1GbE, SGMII), OBSAI,
CPRI and Serial RapidIO.
■
sysDSP™ Block
• 3 to 42 blocks for high performance multiply and
accumulate
• Each block supports
– One 36x36, f our 18X18 or eight 9X9 multipliers
■
Flexible Memory Resources
• 55Kbits to 5308Kbits sysMEM™ Embedded
Block RAM (EBR)
– 18Kbit block
– Single, pseudo dual and true dual port
– Byte Enable Mode support
• 12K to 202Kbits distributed RAM
– Single port and pseudo dual port
■
sysCLOCK Analog PLLs and DLLs
• Two GPLLs and up to six SPLLs per device
– Clock multiply, divide, phase & delay adjust
– Dynamic PLL adjustment
• Two general purpose DLLs per device
■
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated gearing logic
• Source synchronous standards support
– SPI4.2, SFI4 (DDR Mode), XGMII
– High Speed ADC/DAC devices
• Dedicated DDR and DDR2 memory support
– DDR1: 400 (200MHz) / DDR2: 533 (266MHz)
• Dedicated DQS support
■
Programmable sysI/O™ Buffer Supports
Wide Range Of Interfaces
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL 3/2/18 I, II
• HSTL15 I and HSTL18 I, II
• PCI and Differential HSTL, SSTL
• LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
■
Flexible Device Configuration
• 1149.1 Boundary Scan compliant
• Dedicated bank for configuration I/Os
• SPI boot flash interface
• Dual boot images supported
• TransFR™ I/O for simple field updates
• Soft Error Detect macro embedded
■
Optional Bitstream Encryption
(LatticeECP2/M “S” Versions Only)
■
System Level Support
• ispTRACY™ internal logic analyzer capability
• On-chip oscillator for initialization & general use
• 1.2V power supply
Table 1-1. LatticeECP2 (Including “S-Series”) Family Selection
Device ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70
LUTs (K) 6 12 21 32 48 68
Distributed RAM (Kbits) 12 24 42 64 96 136
EBR SRAM (Kbits) 55 221 276 332 387 1032
EBR SRAM Blocks 3 12 15 18 21 60
sysDSP Blocks 36781822
18x18 Multipliers 12 24 28 32 72 88
GPLL + SPLL + DLL 2+0+2 2+0+2 2+0+2 2+0+2 2+2+2 2+4+2
Maximum Available I/O 190 297 402 450 500 583
Packages and I/O Combinations
144-pin TQFP (20 x 20 mm) 90 93
208-pin PQFP (28 x 28 mm) 131 131
256-ball fpBGA (17 x 17 mm) 190 193 193
484-ball fpBGA (23 x 23 mm) 297 331 331 339
672-ball fpBGA (27 x 27 mm) 402 450 500 500
900-ball fpBGA (31 x 31 mm) 583
LatticeECP2/M Family Data Sheet
Introduction
1-2
Introduction
Lattice Semiconductor LatticeECP2/M Family Data Sheet
Table 1-2. LatticeECP2M (Including “S-Series”) Family Selection
Introduction
The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced
DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an
economical FPGA fabric. This combination was achieved through advances in device architecture and the use of
90nm technology.
The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M
devices include LUT-based logic, distr ibuted and embedded memor y, Phase Locked Loops (PLLs), Delay Locked
Loops (DLLs), pre-engineered source synchronous I/O suppor t, enhanced sysDSP blocks and advanced configu-
ration support, including encryption (“S” versions only) and dual boot capabilities.
The LatticeECP2M de vice family features high speed SERDES with PCS . These high jitter tolerance and lo w tr ans-
mission jitter SERDES with PCS blocks can be configured to suppor t an array of popular data protocols including
PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization
settings make SERDES suitable for chip to chip and small form factor backplane applications.
The ispLEVER
®
design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis
tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to
place and route the design in the LatticeECP2/M device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Proper ty) ispLeverCORE™ modules for the LatticeECP2/M
family. By using these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of
their design, increasing their productivity.
Device ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100
LUTs (K) 19 34 48 67 95
sysMEM Blocks (18kb) 66 114 225 246 288
Embedded Memory (Kbits) 1217 2101 4147 4534 5308
Distributed Memory (Kbits) 41 71 101 145 202
sysDSP Blocks 6 8 22 24 42
18x18 Multipliers 24 32 88 96 168
GPLL+SPLL+DLL 2+6+2 2+6+2 2+6+2 2+6+2 2+6+2
Maximum Available I/O 304 410 410 436 520
Packages and SERDES / I/O Combinations
256-ball fpBGA (17 x 17 mm) 4 / 140 4 / 140
484-ball fpBGA (23 x 23 mm) 4 / 304 4 / 303 4 / 270
672-ball fpBGA (27 x 27 mm) 4 / 410 8 / 372
900-ball fpBGA (31 x 31 mm) 8 / 410 16 / 416 16 / 416
1152-ball fpBGA (35 x 35 mm) 16 / 436 16 / 520
3-1 DS1006 DC and Switching_01.8
Data Sheet DS1006
© 2009 Lattice Semiconductor Corp.
Recommended Operating Conditions
Absolute Maximum Ratings1, 2, 3
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V
Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V
Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V
Output Supply V oltage VCCIO . . . . . . . . . . . -0.5 to 3.75V
Input or I/O Tristate Voltage Applied4. . . . . . -0.5 to 3.75V
Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C
Junction Temperature (Tj) . . . . . . . . . . . . . . . . . . +125°C
4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.
Symbol Parameter Min. Max. Units
VCC1, 4, 5 Core Supply Voltage 1.14 1.26 V
VCCAUX1, 3, 4, 5 Auxiliary Supply Voltage 3.135 3.465 V
VCCPLL PLL Supply Voltage 1.14 1.26 V
VCCIO1, 2, 4 I/O Driver Supply Voltage 1.14 3.465 V
VCCJ1Supply Voltage for IEEE 1149.1 Test Access Port 1.14 3.465 V
tJCOM Junction Temperature, Commercial Operation 0 85 °C
tJIND Junction Temperature, Industrial Operation -40 100 °C
SERDES External Power Supply (For LatticeECP2M Family Only)
VCCIB Input Buffer Power Supply (1.2V) 1.14 1.26 V
Input Buffer Power Supply (1.5V) 1.425 1.575 V
VCCOB Output Buffer Power Supply (1.2V) 1.14 1.26 V
Output Buffer Power Supply (1.5V) 1.425 1.575 V
VCCAUX33 Termination Resistor Switching Power Supply 3.135 3.465 V
VCCRX6Receive Power Supply 1.14 1.26 V
VCCTX6Transmit Power Supply 1.14 1.26 V
VCCP6PLL and Reference Clock Buffer Power 1.14 1.26 V
1. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be con-
nected to the same power supply as VCCAUX. VCC and VCCPLL must be connected to the same power supply.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCAUX ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V.
4. For proper power-up configuration, users must ensure that the configuration control signals such as the CFGx, INITN, PROGRAMN and
DONE pins are driven to the proper logic le vels when the device pow ers up. The de vice po w er-up is triggered by the last of VCC, VCCAUX or
VCCIO8 supplies that reaches its minimum valid levels. Alternatively, if the configuration control signals are pulled up by VCCIO8, the VCCIO8
(configuration I/O bank) v oltage must be po wered up prior to or at the same time as the last of VCC or VCCA UX reaches its minimum levels.
5. For power-up, VCC must reach its valid minimum value before powering up VCCAUX (LatticeECP2/M “S” version devices only).
6. VCCRX,VCCTX and VCCP must be tied together in each quad and all quads need to be powered up.
LatticeECP2/M Family Data Sheet
DC and Switching Characteristics
3-2
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
Hot Socketing Specifications1, 2, 3, 4
Symbol Parameter Condition Min. Typ. Max. Units
IDK Input or I/O leakage current 0 ≤ VIN ≤ VIH (MAX.) — — +/-1000 µA
IHDIN5SERDES av erage input current when
device is powered down and inputs
are driven —— 4mA
1. VCC, VCCAUX and VCCIO should rise/fall monotonically. VCC and VCCPLL must be connected to the same power supply (applies to ECP2-6,
ECP2-12 and ECP2-20 only).
2. 0 ≤ VCC ≤ VCC (MAX), 0 ≤ VCCIO ≤ VCCIO (MAX) or 0 ≤ VCCAUX ≤ VCCAUX (MAX).
3. IDK is additive to IPU, IPW or IBH.
4. LVCMOS and LVTTL only.
5. Assumes that the device is powered down with all supplies grounded, both P and N inputs driven by a CML driver with maximum allowed
VCCIB of 1.575V, 8b10b data and internal AC coupling.
3-3
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol Parameter Condition Min. Typ. Max. Units
IIL, IIH1Input or I/O Low Leakage 0 ≤ VIN ≤ (VCCIO - 0.2V) — — 10 µA
IIH1Input or I/O High Leakage (VCCIO - 0.2V) < VIN ≤ 3.6V — — 150 µA
IPU I/O Active Pull-up Current 0 ≤ VIN ≤ 0.7 VCCIO -30 — -210 µA
IPD I/O Active Pull-down Current VIL (MAX) ≤ VIN ≤ VIH (MAX) 30 — 210 µA
IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA
IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCIO -30 — — µA
IBHLO Bus Hold Low Overdrive Current 0 ≤ VIN ≤ VCCIO — — 210 µA
IBHHO Bus Hold High Overdrive Current 0 ≤ VIN ≤ VCCIO — — -210 µA
VBHT Bus Hold Trip Points 0 ≤ VIN ≤ VIH (MAX) VIL (MAX) — VIH (MIN) V
C1 I/O Capacitance2 VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
VCC = 1.2V, VIO = 0 to VIH (MAX) —8—pf
C2 Dedicated Input Capacitance2VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
VCC = 1.2V, VIO = 0 to VIH (MAX) —6—pf
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. TA 25oC, f = 1.0MHz.
3-6
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
LatticeECP2 Initialization Supply Current1, 2, 3, 4
Over Recommended Operating Conditions
Symbol Parameter Device Typ.5, 6 Units
ICC Core Power Supply Current
ECP2-6 34 mA
ECP2-12 54 mA
ECP2-20 82 mA
ECP2-35 135 mA
ECP2-50 187 mA
ECP2-70 267 mA
ICCAUX Auxiliary Power Supply Current
ECP2-6 30 mA
ECP2-12 30 mA
ECP2-20 30 mA
ECP2-35 30 mA
ECP2-50 30 mA
ECP2-70 30 mA
ICCGPLL GPLL Power Supply Current (per GPLL) ECP2-35, -50, -70 Only 0.5 mA
ICCSPLL SPLL Power Supply Current (per SPLL) ECP2-35, -50, -70 Only 0.5 mA
ICCIO Bank Power Supply Current (per Bank) All Devices 3 mA
ICCJ VCCJ Power Supply Current All Devices 4 mA
1. Until DONE signal is active.
2. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.
3. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
4. Frequency 0MHz.
5. TJ = 25oC, power supplies at nominal voltage.
6. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O con-
figuration.
3-19
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
LatticeECP2/M External Switching Characteristics9
Over Recommended Operating Conditions
Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.
General I/O Pin Parameters (using Primary Clock without PLL)1
tCO Clock to Output - PIO Output
Register
LFE2-6 — 3.50 — 3.90 — 4.20 ns
LFE2-12 — 3.50 — 3.90 — 4.20 ns
LFE2-20 — 3.50 — 3.90 — 4.20 ns
LFE2-35 — 3.50 — 3.90 — 4.20 ns
LFE2-50 — 3.50 — 3.90 — 4.20 ns
LFE2-70 — 3.70 — 4.10 — 4.40 ns
LFE2M20 — 3.90 — 4.30 — 4.70 ns
LFE2M35 — 3.90 — 4.30 — 4.70 ns
LFE2M50 — 4.50 — 5.00 — 5.40 ns
LFE2M70 — 4.50 — 5.00 — 5.40 ns
LFE2M100 — 4.50 — 5.00 — 5.40 ns
tSU Clock to Data Setup - PIO Input
Register
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
tHClock to Data Hold - PIO Input
Register
LFE2-6 1.40 — 1.70 — 1.90 — ns
LFE2-12 1.40 — 1.70 — 1.90 — ns
LFE2-20 1.40 — 1.70 — 1.90 — ns
LFE2-35 1.40 — 1.70 — 1.90 — ns
LFE2-50 1.40 — 1.70 — 1.90 — ns
LFE2-70 1.40 — 1.70 — 1.90 — ns
LFE2M20 1.40 — 1.70 — 1.90 — ns
LFE2M35 1.40 — 1.70 — 1.90 — ns
LFE2M50 1.80 — 2.10 — 2.30 — ns
LFE2M70 1.80 — 2.10 — 2.30 — ns
LFE2M100 1.80 — 2.10 — 2.30 — ns
3-20
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
tSU_DEL Clock to Data Setup - PIO Input
Register with Data Input Delay
LFE2-6 1.40 — 1.70 — 1.90 — ns
LFE2-12 1.40 — 1.70 — 1.90 — ns
LFE2-20 1.40 — 1.70 — 1.90 — ns
LFE2-35 1.40 — 1.70 — 1.90 — ns
LFE2-50 1.40 — 1.70 — 1.90 — ns
LFE2-70 1.40 — 1.70 — 1.90 — ns
LFE2M20 1.40 — 1.70 — 1.90 — ns
LFE2M35 1.40 — 1.70 — 1.90 — ns
LFE2M50 1.40 — 1.70 — 1.90 — ns
LFE2M70 1.40 — 1.70 — 1.90 — ns
LFE2M100 1.40 — 1.70 — 1.90 — ns
tH_DEL Clock to Data Hold - PIO Input Reg-
ister with Input Data Delay
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
fMAX_IO Clock F requency of I/O Register and
PFU Register ECP2/M — 420 — 357 — 311 MHz
General I/O Pin Parameters (using Edge Clock without PLL)1
tCOE Clock to Output - PIO Output
Register
LFE2-6 — 2.60 — 2.90 — 3.20 ns
LFE2-12 — 2.60 — 2.90 — 3.20 ns
LFE2-20 — 2.60 — 2.90 — 3.20 ns
LFE2-35 — 2.60 — 2.90 — 3.20 ns
LFE2-50 — 2.60 — 2.90 — 3.20 ns
LFE2-70 — 2.60 — 2.90 — 3.20 ns
LFE2M20 — 2.60 — 2.90 — 3.20 ns
LFE2M35 — 2.60 — 2.90 — 3.20 ns
LFE2M50 — 3.10 — 3.40 — 3.70 ns
LFE2M70 — 3.10 — 3.40 — 3.70 ns
LFE2M100 — 3.10 — 3.40 — 3.70 ns
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.
3-21
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
tSUE Clock to Data Setup - PIO Input
Register
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
tHE Clock to Data Hold - PIO Input
Register
LFE2-6 0.90 — 1.10 — 1.30 — ns
LFE2-12 0.90 — 1.10 — 1.30 — ns
LFE2-20 0.90 — 1.10 — 1.30 — ns
LFE2-35 0.90 — 1.10 — 1.30 — ns
LFE2-50 0.90 — 1.10 — 1.30 — ns
LFE2-70 0.90 — 1.10 — 1.30 — ns
LFE2M20 0.90 — 1.10 — 1.30 — ns
LFE2M35 0.90 — 1.10 — 1.30 — ns
LFE2M50 1.20 — 1.40 — 1.60 — ns
LFE2M70 1.20 — 1.40 — 1.60 — ns
LFE2M100 1.20 — 1.40 — 1.60 — ns
tSU_DELE Clock to Data Setup - PIO Input
Register with Data Input Delay
LFE2-6 1.00 — 1.30 — 1.60 — ns
LFE2-12 1.00 — 1.30 — 1.60 — ns
LFE2-20 1.00 — 1.30 — 1.60 — ns
LFE2-35 1.00 — 1.30 — 1.60 — ns
LFE2-50 1.00 — 1.30 — 1.60 — ns
LFE2-70 1.00 — 1.30 — 1.60 — ns
LFE2M20 1.20 — 1.60 — 1.90 — ns
LFE2M35 1.20 — 1.60 — 1.90 — ns
LFE2M50 1.20 — 1.60 — 1.90 — ns
LFE2M70 1.20 — 1.60 — 1.90 — ns
LFE2M100 1.20 — 1.60 — 1.90 — ns
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.
3-22
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
tH_DELE Clock to Data Hold - PIO Input
Register with Input Data Delay
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
fMAX_IOE Clock Frequency of I/O and PFU
Register ECP2/M — 420 — 357 — 311 MHz
General I/O Pin Parameters (using Primary Clock with PLL)1
tCOPLL10 Clock to Output - PIO Output
Register
LFE2-6 — 2.30 — 2.60 — 2.80 ns
LFE2-12 — 2.30 — 2.60 — 2.80 ns
LFE2-20 — 2.30 — 2.60 — 2.80 ns
LFE2-35 — 2.30 — 2.60 — 2.80 ns
LFE2-50 — 2.30 — 2.60 — 2.80 ns
LFE2-70 — 2.30 — 2.60 — 2.80 ns
LFE2M20 — 2.30 — 2.60 — 2.80 ns
LFE2M35 — 2.30 — 2.60 — 2.80 ns
LFE2M50 — 2.60 — 2.90 — 3.10 ns
LFE2M70 — 2.60 — 2.90 — 3.10 ns
LFE2M100 — 2.70 — 3.00 — 3.20 ns
tSUPLL Clock to Data Setup - PIO Input
Register
LFE2-6 0.70 — 0.80 — 0.90 — ns
LFE2-12 0.70 — 0.80 — 0.90 — ns
LFE2-20 0.70 — 0.80 — 0.90 — ns
LFE2-35 0.70 — 0.80 — 0.90 — ns
LFE2-50 0.70 — 0.80 — 0.90 — ns
LFE2-70 0.70 — 0.80 — 0.90 — ns
LFE2M20 0.70 — 0.80 — 0.90 — ns
LFE2M35 0.70 — 0.80 — 0.90 — ns
LFE2M50 0.70 — 0.80 — 0.90 — ns
LFE2M70 0.70 — 0.80 — 0.90 — ns
LFE2M100 0.80 — 0.90 — 1.00 — ns
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.
3-23
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
tHPLL Clock to Data Hold - PIO Input
Register
LFE2-6 1.00 — 1.20 — 1.40 — ns
LFE2-12 1.00 — 1.20 — 1.40 — ns
LFE2-20 1.00 — 1.20 — 1.40 — ns
LFE2-35 1.00 — 1.20 — 1.40 — ns
LFE2-50 1.00 — 1.20 — 1.40 — ns
LFE2-70 1.00 — 1.20 — 1.40 — ns
LFE2M20 1.00 — 1.20 — 1.40 — ns
LFE2M35 1.00 — 1.20 — 1.40 — ns
LFE2M50 1.00 — 1.20 — 1.40 — ns
LFE2M70 1.00 — 1.20 — 1.40 — ns
LFE2M100 1.00 — 1.20 — 1.40 — ns
tSU_DELPLL Clock to Data Setup - PIO Input
Register with Data Input Delay
LFE2-6 1.80 — 2.00 — 2.20 — ns
LFE2-12 1.80 — 2.00 — 2.20 — ns
LFE2-20 1.80 — 2.00 — 2.20 — ns
LFE2-35 1.80 — 2.00 — 2.20 — ns
LFE2-50 1.80 — 2.00 — 2.20 — ns
LFE2-70 1.80 — 2.00 — 2.20 — ns
LFE2M20 1.80 — 2.00 — 2.20 — ns
LFE2M35 1.80 — 2.00 — 2.20 — ns
LFE2M50 1.90 — 2.10 — 2.30 — ns
LFE2M70 1.90 — 2.10 — 2.30 — ns
LFE2M100 2.00 — 2.20 — 2.40 — ns
tH_DELPLL Clock to Data Hold - PIO Input
Register with Input Data Delay
LFE2-6 0.00 — 0.00 — 0.00 — ns
LFE2-12 0.00 — 0.00 — 0.00 — ns
LFE2-20 0.00 — 0.00 — 0.00 — ns
LFE2-35 0.00 — 0.00 — 0.00 — ns
LFE2-50 0.00 — 0.00 — 0.00 — ns
LFE2-70 0.00 — 0.00 — 0.00 — ns
LFE2M20 0.00 — 0.00 — 0.00 — ns
LFE2M35 0.00 — 0.00 — 0.00 — ns
LFE2M50 0.00 — 0.00 — 0.00 — ns
LFE2M70 0.00 — 0.00 — 0.00 — ns
LFE2M100 0.00 — 0.00 — 0.00 — ns
DDR I/O Pin Parameters2
tDVADQ Data Valid After DQS (DDR Read) ECP2/M — 0.225 — 0.225 — 0.225 UI
tDVEDQ Data Hold After DQS (DDR Read) ECP2/M 0.640 — 0.640 — 0.640 — UI
tDQVBS Data Valid Before DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI
tDQVAS Data Valid After DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI
fMAX_DDR DDR Clock Frequency6ECP2/M 95 200 95 166 95 133 MHz
DDR2 I/O Pin Parameters3
tDVADQ Data Valid After DQS (DDR Read) ECP2/M — 0.225 — 0.225 — 0.225 UI
tDVEDQ Data Hold After DQS (DDR Read) ECP2/M 0.640 — 0.640 — 0.640 — UI
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.
3-24
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
tDQVBS Data Valid Before DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI
tDQVAS Data Valid After DQS (DDR Write) ECP2/M 0.250 — 0.250 — 0.250 — UI
fMAX_DDR2 DDR Clock Frequency ECP2/M 133 266 133 200 133 166 MHz
SPI4.2 I/O Pin Parameters Static Alignment4, 8, 11
Maximum Data Rate
ECP2-20 — 750 — 622 — 622 Mbps
ECP2-35 — 750 — 622 — 622 Mbps
ECP2-50 — 750 — 622 — 622 Mbps
ECP2-70 — 750 — 622 — 622 Mbps
ECP2M20 — 622 — 622 — 622 Mbps
ECP2M35 — 622 — 622 — 622 Mbps
ECP2M50 — 622 — 622 — 622 Mbps
ECP2M70 — 622 — 622 — 622 Mbps
ECP2M100 — 622 — 622 — 622 Mbps
tDVACLKSPI Data Valid After CLK (Receive)
ECP2-20 — 0.25 — 0.25 — 0.25 UI
ECP2-35 — 0.25 — 0.25 — 0.25 UI
ECP2-50 — 0.25 — 0.25 — 0.25 UI
ECP2-70 — 0.25 — 0.25 — 0.25 UI
ECP2M20 — 0.21 — 0.21 — 0.21 UI
ECP2M35 — 0.21 — 0.21 — 0.21 UI
ECP2M50 — 0.21 — 0.21 — 0.21 UI
ECP2M70 — 0.21 — 0.21 — 0.21 UI
ECP2M100 — 0.21 — 0.21 — 0.21 UI
tDVECLKSPI Data Hold After CLK (Receive)
ECP2-20 0.75 — 0.75 — 0.75 — UI
ECP2-35 0.75 — 0.75 — 0.75 — UI
ECP2-50 0.75 — 0.75 — 0.75 — UI
ECP2-70 0.75 — 0.75 — 0.75 — UI
ECP2M20 0.79 — 0.79 — 0.79 — UI
ECP2M35 0.79 — 0.79 — 0.79 — UI
ECP2M50 0.79 — 0.79 — 0.79 — UI
ECP2M70 0.79 — 0.79 — 0.79 — UI
ECP2M100 0.79 — 0.79 — 0.79 — UI
tDIASPI Data Invalid After Clock (Transmit)
ECP2-20 — 280 — 280 — 280 ps
ECP2-35 — 280 — 280 — 280 ps
ECP2-50 — 280 — 280 — 280 ps
ECP2-70 — 280 — 280 — 280 ps
ECP2M20 — 230 — 230 — 230 ps
ECP2M35 — 230 — 230 — 230 ps
ECP2M50 — 230 — 230 — 230 ps
ECP2M70 — 230 — 230 — 230 ps
ECP2M100 — 230 — 230 — 230 ps
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.
3-25
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
tDIBSPI Data Invalid Before Clock (Transmit)
ECP2-20 — 280 — 280 — 280 ps
ECP2-35 — 280 — 280 — 280 ps
ECP2-50 — 280 — 280 — 280 ps
ECP2-70 — 280 — 280 — 280 ps
ECP2M20 — 230 — 230 — 230 ps
ECP2M35 — 230 — 230 — 230 ps
ECP2M50 — 230 — 230 — 230 ps
ECP2M70 — 230 — 230 — 230 ps
ECP2M100 — 230 — 230 — 230 ps
XGMII I/O Pin Parameters (312 Mbps)5
tSUXGMII Data Setup Before Read Clock ECP2/M 480 — 480 — 480 — ps
tHXGMII Data Hold After Read Clock ECP2/M 480 — 480 — 480 — ps
tDVBCKXGMII Data Valid Before Clock ECP2/M 960 — 960 — 960 — ps
tDVACKXGMII Data Valid After Clock ECP2/M 960 — 960 — 960 — ps
Primary
fMAX_PRI7Frequency for Primary Clock Tree ECP2/M — 420 — 357 — 311 MHz
tW_PRI Clock Pulse Width for Primary Clock ECP2/M 0.95 — 1.19 — 2.00 — ns
tSKEW_PRI Primary Clock Skew Within a Bank ECP2/M — 300 — 360 — 420 ps
Edge Clock
fMAX_EDGE7Frequency for Edge Clock ECP2/M — 420 — 357 — 311 MHz
tW_EDGE Clock Pulse Width for Edge Clock ECP2/M 0.95 — 1.19 — 2.00 — ns
tSKEW_EDGE Edge Clock Skew Within an Edge of
the Device ECP2/M — 300 — 360 — 420 ps
1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.
2. DDR timing numbers based on SSTL25 for BGA packages only.
3. DDR2 timing numbers based on SSTL18 for BGA packages only.
4. SPI4.2 and SFI4 timing numbers based on LVDS25 for BGA packages only.
5. XGMII timing numbers based on HSTL class I. A corresponding left/right dedicated clock buffer is used when using the SPI4.2 interface to
the left or right edge of the device. For SPI4.2 mode, the software tool will help in selecting the appropriate clock buffer.
6. IP will be used to support DDR and DDR2 memory data rates down to 95MHz. This approach uses a free-running clock and PFU register to
sample the data instead of the hardwired DDR memory interface.
7. Using the LVDS I/O standard.
8. ECP2-6 and ECP2-12 do not support SPI4.2
9. The AC numbers do not apply to PCLK6 and PCLK7.
10. Applies to CLKOP only.
11. Please refer to TN1159, LatticeECP2/M Pin Assignment Recommendations for best performance.
Timing v.A 0.11
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.
3-28
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
LatticeECP2/M Internal Switching Characteristics1
Over Recommended Operating Conditions
Parameter Description -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.
PFU/PFF Logic Mode Timing
tLUT4_PFU LUT4 delay (A to D inputs to F output) — 0.180 — 0.198 — 0.216 ns
tLUT6_PFU LUT6 delay (A to D inputs to OFX output) — 0.304 — 0.331 — 0.358 ns
tLSR_PFU Set/Reset to output of PFU (Asynchro-
nous) — 0.600 — 0.655 — 0.711 ns
tSUM_PFU Clock to Mux (M0,M1) Input Setup Time 0.128 — 0.129 — 0.129 — ns
tHM_PFU Clock to Mux (M0,M1) Input Hold Time -0.051 — -0.049 — -0.046 — ns
tSUD_PFU Clock to D input setup time 0.061 — 0.071 — 0.081 — ns
tHD_PFU Clock to D input hold time 0.002 — 0.003 — 0.003 — ns
tCK2Q_PFU Clock to Q dela y, (D-type Register Configu-
ration) — 0.285 — 0.309 — 0.333 ns
PFU Dual Port Memory Mode Timing
tCORAM_PFU Clock to Output (F Port) — 0.902 — 1.083 — 1.263 ns
tSUDATA_PFU Data Setup Time -0.172 — -0.205 — -0.238 — ns
tHDATA_PFU Data Hold Time 0.199 — 0.235 — 0.271 — ns
tSUADDR_PFU Address Setup Time -0.245 — -0.284 — -0.323 — ns
tHADDR_PFU Address Hold Time 0.246 — 0.285 — 0.324 — ns
tSUWREN_PFU Write/Read Enable Setup Time -0.122 — -0.145 — -0.168 — ns
tHWREN_PFU Write/Read Enable Hold Time 0.132 — 0.156 — 0.180 — ns
PIC Timing
PIO Input/Output Buffer Timing
tIN_PIO Input Buffer Delay (LVCMOS25) — 0.613 — 0.681 — 0.749 ns
tOUT_PIO Output Buffer Delay (LVCMOS25) — 1.115 — 1.115 — 1.343 ns
IOLOGIC Input/Output Timing
tSUI_PIO Input Register Setup Time (Data Before
Clock) 0.596 — 0.645 — 0.694 — ns
tHI_PIO Input Register Hold Time (Data after
Clock) -0.570 — -0.614 — -0.658 — ns
tCOO_PIO Output Register Clock to Output Delay — 0.61 — 0.66 — 0.72 ns
tSUCE_PIO Input Register Clock Enable Setup Time 0.032 — 0.037 — 0.041 — ns
tHCE_PIO Input Register Clock Enable Hold Time -0.022 — -0.025 — -0.028 — ns
tSULSR_PIO Set/Reset Setup Time 0.184 — 0.201 — 0.217 — ns
tHLSR_PIO Set/Reset Hold Time -0.080 — -0.086 — -0.093 — ns
EBR Timing
tCO_EBR Clock (Read) to output from Address or
Data — 2.51 — 2.75 — 2.99 ns
tCOO_EBR Clock (Write) to output from EBR output
Register — 0.33 — 0.36 — 0.39 ns
tSUDATA_EBR Setup Data to EBR Memory -0.157 — -0.181 — -0.205 — ns
tHDATA_EBR Hold Data to EBR Memory 0.173 — 0.195 — 0.217 — ns
tSUADDR_EBR Setup Address to EBR Memory -0.115 — -0.130 — -0.145 — ns
tHADDR_EBR Hold Address to EBR Memory 0.138 — 0.155 — 0.172 — ns
tSUWREN_EBR Setup Write/Read Enable to PFU Memory -0.128 — -0.149 — -0.170 — ns
3-29
DC and Switching Characteristics
Lattice Semiconductor LatticeECP2/M Family Data Sheet
tHWREN_EBR Hold Write/Read Enable to PFU Memory 0.139 — 0.156 — 0.173 — ns
tSUCE_EBR Clock Enable Setup Time to EBR Output
Register 0.123 — 0.134 — 0.145 — ns
tHCE_EBR Clock Enable Hold Time to EBR Output
Register -0.081 — -0.090 — -0.100 — ns
tRSTO_EBR Reset To Output Delay Time from EBR
Output Register — 1.03 — 1.15 — 1.26 ns
tSUBE_EBR Byte Enable Set-Up Time to EBR Output
Register -0.115 — -0.130 — -0.145 — ns
tHBE_EBR Byte Enable Hold Time to EBR Output
Register 0.138 — 0.155 — 0.172 — ns
GPLL Parameters
tRSTREC_GPLL Reset Recovery to Rising Clock 1.00 — 1.00 — 1.00 — ns
SPLL Parameters
tRSTREC_SPLL Reset Recovery to Rising Clock 1.00 — 1.00 — 1.00 — ns
DSP Block Timing2,3
tSUI_DSP Input Register Setup Time 0.12 — 0.13 — 0.14 — ns
tHI_DSP Input Register Hold Time 0.02 — -0.01 — -0.03 — ns
tSUP_DSP Pipeline Register Setup Time 2.18 — 2.42 — 2.66 — ns
ttHP_DSP Pipeline Register Hold Time -0.68 — -0.77 — -0.86 — ns
tSUO_DSP Output Register Setup Time 4.26 — 4.71 — 5.16 — ns
tHO_DSP Output Register Hold Time -1.25 — -1.40 — -1.54 — ns
tCOI_DSP Input Register Clock to Output Time — 3.92 — 4.30 — 4.68 ns
tCOP_DSP Pipeline Register Clock to Output Time — 1.87 — 1.98 — 2.08 ns
tCOO_DSP Output Register Clock to Output Time — 0.50 — 0.52 — 0.55 ns
tSUADDSUB AddSub Input Register Setup Time -0.24 — -0.26 — -0.28 — ns
tHADDSUB AddSub Input Register Hold Time 0.27 — 0.29 — 0.32 — ns
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
3. DSP Block is configured in Multiply Add/Sub 18x18 Mode.
Timing v.A 0.11
LatticeECP2/M Internal Switching Characteristics1 (Continued)
Over Recommended Operating Conditions
Parameter Description -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.
5-14
Ordering Information
Lattice Semiconductor LatticeECP2/M Family Data Sheet
LatticeECP2M Part Number Description
Ordering Information
Note: LatticeECP2M devices are dual marked. For example, the commercial speed grade LFE2M50E-7F672C is
also marked with industrial grade -6I (LFE2M50E-6F672I). The commercial grade is one speed grade faster than
the associated dual mark industrial grade. The slowest commercial grade does not have industrial markings. The
markings appear as follows:
LFE2M XXX XE – X XXXXXX X
Grade
C = Commercial
I = Industrial
Logic Capacity
20 = 20K LUTs
35 = 35K LUTs
50 = 50K LUTs
70 = 70K LUTs
100 = 100K LUTs
Supply V oltage
E = 1.2V
Speed
5 = Slowest
6
7 = Fastest
Package
F256 = 256-ball fpBGA
F484 = 484-ball fpBGA
F672 = 672-ball fpBGA
F900 = 900-ball fpBGA
F1152 = 1152-ball fpBGA
F1156 = 1156-ball fpBGA
FN256 = 256-ball Lead-free fpBGA
FN484 = 484-ball Lead-free fpBGA
FN672 = 672-ball Lead-free fpBGA
FN900 = 900-ball Lead-free fpBGA
FN1152 = 1152-ball Lead-free fpBGA
FN1156 = 1156-ball Lead-free fpBGA
Device Family
ECP2M (LatticeECP2 FPGA + SERDES)
Encryption
S = Security Series (Encryption Feature)
Blank = Standard Series (No Encryption)
LFE2M35E
7F672C-6I
Datecode
LFE2M35SE
7F672C-6I
Datecode
Contact Your Local Lattice Sales Representative for Product Availability.
5-18
Ordering Information
Lattice Semiconductor LatticeECP2/M Family Data Sheet
LatticeECP2M Standard Series Devices, Lead-Free Packaging
Commercial
Part Number I/Os Voltage Grade Package Pins Temp. LUTs (K)
LFE2M20E-5FN484C 304 1.2V -5 Lead-Free fpBGA 484 COM 20
LFE2M20E-6FN484C 304 1.2V -6 Lead-Free fpBGA 484 COM 20
LFE2M20E-7FN484C 304 1.2V -7 Lead-Free fpBGA 484 COM 20
LFE2M20E-5FN256C 140 1.2V -5 Lead-Free fpBGA 256 COM 20
LFE2M20E-6FN256C 140 1.2V -6 Lead-Free fpBGA 256 COM 20
LFE2M20E-7FN256C 140 1.2V -7 Lead-Free fpBGA 256 COM 20
Part Number I/Os Voltage Grade Package Pins Temp. LUTs (K)
LFE2M35E-5FN672C 410 1.2V -5 Lead-Free fpBGA 672 COM 35
LFE2M35E-6FN672C 410 1.2V -6 Lead-Free fpBGA 672 COM 35
LFE2M35E-7FN672C 410 1.2V -7 Lead-Free fpBGA 672 COM 35
LFE2M35E-5FN484C 303 1.2V -5 Lead-Free fpBGA 484 COM 35
LFE2M35E-6FN484C 303 1.2V -6 Lead-Free fpBGA 484 COM 35
LFE2M35E-7FN484C 303 1.2V -7 Lead-Free fpBGA 484 COM 35
LFE2M35E-5FN256C 140 1.2V -5 Lead-Free fpBGA 256 COM 35
LFE2M35E-6FN256C 140 1.2V -6 Lead-Free fpBGA 256 COM 35
LFE2M35E-7FN256C 140 1.2V -7 Lead-Free fpBGA 256 COM 35
Part Number I/Os Voltage Grade Package Pins Temp. LUTs (K)
LFE2M50E-5FN900C 410 1.2V -5 Lead-Free fpBGA 900 COM 50
LFE2M50E-6FN900C 410 1.2V -6 Lead-Free fpBGA 900 COM 50
LFE2M50E-7FN900C 410 1.2V -7 Lead-Free fpBGA 900 COM 50
LFE2M50E-5FN672C 372 1.2V -5 Lead-Free fpBGA 672 COM 50
LFE2M50E-6FN672C 372 1.2V -6 Lead-Free fpBGA 672 COM 50
LFE2M50E-7FN672C 372 1.2V -7 Lead-Free fpBGA 672 COM 50
LFE2M50E-5FN484C 270 1.2V -5 Lead-Free fpBGA 484 COM 50
LFE2M50E-6FN484C 270 1.2V -6 Lead-Free fpBGA 484 COM 50
LFE2M50E-7FN484C 270 1.2V -7 Lead-Free fpBGA 484 COM 50
Part Number I/Os Voltage Grade Package Pins Temp. LUTs (K)
LFE2M70E-5FN1152C 436 1.2V -5 Lead-Free fpBGA 1152 COM 70
LFE2M70E-6FN1152C 436 1.2V -6 Lead-Free fpBGA 1152 COM 70
LFE2M70E-7FN1152C 436 1.2V -7 Lead-Free fpBGA 1152 COM 70
LFE2M70E-5FN900C 416 1.2V -5 Lead-Free fpBGA 900 COM 70
LFE2M70E-6FN900C 416 1.2V -6 Lead-Free fpBGA 900 COM 70
LFE2M70E-7FN900C 416 1.2V -7 Lead-Free fpBGA 900 COM 70
