Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6 1Publication Order Number:
SN74LS373/D
SN74LS373 SN74LS374
Octal Transparent Latch
with 3-State Outputs;
Octal D-Type Flip-Flop
with 3-State Output
The SN74LS373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 is
manufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families.
•Eight Latches in a Single Package
•3-State Outputs for Bus Interfacing
•Hysteresis on Latch Enable
•Edge-Triggered D-Type Inputs
•Buffered Positive Edge-Triggered Clock
•Hysteresis on Clock Input to Improve Noise Margin
•Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –2.6 mA
IOL Output Current – Low 24 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS373N 16 Pin DIP 1440 Units/Box
SN74LS373DW 16 Pin
SOIC
DW SUFFIX
CASE 751D
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 738
20
1
20
1
SN74LS374N 16 Pin DIP 1440 Units/Box
SN74LS374DW 16 Pin 2500/Tape & Reel
SN74LS373 SN74LS374
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs
D0 – D7
LE
CP
OE
O0 – O7
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
HIGH LOW
(Note a)
LOADING
PIN NAMES
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
SN74LS373 SN74LS374
18 17 16 15 14 13
1234567
20 19
8
VCC
OE
O7D7D6O6D5
O5D4
O0D0D1O1O2D2D3
910
O3GND
12
O4LE
18 17 16 15 14 13
1234567
20 19
8
VCC
OE
O7D7D6O6D5
O5D4
O0D0D1O1O2D2D3
910
O3GND
12 11
O4CP
11
TRUTH TABLE
LS373
DnLE OE On
H H L H
L H L L
X L L Q0
X X H Z*
LS374
DnLE OE On
H L H
L L L
X X H Z*
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
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3
LOGIC DIAGRAMS
SN74LS373
SN74LS374
D
D
GQ
CP
QQ
CP
OE
OE
LE
LATCH
ENABLE
O0O1O2O3O4O5O6O7
D0
14
1
26
73 84
5 9
11
12 16
13
15
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
D
GQ
D1
D
GQ
D2
D
GQ
D3
D
GQ
D4
D
GQ
D5
D
GQ
D6
D
GQ
D7
17 18
19
O0O1O2O3O4O5O6O7
265 9 12 1615 19
D0
1473 84 13
D1D2D3D4D5D6D7
17 18
1
11
DCP
QQ DCP
QQ DCP
QQ DCP
QQ DCP
QQ DCP
QQ DCP
QQ
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.4 3.1 VVCC = MIN, IOH = MAX, VIN = VIH
or VIL per T ruth Table
VO
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 12 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
tp
u
t
LOW
Voltage
0.35 0.5 V IOL = 24 mA
V
IN =
V
IL
or
V
IH
per T ruth Table
IOZH Output Off Current HIGH 20 µA VCC = MAX, VOUT = 2.7 V
IOZL Output Off Current LOW –20 µA VCC = MAX, VOUT = 0.4 V
I
In
p
ut HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
I
IH
Inp
u
t
HIGH
C
u
rrent
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –30 –130 mA VCC = MAX
ICC Power Supply Current 40 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
SN74LS373 SN74LS374
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4
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
LS373 LS374
Symbol Parameter Min Typ Max Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 35 50 MHz
tPLH
tPHL Propagation Delay,
Data to Output 12
12 18
18 ns
C=45
p
F
tPLH
tPHL Clock or Enable
to Output 20
18 30
30 15
19 28
28 ns
C
L =
45
pF
,
RL = 667 Ω
tPZH
tPZL Output Enable T ime 15
25 28
36 20
21 28
28 ns
tPHZ
tPLZ Output Disable T ime 12
15 20
25 12
15 20
25 ns CL = 5.0 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
LS373 LS374
Symbol Parameter Min Max Min Max Unit
tWClock Pulse Width 15 15 ns
tsSetup T ime 5.0 20 ns
thHold T ime 20 0 ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to LE transition from HIGH-to-LOW in order to
be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the LE transition from HIGH-to-LOW that the
logic level must be maintained at the input in order to ensure
continued recognition.
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5
SN74LS373
AC WAVEFORMS
Figure 1.
tWtW
LE 1.3 V
OUTPUT
Dn
tsth
tPLH tPHL
Figure 2. Figure 3.
1.3 V
1.3 V 1.3 V
OE
VOUT
OE
VOUT
tPHZ
1.3 V 1.3 V
tPZL tPLZ
VOL
1.3 V VOH
0.5 V
tPZH
1.3 V 1.3 V
0.5 V
SW2CL*
5.0 kΩ
SW1
VCC
RL
TO OUTPUT
UNDER TEST
Figure 4.
* Includes Jig and Probe Capacitance.
AC LOAD CIRCUIT
SWITCH POSITIONS
Closed
Open
Closed
Closed
Open
Closed
Closed
Closed
tPZH
tPZL
tPLZ
tPHZ
SW2SW1SYMBOL
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6
SN74LS374
AC WAVEFORMS
OE
VOUT
1.3 V 1.3 V
tPZL tPLZ
VOL
1.3 V ≈1.3 V
0.5 V
SW2CL*
5.0 kΩ
SW1
VCC
RL
TO OUTPUT
UNDER TEST
* Includes Jig and Probe Capacitance.
AC LOAD CIRCUIT
CP
Dn
OUTPUT
tPLH
tWHt
WL
1.3 V 1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
tsth
tPHL
Figure 5.
1.3 V
1.3 V 1.3 V
OE
VOUT
tPHZ ≥VOH
0.5 V
tPZH
≈1.3 V
Figure 6.
Figure 7.
Figure 8.
SWITCH POSITIONS
Closed
Open
Closed
Closed
Open
Closed
Closed
Closed
tPZH
tPZL
tPLZ
tPHZ
SW2SW1SYMBOL
SN74LS373 SN74LS374
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7
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J20 PL M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A25.66 27.171.010 1.070
B6.10 6.600.240 0.260
C3.81 4.570.150 0.180
D0.39 0.550.015 0.022
G2.54 BSC0.100 BSC
J0.21 0.380.008 0.015
K2.80 3.550.110 0.140
L7.62 BSC0.300 BSC
M0 15 0 15
N0.51 1.010.020 0.040
____
E1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F1.27 BSC0.050 BSC
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
q
hX 45
_
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
__
SN74LS373 SN74LS374
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8
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SN74LS373/D
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