Features * High-performance, Low-power Atmel(R) AVR(R) 8-bit Microcontroller * Advanced RISC Architecture * * * * * * * * - 131 Powerful Instructions - Most Single-clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 20 MIPS Throughput at 20 MHz - On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments - 16K/32K/64K Bytes of In-System Self-programmable Flash program memory - 512B/1K/2K Bytes EEPROM - 1K/2K/4K Bytes Internal SRAM - Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM - Data retention: 20 years at 85C/100 years at 25C(1) - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features - Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Six PWM Channels - 8-channel, 10-bit ADC Differential mode with selectable gain at 1x, 10x or 200x - Byte-oriented Two-wire Serial Interface - Two Programmable Serial USART - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator - Interrupt and Wake-up on Pin Change Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages - 32 Programmable I/O Lines - 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF (ATmega164P/324P/644P) - 44-pad DRQFN (ATmega164P) Operating Voltages - 1.8V - 5.5V for ATmega164P/324P/644PV - 2.7V - 5.5V for ATmega164P/324P/644P Speed Grades - ATmega164P/324P/644PV: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 10 MHz @ 2.7V - 5.5V - ATmega164P/324P/644P: 0 - 10 MHz @ 2.7V - 5.5V, 0 - 20 MHz @ 4.5V - 5.5V Power Consumption at 1 MHz, 1.8V, 25C for ATmega164P/324P/644PV - Active: 0.4 mA - Power-down Mode: 0.1 A - Power-save Mode: 0.6 A (Including 32 kHz RTC) Note: 8-bit Microcontroller with 16K/32K/64K Bytes In-System Programmable Flash ATmega164P/V ATmega324P/V ATmega644P/V Summary 1. See "Data Retention" on page 8. 8011OS-AVR-07/10 1. Pin Configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF Figure 1-1. Pinout ATmega164P/324P/644P PDIP (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 (PCINT29/OC1A) PD5 (PCINT30/OC2B/ICP) PD6 PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16) PD7 (OC2A/PCINT31) PB4 (SS/OC0B/PCINT12) PB3 (AIN1/OC0A/PCINT11) PB2 (AIN0/INT2/PCINT10) PB1 (T1/CLKO/PCINT9) PB0 (XCK0/T0/PCINT8) GND VCC PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) TQFP/VQFN/QFN/MLF (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) (PCINT28/XCK1/OC1B) (PCINT29/OC1A) (PCINT30/OC2B/ICP) (PCINT31/OC2A) PD3 PD4 PD5 PD6 PD7 VCC GND (PCINT16/SCL) PC0 (PCINT17/SDA) PC1 (PCINT18/TCK) PC2 (PCINT19/TMS) PC3 PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) Note: 2 The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P Pinout - DRQFN DRQFN - Pinout ATmega164P Top view Bottom view B2 B14 B3 B4 B1 B14 B2 A16 B13 A16 B13 B3 A15 B12 A15 Table 1-1. A4 B4 A14 B11 A13 B11 A13 B5 A5 A7 B6 A6 A12 B10 A12 B9 A11 B10 B8 A10 B7 A9 A8 A7 B6 A6 A3 B12 A14 A5 B5 A2 B7 A4 A1 B15 A17 A8 A3 A18 B8 A2 A24 B20 B15 A17 A23 B19 A22 A18 B1 B18 A21 B17 A20 B16 A19 A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24 A1 A9 Figure 1-2. A11 B9 A10 1.2 DRQFN - Pinout ATmega164P/324P A1 PB5 A7 PD3 A13 PC4 A19 PA3 B1 PB6 B6 PD4 B11 PC5 B16 PA2 A2 PB7 A8 PD5 A14 PC6 A20 PA1 B2 RESET B7 PD6 B12 PC7 B17 PA0 A3 VCC A9 PD7 A15 AVCC A21 VCC B3 GND B8 VCC B13 GND B18 GND A4 XTAL2 A10 GND A16 AREF A22 PB0 B4 XTAL1 B9 PC0 B14 PA7 B19 PB1 A5 PD0 A11 PC1 A17 PA6 A23 PB2 B5 PD1 B10 PC2 B15 PA5 B20 PB3 A6 PD2 A12 PC3 A18 PA4 A24 PB4 3 8011OS-AVR-07/10 2. Overview The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PA7..0 PB7..0 VCC Power Supervision POR / BOD & RESET RESET GND PORT A (8) PORT B (8) Watchdog Timer Analog Comparator A/D Converter Watchdog Oscillator USART 0 XTAL1 Oscillator Circuits / Clock Generation Internal Bandgap reference EEPROM SPI XTAL2 8 bit T/C 0 CPU JTAG/OCD TWI 16 bit T/C 1 FLASH PORT C (8) TOSC2/PC7 TOSC1/PC6 PC5..0 SRAM 8 bit T/C 2 USART 1 PORT D (8) PD7..0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 4 ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P The ATmega164P/324P/644P provides the following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1K/2K/4K bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Powersave mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel's high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega164P/324P/644P AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 Comparison Between ATmega164P, ATmega324P and ATmega644P Table 2-1. Differences between ATmega164P and ATmega644P Device Flash EEPROM RAM ATmega164P 16 Kbyte 512 Bytes 1 Kbyte ATmega324P 32 Kbyte 1 Kbyte 2 Kbyte ATmega644P 64 Kbyte 2 Kbyte 4 Kbyte 5 8011OS-AVR-07/10 2.3 2.3.1 Pin Descriptions VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega164P/324P/644P as listed on page 81. 2.3.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega164P/324P/644P as listed on page 83. 2.3.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of the JTAG interface, along with special features of the ATmega164P/324P/644P as listed on page 86. 2.3.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega164P/324P/644P as listed on page 88. 6 ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P 2.3.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in "System and Reset Characteristics" on page 332. Shorter pulses are not guaranteed to generate a reset. 2.3.8 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.9 XTAL2 Output from the inverting Oscillator amplifier. 2.3.10 AVCC AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.11 AREF This is the analog reference pin for the Analog-to-digital Converter. 7 8011OS-AVR-07/10 3. About 3.1 Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 3.2 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. The code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C. 8 ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P 4. Register Summary Address (0xFF) Bit 7 Bit 6 Bit 5 Bit 4 Reserved Name - - - - Bit 3 Bit 2 Bit 1 Bit 0 - - - (0xFE) Reserved - - - - - - - - (0xFD) Reserved - - - - - - - - (0xFC) Reserved - - - - - - - - (0xFB) Reserved - - - - - - - (0xFA) Reserved - - - - - - - (0xF9) Reserved - - - - - - - (0xF8) Reserved - - - - - - - - (0xF7) Reserved - - - - - - - - (0xF6) Reserved - - - - - - - - (0xF5) Reserved - - - - - - - (0xF4) Reserved - - - - - - - - (0xF3) Reserved - - - - - - - - (0xF2) Reserved - - - - - - - - (0xF1) Reserved - - - - - - - (0xF0) Reserved - - - - - - - (0xEF) Reserved - - - - - - - (0xEE) Reserved - - - - - - - - (0xED) Reserved - - - - - - - - (0xEC) Reserved - - - - - - - - (0xEB) Reserved - - - - - - - (0xEA) Reserved - - - - - - - - (0xE9) Reserved - - - - - - - - (0xE8) Reserved - - - - - - - - (0xE7) Reserved - - - - - - - (0xE6) Reserved - - - - - - - - (0xE5) Reserved - - - - - - - - (0xE4) Reserved - - - - - - - - (0xE3) Reserved - - - - - - - (0xE2) Reserved - - - - - - - (0xE1) Reserved - - - - - - - (0xE0) Reserved - - - - - - - (0xDF) Reserved - - - - - - - - (0xDE) Reserved - - - - - - - - (0xDD) Reserved - - - - - - - - (0xDC) Reserved - - - - - - - (0xDB) Reserved - - - - - - - - (0xDA) Reserved - - - - - - - - (0xD9) Reserved - - - - - - - - (0xD8) Reserved - - - - - - - - (0xD7) Reserved - - - - - - - - (0xD6) Reserved - - - - - - - - (0xD5) Reserved - - - - - - - - (0xD4) Reserved - - - - - - - - (0xD3) Reserved - - - - - - - - (0xD2) Reserved - - - - - - - - (0xD1) Reserved - - - - - - - - (0xD0) Reserved - - - - - - - - (0xCF) Reserved - - - - - - - - (0xCE) UDR1 (0xCD) UBRR1H - - - UBRR1L (0xCB) Reserved - - (0xCA) UCSR1C UMSEL11 UMSEL10 - (0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 (0xC8) UCSR1A RXC1 TXC1 UDRE1 - - - (0xC7) Reserved UDR0 (0xC5) UBRR0H - - USART1 I/O Data Register (0xCC) (0xC6) - - 190 USART1 Baud Rate Register High Byte 194/207 USART1 Baud Rate Register Low Byte - 194/207 - - - - - - UDORD1 UCPHA1 UCPOL1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 191/205 FE1 DOR1 UPE1 U2X1 MPCM1 190/205 - - - - - USART0 I/O Data Register - - - (0xC4) UBRR0L (0xC3) Reserved - - (0xC2) UCSR0C UMSEL01 UMSEL00 - (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 Page - 190 USART0 Baud Rate Register High Byte 194/207 USART0 Baud Rate Register Low Byte - 192/206 194/207 - - - - - - UDORD0 UCPHA0 UCPOL0 192/206 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 191/205 9 8011OS-AVR-07/10 Address (0xC0) 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page UCSR0A Name RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 190/205 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 236 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 235 2-wire Serial Interface Data Register 236 233 235 (0xB8) TWBR (0xB7) Reserved - - - 2-wire Serial Interface Bit Rate Register - - - - - 233 (0xB6) ASSR - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB (0xB5) Reserved - - - - - - - - (0xB4) OCR2B Timer/Counter2 Output Compare Register B (0xB3) OCR2A Timer/Counter2 Output Compare Register A 158 (0xB2) TCNT2 Timer/Counter2 (8 Bit) 157 (0xB1) TCCR2B FOC2A FOC2B - - WGM22 CS22 CS21 CS20 156 (0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 - - WGM21 WGM20 153 (0xAF) Reserved - - - - - - - - 158 158 (0xAE) Reserved - - - - - - - - (0xAD) Reserved - - - - - - - - (0xAC) Reserved - - - - - - - - (0xAB) Reserved - - - - - - - - (0xAA) Reserved - - - - - - - - (0xA9) Reserved - - - - - - - - (0xA8) Reserved - - - - - - - - (0xA7) Reserved - - - - - - - - (0xA6) Reserved - - - - - - - - (0xA5) Reserved - - - - - - - - (0xA4) Reserved - - - - - - - - (0xA3) Reserved - - - - - - - - (0xA2) Reserved - - - - - - - - (0xA1) Reserved - - - - - - - - (0xA0) Reserved - - - - - - - - (0x9F) Reserved - - - - - - - - (0x9E) Reserved - - - - - - - - (0x9D) Reserved - - - - - - - - (0x9C) Reserved - - - - - - - - (0x9B) Reserved - - - - - - - - (0x9A) Reserved - - - - - - - - (0x99) Reserved - - - - - - - - (0x98) Reserved - - - - - - - - (0x97) Reserved - - - - - - - - (0x96) Reserved - - - - - - - - (0x95) Reserved - - - - - - - - (0x94) Reserved - - - - - - - - (0x93) Reserved - - - - - - - - (0x92) Reserved - - - - - - - - (0x91) Reserved - - - - - - - - (0x90) Reserved - - - - - - - - (0x8F) Reserved - - - - - - - - (0x8E) Reserved - - - - - - - - (0x8D) Reserved - - - - - - - - (0x8C) Reserved - - - - - - - - (0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte (0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 137 (0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 137 (0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 137 (0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 138 (0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 138 (0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 137 137 (0x84) TCNT1L (0x83) Reserved - - - Timer/Counter1 - Counter Register Low Byte (0x82) TCCR1C FOC1A FOC1B - - - - - - 136 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 135 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 133 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 240 - - 137 - - - ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P Address Name (0x7E) DIDR0 (0x7D) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 260 - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 256 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 239 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH ADC Data Register High byte 258 259 (0x78) ADCL (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) PCMSK3 PCINT31 PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 (0x72) Reserved - - - - - - - - (0x71) Reserved - - - - - - - - (0x70) TIMSK2 - - - - - OCIE2B OCIE2A TOIE2 159 (0x6F) TIMSK1 - - ICIE1 - - OCIE1B OCIE1A TOIE1 138 (0x6E) TIMSK0 - - - - - OCIE0B OCIE0A TOIE0 110 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 71 (0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 71 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 72 (0x6A) Reserved - - - - - - - - (0x69) EICRA - - ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 68 (0x68) PCICR - - - - PCIE3 PCIE2 PCIE1 PCIE0 70 (0x67) Reserved - - - - - - - - (0x66) OSCCAL (0x65) Reserved (0x64) PRR (0x63) Reserved (0x62) Reserved (0x61) CLKPR (0x60) WDTCSR ADC Data Register Low byte 259 Oscillator Calibration Register 71 41 - - - - - - - - PRTWI PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI PRUSART0 PRADC - - - - - - - - 49 - - - - - - - - CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 41 WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 60 0x3F (0x5F) SREG I T H S V N Z C 11 0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 12 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12 0x3C (0x5C) Reserved - - - - - - - - 0x3B (0x5B) RAMPZ - - - - - - - RAMPZ0 0x3A (0x5A) Reserved - - - - - - - - 0x39 (0x59) Reserved - - - - - - - - 0x38 (0x58) Reserved - - - - - - - - 0x37 (0x57) SPMCSR SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN 0x36 (0x56) Reserved - - - - - - - - 0x35 (0x55) MCUCR JTD BODS BODSE PUD - - IVSEL IVCE 92/276 0x34 (0x54) MCUSR - - - JTRF WDRF BORF EXTRF PORF 59/276 48 0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE 0x32 (0x52) Reserved - - - - - - - - 0x31 (0x51) OCDR 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 - - - - - - - - On-Chip Debug Register 15 292 266 258 0x2F (0x4F) Reserved 0x2E (0x4E) SPDR 0x2D (0x4D) SPSR SPIF0 WCOL0 - - - - - SPI2X0 170 0x2C (0x4C) SPCR SPIE0 SPE0 DORD0 MSTR0 CPOL0 CPHA0 SPR01 SPR00 169 0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 0x29 (0x49) Reserved 0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B 0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 109 0x26 (0x46) TCNT0 Timer/Counter0 (8 Bit) 109 0x25 (0x45) TCCR0B FOC0A FOC0B - - WGM02 CS02 CS01 CS00 108 0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 - - WGM01 WGM00 110 0x23 (0x43) GTCCR TSM - - - - - PSRASY PSR5SYNC 160 0x22 (0x42) EEARH - - - - 0x21 (0x41) EEARL 0x20 (0x40) EEDR 0x1F (0x3F) EECR 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK SPI 0 Data Register - - - - 171 29 29 - - - 110 EEPROM Address Register High Byte 24 EEPROM Address Register Low Byte 24 EEPROM Data Register - - EEPM1 - - - EEPM0 EERIE 24 EEMPE EEPE EERE 24 INT2 INT1 INT0 69 General Purpose I/O Register 0 - - 29 11 8011OS-AVR-07/10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1C (0x3C) Address EIFR Name - - - - - INTF2 INTF1 INTF0 Page 69 0x1B (0x3B) PCIFR - - - - PCIF3 PCIF2 PCIF1 PCIF0 70 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 160 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 139 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 110 0x14 (0x34) Reserved - - - - - - - - 0x13 (0x33) Reserved - - - - - - - - 0x12 (0x32) Reserved - - - - - - - - 0x11 (0x31) Reserved - - - - - - - - 0x10 (0x30) Reserved - - - - - - - - 0x0F (0x2F) Reserved - - - - - - - - 0x0E (0x2E) Reserved - - - - - - - - 0x0D (0x2D) Reserved - - - - - - - - 0x0C (0x2C) Reserved - - - - - - - - 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 93 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 93 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 93 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 93 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 93 0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 93 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 92 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 92 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 92 0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 92 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 92 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 92 Notes: 12 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used. ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P 5. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd * Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd Rd * K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 1 COM Rd One's Complement Rd 0xFF - Rd Z,C,N,V 1 NEG Rd Two's Complement Rd 0x00 - Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 Z,C 2 Z,C 2 Z,C 2 2 FMULS Rd, Rr Fractional Multiply Signed FMULSU Rd, Rr Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS RJMP k IJMP Relative Jump PC PC + k + 1 None Indirect Jump to (Z) PC Z None 2 JMP k Direct Jump PC k None 3 RCALL k Relative Subroutine Call PC PC + k + 1 None 4 Indirect Call to (Z) PC Z None 4 Direct Subroutine Call PC k None 5 RET Subroutine Return PC STACK None 5 RETI Interrupt Return PC STACK I 5 ICALL CALL k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 1/2/3 1 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 13 8011OS-AVR-07/10 Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C1 C 1 CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I0 I 1 SES Set Signed Test Flag S1 S 1 CLS Clear Signed Test Flag S0 S 1 SEV Set Twos Complement Overflow. V1 V 1 CLV Clear Twos Complement Overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H1 H0 H H 1 1 Rd Rr Rd+1:Rd Rr+1:Rr None 1 None 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd K None LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 Extended Load Program Memory R0 (RAMPZ:Z) None 3 ELPM Rd, Z Extended Load Program Memory Rd (Z) None 3 ELPM Rd, Z+ Extended Load Program Memory Rd (RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1 None 3 ELPM 14 ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P Mnemonics Operands SPM Description Operation Flags #Clocks Store Program Memory (Z) R1:R0 None - Rd P None 1 IN Rd, P In Port OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A 15 8011OS-AVR-07/10 6. Ordering Information 6.1 ATmega164P Speed (MHz)(3) Power Supply Package(1) Ordering Code (2) 10 20 Notes: 1.8V - 5.5V ATmega164PV-10AU ATmega164PV-10PU(2) ATmega164PV-10MU(2) 44A 40P6 44M1 2.7V - 5.5V ATmega164P-20AU(2) ATmega164P-20PU(2) ATmega164P-20MU(2) 44A 40P6 44M1 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed Grades" on page 329. Package Type 44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 16 ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P 6.2 ATmega324P Speed (MHz)(3) Power Supply Package(1) Ordering Code (2) 10 1.8V - 5.5V ATmega324PV-10AU ATmega324PV-10PU(2) ATmega324PV-10MU(2) (2) 20 Notes: 2.7V - 5.5V ATmega324P-20AU ATmega324P-20PU(2) ATmega324P-20MU(2) 44A 40P6 44M1 44A 40P6 44M1 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed Grades" on page 329. Package Type 44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0 mm Body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 17 8011OS-AVR-07/10 6.3 ATmega644P Speed (MHz)(3) Power Supply Package(1) Ordering Code (2) 10 1.8V - 5.5V ATmega644PV-10AU ATmega644PV-10PU(2) ATmega644PV-10MU(2) (2) 20 Notes: 2.7V - 5.5V ATmega644P-20AU ATmega644P-20PU(2) ATmega644P-20MU(2) 44A 40P6 44M1 44A 40P6 44M1 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see "Speed Grades" on page 329. Package Type 44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN) 18 ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P 7. Packaging Information 7.1 44A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0~7 A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 B 0.30 - 0.45 C 0.09 - 0.20 L 0.45 - 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 44A B 19 8011OS-AVR-07/10 7.2 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0 ~ 15 C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A - - 4.826 A1 0.381 - - SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). D 52.070 - 52.578 E 15.240 - 15.875 E1 13.462 - 13.970 B 0.356 - 0.559 B1 1.041 - 1.651 L 3.048 - 3.556 C 0.203 - 0.381 eB 15.494 - 17.526 e NOTE Note 2 Note 2 2.540 TYP 09/28/01 R 20 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P 7.3 44M1 C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT/2 A19 eR A24 B20 B16 A1 A18 COMMON DIMENSIONS (Unit of Measure = mm) B1 B15 b R0.20 0.40 D2 eT SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.30 C B5 B11 A6 A13 B10 B6 A12 L 0.20 REF D 4.90 5.00 5.10 D2 2.55 2.60 2.65 E 4.90 5.00 5.10 E2 2.55 2.60 2.65 eT - 0.70 - A7 L E2 BOTTOM VIEW Note: NOTE 1. The terminal #1 ID is a Laser-marked Feature. Package Drawing Contact: packagedrawings@atmel.com L eR - 0.40 - K 0.45 - - L 0.30 0.35 0.40 y 0.00 - 0.075 TITLE 44MC, 44QFN (2-Row Staggered), 5 x 5 x 1.00 mm Body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No Lead Package 9/13/07 DRAWING NO. REV. 44MC A 21 8011OS-AVR-07/10 8. Errata 8.1 8.1.1 ATmega164P Rev. A No known Errata. 8.2 8.2.1 ATmega324P Rev. A No known Errata. 8.3 8.3.1 ATmega644P Rev. A Not sampled. 8.3.2 Rev. B No known Errata. 22 ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P 9. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 9.1 Rev. 8011O- 07/10 1. 2. 9.2 Rev. 8011N- 10/09 1. 2. 9.3 Updated Section 6.5 "Low Frequency Crystal Oscillator" on page 34 Added Table 6-8 on page 34. Rev. 8011M- 08/09 1. 2. 3. 4. 5. 6. 9.4 Corrected use of comma in formula for Rp in Table 25-10, "2-wire Serial Bus Requirements," on page 333 Updated document according to Atmel standard Updated "Features" on page 1. Removed VFBGA - pinout from "Pin Configurations" on page 2. Updated "System Control and Reset" on page 50. Updated Input Hysteresis Unit (V) in the "Typical Characteristics". Updated "Ordering Information" on page 420. Removed 44MC and 49C2 packages. Updated "Packaging Information" on page 423. Rev. 8011L- 02/09 1. 2. 3. 4. Updated "Features" on page 1 by inserting a table note 1. Merged Sections 3.1, 3.2 and 3.3 in one section "About" on page 9. Updated the front page by removing "Preliminary". Updated the "DC Characteristics" on page 326 by removing VIL3/VIH3 and VOL3/VOH3 and 5. 6. 6. Updated the table note1 of the Table 25-6 on page 332. Updated "Typical Characteristics" on page 339. Updated "Typical Characteristics" on page 339 the table note 5. 23 8011OS-AVR-07/10 9.5 Rev. 8011K- 09/08 1. 2. 3. 4. 5. 2. 6. 9.6 Rev. 8011J- 09/08 1. 2. 6. 9.7 Updated ATmega644P "Errata" on page 428. Added 49-ball VFBGA pinout for ATmega164P/324P in "Pinout - VFBGA" on page 4. Added 49-ball VFBGA (49C2) to "Packaging Information" on page 425. Rev. 8011I- 05/08 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 2. 6. 24 Updated "Features" on page 1, "Pin Configurations" on page 2 and "Ordering Information" on page 15 according to the updated 44M1 package drawing. Updated VOL in the table of "DC Characteristics" on page 326. Updated tRST and tBOD unites in the table of "System and Reset Characteristics" on page 332. Updated typical values for ATmega324P and ATmega644P in the tables of "DC Characteristics" on page 326. Replaced the package drawing "44M1" on page 426 by a rev H update. Added 49-ball VFBGA pinout for ATmega164P/324P in "Pinout - VFBGA" on page 4. Added 49-ball VFBGA (49C2) to "Packaging Information" on page 19. Updated description in "AVCC" on page 7. Updated "Stack Pointer" on page 14. Updated Data Memory Map addresses, Figure 7-2 on page 21. Updated description of use of external capacitors in "Low Frequency Crystal Oscillator" on page 35. Updated typo in"Alternate Functions of Port C" on page 86. Updated bit description in "TWSR - TWI Status Register" on page 235. Updated typo in "Programming via the JTAG Interface" on page 313. Updated conditions for VOL in the table of "DC Characteristics" on page 326. Updated "External Clock Drive" on page 331. Updated conditions for VINT2 in Table 27-11 (Single Ended channels) in "ADC Characteristics" on page 336. Updated Minimum Reference Voltage in Table 27-12 (Differential channels) in "ADC Characteristics" on page 336. Updated bit bit field typos in "Register Summary" on page 414. Added 49-ball VFBGA pinout for ATmega164P/324P in "Pinout - VFBGA" on page 4. Added 49-ball VFBGA (49C2) to "Packaging Information" on page 425. ATmega164P/324P/644P 8011OS-AVR-07/10 ATmega164P/324P/644P 9.8 Rev. 8011H- 04/08 1. 2. 2. 3. 4. 6. 9.9 Rev. 8011G- 08/07 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 9.10 Updated "Features" on page 1 Added "Data Retention" on page 9. Updated "SPH and SPL - Stack Pointer High and Stack pointer Low" on page 15. LCD reference removed from table note in "Sleep Modes" on page 43. Updated code example in "Bit 0 - IVCE: Interrupt Vector Change Enable" on page 66. Removed reference to External Memory Interface in "Alternate Functions of Port A" on page 81. Updated "Data Reception - The USART Receiver" on page 181. Updated "ADCSRB - ADC Control and Status Register B" on page 239. Updated overview in "ADC - Analog-to-digital Converter" on page 241. Added "ATmega644P Typical Characteristic" on page 389. Updated Figure 28-31 on page 355, Figure 28-32 on page 356,Figure 28-33 on page 356 Updated notes in Table 8-3 on page 33.Table 8-8 on page 36, Table 8-9 on page 37, and Table 8-11 on page 38. Updated Table 13-7 on page 85, Table 13-8 on page 85, Table 13-10 on page 87, Table 13-11 on page 88, Table 13-14 on page 91, Table 27-1 on page 328,Table 27-2 on page 328,Table 27-5 on page 331, Table 27-9 on page 333, and Table 27-12 on page 337 Updated "ATmega324P DC Characteristics" on page 328 and "ATmega644P DC Characteristics" on page 329. Updated Table 27-7 on page 332 and Table 8-13 on page 38. Rev. 8011F- 04/07 1. 9.11 Added 44-pad DRQFN pinout for ATmega164P in "Pinout - DRQFN" on page 3. Added 49-ball VFBGA pinout for ATmega164P/324P in "Pinout - VFBGA" on page 4. Added note to "Address Match Unit" on page 215. Updated ATmega164P "Ordering Information" on page 421. Added 44-lead QFN (44MC) to "Packaging Information" on page 424. Added 49-ball VFBGA (49C2) to "Packaging Information" on page 425. Updated "Watchdog Timer Configuration" on page 60. Rev. 8011E - 04/07 1. 2. Updated "GTCCR - General Timer/Counter Control Register" on page 160. Updated "EECR - The EEPROM Control Register" on page 24. 25 8011OS-AVR-07/10 9.12 Rev. 8011D - 02/07 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 9.13 Rev. 8011C - 10/06 1. 9.14 Updated "Pinout ATmega164P/324P/644P" on page 2. Updated "Power-down Mode" on page 45. Updated note in Table 12-1 on page 69. Updated Table 24-1 on page 273. Updated "Boot Size Configuration(1)" on page 290. Updated VOL limits in "DC Characteristics" on page 326. Updated note 3 and 4 in "DC Characteristics" on page 326. Added note to "ATmega164P DC Characteristics" on page 328. Added note to "ATmega324P DC Characteristics" on page 328. Updated Figure 28-13 on page 346 and Figure 28-60 on page 371. Updated "DC Characteristics" on page 326. Rev. 8011B - 09/06 1. Updated "DC Characteristics" on page 326. ATmega164P/324P/644P 9.15 Rev. 8011A - 08/06 1. Initial revision. 27 8011OS-AVR-07/10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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