intel 27128A 128K (16K x 8) PRODUCTION AND UV ERASABLE PROMs w Fast 150 nsec Access Time m intgligent identifier Mode HMOS* II-E Technology Automated Programming Operations m Low Power m +10% Vcc Tolerance Available 100 mA Maximum Active @ Available in 28-Pin Cerdip Package 40 mA Maximum Standby (See Packaging Spec, Order #231369) The Intel 271284 is a 5V only, 131,072-bit ultraviolet erasable and electrically programmable read-only memo- ry (EPROM). The 27128A is fabricated with Intel's HMOS* |I-E technology which significantly reduces die size and greatly improves the devices performance, reliability and manufacturability. The 27128A is currently available in the CERDIP package providing flexibility in prototyping and R&D environ- ments where reprogrammability is required. The 27128A is available in fast access times including 150 ns (27128A-1). This ensures compatibility with high- performance microprocessors, such as intels 8 MHz 80186 allowing full speed operation without the addition of WAIT states. The 27128A is also directly compatible with the 12 MHz 8051 family. *HMOS is a patented process of Intel Corporation. y DATA OUTPUTS : fee a 0-9, TN, Yoo ttt ttt OE | OUTPUT ENABLE . PGM ] CHIP ENABLE ce PROG LaGIC | OUTPUT BUFFERS Y =F] ecopEer fy GATING Ao-Aig = ADDRESS 4 >} x Reus ~ 131,072-BIT | DECODER | CELL MATRIX P] > 230849-1 Figure 1. Block Diagram October 1990 5-28 Order Number: 230849-009ntel 27128A Pin Names Ag-Aig | ADDRESSES Ce CHIP ENABLE oe OUTPUT ENABLE Qo-07 | OUTPUTS PGM | PROGRAM NC NO INTERNAL CONNECT 2764A 2764A 27512 | 27256 27128A 27256 | 27512 o7cs12 | 27c28 | 27084 | 272A | 2716 2716 | 2732A | 27064) - one | o7csi2 87064 VL 87664 Vep C41 28D Vee At5 Vpp Vep o Voc Vec Voc Ay 2 272 Pw A Aw Ar A743 26a PGM | Ata Ata Az Ay Ar Ay Ay x d. ash a Vec | Veco N.C. Aa Aig As Ag Ae | Ag | As L . Ag | Ag Ag As Ag As As As As As sq 2A . Ag Ag Ag Ag Ag Ag Ag As | Aa | Aa ace 23F An Vep | Any | An | And | Ant Ag Ag Ag Ag Ag 437 22 OE OE | CE/Vpp| OF OE | OE/Vpp Ag Ag Ag Ag Aa Ags 21P Ato Ato | Ato Ato Ato Ato Ay Ay Ay AY Ay 49 20) cE cE cE acice | acice CE Ao Ao Ag Ao Ao Ap C4 10 19Flo, O7 O7 O7 07 o7 Oo Oo Oo Oo Oo OC t1 1895) Og O6 Og O65 O68 O6 0; oO; Oy oO, 0; 0, C12 17D 05 Og Os Os Os Os 02 O2 O2 O2 O2 02 C413 16D 0, O4 O4 O4 O4 O4 GND GND | GND { GND | GND cNDCY 14 150, Og 03 Og O3 03 230849-2 NOTE: Intet Universal SiteCompatible EPROM Pin Configurations are Shown in the Blocks Adjacent to the 27128A Pins Figure 2. Cerdip(D) DIP Pin Configuration 5-29intel 27128A EXTENDED TEMPERATURE (EXPRESS) EPROMS The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match sys- tem applications. EXPRESS EPROM products are EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITIONS Type | Operating Temperature | Burn-in 125C (hr) Q OC to + 70C 168 +8 T 40C to + 85C None L 40C to + 85C 168 +8 READ OPERATION available with 168 +8 hour, 125C dynamic burn-in using Intels standard bias configuration. This pro- cess exceeds or meets most industry specifications of burn-in. The standard EXPRESS EPROM operat- ing temperature range is 0C to 70C. Extended op- erating temperature range ( 40C to + 85C) EX- PRESS products are available. Like all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AQL. This may allow the user to reduce or eliminate incoming inspection testing. EXPRESS OPTIONS 27128A Versions Packaging Options Speed Versions Cerdip -20 T,LQ DC CHARACTERISTICS Electrical Parameters of Express EPROM Products are identical to standard EPROM parameters except for. Symbol Parameter 1D27128A, LD27128A Test Conditions Min Max isp Voc Standby Current (mA) 50 CE = Vin, OE = Vit loca) Vcc Active Current (mA) 125 OE = CE= Vi Vcc Active Current 100 OE = CE = Vit. Vep = Voc at High Temperature (mA) Tambient = 85C NOTE: 1. The maximum current value is with Outputs Og to O7 unloaded. XL Vpp C41 28) Vcc Ay2 2 2712 PGM 4,093 26D As 30 ys A,Ch4 25 Ag . 4,5 24D Ag Ao | | 4,6 23 Ain 4,047 22) o TI r ade 271284 F Ato Ay Arts 20 CE, Vor : Yecq Ao tJ 10 19 Dewe@ 07 Aas Og downed 11 ishewes 0 230849-11 0 R R 6 Binary Sequence from Ag to A13 O, pee 12 17 pw Os 0p wT] 13 16 ae O, Vss CJ 14 15 ew 0; 230849-10 OE =+5V R=1kKN Voo= +5V vpp = +5V Vss = GND CE = GND Burn-in Bias and Timing Diagrams 5-30intel 27128A ABSOLUTE MAXIMUM RATINGS* Operating Temperature During Read........... 0. cece eee eee 0C to + 70C Temperature Under Bias......... 10C to +80C Storage Temperature ..... eee ~ 65C to + 125C All Input or Output Voltages with Respect to Ground........... 0.6V to +6.25V Voltage on Ag with Respect to Ground ........... 0.6V to + 13.5V Vpp Supply Voltage with Respect to Ground During Programming ....0.6V to + 14V Voc Supply Voltage with Respect to Ground ........ 0.6V to +7.0V READ OPERATION DC CHARACTERISTICS orc < Ta < +70C NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. Symbol Parameter Notes - Limits Units Conditions Min Typ) Max lu Input Load Current 10 pA Vin = OV to Voc ILo Output Leakage Current 10 pA Vout = OV to Voc lppy Vpp Current Read 2 5 mA Vpp=5.5V isp Voc Current Standby 40 mA CE=Vin lect Vec Current Active 2 100 mA CE=OE=Vi_ Vit Input Low Voltage -01 +0.8 Vv Vin Input High Voitage 2.0 Voco+1 v VoL Output Low Voltage 0.45 v loL=2.1 mA VoH Output High Voltage 2.4 v lon = 400 pA Vpp Vpp Read Voltage 2 3.8 Voc Vv Voc = 5.0V +0.25 AC CHARACTERISTICS orc < Ta < +70C Veco + 5% 27128A-1 27128A-2 27128A Versions(5) Notes Unit Voc + 10% 27128A-20 27128A-25 Symbol Characteristics Min Max Min Max Min Max tacc Address to Output Delay 150 200 250 ns toe CE to Output Delay 150 200 250 ns toe OE to Output Delay 65 75 100 ns tor OE High to Output Float 55 0 55 0 60 ns {oH Output Hold from___ 0 0 ns Addresses CE or OE Whichever Occurred First NOTES: 1. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2, Vpp may be connected directly to Vcc except during programming. The supply current would then be the sum of icc and Ippy. The maximum current value is with Outputs Og to O7 unloaded. 3. Typical values are for Ta = 25C and nominal supply voltages. 4. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer drivensee timing diagram. 5-3127128A CAPACITANCE(2) T, = 25C, f = 1MHz Symbol Parameter Typ() | Max | Unit | Conditions Cin Input Capacitance 4 6 pF Vin = OV Cout Output Capacitance 8 12 pF Vout = 0V AC TESTING INPUT/OUTPUT WAVEFORM AC TESTING LOAD CIRCUIT 1.3V 1N914 2.4 5 INPUT 20 > test POINTS << 70 ourpur 0.8 a 0.8 3.3K0 0.45 *Y DEVICE our _ UNDER 230849-3 TEST CL= 100 pF A.C. testing inputs are driven at 2.4V for a Logic 1 and 0.45V for a Logic 0. Timing measurements are made at 2.0V for a ic 1 and 0. ic 0. = Logic and 0.8V for a Lagic 0 ,, = 100 pF 230849-4 CG, Includes Jig Capacitance AC WAVEFORMS Vin y- eeee ADDRESSES ADDRESS vi N wees Vi reel CE Vin eeee + tog 1] Vif OE Vin mas 8 08 ft jt tog "1 _ >| t-_ tac -$_____ toy !2! < p= @e8e Ll 5 HIGH Z HIGH Z output < \ \ . VALID OUTPUT ~=~<eees / 230849-5 NOTES: 1. Typical values are for Ta = 25C and nominal supply voitages. 2. This parameter is only sampled and is not 100% tested. 3. OE may be delayed up to tcetoe after the falling edge of CE without impact on tog. 5-32intel 27128A DEVICE OPERATION The modes of operation of the 27128A are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vpp and 12V on Ag for inteligent tdentifier. Table 1. Modes Selection Mode Notes | CE | OE | PGM | Ag | Ao | Vpp | Vcc | Outputs Read 1 VIL Vit Vin x x Veco | 5.0V Dout Output Disable Vil Vin | Vin | X | X | Voc | 5.0v | Highz Standby Ving X xX X Xx Voc | 5.0V High Z Programming 4 Vit Vin Vit X Xx Vpp 6.0V Din Program Verify 4 ViL Vit Vin xX Xx Vpp 6.0V DoutT Program Inhibit 4 ViH X Xx X X Vpp | 6.0V High Z intgligent | Manufacturer 2,3 VIL Vit Vin Vu Vit Voc | 5.0V 89H identifier Device 23 | Ve | Vi | Vm | Va | Vin | Voc | 5.0V 89H NOTES: 1. X can be Vit or Vin 2. Vy = 12.0V +0.5V 3. Ay-Ag, Aio-At2 = ViL 4. See Table 2 for Voc and Vpp voltages. Read Mode The 27128A has two control functions, both of which must be iogically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data from the output pins, independent of de- vice selection. Assuming that addresses are stable, the address access time (tacc) is equal to the delay from CE to output (tce). Data is available at the out- puts after a delay of tog from the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacc-tog. Standby Mode EPROMs can be placed in standby mode which re- duces the maximum current of the device by apply- ing a TTL-high signal to the CE input. When in stand- by mode, the outputs are in a high impedance state, independent of the OE input. Two Line Output Control Because EPROMs are usually used in larger memo- ry arrays, Intel has provided 2 control lines which accommodate this multiple memory connection. The two control lines allow for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur 5-33 To use these two control lines most efficiently, CE should be decoded and used as the primary device selecting function, while OE should be made a com- mon connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are active only when data is desired from a particular memory device. SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- quire careful decoupling of the devices. The supply current, Icc, has three segments that are of interest to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enable. The magnitude of these tran- sient current peaks is dependent on the output ca- pacitive and inductive loading of the device. The as- sociated transient voltage peaks can be suppressed by complying with Intels Two-Line Control, and by properly selected decoupling capacitors. It is recom- mended that a 0.1 pF ceramic capacitor be used on every device between Vcc and GND. This should be a high frequency capacitor for low inherent induc- tance and should be placed as close to the device as possible. In addition, a 4.7 uF bulk electrolytic capacitor should be used between Vcc and GND for every eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effect of PC board-traces.ntel 27128A PROGRAMMING MODES Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, and after each erasure, all bits of the EPROM are in the 1 state. Data is introduced by selectively programming Os into the desired bit lo- cations. Although only Os will be programmed, both ts and Os can be present in the data word. The only way to change a 0 to a 1 is by ultravio- let light erasure. The device is in the programming mode when Vpp is raised to its programming voltage (See Table 2) and CE and PGM are both at TTL low. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. Program Inhibit Programming of multiple EPROMS in paralle! with different data is easily accomplished by using the Program Inhibit mode. A high-level CE or PGM input inhibits the other devices from being programmed. Except for CE, all like inputs (including OE) of the parallel EPROMs may be common. A TTL low-level pulse applied to the PGM input with Vpp at its pro- gramming voltage and CE at TTL-Low will program the selected device. Program Verify A verify should be performed on the programmed bits to determine that they have been correctly pro- grammed. The verify is performed with OE at Vj_, CE at Vit, PGM at Vi and Vpp and Vcc at their pro- gramming voltages. inteligent Identifier Mode The inteligent Identifier Mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose 5-34 of automatically matching the device to be pro- grammed with its corresponding programming algo- rithm. This mode is functional in the 25C +5C am- bient temperature range that is required when pro- gramming the device. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line Ag of the EPROM. Two identifier bytes may then be se- quenced from the device outputs by toggling ad- dress line Ag from Vj. to Viy. All other address lines must be held at Vi_ during the intgligent Identifier Mode. Byte 0 (Ap = Vi_) represents the manufacturer code and byte 1 (Ap = Vix) the device identifier code. These two identifier bytes are given in Table 1. ERASURE CHARACTERISTICS The erasure characteristics are such that erasure begins to occur upon exposure to light with wave- lengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range. Data shows that constant expo- sure to room level fluorescent lighting could erase the EPROM in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the device is to be ex- posed to these types of lighting conditions for ex- tended periods of time, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity < exposure time) for erasure should be a minimum of 15 Wsec/cm?. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 4z.W/cm2 power rat- ing. The EPROM should be placed within 1 inch of the lamp tubes during erasure. The maximum inte- grated dose an EPROM can be exposed to without damage is 7258 Wsec/cm2 (1 week @ 12000 ,W/ cm?2). Exposure of the device to high intensity UV light for longer periods may cause permanent dam- age.27128A START ADOR = FIRST LOCATION Voc = 6.0V Vpp = 12.5V r {PROGRAM ONE 1 msec PULSE INCREMENT ADDR COMPARE ALL BYTES TO ORIGINAL DEVICE PASSED DEVICE FAILED DEVICE FAILED 230849-6 Figure 3. inteligent Programming Flowchart inteligent Programming Algorithm The intgligent Programming Algorithm, a standard in the industry for the past few years, is required for the 27128A. A flow-chart of the intgligent Program- ming Algorithm is shown in Figure 3. The intgligent Programming Algorithm utilizes two different pulse types: initial and overprogram. The duration of the initial pulse(s) is one millisecond, which will then be followed by a larger overprogram 5-35 pulse of length 3X msec. X is an iteration counter and is equal to the number of the initial one millisec- ond pulses applied to a particular location, before a correct verify occurs. Up to 25 one-millisecond puls- es per byte are provided for before the overprogram pulse is applied. The entire sequence of program pulses and byte verifications is performed at Vcc = 6.0V and Vep = 12.5V. When the inteligent Programming cy- cle has been completed, all bytes should be com- pared to the original data with Vcc = Vpp = 5.0V.intel 27128A DC PROGRAMMING CHARACTERISTICS Ta = 25C +5C Limits Test Conditions Symbol Parameter Min Max Unit (Note 1) Iu) Input Current (All Inputs) 10 pA Vin = Vicor Vin Vit Input Low Level (All Inputs) -0.41 0.8 Vv VIH Input High Level 2.0 Voct1 Vv VoL Output Low Voltage During Verify 0.45 Vv lop = 2.1mA VoH Output High Voitage During Verify 2.4 Vv lon = 400 uA Iocel4) Voc Supply Current (Program & Verify) 100 mA Ippo Vpp Supply Current (Program) 50 mA CE = Vi Vip Ag inteligent Identifier Voltage 11.5 12.5 Vv Vpp inteligent Programming Algorithm 12.0 13.0 v CE = PGM = Vit Voc intgligent Programming Algorithm 5.75 6.25 Vv AC PROGRAMMING CHARACTERISTICS Ta = 25C +5C (See Table 2 for Voc and Vpp voltages.) Symbol Parameter Limits Conditions* Min Typ Max Unit (Note 1) tas Address Setup Time 2 ps toes OE Setup Time 2 ps tos Data Setup Time 2 ps taH Address Hold Time 0 BS tbH Data Hold Time 2 ps torp OE High to Output Float Delay 0 130 ns (Note 3) typs Vpp Setup Time 2 ws tycs Voc Setup Time 2 ps tces CE Setup Time 2 ps tpw PGM Initial Program Pulse Width 0.95 1.0 1.05 ms topw PGM Overprogram Pulse Width 2.85 78.75 ms (Note 2) toe Data Valid from OE 150 ns NOTES: *AC CONDITIONS OF TEST Input Rise and Fail Times (10% to 90%)...... 20 ns Input Pulse Levels .................. 0.45V to 2.4V Input Timing Reference Level ....... 0.8V and 2.0V Output Timing Reference Level ...... 0.8V and 2.0V 5-36 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X. 3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no long- er drivensee timing diagram. 4, The maximum current value is with outputs Og-O7 un- loaded.intel 27128A PROGRAMMING WAVEFORMS PROGRAM VERIFY _} eC ADDRESSES x ADDRESS STABLE Vin < tas > HIGH Z DATA DATA IN STABLE DATA OUT VALIO fc. > we t t DEP os > Lg tH ~ J , aL 12.5V >a. y we Vep 5.0V nd ves pae 9S __pe} 6.0V yy xe Vee ] r 5.0V Vin cE a Viv ve tces__] Vf A a PGM \ Vit tow toes toe Vin _ _____ | forw OE YY Vie 230849-7 NOTES: 1. The input Timing Reference Level is 0.8V for Vi_ and 2V for a Vix. 2. tog and tpgp are characteristics of the device but must be accommodated by the programmer. 3. When programming the 27128A, a 0.1 wF capacitor is required across Vpp and ground to suppress spurious voltage transients which can damage the device. REVISION HISTORY Number Description 009 Removed Plastic Package 5-37