74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 2 -- 6 September 2013 Product data sheet 1. General description The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC74-Q100: CMOS level For 74HCT74-Q100: TTL level Symmetrical output impedance Low power dissipation High noise immunity Balanced propagation delays Specified in compliance with JEDEC standard no. 7A ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC74N-Q100 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HC74D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm SOT762-1 74HCT74D-Q100 74HC74PW-Q100 74HCT74PW-Q100 74HC74BQ-Q100 74HCT74BQ-Q100 4. Functional diagram 4 2 3 1SD 1D 1CP SD Q D Q 4 3 1SD 2SD 2 2 12 3 11 SD 1D D 2D 1CP CP 2CP 1Q Q 2Q 1 5 9 10 FF Q RD 1Q 2Q 6 8 11 12 13 1RD 2RD 1 13 Fig 1. Logic symbol 74HC_HCT74_Q100 Product data sheet Fig 2. 1Q 6 RD S 5 1 C1 1D 6 10 1RD 2SD R 12 S 9 11 C1 2D 2CP SD Q D 2Q 9 CP FF 1D Q 8 2Q 8 RD R 13 mna419 mna418 5 CP FF 4 10 1Q IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 Fig 3. 2RD mna420 Functional diagram (c) NXP B.V. 2013. All rights reserved. 2 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger Q C C C C C C D Q C C RD SD mna421 C CP C Fig 4. Logic diagram for one flip-flop 5. Pinning information 5.1 Pinning terminal 1 index area 1 74HC74-Q100 74HCT74-Q100 14 VCC 1RD 74HC74-Q100 74HCT74-Q100 1D 2 13 2RD 1RD 1 14 VCC 1CP 3 12 2D 1D 2 13 2RD 1SD 4 11 2CP 1CP 3 12 2D 1Q 5 1SD 4 11 2CP 1Q 5 10 2SD 1Q 6 1Q 6 9 2Q GND 7 8 2Q GND(1) 10 2SD 7 8 GND 2Q 9 2Q aaa-004597 Transparent top view aaa-004596 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration for DIP14, SO14 and TSSOP14 74HC_HCT74_Q100 Product data sheet Fig 6. Pin configuration for DHVQFN14 All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 3 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger 5.2 Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW) 1D 2 data input 1CP 3 clock input (LOW-to-HIGH, edge-triggered) 1SD 4 asynchronous set-direct input (active LOW) 1Q 5 output 1Q 6 complement output GND 7 ground (0 V) 2Q 8 complement output 2Q 9 output 2SD 10 asynchronous set-direct input (active LOW) 2CP 11 clock input (LOW-to-HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset-direct input (active LOW) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H [1] H = HIGH voltage level; L = LOW voltage level; X = don't care. Table 4. Function table[1] Input Output nSD nRD nCP nD nQn+1 nQn+1 H H L L H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition; X = don't care. 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 4 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage Min Max Unit 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 25 mA ICC supply current - +100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C DIP14 package [1] - 750 mW SO14, TSSOP14 and DHVQFN14 packages [1] - 500 mW total power dissipation Ptot [1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. For SO14 packages: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage Conditions 74HC74-Q100 74HCT74-Q100 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate - - 625 - - - VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V VCC = 2.0 V ns/V 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Tamb = 40 C to +85 C Min Typ[1] VCC = 2.0 V 1.5 VCC = 4.5 V VCC = 6.0 V Tamb = 40 C to +125 C Unit Max Min Max 1.2 - 1.5 - V 3.15 2.4 - 3.15 - V 4.2 3.2 - 4.2 - V 74HC74-Q100 VIH HIGH-level input voltage 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 5 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger Table 7. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Min VIL LOW-level input voltage VOH VOL Tamb = 40 C to +125 C Typ[1] Max Min Max Unit VCC = 2.0 V - 0.8 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 V IO = 4.0 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 40 - 80 A CI input capacitance 3.5 pF 74HCT74-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V 3.84 4.32 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 4.0 mA - 0.15 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 40 - 80 A ICC additional supply current VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A per input pin; nD, nRD inputs - 70 315 - 343 A per input pin; nSD, nCP input - 80 360 - 392 A CI [1] IO = 4 mA input capacitance 3.5 pF All typical values are measured at Tamb = 25 C. 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 6 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9. Symbol Parameter Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max - 47 220 - 265 ns 74HC74-Q100 tpd propagation delay nCP to nQ, nQ; see Figure 7 [2] VCC = 2.0 V VCC = 4.5 V - 17 44 - 53 ns VCC = 5 V; CL = 15 pF - 14 - - - ns - 14 37 - 45 ns VCC = 2.0 V - 50 250 - 300 ns VCC = 4.5 V - 18 50 - 60 ns VCC = 5 V; CL = 15 pF - 15 - - - ns - 14 43 - 51 ns - 52 250 - 300 ns VCC = 6.0 V nSD to nQ, nQ; see Figure 8 [2] VCC = 6.0 V nRD to nQ, nQ; see Figure 8 [2] VCC = 2.0 V VCC = 4.5 V - 19 50 - 60 ns VCC = 5 V; CL = 15 pF - 16 - - - ns - 15 43 - 51 ns VCC = 6.0 V tt tW transition time pulse width nQ, nQ; see Figure 7 [3] VCC = 2.0 V - 19 95 - 110 ns VCC = 4.5 V - 7 19 - 22 ns VCC = 6.0 V - 6 16 - 19 ns VCC = 2.0 V 100 19 - 120 - ns VCC = 4.5 V 20 7 - 24 - ns VCC = 6.0 V 17 6 - 20 - ns VCC = 2.0 V 100 19 - 120 - ns VCC = 4.5 V 20 7 - 24 - ns VCC = 6.0 V 17 6 - 20 - ns VCC = 2.0 V 40 3 - 45 - ns VCC = 4.5 V 8 1 - 9 - ns VCC = 6.0 V 7 1 - 8 - ns nCP HIGH or LOW; see Figure 7 nSD, nRD LOW; see Figure 8 trec recovery time 74HC_HCT74_Q100 Product data sheet nSD, nRD; see Figure 8 All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 7 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9. Symbol Parameter tsu th fmax set-up time hold time maximum frequency Tamb = 40 C to +85 C Conditions Min Max Min Max VCC = 2.0 V 75 6 - 90 - ns VCC = 4.5 V 15 2 - 18 - ns VCC = 6.0 V 13 2 - 15 - ns VCC = 2.0 V 3 6 - 3 - ns VCC = 4.5 V 3 2 - 3 - ns VCC = 6.0 V 3 2 - 3 - ns VCC = 2.0 V 4.8 23 - 4.0 - MHz VCC = 4.5 V 24 69 - 20 - MHz - 76 - - - MHz 28 82 - 24 - MHz - 24 - - - pF - 18 44 - 53 ns - 15 - - - ns - 23 50 - 60 ns - 18 - - - ns - 24 50 - 60 ns - 18 - - - ns - 7 19 - 22 ns 23 9 - 27 - ns 20 9 - 24 - ns 8 1 - 9 - ns 15 5 - 18 - ns nD to nCP; see Figure 7 nD to nCP; see Figure 7 nCP; see Figure 7 VCC = 5 V; CL = 15 pF VCC = 6.0 V CPD power dissipation capacitance Tamb = 40 C to +125 C Unit Typ[1] CL = 50 pF; f = 1 MHz; VI = GND to VCC [4] nCP to nQ, nQ; see Figure 7 [2] 74HCT74-Q100 tpd propagation delay VCC = 4.5 V VCC = 5 V; CL = 15 pF nSD to nQ, nQ; see Figure 8 [2] VCC = 4.5 V VCC = 5 V; CL = 15 pF nRD to nQ, nQ; see Figure 8 [2] VCC = 4.5 V VCC = 5 V; CL = 15 pF tt tW transition time nQ, nQ; see Figure 7 pulse width nCP HIGH or LOW; see Figure 7 VCC = 4.5 V VCC = 4.5 V [3] nSD, nRD LOW; see Figure 8 VCC = 4.5 V trec tsu recovery time nSD, nRD; see Figure 8 set-up time nD to nCP; see Figure 7 VCC = 4.5 V VCC = 4.5 V 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 8 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9. Symbol Parameter Tamb = 40 C to +85 C Conditions th hold time nD to nCP; see Figure 7 fmax maximum frequency nCP; see Figure 7 VCC = 4.5 V VCC = 4.5 V VCC = 5 V; CL = 15 pF CPD power dissipation capacitance [4] CL = 50 pF; f = 1 MHz; VI = GND to VCC 1.5 V [1] All typical values are measured at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL. Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max 3 3 - 3 - ns 22 54 - 18 - MHz - 59 - - - MHz - 29 - - - pF [3] tt is the same as tTHL and tTLH. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 9 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger 11. Waveforms 9, Q'LQSXW 90 *1' WK WK WVX WVX IPD[ 9, Q&3LQSXW 90 *1' W: W3+/ W3/+ 92+ 90 Q4RXWSXW 92/ W3/+ W3+/ 92+ Q4RXWSXW 90 92/ W7/+ W7+/ DDD Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the maximum frequency (CP) 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 10 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger VI VM nCP input GND t rec VI VM nSD input GND tW tW VI VM nRD input GND t PLH t PHL VOH nQ output VM VOL VOH VM nQ output VOL t PHL t PLH mna423 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. The set (nSD) and reset (nRD) input to output (nQ,nQ) propagation delays, set and reset pulse widths and the nSD, nRD to nCP recovery time Table 9. Measurement points Type Input Output VM VM 74HC74-Q100 0.5VCC 0.5VCC 74HCT74-Q100 1.3 V 1.3 V 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 11 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger tW VI 90 % negative pulse VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 9. Test circuit for measuring switching times Table 10. Test data Type Input VI tr, tf CL RL 74HC74-Q100 VCC 6 ns 15 pF, 50 pF 1 k tPLH, tPHL 74HCT74-Q100 3V 6 ns 15 pF, 50 pF 1 k tPLH, tPHL 74HC_HCT74_Q100 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 Test (c) NXP B.V. 2013. All rights reserved. 12 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 10. Package outline SOT27-1 (DIP14) 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 13 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT108-1 (SO14) 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 14 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 12. Package outline SOT402-1 (TSSOP14) 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 15 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT762-1 (DHVQFN14) 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 16 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT74_Q100 v.2 20130906 Product data sheet - 74HC_HCT74_Q100 v.1 - - Modifications: 74HC_HCT74_Q100 v.1 74HC_HCT74_Q100 Product data sheet * 74HC74N-Q100 (DIP14) added. 20120807 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 17 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT74_Q100 Product data sheet Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 18 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 6 September 2013 (c) NXP B.V. 2013. All rights reserved. 19 of 20 74HC74-Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive edge-trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 September 2013 Document identifier: 74HC_HCT74_Q100