1. General description
The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ out pu ts. Data at the nD-input, th at mee ts the set-u p and ho ld time
requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and
appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit
highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC74-Q100: CMOS level
For 74HCT74-Q100: TTL level
Symmetrical output impedance
Low power dissipation
High noise immunity
Balanced propagation delays
Specified in compliance with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 2 — 6 September 2013 Product data sheet
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 2 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC74N-Q100 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC74D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads; body
width 3.9 mm SOT108-1
74HCT74D-Q100
74HC74PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package;
14 leads; body width 4.4 m m SOT402-1
74HCT74PW-Q100
74HC74BQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no
leads; 14 terminals; body 2.5 30.85 mm
SOT762-1
74HCT74BQ-Q100
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram
mna418
RD
FF
SD
410
Q1Q
2Q
1Q
2Q
5
9
2
12
3
11 6
8
Q
1SD
CP
2CP
1CP
2D
1D D
2SD
113
1RD 2RD
mna419
6
3
2C1
4S
1D
1R
5
8
11
12 C1
10 S
1D
13 R
9
RD
FF
SD
4
Q1Q
1Q
5
2
3
6
Q
1SD
CP
1CP
1D D
11RD
mna420
RD
FF
SD
10
Q2Q
2Q
9
12
11
8
Q
2SD
CP
2CP
2D D
13 2RD
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 3 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
5. Pinning information
5.1 Pinning
Fig 4. Logic diagram for one flip-flop
mna421
SD
CP
RD
D
C
C
Q
C
C
C
C
C
C
Q
C
C
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuratio n for DIP14, SO14 and
TSSOP14 Fig 6. Pin configuration for DHVQFN14
74HC74-Q100
74HCT74-Q100
1RD V
CC
1D 2RD
1CP 2D
1SD 2CP
1Q 2SD
1Q 2Q
GND 2Q
aaa-004596
1
2
3
4
5
6
78
10
9
12
11
14
13
aaa-004597
74HC74-Q100
74HCT74-Q100
Transparent top view
1Q 2Q
1Q 2SD
1SD 2CP
1CP 2D
1D 2RD
GND(1)
GND
2Q
1RD
VCC
6 9
510
411
312
213
7
8
1
14
terminal 1
index area
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 4 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition;
X = don’t care.
Table 2. Pin description
Symbol Pin Description
1RD 1 asynchronous reset-direct input (active LOW)
1D 2 data input
1CP 3 clock input (LOW-to-HIGH, edge-triggered)
1SD 4 asynchronous set-direct input (active LOW)
1Q 5 output
1Q 6 complement outp ut
GND 7 ground (0 V)
2Q 8 complement outp ut
2Q 9 output
2SD 10 asynchronous set-direct input (active LOW)
2CP 11 clock input (LOW-to-HIGH, edge-triggered)
2D 12 data input
2RD 13 asynchronous reset-direct input (active LOW)
VCC 14 supply voltage
Table 3. Function table[1]
Input Output
nSDnRDnCP nD nQ nQ
LHXXHL
HLXXLH
LLXXHH
Table 4. Function table[1]
Input Output
nSDnRDnCP nD nQn+1 nQn+1
HHLLH
HHHHL
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 5 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
7. Limiting values
[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 packages: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
9. Static characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP14 package [1] - 750 mW
SO14, TSSOP14 and DHVQFN14
packages [1] - 500 mW
Table 6. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC74-Q100 74HCT74-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate V CC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
74HC74-Q100
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 6 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
[1] All typical values are measured at Tamb =25C.
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=4.0 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V
IO=5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=4.0mA; V
CC = 4.5 V - 0.15 0.33 - 0.4 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V --40 - 80A
CIinput
capacitance 3.5 pF
74HCT74-Q100
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=4 mA 3.84 4.32 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO= 4.0 mA - 0.15 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V --40 - 80A
ICC additional
supply current VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO=0A
per input pin; nD, nRD
inputs - 70 315 - 343 A
per input pin; nSD, nCP
input - 80 360 - 392 A
CIinput
capacitance 3.5 pF
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 7 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
10. Dynamic characteristics
Table 8. Dy namic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
74HC74-Q100
tpd propagation
delay nCP to nQ, nQ; see
Figure 7 [2]
VCC = 2.0 V - 47 220 - 265 ns
VCC = 4.5 V - 17 44 - 53 ns
VCC =5V; C
L=15pF - 14 - - - ns
VCC = 6.0 V - 14 37 - 45 ns
nSD to nQ, nQ; see
Figure 8 [2]
VCC = 2.0 V - 50 250 - 300 ns
VCC = 4.5 V - 18 50 - 60 ns
VCC =5V; C
L=15pF - 15 - - - ns
VCC = 6.0 V - 14 43 - 51 ns
nRD to nQ, nQ; see
Figure 8 [2]
VCC = 2.0 V - 52 250 - 300 ns
VCC = 4.5 V - 19 50 - 60 ns
VCC =5V; C
L=15pF - 16 - - - ns
VCC = 6.0 V - 15 43 - 51 ns
tttransition
time nQ, nQ; see Figure 7 [3]
VCC = 2.0 V - 19 95 - 110 ns
VCC = 4.5 V - 7 19 - 22 ns
VCC = 6.0 V - 6 16 - 19 ns
tWpulse width nCP HIGH or LOW;
see Figure 7
VCC = 2.0 V 100 19 - 120 - ns
VCC = 4.5 V 20 7 - 24 - ns
VCC = 6.0 V 17 6 - 20 - ns
nSD, nRD LOW;
see Figure 8
VCC = 2.0 V 100 19 - 120 - ns
VCC = 4.5 V 20 7 - 24 - ns
VCC = 6.0 V 17 6 - 20 - ns
trec recovery
time nSD, nRD; see Figure 8
VCC = 2.0 V 40 3 - 45 - ns
VCC = 4.5 V 8 1 - 9 - ns
VCC = 6.0 V 7 1 - 8 - ns
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 8 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
tsu set-up time nD to nCP; see Figure 7
VCC = 2.0 V 75 6 - 90 - ns
VCC = 4.5 V 15 2 - 18 - ns
VCC = 6.0 V 13 2 - 15 - ns
thhold time nD to nCP; see Figure 7
VCC = 2.0 V 3 6- 3 -ns
VCC = 4.5 V 3 2- 3 -ns
VCC = 6.0 V 3 2- 3 -ns
fmax maximum
frequency nCP; see Figure 7
VCC = 2.0 V 4.8 23 - 4.0 - MHz
VCC = 4.5 V 24 69 - 20 - MHz
VCC =5V; C
L=15pF - 76 - - - MHz
VCC = 6.0 V 28 82 - 24 - MHz
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[4] -24 - - -pF
74HCT74-Q100
tpd propagation
delay nCP to nQ, nQ; see
Figure 7 [2]
VCC = 4.5 V - 18 44 - 53 ns
VCC =5V; C
L=15pF - 15 - - - ns
nSD to nQ, nQ; see
Figure 8 [2]
VCC = 4.5 V - 23 50 - 60 ns
VCC =5V; C
L=15pF - 18 - - - ns
nRD to nQ, nQ; see
Figure 8 [2]
VCC = 4.5 V - 24 50 - 60 ns
VCC =5V; C
L=15pF - 18 - - - ns
tttransition
time nQ, nQ; see Figure 7 [3]
VCC = 4.5 V - 7 19 - 22 ns
tWpulse width nCP HIGH or LOW;
see Figure 7
VCC = 4.5 V 23 9 - 27 - ns
nSD, nRD LOW;
see Figure 8
VCC = 4.5 V 20 9 - 24 - ns
trec recovery
time nSD, nRD; see Figure 8
VCC = 4.5 V 8 1 - 9 - ns
tsu set-up time nD to nCP; see Figure 7
VCC = 4.5 V 15 5 - 18 - ns
Table 8. Dy namic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 9 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTLH.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
thhold time nD to nCP; see Figure 7
VCC = 4.5 V 3 3- 3 -ns
fmax maximum
frequency nCP; see Figure 7
VCC = 4.5 V 22 54 - 18 - MHz
VCC =5V; C
L=15pF - 59 - - - MHz
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC 1.5 V [4] -29 - - - pF
Table 8. Dy namic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 10 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
11. Waveforms
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the
maximum frequency (CP)
WK
WVX WVX
WK
W3+/
W3+/
W:
W3/+
W
3/+
IPD[
90
90
90
90
9
,
9,
92+
92+
92/
92/
*1'
*1'
Q'LQSXW
Q&3
LQSXW
Q4RXWSXW
DDD
Q4RXWSXW
W
7+/
W7/+




74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 11 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. The s e t (nS D) and reset (nRD) input to output (nQ,nQ) propagation delays, set and reset pulse widths and
the nSD, nRD to nCP recovery time
mna423
trec
tPHL
tPHL
tW
tPLH
tPLH
VM
VM
VM
tW
VM
VM
VI
GND
VI
GND
nSD input
VI
GND
nRD input
nCP input
VOH
VOL
nQ output
VOH
VOL
nQ output
Table 9. Measurement points
Type Input Output
VMVM
74HC74-Q100 0.5VCC 0.5VCC
74HCT74-Q100 1.3 V 1.3 V
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 12 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 9. Test circuit for measuring switching times
Table 10 . Test da ta
Type Input Load Test
VItr, tfCLRL
74HC74-Q100 VCC 6ns 15pF, 50 pF 1ktPLH, tPHL
74HCT74-Q100 3 V 6 ns 15 pF, 50 pF 1 ktPLH, tPHL
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 13 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
12. Package outline
Fig 10. Package outline SOT27-1 (DIP14)
UNIT A
max. 1 2 (1) (1)
b1cD (1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
ME
e1
1.73
1.13 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 2.24.2 0.51 3.2
0.068
0.044 0.021
0.015 0.77
0.73
0.014
0.009 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 14 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig 11. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 15 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig 12. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 16 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig 13. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 17 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
13. Abbreviations
14. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT74_Q100 v.2 20130906 Product data sheet - 74HC_HCT74_Q100 v.1
Modifications: 74HC74N-Q100 (DIP14) adde d.
74HC_HCT74_Q100 v.1 20120807 Product data sheet - -
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 18 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet D evelopment This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 6 September 2013 19 of 20
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 September 2013
Document identifier: 74HC_ HCT74_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Contact information. . . . . . . . . . . . . . . . . . . . . 19
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20