1/47August 2004
M50FW080
8 Mbit (1M x8, Uniform Block)
3V Supply Firmware Hub Flash Memory
FEATURES SUMMARY
■SUPPLY VOLTAGE
–V
CC = 3V to 3.6V for Program, Erase and
Read Operations
–V
PP = 12V for Fast Program and Fast
Erase (optional)
■TWO INTERFACES
– Firmware Hub (FWH) Interface for
embedded operation with PC Chipsets
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility
■FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface
supporting Read and Write Operations
– Hardware Write Protect Pins for Block
Protection
– Register Based Read and Write
Protection
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33MHz PCI clock
■PROGRAMMING TIME
– 10µs typical
– Quadruple Byte Programming Option
■16 UNIFORM 64 KByte MEMORY BLOCKS
■PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block/Chip
Erase algorithms
– Status Register Bits
■PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase
Suspend
■FOR USE in PC BIOS APPLICATIONS
■ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 2Dh
Figure 1. Packages
TSOP32 (NB)
8 x 14mm
PLCC32 (K)
TSOP40 (N)
10 x 20mm
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TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram (FWH Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input/Output Communications (FWH0-FWH3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Top Block Lock (TBL).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3/47
M50FW080
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 21
Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M50FW080
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Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 14. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10.A/A Mux Interface AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 24. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 25. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 35
Table 26. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 36
Figure 17.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 37
Table 27. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 37
Figure 18.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . 38
Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 38
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
APPENDIX A.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 19.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 41
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M50FW080
Figure 21.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 42
Figure 22.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 43
Figure 23.Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 24.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 45
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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SUMMARY DESCRIPTION
The M50FW080 is an 8 Mbit (1Mbit x8) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing in production
lines an optional 12V power supply can be used to
reduce the programming and the erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Pro-
gram or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
need for the ISA bus in current PC Chipsets; the
M50FW080 acts as the PC BIOS on the Low Pin
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
7/47
M50FW080
Figure 2. Logic Diagram (FWH Interface)
Figure 3. Logic Diagram (A/A Mux Interface)
Table 1. Signal Names (FWH Interface)
Table 2. Signal Names (A/A Mux Interface)
AI03979
4
FWH4
FWH0-
FWH3
VCC
M50FW080
CLK
VSS
4
IC
RP
TBL
5
INIT
WP
ID0-ID3
FGPI0-
FGPI4
VPP
AI03981
11
RC
DQ0-DQ7
VCC
M50FW080
IC
VSS
8
G
W
RB
RP
A0-A10
VPP
FWH0-FWH3 Input/Output Communications
FWH4 Input Communication Frame
ID0-ID3 Identification Inputs
FGPI0-FGPI4 General Purpose Inputs
IC Interface Configuration
RP Interface Reset
INIT CPU Reset
CLK Clock
TBL Top Block Lock
WP Write Protect
RFU Reserved for Future Use. Leave
disconnected
VCC Supply Voltage
VPP Optional Supply Voltage for Fast
Erase Operations
VSS Ground
NC Not Connected Internally
IC Interface Configuration
A0-A10 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
GOutput Enable
WWrite Enable
RC Row/Column Address Select
RB Ready/Busy Output
RP Interface Reset
VCC Supply Voltage
VPP Optional Supply Voltage for Fast
Program and Fast Erase Operations
VSS Ground
NC Not Connected Internally
M50FW080
8/47
Figure 4. PLCC Connections
Note: Pins 27 and 28 are not internally connected.
Figure 5. TSOP32 Connections
AI04897
FGPI4
NC
FWH4
RFU
17
ID1
ID0
FWH0
FWH1
FWH2
FWH3
RFU
FGPI1
TBL
ID3
ID2
FGPI0
WP
9
CLK
VSS
1
RP
VCC
NC
FGPI2
RFU
32
VPP
VCC
M50FW080
FGPI3
IC (VIL)
RFU
INIT
RFU
25
VSS
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A10
RC
RP
A8
VPP
VCC
A9
NC
W
VSS
VCC
NC
DQ7
IC (VIH)
G
RB
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
VSS
A/A Mux A/A Mux
A/A MuxA/A Mux
AI09757B
A1
A0
DQ0
A7
A4 A3
A2
A6
A5
A9
A8
W
DQ7
G
NC
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A/A Mux
A/A Mux
ID1
FWH1/LAD1
FWH2/LAD2
GPI3
TBL
ID2
GPI0
WP
NC
NC
RFU
GPI4
NC
FWH4/LFRAME
RFU
FWH3/LAD3
VSS
RFU
RFU
CLK
RP
VPP
VCC M50FW080
8
1
9
16 17
24
25
32
ID3
VSS
INIT
IC
NC
GPI2 FWH0/LAD0
GPI1 ID0
NC
NC
IC (VIH)
NC
NC
RC
RP
VPP
VCC
A10
VSS
9/47
M50FW080
Figure 6. TSOP40 Connections
AI03980
A1
A0
DQ0
A7
A4 A3
A2
A6
A5
A9
A8
W
VSS
VCC
DQ7
G
RB
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A/A Mux
A/A Mux
ID1
FWH1
FWH2
FGPI3
TBL
ID2
FGPI0
WP
NC
VCC
NC
IC (VIL)
RFU
FGPI4
NC
VSS
FWH4
RFU
FWH3
VSS
VCC
RFU
RFU
NC
CLK
RP
NC
VPP
VCC
NC
M50FW080
10
1
11
20 21
30
31
40
ID3
NC INIT
NC RFU
FGPI2 FWH0
FGPI1 ID0
VSS
NC
NC
NC
IC (VIH)
NC
NC
NC
NC
RC
RP
VPP
VCC
NC
A10
VSS
VSS
VCC
M50FW080
10/47
SIGNAL DESCRIPTIONS
There are two distinct bus interfaces available on
this device. The active interface is selected before
power-up, or during Reset, using the Interface
Configuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub (FWH) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section, respectively, while
the supply signals are discussed in the Supply Sig-
nal Descriptions section.
Firmware Hub (FWH) Signal Descriptions
For the Firmware Hub (FWH) Interface see Figure
2. and Table 1..
Input/Output Communications (FWH0-FWH3).
All Input and Output Communication with the
memory take place on these pins. Addresses and
Data for Bus Read and Bus Write operations are
encoded on these pins.
Input Communication Frame (FWH4). The In-
put Communication Frame (FWH4) signals the
start of a bus operation. When Input Communica-
tion Frame is Low, VIL, on the rising edge of the
Clock a new bus operation is initiated. If Input
Communication Frame is Low, VIL, during a bus
operation then the operation is aborted. When In-
put Communication Frame is High, VIH, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The Identifica-
tion Inputs select the address that the memory re-
sponds to. Up to 16 memories can be addressed
on a bus. For an address bit to be ‘0’ the pin can
be left floating or driven Low, VIL; an internal pull-
down resistor is included with a value of RIL. For
an address bit to be ‘1’ the pin must be driven
High, VIH; there will be a leakage current of ILI2
through each pin when pulled to VIH; see Table
20..
By convention the boot memory must have ad-
dress ‘0000’ and all additional memories take se-
quential addresses starting from ‘0001’.
General Purpose Inputs (FGPI0-FGPI4). The
General Purpose Inputs can be used as digital in-
puts for the CPU to read. The General Purpose In-
put Register holds the values on these pins. The
pins must have stable data from before the start of
the cycle that reads the General Purpose Input
Register until after the cycle is complete. These
pins must not be left to float, they should be driven
Low, VIL, or High, VIH.
Interface Configuration (IC). The Interface Con-
figuration input selects whether the Firmware Hub
(FWH) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Firmware Hub (FWH) Interface the
Interface Configuration pin should be left to float or
driven Low, VIL; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, VIH. An internal pull-down resistor is
included with a value of RIL; there will be a leakage
current of ILI2 through each pin when pulled to VIH;
see Table 20..
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, VIL, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, VIH, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock in-
put is used to prevent the Top Block (Block 15)
from being changed. When Top Block Lock, TBL,
is set Low, VIL, Program and Block Erase opera-
tions in the Top Block have no effect, regardless of
the state of the Lock Register. When Top Block
Lock, TBL, is set High, VIH, the protection of the
Block is determined by the Lock Register. The
state of Top Block Lock, TBL, does not affect the
protection of the Main Blocks (Blocks 0 to 14).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL during Program or Erase Suspend.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 14)
from being changed. When Write Protect, WP, is
set Low, VIL, Program and Block Erase operations
in the Main Blocks have no effect, regardless of
the state of the Lock Register. When Write Protect,
WP, is set High, VIH, the protection of the Block
determined by the Lock Register. The state of
Write Protect, WP, does not affect the protection of
the Top Block (Block 15).
Write Protect, WP, must be set prior to a Program
or Block Erase operation is initiated and must not
be changed until the operation completes or un-
11/47
M50FW080
predictable results may occur. Care should be tak-
en to avoid unpredictable behavior by changing
WP during Program or Erase Suspend.
Reserved for Future Use (RFU). These pins do
not have assigned functions in this revision of the
part. They must be left disconnected.
Table 3. Block Addresses
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 3. and Table 2..
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A19). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read opera-
tion. During Bus Write operations they represent
the commands sent to the Command Interface of
the internal state machine. The Data Inputs/Out-
puts, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row Ad-
dress bits (A0-A10) or the Column Address bits
(A11-A19). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad-
dress bits are latched on the rising edge.
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, VOL, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase Sus-
pend command. When Ready/Busy is High, VOH,
the memory is ready for any Read, Program or
Erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfac-
es.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid. After VCC
becomes valid the Command Interface is reset to
Read mode.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pins and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents re-
quired during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Pro-
gram (see the Quadruple Byte Program Command
description) and Fast Erase options of the memory
and to protect the memory. When VPP < VPPLK
Program and Erase operations cannot be per-
formed and an error is reported in the Status Reg-
ister if an attempt to change the memory contents
is made. When VPP = VCC Program and Erase op-
erations take place as normal. When VPP = VPPH
Fast Program (if A/A Mux interface is selected)
and Fast Erase operations are used. Any other
voltage input to VPP will result in undefined behav-
ior and should not be used.
Size
(Kbytes) Address Range Block
Number Block Type
64 F0000h-FFFFFh 15 Top Block
64 E0000h-EFFFFh 14 Main Block
64 D0000h-DFFFFh 13 Main Block
64 C0000h-CFFFFh 12 Main Block
64 B0000h-BFFFFh 11 Main Block
64 A0000h-AFFFFh 10 Main Block
64 90000h-9FFFFh 9 Main Block
64 80000h-8FFFFh 8 Main Block
64 70000h-7FFFFh 7 Main Block
64 60000h-6FFFFh 6 Main Block
64 50000h-5FFFFh 5 Main Block
64 40000h-4FFFFh 4 Main Block
64 30000h-3FFFFh 3 Main Block
64 20000h-2FFFFh 2 Main Block
64 10000h-1FFFFh 1 Main Block
64 00000h-0FFFFh 0 Main Block
M50FW080
12/47
VPP should not be set to VPPH for more than 80
hours during the life of the memory. VSS Ground. VSS is the reference for all the volt-
age measurements.
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Firmware Hub (FWH) Interface is the usual in-
terface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/Ad-
dress Multiplexed (A/A Mux) Interface.
See the sections: The Firmware Hub (FWH) Bus
Operations and Address/Address Multiplexed (A/
A Mux) Bus Operations, for details of the bus op-
erations on each interface.
Firmware Hub (FWH) Bus Operations
The Firmware Hub (FWH) Interface consists of
four data signals (FWH0-FWH3), one control line
(FWH4) and a clock (CLK). In addition protection
against accidental or malicious data corruption
can be achieved using two further signals (TBL
and WP). Finally two reset signals (RP and INIT)
are available to put the memory into a known
state.
The data signals, control signal and clock are de-
signed to be compatible with PCI electrical specifi-
cations. The interface operates with clock speeds
up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Firmware Hub Registers. A valid Bus
Read operation starts when Input Communication
Frame, FWH4, is Low, VIL, as Clock rises and the
correct Start cycle is on FWH0-FWH3. On the fol-
lowing clock cycles the Host will send the Memory
ID Select, Address and other control bits on
FWH0-FWH3. The memory responds by output-
ting Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.
See Table 4. and Figure 7., for a description of the
Field definitions for each clock cycle of the trans-
fer. See Table 22. and Figure 12., for details on the
timings of the signals.
Bus Write. Bus Write operations write to the
Command Interface or Firmware Hub Registers. A
valid Bus Write operation starts when Input Com-
munication Frame, FWH4, is Low, VIL, as Clock
rises and the correct Start cycle is on FWH0-
FWH3. On the following Clock cycles the Host will
send the Memory ID Select, Address, other control
bits, Data0-Data3 and Data4-Data7 on FWH0-
FWH3. The memory outputs Sync data until the
wait-states have elapsed.
See Table 5. and Figure 8., for a description of the
Field definitions for each clock cycle of the trans-
fer. See Table 22. and Figure 12., for details on the
timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when FWH4 is driven Low, VIL,
during the bus operation; the memory will tri-state
the Input/Output Communication pins, FWH0-
FWH3.
Note that, during a Bus Write operation, the Com-
mand Interface starts executing the command as
soon as the data is fully received; a Bus Abort dur-
ing the final TAR cycles is not guaranteed to abort
the command; the bus, however, will be released
immediately.
Standby. When FWH4 is High, VIH, the memory
is put into Standby mode where FWH0-FWH3 are
put into a high-impedance state and the Supply
Current is reduced to the Standby level, ICC1.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, VIL. RP or INIT must be held
Low, VIL, for tPLPH. The memory resets to Read
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset, see Table 14.. If RP or
INIT goes Low, VIL, during a Program or Erase op-
eration, the operation is aborted and the memory
cells affected no longer contain valid data; the
memory can take up to tPLRH to abort a Program
or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux) Inter-
face has a more traditional style interface. The sig-
nals consist of a multiplexed address signals (A0-
A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An additional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Inter-
face is included for use by Flash Programming
13/47
M50FW080
equipment for faster factory programming. Only a
subset of the features available to the Firmware
Hub (FWH) Interface are available; these include
all the Commands but exclude the Security fea-
tures and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are unprotect-
ed. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature and the Status Register. A valid
Bus Read operation begins by latching the Row
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and
the Row/Column Address Select RC. Then Write
Enable (W) and Interface Reset (RP) must be
High, VIH, and Output Enable, G, Low, VIL, in order
to perform a Bus Read operation. The Data Inputs/
Outputs will output the value, see Figure 14. and
Table 24., for details of when the output becomes
valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the Ad-
dress Inputs, A0-A10, and the Row/Column Ad-
dress Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Inter-
face Reset, RP, must be High, VIH and Write En-
able, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write En-
able, W. See Figure 15. and Table 25., for details
of the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, VIL. RP must be
held Low, VIL for tPLPH. If RP is goes Low, VIL, dur-
ing a Program or Erase operation, the operation is
aborted and the memory cells affected no longer
contain valid data; the memory can take up to tPL-
RH to abort a Program or Erase operation.
Table 4. FWH Bus Read Field Definitions
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1101b I On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Read cycle.
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with the most
significant nibble first.
10 1 MSIZE 0000b I Always 0000b (only single byte transfers are supported).
11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
12 1 TAR 1111b
(float) OThe FWH Flash Memory takes control of FWH0-FWH3
during this cycle.
13-14 2 WSYNC 0101b O
The FWH Flash Memory drives FWH0-FWH3 to 0101b
(short wait-sync) for two clock cycles, indicating that the data
is not yet available. Two wait-states are always included.
15 1 RSYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating that data will be available during the next clock
cycle.
16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least
significant nibble.
M50FW080
14/47
Figure 7. FWH Bus Read Waveforms
Table 5. FWH Bus Write Field Definitions
18 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b to
indicate a turnaround cycle.
19 1 TAR 1111b
(float) N/A The FWH Flash Memory floats its outputs, the host takes
control of FWH0-FWH3.
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1110b I On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with the most
significant nibble first.
10 1 MSIZE 0000b I Always 0000b (single byte transfer).
11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least significant
nibble.
13 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
14 1 TAR 1111b
(float) OThe FWH Flash Memory takes control of FWH0-FWH3
during this cycle.
15 1 SYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
16 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
17 1 TAR 1111b
(float) N/A The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
AI03437
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE TAR SYNC DATA TAR
11712322
15/47
M50FW080
Figure 8. FWH Bus Write Waveforms
Table 6. A/A Mux Bus Operations
Table 7. Manufacturer and Device Codes
Operation G WRP VPP DQ7-DQ0
Bus Read VIL VIH VIH Don’t Care Data Output
Bus Write VIH VIL VIH VCC or VPPH Data Input
Output Disable VIH VIH VIH Don’t Care Hi-Z
Reset VIL or VIH VIL or VIH VIL Don’t Care Hi-Z
Operation G WRP A19-A1 A0 DQ7-DQ0
Manufacturer Code VIL VIH VIH VIL VIL 20h
Device Code VIL VIH VIH VIL VIH 2Dh
AI03441
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE DATA TAR SYNC TAR
11712212
M50FW080
16/47
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table 9., Com-
mands. The following text descriptions should be
read in conjunction with Table 9..
Read Memory Array Command. The Read
Memory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Read mode. Once the command is is-
sued the memory remains in Read mode until an-
other command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the memory will not
accept the Read Memory Array command until the
operation completes.
Read Status Register Command. The Read
Status Register command is used to read the Sta-
tus Register. One Bus Write cycle is required to is-
sue the Read Status Register command. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Read Electronic Signature Command. The
Read Electronic Signature command is used to
read the Manufacturer Code and the Device Code.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once the com-
mand is issued subsequent Bus Read operations
read the Manufacturer Code or the Device Code
until another command is issued.
After the Read Electronic Signature Command is
issued the Manufacturer Code and Device Code
can be read using Bus Read operations using the
addresses in Table 8..
Table 8. Read Electronic Signature
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write opera-
tions are required to issue the command; the sec-
ond Bus Write cycle latches the address and data
in the internal state machine and starts the Pro-
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the address falls in a protected block then the
Program operation will abort, the data in the mem-
ory array will not be changed and the Status Reg-
ister will output the error.
During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Program
times are given in Table 14..
Note that the Program command cannot change a
bit set at ‘0’ back to ‘1’ and attempting to do so will
not cause any modification on its value. One of the
Erase commands must be used to set all of the
bits in the block to ‘1’.
See Figure 19., for a suggested flowchart on using
the Program command.
Quadruple Byte Program Command. The Qua-
druple Byte Program Command can be only used
in A/A Mux mode to program four adjacent bytes
in the memory array at a time. The four bytes must
differ only for the addresses A0 and A10. Pro-
gramming should not be attempted when VPP is
not at VPPH. The operation can also be executed if
VPP is below VPPH, but result could be uncertain.
Five Bus Write operations are required to issue the
command. The second, the third and the fourth
Bus Write cycle latches respectively the address
and data of the first, the second and the third byte
in the internal state machine. The fifth Bus Write
cycle latches the address and data of the fourth
byte in the internal state machine and starts the
Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
During the Quadruple Byte Program operation the
memory will only accept the Read Status register
command and the Program/Erase Suspend com-
mand. All other commands will be ignored. Typical
Quadruple Byte Program times are given in Table
8..
Note that the Quadruple Byte Program command
cannot change a bit set to ‘0’ back to ‘1’ and at-
tempting to do so will not cause any modification
on its value. One of the Erase commands must be
used to set all of the bits in the block to ‘1’.
See Figure 20., Quadruple Byte Program Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Quadruple Byte Program command.
Code Address Data
Manufacturer Code 00000h 20h
Device Code 00001h 2Dh
17/47
M50FW080
Chip Erase Command. The Chip Erase Com-
mand can be only used in A/A Mux mode to erase
the entire chip at a time. Erasing should not be at-
tempted when VPP is not at VPPH. The operation
can also be executed if VPP is below VPPH, but re-
sult could be uncertain. Two Bus Write operations
are required to issue the command and start the
Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits. During the Chip Erase operation the
memory will only accept the Read Status Register
command. All other commands will be ignored.
Typical Chip Erase times are given in Table 14..
The Chip Erase command sets all of the bits in the
memory to ‘1’. See Figure 22., for a suggested
flowchart on using the Chip Erase command.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the block address
in the internal state machine and starts the Pro-
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the block is protected then the Block Erase oper-
ation will abort, the data in the block will not be
changed and the Status Register will output the er-
ror.
During the Block Erase operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Block
Erase times are given in Table 14..
The Block Erase command sets all of the bits in
the block to ‘1’. All previous data in the block is
lost.
See Figure 22., for a suggested flowchart on using
the Erase command.
Clear Status Register Command. The Clear
Status Register command can be used to reset
bits 1, 3, 4 and 5 in the Status Register to ‘0’. One
Bus Write is required to issue the Clear Status
Register command. Once the command is issued
the memory returns to its previous mode, subse-
quent Bus Read operations continue to output the
same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Sta-
tus Register by issuing the Clear Status Register
command before attempting a new Program or
Erase command.
Program/Erase Suspend Command. The Pro-
gram/Erase Suspend command can be used to
pause a Program or Block Erase operation. One
Bus Write cycle is required to issue the Program/
Erase Suspend command and pause the Pro-
gram/Erase Controller. Once the command is is-
sued it is necessary to poll the Program/Erase
Controller Status bit to find out when the Program/
Erase Controller has paused; no other commands
will be accepted until the Program/Erase Control-
ler has paused. After the Program/Erase Control-
ler has paused, the memory will continue to output
the Status Register until another command is is-
sued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once Program/Erase Control-
ler Status bit indicates that the Program/Erase
Controller is no longer active, the Program Sus-
pend Status bit or the Erase Suspend Status bit
can be used to determine if the operation has com-
pleted or is suspended. For timing on the delay be-
tween issuing the Program/Erase Suspend
command and the Program/Erase Controller
pausing see Table 14..
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature and Program/Erase Resume com-
mands will be accepted by the Command Inter-
face. Additionally, if the suspended operation was
Block Erase then the Program command will also
be accepted; only the blocks not being erased may
be read or programmed correctly.
See Figure 21., and Figure 24., for suggested
flowcharts on using the Program/Erase Suspend
command.
Program/Erase Resume Command. The Pro-
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend has paused it. One Bus
Write cycle is required to issue the Program/Erase
Resume command. Once the command is issued
subsequent Bus Read operations read the Status
Register.
M50FW080
18/47
Table 9. Commands
Note: X Don’t Care, PA Program Address, PD Program Data, A1,2,3,4 Consecutive Addresses, BA Any address in the Block.
Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.
Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.
Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-
mand is issued.
Block Erase, Program. After these commands read the Status Register until the command completes and another command is is-
sued.
Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A1, A2, A3 and A4 must be consecutive addresses
differing only for address bit A0 and A10. After this command read the Status Register until the command completes and another com-
mand is issued.
Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes
and another command is issued.
Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status
Register, Program (during Erase suspend) and Program/Erase resume commands.
Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the
Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.
Invalid/Reserved. Do not use Invalid or Reserved commands.
Command
Cycles
Bus Write Operations
1st 2nd 3rd 4th 5th
Addr Data Addr Data Addr Data Addr Data Addr Data
Read Memory Array 1 X FFh
Read Status Register 1 X 70h
Read Electronic Signature 1X 90h
1X 98h
Program 2X 40hPAPD
2X 10hPAPD
Quadruple Byte Program 5 X 30h A1PD A2PD A3PD A4PD
Chip Erase 2 X 80h X 10h
Block Erase 2 X 20h BA D0h
Clear Status Register 1 X 50h
Program/Erase Suspend 1 X B0h
Program/Erase Resume 1 X D0h
Invalid/Reserved
1X 00h
1X 01h
1X 60h
1X 2Fh
1XC0h
19/47
M50FW080
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey differ-
ent information and errors on the operation.
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase and
Program/Erase Resume commands are issued.
The Status Register can be read from any ad-
dress.
The Status Register bits are summarized in Table
10.. The following text descriptions should be read
in conjunction with Table 10..
Program/Erase Controller Status (Bit 7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive. When the Program/Erase Controller Sta-
tus bit is ‘0’, the Program/Erase Controller is ac-
tive; when the bit is ‘1’, the Program/Erase
Controller is inactive.
The Program/Erase Controller Status is ‘0’ imme-
diately after a Program/Erase Suspend command
is issued until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Pro-
gram/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Protection Status bits should be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that a Block Erase oper-
ation has been suspended and is waiting to be
resumed. The Erase Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’ the Pro-
gram/Erase Controller is active or has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block(s)
and still failed to verify that the block(s) has erased
correctly. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block(s) has erased
correctly; when the Erase Status bit is ‘1’ the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the block(s) and still failed to
verify that the block(s) has erased correctly.
Once the Erase Status bit is set to ‘1’ it can only be
reset to ‘0’ by a Clear Status Register command or
a hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail.
Program Status (Bit 4). The Program Status bit
can be used to identify if the memory has applied
the maximum number of program pulses to the
byte and still failed to verify that the byte has pro-
grammed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has pro-
grammed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to verify that the byte has programmed cor-
rectly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
cur if VPP becomes invalid during a Program or
Erase operation.
When the VPP Status bit is ‘0’ the voltage on the
VPP pin was sampled at a valid voltage; when the
VPP Status bit is ‘1’ the VPP pin has a voltage that
is below the VPP Lockout Voltage, VPPLK, the
memory is protected; Program and Erase opera-
tion cannot be performed.
Once the VPP Status bit set to ‘1’ it can only be re-
set to ‘0’ by a Clear Status Register command or a
hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail.
M50FW080
20/47
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has complet-
ed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if the Pro-
gram or Block Erase operation has tried to modify
the contents of a protected block. When the Block
Protection Status bit is to ‘0’ no Program or Block
Erase operations have been attempted to protect-
ed blocks since the last Clear Status Register
command or hardware reset; when the Block Pro-
tection Status bit is ‘1’ a Program or Block Erase
operation has been attempted on a protected
block.
Once it is set to ‘1’ the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Block
Erase command is issued, otherwise the new
command will appear to fail.
Using the A/A Mux Interface the Block Protection
Status bit is always ‘0’.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
Table 10. Status Register Bits
Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Program active ‘0’X(1) ‘0’‘0’‘0’‘0’‘0’
Program suspended ‘1X(1) ‘0’‘0’‘0’‘1’‘0’
Program completed successfully ‘1’X(1) ‘0’‘0’‘0’‘0’‘0’
Program failure due to VPP Error ‘1’X(1) ‘0’‘0’‘1’‘0’‘0’
Program failure due to Block Protection (FWH Interface only) ‘1’X(1) ‘0’‘0’‘0’‘0’‘1’
Program failure due to cell failure ‘1’X(1) ‘0’‘1’‘0’‘0’‘0’
Erase active ‘0’‘0’‘0’‘0’‘0’‘0’‘0’
Block Erase suspended ‘1’‘1’‘0’‘0’‘0’‘0’‘0’
Erase completed successfully ‘1’‘0’‘0’‘0’‘0’‘0’‘0’
Erase failure due to VPP Error ‘1’‘0’‘0’‘0’‘1’‘0’‘0’
Block Erase failure due to Block Protection (FWH Interface
only) ‘1’‘0’‘0’‘0’‘0’‘0’‘1’
Erase failure due to failed cell(s) ‘1’‘0’‘1’‘0’‘0’‘0’‘0’
21/47
M50FW080
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS
When the Firmware Hub Interface is selected sev-
eral additional registers can be accessed. These
registers control the protection status of the
Blocks, read the General Purpose Input pins and
identify the memory using the Electronic Signature
codes. See Table 11. for the memory map of the
Configuration Registers.
Lock Registers
The Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block, the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written,
though care should be taken when writing as, once
the Lock Down Bit is set, ‘1’, further modifications
to the Lock Register cannot be made until cleared,
to ‘0’, by a reset or power-up.
See Table 12. for details on the bit definitions of
the Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Block Erase Command).
When the Write Lock Bit is set, ‘1’, the block is
write protected; any operations that attempt to
change the data in the block will fail and the Status
Register will report the error. When the Write Lock
Bit is reset, ‘0’, the block is not write protected
through the Lock Register and may be modified
unless write protected through some other means.
When VPP is less than VPPLK all blocks are pro-
tected and cannot be modified, regardless of the
state of the Write Lock Bit. If Top Block Lock, TBL,
is Low, VIL, then the Top Block (Block 15) is write
protected and cannot be modified. Similarly, if
Write Protect, WP, is Low, VIL, then the Main
Blocks (Blocks 0 to 14) are write protected and
cannot be modified.
After power-up or reset the Write Lock Bit is al-
ways set to ‘1’ (write protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read
(from Read mode). When the Read Lock Bit is set,
‘1’, the block is read protected; any operation that
attempts to read the contents of the block will read
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations in the Block return the data pro-
grammed into the block as expected.
After power-up or reset the Read Lock Bit is al-
ways reset to ‘0’ (not read protected).
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset or power-up is required be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
M50FW080
22/47
Table 11. Firmware Hub Register Configuration Map
Mnemonic Register Name Memory
Address Default
Value Access
T_BLOCK_LK Top Block Lock Register (Block 15) FBF0002h 01h R/W
T_MINUS01_LK Top Block [-1] Lock Register (Block 14) FBE0002h 01h R/W
T_MINUS02_LK Top Block [-2] Lock Register (Block 13) FBD0002h 01h R/W
T_MINUS03_LK Top Block [-3] Lock Register (Block 12) FBC0002h 01h R/W
T_MINUS04_LK Top Block [-4] Lock Register (Block 11) FBB0002h 01h R/W
T_MINUS05_LK Top Block [-5] Lock Register (Block 10) FBA0002h 01h R/W
T_MINUS06_LK Top Block [-6] Lock Register (Block 9) FB90002h 01h R/W
T_MINUS07_LK Top Block [-7] Lock Register (Block 8) FB80002h 01h R/W
T_MINUS08_LK Top Block [-8] Lock Register (Block 7) FB70002h 01h R/W
T_MINUS09_LK Top Block [-9] Lock Register (Block 6) FB60002h 01h R/W
T_MINUS10_LK Top Block [-10] Lock Register (Block 5) FB50002h 01h R/W
T_MINUS11_LK Top Block [-11] Lock Register (Block 4) FB40002h 01h R/W
T_MINUS12_LK Top Block [-12] Lock Register (Block 3) FB30002h 01h R/W
T_MINUS13_LK Top Block [-13] Lock Register (Block 2) FB20002h 01h R/W
T_MINUS14_LK Top Block [-14] Lock Register (Block 1) FB10002h 01h R/W
T_MINUS15_LK Top Block [-15] Lock Register (Block 0) FB00002h 01h R/W
FGPI_REG Firmware Hub (FWH) General Purpose Input Register FBC0100h N/A R
MANUF_REG Manufacturer Code Register FBC0000h 20h R
DEV_REG Device Code Register FBC0001h 2Dh R
23/47
M50FW080
Firmware Hub (FWH) General Purpose Input
Register
The Firmware Hub (FWH) General Purpose Input
Register holds the state of the Firmware Hub Inter-
face General Purpose Input pins, FGPI0-FGPI4.
When this register is read, the state of these pins
is returned. This register is read-only and writing to
it has no effect.
The signals on the Firmware Hub Interface Gener-
al Purpose Input pins should remain constant
throughout the whole Bus Read cycle in order to
guarantee that the correct data is read.
Manufacturer Code Register
Reading the Manufacturer Code Register returns
the manufacturer code for the memory. The man-
ufacturer code for STMicroelectronics is 20h. This
register is read-only and writing to it has no effect.
Device Code Register
Reading the Device Code Register returns the de-
vice code for the memory, 2Dh. This register is
read-only and writing to it has no effect.
Table 12. Lock Register Bit Definitions
Note: Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-15] Lock Reg-
ister (T_MINUS15_LK).
Table 13. General Purpose Input Register Definition
Note: Applies to the General Purpose Input Register (FGPI_REG).
Bit Bit Name Value Function
7-3 Reserved
2 Read-Lock
‘1’Bus Read operations in this Block always return 00h.
‘0’Bus read operations in this Block return the Memory Array contents. (Default
value).
1 Lock-Down
‘1’Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a
‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset
to ‘0’ following a Reset (using RP or INIT) or after power-up.
‘0’Read-Lock and Write-Lock can be changed by writing new values to them. (Default
value).
0 Write-Lock
‘1’Program and Block Erase operations in this Block will set an error in the Status
Register. The memory contents will not be changed. (Default value).
‘0’Program and Block Erase operations in this Block are executed and will modify the
Block contents.
Bit Bit Name Value Function
7-5 Reserved
4FGPI4 ‘1’Input Pin FGPI4 is at VIH
‘0’Input Pin FGPI4 is at VIL
3FGPI3 ‘1’Input Pin FGPI3 is at VIH
‘0’Input Pin FGPI3 is at VIL
2FGPI2 ‘1’Input Pin FGPI2 is at VIH
‘0’Input Pin FGPI2 is at VIL
1FGPI1 ‘1’Input Pin FGPI1 is at VIH
‘0’Input Pin FGPI1 is at VIL
0FGPI0 ‘1’Input Pin FGPI0 is at VIH
‘0’Input Pin FGPI0 is at VIL
M50FW080
24/47
PROGRAM AND ERASE TIMES
The Program and Erase times are shown in Table
14..
Table 14. Program and Erase Times
Note: 1. TA = 25°C, VCC = 3.3V
2. This time is obtained executing the Quadruple Byte Program Command.
3. Sampled only, not 100% tested.
Parameter Interface Test Condition Min Typ (1) Max Unit
Byte Program 10 200 µs
Quadruple Byte Program A/A Mux VPP = 12V ± 5% 10 200 µs
Chip Erase A/A Mux VPP = 12V ± 5% 9sec
Block Program A/A Mux VPP = 12V ± 5% 0.1 (2) 5sec
VPP = VCC 0.4 5 sec
Block Erase VPP = 12V ± 5% 0.75 8 sec
VPP = VCC 110sec
Program/Erase Suspend to Program pause (3) 5µs
Program/Erase Suspend to Block Erase pause (3) 30 µs
25/47
M50FW080
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 15. Absolute Maximum Ratings
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to VCC + 2V for
less than 20ns during transitions.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1°C
VIO Input or Output range 2–0.50 VCC + 0.6 V
VCC Supply Voltage –0.50 4 V
VPP Program Voltage –0.6 13 V
VESD Electrostatic Discharge Voltage (Human Body model) 3–2000 2000 V
M50FW080
26/47
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 16., Table 17.
and Table 18.. Designers should check that the
operating conditions in their circuit match the oper-
ating conditions when relying on the quoted pa-
rameters.
Table 16. Operating Conditions
Table 17. FWH Interface AC Measurement Conditions
Table 18. A/A Mux Interface AC Measurement Conditions
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 3.0 3.6 V
TA
Ambient Operating Temperature (Device Grade 5) –20 85 °C
Ambient Operating Temperature (Device Grade 1) 0 70 °C
Parameter Value Unit
Load Capacitance (CL)10 pF
Input Rise and Fall Times ≤ 1.4 ns
Input Pulse Voltages 0.2 VCC and 0.6 VCC V
Input and Output Timing Ref. Voltages 0.4 VCC V
Parameter Value Unit
Load Capacitance (CL)30 pF
Input Rise and Fall Times ≤ 10 ns
Input Pulse Voltages 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 V
27/47
M50FW080
Figure 9. FWH Interface AC Testing Input Output Waveforms
Figure 10. A/A Mux Interface AC Testing Input Output Waveform
Table 19. Impedance
Note: 1. Sampled only, not 100% tested.
2. See PCI Specification.
3. TA = 25°C, f = 1MHz.
Symbol Parameter Test Condition Min Max Unit
CIN(1) Input Capacitance VIN = 0V 13 pF
CCLK(1) Clock Capacitance VIN = 0V 312pF
LPIN(2) Recommended Pin
Inductance 20 nH
AI03404
0.6 VCC
0.2 VCC
0.4 VCC
IO > ILO
IO < ILO IO < ILO
Input and Output AC Testing Waveform
Output AC Tri-state Testing Waveform
AI01417
3V
0V
1.5V
M50FW080
28/47
Table 20. DC Characteristics
Note: 1. Sampled only, not 100% tested.
2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.
Symbol Parameter Interface Test Condition Min Max Unit
VIH Input High Voltage FWH 0.5 VCC VCC + 0.5 V
A/A Mux 0.7 VCC VCC + 0.3 V
VIL Input Low Voltage FWH –0.5 0.3 VCC V
A/A Mux -0.5 0.8 V
VIH(INIT)INIT Input High Voltage FWH 1.35 VCC + 0.5 V
VIL(INIT)INIT Input Low Voltage FWH –0.5 0.2 VCC V
ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA
ILI2 IC, IDx Input Leakage
Current IC, ID0, ID1, ID2, ID3 = VCC 200 µA
RIL IC, IDx Input Pull Low
Resistor 20 100 kΩ
VOH Output High Voltage FWH IOH = –500µA0.9 VCC V
A/A Mux IOH = –100µAVCC – 0.4 V
VOL Output Low Voltage FWH IOL = 1.5mA 0.1 VCC V
A/A Mux IOL = 1.8mA 0.45 V
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA
VPP1 VPP Voltage 33.6V
VPPH VPP Voltage (Fast
Program/Fast Erase) 11.4 12.6 V
VPPLK(1) VPP Lockout Voltage 1.5 V
VLKO(1) VCC Lockout Voltage 1.8 2.3 V
ICC1 Supply Current (Standby) FWH
FWH4 = 0.9 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz
100 µA
ICC2 Supply Current (Standby) FWH
FWH4 = 0.1 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz
10 mA
ICC3
Supply Current
(Any internal operation
active)
FWH
VCC = VCC max, VPP = VCC
f(CLK) = 33MHz
IOUT = 0mA
60 mA
ICC4 Supply Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA
ICC5(1) Supply Current
(Program/Erase) A/A Mux Program/Erase Controller Active 20 mA
IPP VPP Supply Current
(Read/Standby) VPP > VCC 400 µA
IPP1(1) VPP Supply Current
(Program/Erase active)
VPP = VCC 40 mA
VPP = 12V ± 5% 15 mA
29/47
M50FW080
Figure 11. FWH Interface Clock Waveform
Table 21. FWH Interface Clock Characteristics
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed
by design rather than tested. Refer to PCI Specification.
Symbol Parameter Test Condition Value Unit
tCYC CLK Cycle Time(1) Min 30 ns
tHIGH CLK High Time Min 11 ns
tLOW CLK Low Time Min 11 ns
CLK Slew Rate peak to peak Min 1 V/ns
Max 4 V/ns
AI03403
tHIGH tLOW
0.6 VCC
tCYC
0.5 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.4 VCC, p-to-p
(minimum)
M50FW080
30/47
Figure 12. FWH Interface AC Signal Timing Waveforms
Table 22. FWH Interface AC Signal Timing Characteristics
Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-
ification.
2. Applies to all inputs except CLK.
Symbol PCI
Symbol Parameter Test Condition Value Unit
tCHQV tval CLK to Data Out Min 2 ns
Max 11 ns
tCHQX(1) ton CLK to Active
(Float to Active Delay) Min 2 ns
tCHQZ toff CLK to Inactive
(Active to Float Delay) Max 28 ns
tAVCH
tDVCH tsu Input Set-up Time(2) Min 7 ns
tCHAX
tCHDX thInput Hold Time(2) Min 0 ns
AI03405
tCHQV
tCHQX
tCHQZ
tCHDX
VALID
FWH0-FWH3
tDVCH
CLK
VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA
31/47
M50FW080
Figure 13. Reset AC Waveforms
Table 23. Reset AC Characteristics
Note: 1. See Chapter 4 of the PCI Specification.
Symbol Parameter Test Condition Value Unit
tPLPH RP or INIT Reset Pulse Width Min 100 ns
tPLRH RP or INIT Low to Reset Program/Erase Inactive Max 100 ns
Program/Erase Active Max 30 µs
RP or INIT Slew Rate(1) Rising edge only Min 50 mV/ns
tPHFL RP or INIT High to FWH4 Low FWH Interface only Min 30 µs
tPHWL
tPHGL
RP High to Write Enable or Output
Enable Low A/A Mux Interface only Min 50 µs
AI03420
RP, INIT
W, G, FWH4
tPLPH
RB
tPLRH
tPHWL, tPHGL, tPHFL
M50FW080
32/47
Figure 14. A/A Mux Interface Read AC Waveforms
Table 24. A/A Mux Interface Read AC Characteristics
Note: 1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV.
Symbol Parameter Test Condition Value Unit
tAVAV Read Cycle Time Min 250 ns
tAVCL Row Address Valid to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC high Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tCHQV(1) RC High to Output Valid Max 150 ns
tGLQV(1) Output Enable Low to Output Valid Max 50 ns
tPHAV RP High to Row Address Valid Min 1 µs
tGLQX Output Enable Low to Output Transition Min 0 ns
tGHQZ Output Enable High to Output Hi-Z Max 50 ns
tGHQX Output Hold from Output Enable High Min 0 ns
AI03406
tAVAV
tCLAX tCHAX
tGLQX
tGLQV
tGHQX
VALID
A0-A10
G
DQ0-DQ7
RC
tCHQV
tGHQZ
COLUMN ADDR VALID
W
RP
tPHAV
ROW ADDR VALID NEXT ADDR VALID
tAVCL tAVCH
33/47
M50FW080
Figure 15. A/A Mux Interface Write AC Waveforms
AI04194
tCLAX
tCHAX
tWHDXtDVWH
VALID SRD
A0-A10
G
DQ0-DQ7
RC
tCHWH
tWHRL
C1
W
R1
tAVCL
tAVCH
R2 C2
tWLWH
tWHWL
RB
VPP
tVPHWH tWHGL
tQVVPL
DIN1 DIN2
Write erase or
program setup
Write erase confirm or
valid address and data
Automated erase
or program delay
Read Status
Register Data
Ready to write
another command
M50FW080
34/47
Table 25. A/A Mux Interface Write AC Characteristics
Note: 1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
Symbol Parameter Test Condition Value Unit
tWLWH Write Enable Low to Write Enable High Min 100 ns
tDVWH Data Valid to Write Enable High Min 50 ns
tWHDX Write Enable High to Data Transition Min 5 ns
tAVCL Row Address Valid to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC High Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tWHWL Write Enable High to Write Enable Low Min 100 ns
tCHWH RC High to Write Enable High Min 50 ns
tVPHWH(1) VPP High to Write Enable High Min 100 ns
tWHGL Write Enable High to Output Enable Low Min 30 ns
tWHRL Write Enable High to RB Low Min 0 ns
tQVVPL(1,2) Output Valid, RB High to VPP Low Min 0 ns
35/47
M50FW080
PACKAGE MECHANICAL
Figure 16. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline
Note: Drawing is not to scale.
PLCC-A
D
E3 E1 E
1 N
D1
D3
CP
B
E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
E2
D2 D2
M50FW080
36/47
Table 26. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 3.18 3.56 0.125 0.140
A1 1.53 2.41 0.060 0.095
A2 0.38 –0.015 –
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
CP 0.10 0.004
D 12.32 12.57 0.485 0.495
D1 11.35 11.51 0.447 0.453
D2 4.78 5.66 0.188 0.223
D3 7.62 ––0.300 ––
E 14.86 15.11 0.585 0.595
E1 13.89 14.05 0.547 0.553
E2 6.05 6.93 0.238 0.273
E3 10.16 ––0.400 ––
e1.27 ––0.050 ––
F 0.00 0.13 0.000 0.005
R0.89 ––0.035 ––
N32 32
37/47
M50FW080
Figure 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline
Note: Drawing is not to scale.
Table 27. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
α05 05
B 0.170 0.270 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D 13.800 14.200 0.5433 0.5591
D1 12.300 12.500 0.4843 0.4921
e0.500 ––0.0197 ––
E 7.900 8.100 0.3110 0.3189
L 0.500 0.700 0.0197 0.0276
N32 32
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
M50FW080
38/47
Figure 18. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
Note: Drawing is not to scale.
Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A1.200 0
A1 0.050 0.150 0 0
A2 0.950 1.050 0 0
B 0.170 0.270 0 0
C 0.100 0.210 0 0
CP 0.100 0
D 19.800 20.200 1 1
D1 18.300 18.500 1 1
e0.500 ––0––
E 9.900 10.100 0 0
L 0.500 0.700 0 0
α05 05
N40 40
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
39/47
M50FW080
PART NUMBERING
Table 29. Ordering Information Scheme
Devices are shipped from the factory with the
memory content bits erased to ’1’.For a list of available options (Speed, Package,
etc.) or for further information on any aspect of this
device, please contact the ST Sales Office nearest
to you.
Example: M50FW080 N 5 T G
Device Type
M50 = Flash Memory for PC BIOS
Architecture
F = Firmware Hub Interface
Operating Voltage
W = VCC = 3.0 to 3.6V
Device Function
080 = 8 Mbit (1Mbx8), Uniform Blocks
Package
K = PLCC32
NB = TSOP32: 8 x 14mm
N = TSOP40: 10 x 20mm
Device Grade
5 = Temperature range –20 to 85 °C.
Device tested with standard test flow
1 = Temperature range 0 to 70 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
M50FW080
40/47
APPENDIX A. FLOWCHARTS AND PSEUDO CODES
Figure 19. Program Flowchart and Pseudo Code
Note: 1. A Status check of SR1 (Protected Block), SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation
by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
Write 40h or 10h
AI08425B
Start
Write Address
and Data
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Program command:
– Write 40h or 10h
– Write Address and Data
(memory enters read status state after
the Program command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1,
– Enter the "VPP invalid" error handler
If SR4 = 1,
– Enter the "Program error" error handler
YES
End
YES
NO
SR1 = 0 Program to Protected
Block Error (1, 2)
If SR1 = 1,
– Enter the "Program to protected
block" error handler
Suspend
Suspend
Loop
NO
YES
FWH/LPC
Interface
Only
41/47
M50FW080
Figure 20. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)
Note: 1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct
command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.
AI08437B
Write Address 4
& Data 4
(3)
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Quadruple Byte Program command:
– write 30h
– write Address 1 & Data 1
(3)
– write Address 2 & Data 2
(3)
– write Address 3 & Data 3
(3)
– write Address 4 & Data 4
(3)
(memory enters read status state after
the Quadruple Byte Program command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1, VPP invalid error:
– error handler
If SR4 = 1, Program error:
– error handler
End
YES
Suspend
Suspend
Loop
NO
YES
Write 30h
Start
Write Address 1
& Data 1
(3)
Write Address 2
& Data 2
(3)
Write Address 3
& Data 3
(3)
M50FW080
42/47
Figure 21. Program Suspend and Resume Flowchart and Pseudo Code
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.
Write 70h
AI08426B
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR2 = 1
Program Continues
Write a read
Command
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while SR7 = 0
If SR2 = 0 Program completed
Write D0h
Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
Read data from
another address
Start
Write B0h
Program Complete
Write FFh
Read Data
43/47
M50FW080
Figure 22. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
Write 80h
AI08428B
Start
Write 10h
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4, SR5 = 0
VPP Invalid
Error (1)
Command
Sequence Error (1)
Chip Erase command:
– write 80h
– write 10h
(memory enters read Status Register after
the Chip Erase command)
do:
– read Status Register
while SR7 = 0
If SR3 = 1, VPP invalid error:
– error handler
If SR4, SR5 = 1, Command sequence error:
– error handler
YES
NO
SR5 = 0 Erase Error (1) If SR5 = 1, Erase error:
– error handler
End
YES
M50FW080
44/47
Figure 23. Block Erase Flowchart and Pseudo Code
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
Write 20h/32h
AI08424B
Start
Write Block
Address and D0h
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4, SR5 = 0
VPP Invalid
Error (1)
Command
Sequence Error (1)
Block Erase command:
– Write 20h/32h
– Write block Address and D0h
(memory enters read Status Register after
the Block Erase command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1,
– Enter the "VPP invalid" error handler
If SR4, SR5 = 1,
– Enter the "Command sequence"error handler
YES
NO
SR5 = 0 Erase Error (1)
YES
NO
Suspend
Suspend
Loop
If SR5 = 1,
– Enter the "Erase Error" error handler
End
YES
NO
SR1 = 0 Erase to Protected
Block Error (1)
If SR1 = 1,
– Enter the "Erase to protected block"
error handler
YES
FWH/LPC
Interface
Only
45/47
M50FW080
Figure 24. Erase Suspend and Resume Flowchart and Pseudo Code
Write 70h
AI08429B
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR6 = 1
Erase Continues
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while SR7 = 0
If SR6 = 0, Erase completed
Write D0h
Read data from
another block/sector
or
Program
Start
Write B0h
Erase Complete
Write FFh
Read Data
Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
M50FW080
46/47
REVISION HISTORY
Table 30. Document Revision History
Date Version Revision Details
April 2001 -01 First Issue
18-May-2001 -02 Document type: from Product Preview to Preliminary Data
22-Jun-2001 -03 PLCC32 package added
6-Jul-2001 -04 Note 2 changed (Table 15., Absolute Maximum Ratings)
30-Jan-2002 -05 Document promoted from Preliminary Data to Full Data Sheet
01-Mar-2002 -06 RFU pins must be left disconnected
12-Mar-2002 -07 Specification of PLCC32 package mechanical data revised
19-May-2004 8.0 TSOP32 package added. Part numbering information updated. Flow-chart
illustrations, in Appendix, updated. Document reformatted
19-Aug-2004 9.0 Pins 2 and 5 of the TSOP32 Connections illustration corrected
47/47
M50FW080
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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