Final datasheet Please read the Important Notice and Warnings at the end of this document Rev. 2.10
www.infineon.com 2019-02-11
GaN EiceDRIVER™ product family
Single-channel functional and reinforced isolated gate-drive ICs for
high-voltage enhancement-mode GaN HEMTs
Features
• Dedicated gate driver ICs for high-voltage GaN power switches (CoolGaN™, GIT technology based products)
– low driving impedance (on-resistance 0.85 Ω source, 0.35 Ω sink)
– resistor programmable gate current (typ. 10 mA) in steady “on” state
– programmable negative gate voltage to completely avoid spurious turn-on
• Single output supply voltage (typ. 8 V, floating)
• Switching behavior independent of duty-cycle (2 "off" voltage levels)
• Differential concept to ensure negative gate drive voltage under any condition
• Fast input-to-output propagation (37 ns) with excellent stability (+7/-6 ns)
• Galvanic input-to-output isolation based on coreless transformer (CT) technology
• Common mode transient immunity (CMTI) > 200 V/ns
• 3 package versions
– 1EDF5673K: 13-pin LGA (5 x 5 mm, PG-TFLGA-13-1) for functional isolation (1.5 kV)
– 1EDF5673F: 16-pin P-DSO (150 mil, PG-DSO-16-11) for functional isolation (1.5 kV)
– 1EDS5663H: 16-pin P-DSO (300 mil, PG-DSO-16-30) for safe isolation (6 kV)
• Fully qualified according to JEDEC for Industrial Applications
Description
CoolGaN™ and similar GaN switches require a continuous gate current of a few mA in their "on" state. Besides,
due to low threshold voltage and extremely fast switching transients, a negative "off" voltage level may be
needed. The widely used RC-coupled gate driver fulfils these requirements, however it suffers from a duty-cycle
dependence of switching dynamics and the lack of negative gate drive in specific situations.
Infineon's GaN EiceDRIVER™ solves these issues with very low effort. The two output stages shown below enable
a zero “off" level to eliminate any duty-cycle dependence. In addition, the differential topology is able to provide
negative gate drive without the need for a negative supply voltage. However, it requires a floating supply voltage
not compatible with bootstrapping.
DISABLE
GNDI
VDDI
VDDG
OUTG
GNDG
TX RX
Control
Logic
GaN EiceDRIVER™
VDDS
OUTS
GNDS
RX
TX
VDD
GNDI
Controller
CVDDI
UVLOin
SLDO
SLDO
RVDDI
VDDO
CC
Rtr
RSS
TNEG
Rt1
delay
t1
CVDDO
D
S
G
SS
IGx60Rxx
UVLOoutS
UVLOoutG
Control
Logic
Control
Logic
Input-to-output
isolation
S1
S2
S3
S4
GND
GPIOx
PWM
PWM
CoolGaN™
CT
Ishunt
VDD
VDD > 3.5V
Final datasheet 2 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Potential applications
• High-voltage AC/DC conversion
• High-voltage DC/DC conversion
in server and telecom SMPS
Isolation and safety approval
• 1EDS5663H with reinforced isolation: certification by VDE, UL, CSA, CQC according to
– DIN V VDE V 0884-10 (2006-12) with VIOTM = 8 kVpk, VIOSM = 6.25 kVpk (tested at 10 kVpk)
– UL1577 (Ed. 5) with VISO = 5.7 kVRMS
– IEC60950 and IEC602386 system standards and corresponding CQC certificates
• 1EDF5673K and 1EDF5673F with functional isolation: production test with 1.5 kV for 10 ms
Product versions
In accordance with the isolation classification for primary and secondary side control, GaN EiceDRIVER™ is
available in different package versions
Table 1 GaN EiceDRIVER™ product family overview
Part
number
Package Source/sink
output
resistance
Input-to-output isolation
Isolation class Rating Surge testing Safety
certification1)
1) certification pending
1EDF5673K LGA-13
5 x 5 mm
0.85 Ω / 0.35 Ωfunctional VIO = 1.5 kVDC n.a n.a
1EDF5673F DSO-16
150 mil
0.85 Ω / 0.35 Ωfunctional VIO= 1.5 kVDC n.a n.a
1EDS5663H DSO-16
300 mil
0.85 Ω / 0.35 Ωreinforced
(safe)
VIOTM = 8 kVpk
(VDE0884-10)
VISO = 5.7 kVRMS
(UL1577)
VIOSM >10 kVpk
(IEC60065)
VDE0884-10
UL1577
IEC60950,
62386 (CQC)
Final datasheet 3 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Background and system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.1 Input supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2 Output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.3 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 CT communication and data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 Signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1 Functional isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1.1 Functional isolation in PG-TFLGA-13-1 package (1EDF5673K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1.2 Functional isolation in NB PG-DSO-16-11 package (1EDF5673F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Reinforced isolation in WB PG-DSO-16-30 package (1EDS5663H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 Safety-limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1 Dimensioning guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10 Package outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1 Package PG-TFLGA-13-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.2 Package PG-DSO-16-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3 Package PG-DSO-16-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11 Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents
Final datasheet 4 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Pin configuration and description
1 Pin configuration and description
Figure 1 Pin configuration for DSO-16 and LGA-13 packages, top view
Table 2 Pin description
Pin DSO Pin LGA Symbol Description
1 2 PWM Input signal (default state Low)
Controls switching sequence at OUTG and OUTS
2 3 N.C. Do not connect
3 7 VDDI Input supply voltage (+3.3 V)
4 1 GNDI Input GND
5 5 DISABLE Input signal (defaut state Low)
Logic High is equivalent to a low state at PWM input
6 6 TNEG Resistor programmable input to control the duration t1 of negative "off" level
(Figure 4); t1 = Rt1 * 1.8 pF
7 7 N.C. Not connected
8 4 SLDO N.C. or connected to VDDI: applied voltage (3.3 V) directly used as input supply
voltage
Connected to GNDI: Internal shunt regulator activated (VDD > 3.5 V)
9 8 GNDG Ground for OUTG
10 9 OUTG Output connectd to GaN gate
11 10 VDDG Positive supply voltage for gate connected output stage
12 - N.C. Not connected
13 - N.C. Not connected
14 11 GNDS Ground for OUTS (has to be connected with GNDG)
15 12 OUTS Output connected to GaN source
16 13 VDDS Positive supply voltage for source connected output stage (has to be connected
with VDDG)
2
1
GNDI
12
LGA-13 (5 x 5 mm)
11
4
3
10
6
5
9
8
7
1EDF5673K
13
PWM
N.C.
VDDI
DISABLE
TNEG
SLDO
VDDS
OUTS
GNDS
VDDG
OUTG
GNDG
PWM
DSO-16
1
narrow-body
(150 mil)
1EDF5673F
wide-body
(300 mil)
1EDS5663H
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N.C.
VDDI
GNDI
DISABLE
TNEG
N.C.
SLDO
VDDS
OUTS
GNDS
N.C.
N.C.
VDDG
OUTG
GNDG
Final datasheet 5 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Background and system description
2 Background and system description
Although gallium nitride high electron mobility transistors (GaN HEMTs) with ohmic pGaN gate like Infineon’s
600 V CoolGaN™ power switches are robust enhancement-mode ("normally-on") devices, they differ significantly
from MOSFETs. The gate module is not isolated from the channel, but behaves like a diode with a forward voltage
VF of 3 to 4 V. Equivalent circuit and typical gate input characteristic are given in Figure 2. In the steady "on" state
a continuous gate current is required to achieve stable operating conditions. The switch is "normally-off", but the
threshold voltage Vth is rather low (~ +1 V). This is why in certain applications a negative gate voltage -VN, typically
in the range of several volts, is required to safely keep the switch "off" (Figure 2b).
Figure 2 Equivalent circuit (a) and gate input characteristics (b) of typical normally-off GaN HEMT
Obviously the transistor in Figure 2 cannot be driven like a conventional MOSFET due to the need for a steady-
state "on" current Iss and a negative "off" voltage -VN. While an Iss of a few mA is sufficient, fast switching transients
require gate charging currents Ion and Ioff in the 1 A range. To avoid a dedicated driver with 2 separate "on" paths
and bipolar supply voltage, the solution depicted in Figure 3 is usually chosen, combining a standard gate driver
with a passive RC circuit to achieve the intended behavior. The high-current paths containing the small gate
resistors Ron and Roff, respectively, are connected to the gate via a coupling capacitance CC. CC is chosen to have
no significant effect on the dynamic gate currents Ion and Ioff. In parallel to the high-current charging path the
much larger resistor Rss forms a direct gate connection to continuously deliver the small steady-state gate
current, Iss. In addition, CC can be used to generate a negative gate voltage. Obviously, in the "on"-state CC is
charged to the difference of driver supply VDDO and diode voltage VF. When switching to the "off" state, this charge
is redistributed between CC and CGS and causes an initial negative VGS of value
(2.1)
with QGeq denoting an equivalent application-specific gate charge, i.e. QGeq ~ QGS for hard-switching and QGeq ~ QGS
+ QGD for soft-switching transitions. VN can thus be controlled by proper choice of VDDO and CC. During the "off"
state the negative VGS decreases, as CC is discharged via Rss. The associated time constant cannot be chosen
independently, but is related to the steady-state current and is typically in the 1 µs range. The negative gate
voltage at the end of the "off" phase (VNf in Figure 3b) thus depends on the "off" duration. It lowers the effective
driver voltage for the following switching "on" event, resulting in a dependence of switching dynamics on
frequency and duty cycle as one drawback of this approach.
−
=−
∙(
−
)−
+
Final datasheet 6 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Background and system description
Figure 3 Equivalent circuit of GaN switch with RC gate drive (a) and gate-to-source voltage VGS (b)
A second problem might happen if two switches are used alternately in a half-bridge configuration. In normal
operation always one of the switches is "on", and before switching on the other one, it has to be switched off,
thereby generating the negative gate voltage VN. The usually short period with both switches "off" (dead time td)
does not cause a significant increase of VGS. If, however, there is by any reason a longer period with both switches
in "off" state (e.g. during system start-up, burst mode operation etc.), both coupling capacitors (CC) will be
discharged. Thus, for the first switching pulse after such an extended non-switching period no negative voltage
is available. This could lead to increased transistor stress or even instabilities due to spurious turn-on effects in
half-bridge topologies.
To solve the problems described above, a shape of VGS like the one in Figure 4b) would be required rather than
the one in Figure 4a) which results from the simple RC circuit. As explained, a negative VGS might be needed for
safe "off" states during the switching transients, but it should be as low as possible. Due to the lack of a physical
body diode any negative VGS adds to the voltage drop of a GaN transistor in reverse polarity (diode operation)
thereby increasing the conduction losses during dead time. Thus in the idealized waveform of Figure 4b) VGS is
switched to the minimum required VN for a constant time t1 longer than the system dead time td. After that VGS is
switched back to zero to ensure identical conditions for the next switch "on" event and to minimize losses from
diode operation. If, however, an "off" state lasts for a time t2 significantly longer than a normal switching period
1/fsw (e.g. several µs), VGS should be switched again to -VN to avoid the described "first pulse" problem.
Figure 4 VGS voltage waveforms with RC circuit (a), improved (b) and proposed shape (c)
off
on
VGS
t
0
VF
-VN
-VNf
VDDO
b)
+
Ron
Rss
CC
Roff
Gate drive
VDDO
Iss
Ion
Ioff
S1
S2
CGD
CGS
CDS
D
G
S
a)
GaN switch
c)
V
GS
a)
b)
t
1
> t
d
-V
N
-V
N
PWM
V
GS
t
2
>> 1/f
sw
V
GS
-V
N
-V
DDO
Final datasheet 7 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Background and system description
The conceptual goal of the GaN EiceDRIVER™ is to provide the gate voltage of Figure 4b) or a functional
equivalent without significantly increasing driving complexity. This is achieved by slightly modifying the gate
drive waveform as depicted in Figure 4c). The "off" level after a long deadtime need not be the optimized
negative voltage -VN, it could also be the more negative level -VDDO. As these "first pulse" situations happen very
rarely compared with regular switching cycles, the resulting higher reverse voltage drop has negligible effect on
switching losses.
Although going from the 3-level signal of Figure 4b) to the 4 levels of Figure 4c) seems to increase complexity at
first sight, this is finally not true. Waveform c) can be realized in a very convenient way, if VN is generated by the
RC network as described above. Then the differential driver concept of Figure 5a) with switch control signals as
given in Figure 5b) is able to fulfil all discussed requirements with lowest effort: a single supply voltage, 4
switches and 4 connection pins are sufficient.
As mentioned, utilizing -VDDO instead of -VN only during extended "off"-phases has no impact on switching losses.
However, care has to be taken when switching on again, because CC is fully charged to VDDO in this "first pulse"
situation and no current flow is possible via the capacitive path. With the standard switching-on scheme
(open S1 / close S2) the transient current thus would be limited to the small steady-state current. To achieve a
faster turn-on, CGS will be discharged prior to the "on"-transient by switching on S3 for a short time t3 before
initiating the actual "on"-transient via S1 and S2. A t3-duration of typically 20 ns is sufficient.
Figure 5 GaN EiceDRIVER™ concept (a) and switch control signals (b)
In the topology of Figure 5a) a single resistor Rtr is responsible for setting the maximum transient charging and
discharging current. This is often acceptable. If it is not, an additional resistor Roff with series diode in parallel with
Rtr can be used to realize different impedances for "on" and "off" transients, respectively. All relevant driving
parameters are thus easily programmable by choosing VDDO, Rss, Rtr, Roff and CC according to Equation (2.1) and
the relations
(2.2)
b)
a)
R
ss
PWM
S
1
S
2
S
3
t
2
>> 1/f
sw
V
GS
-V
N
-V
DDO
t
3
S
4
t
1
on
off
+
S
4
S
3
S
1
S
2
V
DDO
R
tr
C
C
R
off
=
−
,
,
=
+
,
,
=
ℎ
+
Final datasheet 8 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Functional description
3 Functional description
3.1 Block diagram
A simplified functional block diagram of the GaN EiceDRIVER™ is given in Figure 6. The 4 output transistors are
placed on 2 separate dies. Isolation between input and outputs is achieved by means of two coreless transformer
structures (CT) situated on the input die.
Figure 6 Block diagram
3.2 Isolation
The GaN EiceDRIVER™ is available in three package versions in accordance with different classes of input-to-
output isolation voltage requirements
• 1EDF5673K in LGA-13 5 x 5 mm package for functional isolation (1.5 kV)
• 1EDF5673F in DSO-16 narrow-body (150 mil) package for functional isolation (1.5 kV)
• 1EDS5663H in DSO-16 wide-body (300 mil) package for reinforced safe isolation (6 kV)
In SMPS functional isolation is typical for high-voltage systems that are controlled from their primary side,
whereas high-voltage switches controlled from the secondary side require safe isolation.
The safe isolation version 1EDS5663H is tested according to VDE0884-10 / IEC60747-17 standards as specified in
Table 15 to Table 18. As the CT forming this barrier is placed on the input die, a true "fail-safe" isolation is
achieved, i.e. even in case of a destruction of the power switch the driver input remains safely isolated from the
output.
DISABLE
GNDI
VDDI
VDDG
OUTG
GNDG
RX
UVLOoutG
Control
Logic
Control Logic
Input-to-output
isolation
VDDS
OUTS
GNDS
UVLOoutS
Control
Logic
PWM
GNDI
GNDI
UVLOin
SLDO
TNEG Delay t1
TX
TX RX S1
S2
S4
S3
SLDO Ishunt
Final datasheet 9 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Functional description
3.3 Power supply
Due to the isolation between input and output side, two power domains with independent power management
are required. Undervoltage Lockout (UVLO) functions for both input and output supplies ensure a defined start-
up and robust functionality under all operating conditions.
3.3.1 Input supply voltage
The input die is supplied via VDDI with a nominal voltage of 3.3 V. Power consumption to some extent depends
on switching frequency, as the input signal is converted into a train of repetitive current pulses to drive the
coreless transformer. Due to the chosen robust encoding scheme the average repetition rate of these pulses and
thus the average supply current depends on the switching frequency fsw. However, for fsw < 500 kHz this effect is
very small.
The input side can also be operated with supply voltages higher than 3.3 V. Then a shunt LDO voltage regulator
(SLDO) is enabled by connecting pin SLDO to GND. The SLDO regulates the current through an external resistor
RVDDI connected between the external supply voltage VDD and pin VDDI as depicted in the typical application
circuit on Page 1 to generate the required voltage drop. For proper operation it has to be ensured that the current
through RVDDI always exceeds the maximum supply current IVDDI,max of the input chip. RVDDI thus has to fulfil
(3.1)
Then Ishunt, the excess current through RVDDI, can be controlled by the SLDO to regulate VDDI to a constant 3.3 V. A
typical choice for VDD = 5 V could be RVDDI = 470 Ω, resulting in sufficient margin between resistor current and
maximum average operating current. As usual, the dynamic peak current is provided by a blocking cap (10 to 22
nF) between VDDI and GNDI.
3.3.2 Output supply voltage
Both output dies and the respective output switches are supplied by a common voltage of typically 8 V between
pins VDDS/G and GNDS/G. A ceramic bypass capacitance in the 20 to 100 nF range has to be placed close to the
supply pins. The output supply must be floating with respect to the input supply system. This is not only required
by the Kelvin source connection of the GaN switch (results in inductive voltage peaks between input and output
ground during switching transient), but also by the differential driving concept as explained in Chapter 2.
Again the minimum operating supply voltage is set by an undervoltage lockout function (UVLOout), operating
independently of the input UVLO function.
3.3.3 Power dissipation
The main power components associated with gate drive are the following: as usual, a first small part (< 20 mW) is
due to the internal driver supply currents IVDDI and IVDDO; they slightly depend on switching frequency via the CT
encoding scheme (see Typical characteristics in Chapter 6). The second component results from charging the
gate capacitance and is in the same range due to the low gate charge of GaN switches.
However, there are 2 more GaN-specific power components. The continuous gate current any CoolGaN™ switch
requires in the steady on-state causes some tens of mW to be dissipated. And, as a consequence of the differential
driving concept, additional power is dissipated during longer non-switching periods; this is associated with the
application of VDDO as negative gate-to-source voltage, because VDDO is then loaded directly with Rss (see
Figure 5). In burst-mode operation the power depends on the burst/pause ratio and is typically also only a few
tens of mW. During extended stand-by modes, however, powering down the VDDO supply could save about
<
−3.3
,
Final datasheet 10 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Functional description
100 mW. It should also be pointed out that the internal gate/source clamp implemented in CoolGaN™ is
connected in parallel with Rss in this state. To avoid any significant additional current and power dissipation, VDDO
should be strictly limited to a maximum of 12 V.
As a summary, the total gate-drive power always stays in the 50 to 150 mW range and is thus sufficiently small to
not cause any critical on-chip temperature increase.
3.4 Driver outputs
The rail-to-rail driver output stage realized with complementary MOS transistors is able to provide a typical 4 A
sourcing and 8 A sinking current. Although these current levels are neither needed nor reached when driving
GaN HEMTs (due to their low gate charge of only a few nC), the low on-resistance coming together with high
driving current is nevertheless beneficial. With an Ron of 0.85 Ω for the sourcing pMOS and 0.35 Ω for the sinking
nMOS transistor the driver can be considered as a nearly ideal switch. The gate drive parameters can thus be
determined easily and accurately by the external components as described in Chapter 2. The p-channel sourcing
transistor enables real rail-to-rail behavior without suffering from the voltage drop unavoidably associated with
nMOS source follower stages.
3.5 Undervoltage Lockout (UVLO)
The Undervoltage Lockout function ensures that the outputs can be switched only, if both input and output
supply voltages exceed the corresponding UVLO threshold voltages. Thus it can be guaranteed, that the switch
transistors are not operated, if the driving voltage is too low for complete and fast switching on, thereby avoiding
excessive power dissipation.
The UVLO levels for the output supply are set to a typical "on" value of 4.5 and 5.5 V (with 0.3 V hysteresis) for
OUTG and OUTS, respectively, whereas UVLOin for VDDI is set to 2.85 V with 0.15 V hysteresis. The different UVLO
levels for OUTG and OUTS help to safely avoid any erroneous turn-on of the GaN switch despite the low GaN
threshold voltage. Special attention has been paid to cover all possible operating conditions, like start-up or
arbitrary supply voltage situations:
•if VDDI drops below UVLOin, a "switch-to-low" command is sent to output OUTG, whereas OUTS is switched to
"high"; this corresponds to the final state in extended "off" periods with VGS = -VDDO
•for VDD lower than the output UVLO levels, an effective clamping concept has been realized by means of 100 kΩ
resistors connecting the outputs OUTS and OUTG to the respective gates of the sourcing pMOS transistors in
the output stage
As a result, safe operation of the GaN switch can be guaranteed under any circumstances.
3.6 CT communication and data transmission
A coreless transformer (CT) based communication module is used for PWM signal transfer between input and
outputs. A proven high-resolution pulse repetition scheme in the transmitter combined with a watchdog time-
out at the receiver side enables recovery from communication fails and ensures safe system shut-down in failure
cases.
Besides, the repetition scheme is also used to signal a "first pulse" situation (Figure 5). If an "off"-state lasts
longer than 32 µs, the repetition rate of the CT pulses is reduced to a value that causes the watchdog on the
output chip to wake up and initiate a change in the "off" state acc. to Figure 5 (switch S3 to "off" and S4 to "on"
state).
3.7 Signal timing
From the above, the extended "off"-phase t2 defining a "first pulse" situation, is fixed at a typical value of 32 µs.
The other important timing parameter t1, i.e. the duration of the negative "off"-voltage, can be programmed by
Final datasheet 11 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Functional description
a resistor Rt1 connected from TNEG to GNDI according to t1 = Rt1 * 1.8 pF. As the main idea is to keep the switch in
a safe "off" state during the switching transient, t1 must be longer than the system dead time td, i.e. the maximum
time between an "off"-command and the subsequent switching transient. The upper limit for t1 obviously is the
minimum "off"-period; thus there is usually sufficient margin in the choice of t1.
However, it should be mentioned that the actual value of t1 can be influenced by the switching transient itself due
to small, but unavoidable coupling capacitances between output and input pins. Even with an optimized PCB
layout, capacitances inside the package may cause a shortening of t1 for the high-side switch in fast-switching
half-bridges to approximately 50% of the static value. But, as the effect is triggered by the transient of the
switching node, the essential requirement, i.e. to apply the negative gate voltage during this transient, is always
met automatically and the described behavior does not cause any adverse effect in the system. Nevertheless, it
is possible to reduce the shortening effect by connecting a capacitance of a few 100 pF in parallel with Rt1.
Final datasheet 12 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Electrical characteristics
4 Electrical characteristics
4.1 Absolute maximum ratings
The absolute maximum ratings are listed in Table 3. Stresses beyond these values may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 3 Absolute maximum ratings
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Input supply voltage VDDI -0.3 – 4.0 V SLDO inactive (N.C. or
connected to VDDI)
Output supply voltage VDDO -0.3 – 22 V –
Voltage at pins PWM and
DISABLE
VIN -0.3 – 17 V –
-5 – – V < 50 ns for transient 1)
1) parameter verified by design, not tested in production
Voltage at pins TNEG and SLDO VTNEG
VSLDO
-0.3 – VDDI + 0.3 V –
Voltage at pins OUTS, OUTG VOUTS/G -0.3 – VDDO + 0.3 V –
-2 – VDDO + 1.5 V < 200 ns 1)
Reverse current peak at pins
OUTS, OUTG
ISRC_rev -5 – – Apk < 500 ns 1)
ISNK_rev ––5Apk
Non-destructive Common
Mode Transient Immunity
CMTI 400 – – V/ns outputs with respect to
input
Junction temperature TJ-40 – 150 °C –
Storage temperature TSTG -65 – 150 °C –
Soldering temperature TSOL – – 260 °C reflow / wave soldering 2)
2) according to JESD22A111
ESD capability VESD_CDM – – 0.5 kV Charged Device Model
(CDM) 3)
3) according to JESD22-002
ESD capability VESD_HBM – – 2 kV Human Body Model
(HBM) 4)
4) according to JESD22-A114-B (discharging 100 pF capacitor through 1.5 kΩ resistor)
Final datasheet 13 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Electrical characteristics
4.2 Thermal characteristics
Table 4 Thermal characteristics at TA= 25°C
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
PG-TFLGA-13-1 package
Thermal resistance junction-
ambient 1)
1) obtained by simulating a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in
JESD51-2a.
RthJA25 – 112 – K/W –
Thermal resistance junction-case
(top) 2)
2) obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close
description can be found in the ANSI SEMI standard G30-88.
RthJC25 –44–K/W–
Thermal resistance junction-board 3)
3) obtained by simulating an environment with a ring cold plate fixture to control the PCB temperature, as described in
JESD51-8.
RthJB25 –66–K/W–
Characterization parameter
junction-top 4)
4) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining
Rth, using a procedure described in JESD51-2a (sections 6 and 7).
ΨthJT25 –7.7–K/W–
Characterization parameter
junction-board 4)
ΨthJB25 –5.6–K/W–
PG-DSO-16-30 package
Thermal resistance junction-
ambient 1)
RthJA25 –59–K/W–
Thermal resistance junction-case
(top) 2)
RthJC25 –32–K/W–
Thermal resistance junction-board 3) RthJB25 –33–K/W–
Characterization parameter
junction-top 4)
ΨthJT25 –8.9–K/W–
Characterization parameter
junction-board 4)
ΨthJB25 –7.7–K/W–
PG-DSO-16-11 package
Thermal resistance junction-
ambient 1)
RthJA25 –51–K/W–
Thermal resistance junction-case
(top) 2)
RthJC25 –25–K/W–
Thermal resistance junction-board 3) RthJB25 –36–K/W–
Characterization parameter
junction-top 4)
ΨthJT25 –4.4–K/W–
Characterization parameter
junction-board 4)
ΨthJB25 –5.4–K/W–
Final datasheet 14 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Electrical characteristics
4.3 Operating range
4.4 Electrical characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits, respectively. They are
valid within the full operating range. Typical values are given at TJ = 25°C with VDDI = 3.3 V and VDDO = 8 V
Table 5 Operating range
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
Input supply voltage VDDI 3 – 3.5 V SLDO inactive (N.C. or
connected to VDDI)
Output supply voltage VDDO 6.5 8 201)
1) for CoolGaN™ HEMTs VDDO < 12 V is recommended
V Min. defined by UVLO
VDDI blocking capacitance CVDDI ––22nFSLDO active
(connected to GNDI)
Logic input voltage at pins
PWM and DISABLE
VIN 0–6.5V–
Voltage at pins TNEG and SLDO VTNEG
VSLDO
0–5V–
Junction temperature TJ-40 – 1502)
2) continuous operation above 125°C may reduce lifetime
°C
Ambient temperature TA-40 – 125 °C –
Table 6 Power supply
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
VDDI quiescent current IVDDIqu – 1.5 – mA no switching
VDDO quiescent current IVDDOqu – 1.3 – mA no switching
Table 7 Static output characteristics
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
High level (sourcing) output
resistance
Ron_SRC 0.42 0.85 1.6 Ω ISRC = 50 mA
Peak sourcing output current ISRC_pk –41)
1) actively limited to approx. 5.2 Apk, not subject to production test - verified by design / characterization
A–
Low level (sinking) output
resistance
Ron_SNK 0.18 0.35 0.75 Ω ISNK = 50 mA
Peak sinking output current ISNK_pk
2)
2) actively limited to approx. -10.2 Apk, not subject to production test - verified by design / characterization
-8 – A –
Final datasheet 15 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Electrical characteristics
Table 8 Dynamic characteristics, TJ,max = 125°C (see Figure 7 and Figure 8)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
PWM to OUTS propagation
delay
tPDonS
tPDoffS
31
–
37
41
44
–
ns load between OUTS and
GNDS
CLS = 1.8 nF
PWM to OUTG propagation
delay
tPDonG –tPDoffS + t1– ns load between OUTG and
GNDG
ZLG = 1.8 nF // 20 Ω
tPDoffG 31 37 44 ns
DISABLE to OUTS propagation
delay
tPD_DISon
tPD_DISoff
– – 100 ns CLS = 1.8 nF
Rise time OUTS / OUTG trise –6.512
1)
1) verified by design, not tested in production
ns CLS = CLG = 1.8 nF,
10% to 90%
Fall time OUTS tfall –4.58
1) ns CLS = 1.8 nF, 90% to 10%
Minimum input pulse width
that changes output state
tPW –18–ns–
Duration of negative gate “off”
voltage
t1– 180 – ns Rt1 = 100 kΩ
Minimum “off” time before
entering “first pulse” mode
t2–32
1) –µs–
Discharging time in “first
pulse” mode
t3–20
1) –ns–
Table 9 Undervoltage Lockout
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
Undervoltage Lockout input
(UVLOin) turn on threshold
UVLOin 2.75 2.85 2.95 V –
Undervoltage Lockout (UVLOin)
turn off threshold
UVLOin- –2.7–V–
UVLOin threshold hysteresis ∆UVLOin 0.1 0.15 0.2 V –
Undervoltage Lockout outputs
(UVLOoutG/S) turn on threshold
UVLOoutG 4.7 5.0 5.3 V –
UVLOoutS 5.4 5.8 6.2 V –
UVLOout turn off thresholds UVLOoutG- –4.5–V–
UVLOoutS- –5.2–V–
UVLOout threshold hysteresis ∆UVLOoutG 0.3 0.45 0.6 V –
∆UVLOoutS 0.4 0.6 0.8 V –
Final datasheet 16 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Electrical characteristics
Table 10 Logic inputs PWM and DISABLE
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
Input voltage threshold for
transition LH
VINL 1.7 2.0 2.3 V independent of VDDI
Input voltage threshold for
transition HL
VINH – 1.2 – V independent of VDDI
Input voltage hysteresis ∆VIN 0.4 0.8 1.2 V –
Input pull down resistor RIN – 150 – kΩ –
Final datasheet 17 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Timing diagrams
5 Timing diagrams
Figure 7 depicts rise, fall and delay times as observed at the capacitively loaded outputs OUTS and OUTG, resp.
As OUTG is not actively switched to low, a resistor in parallel with the load capacitance has to be used for testing.
In addition to the signal propagation delay tPDon, the rising edge of OUTG is delayed by a time t1 defining the
duration of negative VGS.
Figure 7 Propagation delay, rise and fall time
Figure 8 illustrates a complete switching sequence of the four switches forming the two output stages of
GaN EiceDRIVER™ (delay, rise and fall times not shown). The sequence in the left part of Figure 8 corresponds to
the normal switching operation, whereas in the right part the "first pulse" situation is depicted. This situation is
assumed to happen whenever there is no switching action for an extended period t2. Clearly t2 must be
significantly longer than a regular switching period. A typical duration of 32 µs has been chosen, as GaN switches
usually operate at switching frequencies significantly above 50 kHz (switching period below 20 µs).
Figure 8 Input signal, output switch sequence and resulting VGS for normal operation and
"first pulse" situation
V
INH
V
INL
PWM
OUTS
t
PDon
90%
t
PDoffS
10%
90%
t
rise
t
fall
10%
OUTG 10%
90%
t
rise
10%
t
1
t
PDoffG
PWM
S1
S2
S3
t
2
>> 1/f
sw
V
GS
-V
N
-V
DDO
t
3
S
4
normal operation
on off
“first pulse“
on
off
t
1
Final datasheet 18 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Typical characteristics
6 Typical characteristics
VDD= 8 V, VDDI = 3.3 V, TA = 25°C, no load (unless otherwise noted)
Figure 9 Supply current VDDI
Figure 10 Supply current VDDO
1.2
1.4
1.6
1.8
2.0
-50 0 50 100 150
I
VDDI
[mA]
TJ[°C]
Typical VDDI quiescent current
vs. temperature
0
1.0
2.0
3.0
4.0
5.0
6.0
-50 0 50 100 150
50kHz
1MHz
3MHz
I
VDDI
[mA]
TJ[°C]
Typical VDDI current vs.
temperature and frequency
0.8
1.2
1.6
2.0
-50 0 50 100 150
0
2
4
6
8
10
12
14
-50 0 50 100 150
50kHz
1MHz
3MHz
TJ [°C] TJ [°C]
I
VDDO
[mA]
I
VDDO
[mA]
Typical VDDO current vs.
temperature and frequency, no load
Typical VDDO quiescent current
vs. temperature
Final datasheet 19 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Typical characteristics
Figure 11 Supply current VDDO (with load) and output resistance
Figure 12 Logic input thresholds and VDDI UVLO
0
2
4
6
8
10
12
14
16
0 200 400 600 800 1000
switching frequency [kHz]
Duty Cycle 50%,
CC = 2nF, VDDO = 8V
0
0.2
0,4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50 0 50 100 150
Ron_src
Ron_snk
Typical output resistance vs.
temperature
I
VDDO
[mA]
R
on
[Ω]
TJ [°C]
Typical VDDO current with 70 mΩ
CoolGaN switch vs. switching frequency
0.5
1.0
1.5
2.0
2.5
-50 0 50 100 150
ON threshold
OFF threshold
TJ [°C]
V
IN
[V]
Typical input voltage thresholds
vs. temperature
2.5
2.7
2.9
-50 0 50 100 150
V
DDI
[V]
UVLO on
UVLO off
TJ [°C]
Typical undervoltage lockout threshold
VDDI vs. temperature
Final datasheet 20 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Typical characteristics
Figure 13 Output UVLO
Figure 14 Propagation delay and rise / fall time
Typical Undervoltage Lockout threshold
OUTG vs. temperature
4.5
5.0
5.5
6.0
-50 0 50 100 150
V
DDO
[V]
UVLO OUTG
T
J
[°C]
4.5
5.0
5.5
6.0
-50 0 50 100 150
T
J
[°C]
Typical Undervoltage Lockout threshold
OUTS vs. temperature
UVLO OUTG-
UVLO OUTS
UVLO OUTS-
V
DDO
[V]
T
J
[°C]
tPD [ns]
Typical propagation delays
t
PDonS
and t
PDoffG
vs. temperature
T
J
[°C]
trise/fall [ns]
Typical rise and fall time vs. temperature
25
30
35
40
45
50
-50 0 50 100 150
3
4
5
6
7
8
-50 0 50 100 150
trise
tfall
VDD = 8V
Cload = 1.8nF
Final datasheet 21 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Typical characteristics
Figure 15 Typical negative "off" voltage duration t1 vs. Rt1
Figure 16 Thermal derating curves
Typical negative "off" voltage duration t1 vs Rt1
0
50
100
150
200
250
300
350
0 50 100 150 200
t
1
[ns]
Rt1 [kΩ]
0
50
100
150
200
250
300
-50 0 50 100 150 0
500
1000
1500
2000
2500
-50 0 50 100 150
Thermal derating for safety-related
limiting current
T
J
[°C]
I
DDO
[mA]
Thermal derating for safety-related
limiting power
T
J
[°C]
P
lim
[mW]
Final datasheet 22 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Isolation specifications
7 Isolation specifications
The following tables summarize the package-specific isolation characteristics and test methods. For reinforced
isolation, the regulatory tests described in the component and system standards are applied; functional isolation
is guaranteed by the specified in-house test methods.
As soon as the regulatory certificates are available, the reference and / or documents will become available for
public download on the Infineon website.
As finally creepage and clearance distances are influenced by PCB layout, it is the customer's responsibility to
verify the respective requirements on system level.
7.1 Functional isolation specifications
7.1.1 Functional isolation in PG-TFLGA-13-1 package (1EDF5673K)
Table 11 Functional isolation input-to-output (PG-TFLGA-13-1)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Functional isolation test
voltage
VIO 1500 – – VDC impulse test >10 ms,
production tested
Maximum isolation working
voltage
VIOWM 460 – – VRMS according to IEC 60664-1
(PD 2; MG II)
Package clearance CLR – 3.4 – mm shortest distance over
air, from any input pin to
any output pin
Package creepage CPG – 3.4 – mm shortest distance over
surface, from any input
pin to any output pin
Common Mode Transient
Immunity
CMTI 200 – – V/ns according to VDE V0884-
10, static and dynamic
test
Capacitance input-to-output CIO –2–pF–
Resistance input-to-output RIO – >1000 – MΩ–
Final datasheet 23 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Isolation specifications
7.1.2 Functional isolation in NB PG-DSO-16-11 package (1EDF5673F)
Table 12 Package characteristics (PG-TFLGA-13-1)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Comparative tracking Index of
package mold
CTI 400 – 600 V according to DIN EN
60112 (VDE 0303-11)
Material group – – II – – according to IEC 60112
Table 13 Functional isolation input-to-output (NB PG-DSO-16-11)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Functional isolation test
voltage
VIO 1500 – – VDC impulse test > 10 ms,
sample tested
Maximum isolation working
voltage
VIOWM 510 – – VRMS according to IEC 60664-1
(PD2; MG II)1)
1) verified by design, not tested in production
Package clearance CLR – 4.0 – mm shortest distance over air,
from any input pin to any
output pin
Package creepage CPG – 4.0 – mm shortest distance over
surface, from any input
pin to any output pin
Common Mode Transient
Immunity
CMTI 200 – – V/ns according to VDE V0884-
10, static and dynamic
test
Capacitance input-to-output1) CIO –2–pF–
Resistance input-to-output1) RIO – >1000 – MΩ–
Table 14 Package characteristics (NB PG-DSO-16-11)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Comparative tracking Index of
package mold
CTI 400 – 600 V according to DIN EN 60112
(VDE 0303-11)
Material group – – II – – according to IEC 60112
Final datasheet 24 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Isolation specifications
7.2 Reinforced isolation in WB PG-DSO-16-30 package (1EDS5663H)
Table 15 Input-to-output isolation specification according to VDE0884-10 (WB PG-DSO-16-30 )
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Maximum transient isolation
voltage
VIOTM 8000 – – Vpk qualification for t = 60 s;
production test with
VIOTM_test = VIOTM * 1.2 for t =1 s
Maximum repetitive peak
isolation voltage
VIORM 1420 – – Vpk Time Dependent Dielectric
Breakdown test method
Maximum isolation working
voltage
VIOWM 1420 – – VDC
1000 – – VRMS
Partial discharge voltage VPD 4500 – – Vpk production test for t=1s,
partial discharge QPD < 5 pC
Maximum surge isolation
voltage
VIOSM 6250 – – Vpk VIOSM_test = 1.6 x VIOSM >10 kVpk;
sample tested 1)
1) surge pulse tests applied according to IEC60065-10.1 (Ed 8.0 2014), 61000-4-5, 60060-1 waveforms (1.2 µs slope, 50 µs
decay)
Package clearance CLR – 8.0 – mm from any input pin to any
output pin
Package creepage CPG – 8.0 – mm from any input pin to any
output pin
Overvoltage category per
IEC 60664-1 table F.1
– I – IV rated mains voltage
≤ 150 VRMS
I–III ≤ 300 VRMS
I–II ≤ 600 VRMS
Capacitance input-to-output CIO –2 –pF–
Resistance input-to-output RIO – >1000 – MΩ–
Common Mode Transient
Immunity
CMTI 200 – – V/ns input to output static and
dynamic; sample test
Table 16 Reinforced isolation package characteristics (WB PG-DSO-16-30)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Comparative Tracking Index
of package mold
CTI 400 – 600 V according to DIN EN 60112
(VDE 0303-11)
Material group – – II – – according to IEC 60112
Pollution degree – – 2 – – –
Climatic category – – 40/125/
21
–– –
Final datasheet 25 Rev. 2.10
2019-02-11
1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Isolation specifications
7.3 Safety-limiting values
According to VDE0884-10 and UL1577, safety-limiting values define the operating conditions under which the
isolation barrier can be guaranteed to stay unaffected. This corresponds with the maximum allowed junction
temperature, as temperature-induced failures might cause significant overheating and eventually damage the
isolation barrier.
Table 17 Reinforced input-to-output isolation according to UL1577 Ed 51) (WB PG-DSO-16-30)
1) certification pending
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Withstand isolation
voltage
VISO 5700 – – VRMS VISO= 5700 VRMS for t = 60 s
(qualification);
VISO_test > 1.2 x VISO = 6840 V for t = 1 s
Table 18 Reinforced isolation safety-limiting values as outlined in VDE-0884-10 (WB PG-DSO-16-30)
Parameter Side Values Unit Note or Test Condition
Min. Typ. Max.
Safety supply power Input – – 20.0 mW RthJA = 59 K/W1),
TA = 25°C,
TJ = 150°C
1) Calculated with the Rth of WB-DSO-16-30 package (see Table 4)
Output – – 2100 mW
Total – – 2120 mW
Safety supply current Output – – 265 mA RthJA = 59 K/W1),
VDDO = 8 V,
TA= 25°C, TJ = 150°C
Safety temperature Ts– – 150 °C Ts = TJ,max
Final datasheet 26 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Application circuit
8 Application circuit
Figure 17 depicts a typical application for CoolGaN™ switches in a so-called "totem-pole" PFC. It consists of a
70 mΩ GaN half-bridge controlled by two GaN EiceDRIVERs; the diode functions indicated in the power path are
usually realized with low-RDSON MOSFETs operating as synchronous rectifiers. 2.5 kW of power can be handled at
very high efficiency (above 99%).
The topology in Figure 17 differs from standard PFCs mainly by the fact that both GaN transistors are used
alternately in switch and diode operation mode, depending on the polarity of the input voltage. This eliminates
the need for rectifying the input voltage and therefore avoids a significant loss contributor. Such a topology
cannot be realized with MOS-switches due to their inherent body diode and the associated large recovery charge.
Further details can be found in application note: www.infineon.com/driving-coolgan
Figure 17 Typical application circuit for 2.5 kW GaN "totem-pole" PFC
8.1 Dimensioning guidelines
Due to low output impedance, high current limits and fast transients, the driver output stages can be regarded to
behave like ideal switches. Thus half-bridge switching dynamics are exclusively and predictably controlled by the
passive external components in the gate loop, allowing an easy adaptation to different applications and switch
sizes.
IGT60R070
VDDI
TX RX
Control
Logic
OUTS
RX
TX
GNDI
UVLOin
SLDO
8V
3.3n
10
560
TNEG delay
t1
D
S
G
SS
IGT60R070
UVLOoutS
UVLOoutG
Control
Logic
Control
Logic
Input-to-output
isolation
S1
S2
S3
S4
PWM
CT
VDDOhs
OUTG
GNDI
VDDI
GNDG
TX RX
Control
Logic
OUTS
RX
TX
GNDI
UVLOin
SLDO
8V
3.3n
10
560
TNEG delay
t1
D
S
G
SS
UVLOoutS
UVLOoutG
Control
Logic
Control
Logic
Input-to-output
isolation
S1
S2
S3
S4
PWM
CT
VDDG
OUTG
+400V V
out
100n
100n
100k
LS
HS
100k
GNDI
V
in
AC
3.3V
SD
SD
330p
VDDOls
GNDS
GNDG
VDDS
VDDS
GNDS
VDDG
VDD
22n
2
2
Final datasheet 27 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Application circuit
As a first step in dimensioning these components the intended initial negative gate voltage -VN has to be defined.
The correlation between VN, VDDO and CC as given in Equation (2.1) is graphically depicted in Figure 18 for a hard-
switched 70 mΩ CoolGaN™ transistor.
Figure 18 -VN as a function of VDDO and CC for hard-switched 70 mΩ CoolGaN™
A typical choice for -VN could be -4 V for hard-switched and -2 V for soft-switched applications, respectively.
Additionally, due to the low GaN threshold voltage, even under worst-case conditions -VN should never be
allowed to become positive. This requirement defines the minimum coupling capacitance CCmin. Under typical
conditions CCmin then in fact generates a VN of about 2 V, and thus this capacitance value can be recommended to
be used in soft-switching topologies. Beside CCmin, Table 19 also summarizes recommended values for CChs, the
coupling capacitance in hard-switching topologies, and resistor Rss for different CoolGaN™ switches (currently 70
and 190 mΩ ).
The application circuit of Figure 17 uses different gate resistors for the "on" and "off" gate loops by introducing
resistor Roff and (Schottky-)diode SD. The values of Rtr and Roff define the respective peak gate currents and thus
switching times according to Equation (2.2). Due to the basic trade-off between switching time and inductive
voltage overshoot, parasitic power and gate loop inductances have a strong influence on the optimum values of
the gate resistors. For a 70 mΩ CoolGaN™ switch they are typically in the 5 to 20 Ω range for Rtr, whereas 2 to 5 Ω
are a reasonable choice for Roff.
Finally, also indicated in Figure 17, the 330 pF capacitance in parallel with resistor Rt1 on the high-side helps to
minimize the variation of t1 as explained in Chapter 3.6.
Table 19 Recommended values of CCmin, CChs and Rss
IGx60R070x (70 mΩ) IGx60R190x (190 mΩ)
VDDO [V] CCmin [nF] CChs [nF] Rss [kΩ]CCmin [nF] CChs [nF] Rss [kΩ]
8 1.8 3.3 0.56 1 1.8 1.2
10 1.2 1.8 0.82 0.8 1 1.8
12 1 1 1 0.5 0.5 2.2
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0123456
V
DDO
= 8
V
DDO
= 10
V
DDO
= 12
-V
N
[V]
C
C
[nF]
IGT60 R070
Q
Geq
= 3 nC
C
iss
= 0.4 nF
V
F
= 3 V
Final datasheet 28 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Layout guidelines
9 Layout guidelines
For any fast-switching power system the PCB layout is crucial to achieve optimum performance. Among the many
existing rules, recommendations, guidelines, tips and tricks, the following are of highest importance:
• minimize power loop inductance, the most critical limitation of switching speed due to the unavoidable
voltage overshoots generated by fast current commutation
• use low-ESR decoupling capacitances for the driver supply voltages and place them as close as possible to the
driver (in the layout proposals below the output capacitance has been split and connected to both supply
pins)
• strictly avoid any additional coupling capacitance between input and output pins due to PCB layout (see
Chapter 3.7)
Respective layout proposals for the immediate driver surroundings are given in Figure 19, Figure 20 and
Figure 21 for the different available package types.
Figure 19 Layout recommendation for PG-TFLGA-13-1 package
!
"
#
#
$"
$"
#
%
!
#
!
&!
#
'#
#(#)
#
'"
'
'"'
Final datasheet 29 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Layout guidelines
Figure 20 Layout recommendation for PG-DSO-16-11 package
Figure 21 Layout recommendation for PG-DSO-16-30 package
!
"
"
#!
#!
"
$
"
%
"
&"
"
"
"
&!
&
&!&
!
!
"
"
!
#
!
$
!
%!
!&
!'
!
%
%
% %
Final datasheet 30 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Package outline dimensions
10 Package outline dimensions
The following package versions are available.
• an area optimized 5 x 5 mm2 PG-TFLGA-13-1
• an NB PG-DSO-16-11 package with typ. 4 mm creepage input to output
• a WB PG-DSO-16-30 package with typ. 8 mm creepage input to output
Note: For further information on package types, recommendation for board assembly, please go to
https://www.infineon.com/packages
10.1 Package PG-TFLGA-13-1
Figure 22 PG-TFLGA-13-1 outline
Final datasheet 31 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Package outline dimensions
Figure 23 PG-TFLGA-13-1 footprint
Figure 24 PG-TFLGA-13-1 packaging
Final datasheet 32 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Package outline dimensions
10.2 Package PG-DSO-16-11
Figure 25 PG-DSO-16-11 outline
Figure 26 PG-DSO-16-11 footprint
0.1 C
SEATING
PLANE
0.25 D C 16x
STAND OFF
C
8
COPLANARITY
16x
1.75 MAX.
0.1 MIN.
0.33
+0.17
-0.08
x45°
0.2
+0.05
-0.01
8°M
AX.
0.64
±0.25
6
±0.2
1
9
16
1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.25 MAX. PER SIDE
1)
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [ ]
INDEX
MARKING
BOTTOM VIEW
0.25
GAUGE
PLANE
4
0.0
-0.2
0.41
+0.08
-0.06
D
10
0.0
-0.2
1.27
1)
1
8
916
Final datasheet 33 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Package outline dimensions
Figure 27 PG-DSO-16-11 packaging
10.3 Package PG-DSO-16-30
Figure 28 PG-DSO-16-30 outline
$// ',0(16,216 $5( ,1 81,76 00
7+( '5$:,1* ,6 ,1 &203/,$1&( :,7+ ,62 352-(&7,21 0(7+2' > @
,1'(; 0$5.,1*
3,1
1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.15 MAX. PER SIDE
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [ ]
INDEXMARKING
BOTTOM VIEW
2) DOES NOT INCLUDE DAMBAR PROTRUSION OF 0.1 MAX.
10.3
(1.1)
(2.35)
0.15±0.05
0.2 A-B C2x
7.5
2.65 MAX.
STAND OFF
0.7
±0.2
10.3 0.3 D C 16x
0°..8°
0.25
GAUGE
PLANE
(0.25)
0.1 C
SEATING
PLANE
C
COPLANARITY
16x
A
B
0.4
±0.08
1) 1)
2)
1.27
0.1 2x
0.25 CA-B D16x
8
1
9
16
1
8
916
0.35 x 45°
D
(BALL SHAPE)
EJECTOR MARK
(FLAT SHAPE)
TOP VIEW
Final datasheet 34 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Package outline dimensions
Figure 29 PG-DSO-16-30 footprint
Figure 30 PG-DSO-16-30 packaging
24
11
10.8
16
4
3.2
2.7
PIN 1
INDEX MARKING
The drawing is in compliance with ISO 128-30, Projection Method 1 [ ]
All dimensions are in units mm
0.3
Final datasheet 35 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Device numbers and markings
11 Device numbers and markings
Table 20 Device numbers and markings
Part number Package Orderable part number (OPN) Device marking
1EDF5673K PG-TFLGA-13-1 1EDF5673KXUMA1 1F5673A
1EDF5673F PG-DSO-16-11 1EDF5673FXUMA1 1F5673A
1EDS5663H PG-DSO-16-30 1EDS5663HXUMA1 1S5663A
Final datasheet 36 Rev. 2.10
2019-02-11
GaN EiceDRIVER™ product family
GaN gate driver
Revision History
12 Revision History
Page or Item Subjects (major changes since previous revision)
Rev. 2.10, 2019-02-11
Page 1 package diagrams update
Page 1 application diagram update
Figure 1 & Chapter 1 repaired typo in pin config diagram and chapter
Equation (2.1) updated equation and relevant text
Figure 5 added optional resistor and diode
Equation (2.2) updated to include Roff
Chapter 3.3.1 added description of Ishunt
Chapter 3.3.3 added chapter to describe power dissipation
Chapter 3.7 added description of possibility to reduce shortening effect
Chapter 4.3 updated footnote (1)) about VDDO recommendation
Table 3 max. VDDI: 3.7 V → 4.0 V
Table 5 TA max. value 85°C → 125°C
Figure 17 updated components and dimensions
Chapter 8.1 added chapter on dimensioning guidelines
Figure 21 format change
Chapter 10 latest footprints, outlines and packaging
Rev. 2.00, 2018-11-07
Final datasheet created
Rev. 1.00, 2018-10-25
Initial version available
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2019-02-11
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2019 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
1EDF5673K, 1EDF5673F, 1EDS5663H
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hereby disclaims any and all warranties and liabilities
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