MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
MIXED SIGNAL MICROCONTROLLER
1FEATURES
23• Low Supply Voltage Range: 1.8 V to 3.6 V • Two Configurable Operational Amplifiers
(MSP430F22x4 Only)
• Ultra-Low Power Consumption • Brownout Detector
– Active Mode: 270 µA at 1 MHz, 2.2 V • Serial Onboard Programming, No External
– Standby Mode: 0.7 µA Programming Voltage Needed, Programmable
– Off Mode (RAM Retention): 0.1 µA Code Protection by Security Fuse
• Ultra-Fast Wake-Up From Standby Mode in • Bootstrap Loader
Less Than 1 µs • On-Chip Emulation Module
• 16-Bit RISC Architecture, 62.5-ns Instruction • Family Members Include:
Cycle Time – MSP430F2232
• Basic Clock Module Configurations – 8KB + 256B Flash Memory
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1% – 512B RAM
– Internal Very-Low-Power Low-Frequency – MSP430F2252
Oscillator – 16KB + 256B Flash Memory
– 32-kHz Crystal – 512B RAM
– High-Frequency (HF) Crystal up to 16 MHz – MSP430F2272
– Resonator – 32KB + 256B Flash Memory
– External Digital Clock Source – 1KB RAM
– External Resistor – MSP430F2234
• 16-Bit Timer_A With Three Capture/Compare – 8KB + 256B Flash Memory
Registers – 512B RAM
• 16-Bit Timer_B With Three Capture/Compare – MSP430F2254
Registers – 16KB + 256B Flash Memory
• Universal Serial Communication Interface – 512B RAM
– Enhanced UART Supporting Auto-Baudrate – MSP430F2274
Detection (LIN) – 32KB + 256B Flash Memory
– IrDA Encoder and Decoder – 1KB RAM
– Synchronous SPI • Available in a 38-Pin Thin Shrink Small-Outline
– I2C™ Package (TSSOP) (DA), 40-Pin QFN Package
• 10-Bit 200-ksps Analog-to-Digital (A/D) (RHA), and 49-Pin Ball Grid Array Package
Converter With Internal Reference, Sample- (YFF) (See Table 1)
and-Hold, Autoscan, and Data Transfer • For Complete Module Descriptions, See the
Controller MSP430x2xx Family User's Guide (SLAU144)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2MSP430 is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430F22x4/MSP430F22x2 series is an ultra-low-power mixed signal microcontroller with two built-in 16-
bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data
transfer controller (DTC), two general-purpose operational amplifiers in the MSP430F22x4 devices, and 32 I/O
pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front
ends are another area of application.
Table 1. Available Options
PACKAGED DEVICES(1)(2)
TAPLASTIC 49-PIN BGA PLASTIC 38-PIN TSSOP PLASTIC 40-PIN QFN
(YFF) (DA) (RHA)
MSP430F2232IYFF MSP430F2232IDA MSP430F2232IRHA
MSP430F2252IYFF MSP430F2252IDA MSP430F2252IRHA
MSP430F2272IYFF MSP430F2272IDA MSP430F2272IRHA
-40°C to 85°C MSP430F2234IYFF MSP430F2234IDA MSP430F2234IRHA
MSP430F2254IYFF MSP430F2254IDA MSP430F2254IRHA
MSP430F2274IYFF MSP430F2274IDA MSP430F2274IRHA
MSP430F2232TDA MSP430F2232TRHA
MSP430F2252TDA MSP430F2252TRHA
MSP430F2272TDA MSP430F2272TRHA
-40°C to 105°C MSP430F2234TDA MSP430F2234TRHA
MSP430F2254TDA MSP430F2254TRHA
MSP430F2274TDA MSP430F2274TRHA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Development Tool Support
All MSP430™ microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
• Debugging and Programming Interface
– MSP-FET430UIF (USB)
– MSP-FET430PIF (Parallel Port)
• Debugging and Programming Interface with Target Board
– MSP-FET430U38 (DA package)
• Production Programmer
– MSP-GANG430
2Copyright © 2006–2012, Texas Instruments Incorporated
1TEST/SBWTCK
2DVCC
3P2.5/ROSC
4
XOUT/P2.7 5
XIN/P2.6 6
RST/NMI/SBWTDIO 7
P2.0/ACLK/A0/OA0I0 8
P2.1/TAINCLK/SMCLK/A1/OA0O 9
P2.2/TA0/A2/OA0I1 10
P3.0/UCB0STE/UCA0CLK/A5 11
P3.1/UCB0SIMO/UCB0SDA 12
P3.2/UCB0SOMI/UCB0SCL 13
P3.3/UCB0CLK/UCA0STE 14
P4.0/TB0
15
P4.1/TB1
16
P4.2/TB2
17
P4.3/TB0/A12/OA0O
18 P4.4/TB1/A13/OA1O
19
38 P1.7/TA2/TDO/TDI
37 P1.6/TA1/TDI
36 P1.5/TA0/TMS
35 P1.4/SMCLK/TCK
34 P1.3/TA2
33 P1.2/TA1
32 P1.1/TA0
31 P1.0/TACLK/ADC10CLK
30 P2.4/TA2/A4/VREF+/VeREF+/OA1I0
29 P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O
28 P3.7/A7/OA1I2
27 P3.6/A6/OA0I2
26 P3.5/UCA0RXD/UCA0SOMI
25 P3.4/UCA0TXD/UCA0SIMO
24
23AVCC
22
AVSS
21
P4.7/TBCLK
20
P4.6/TBOUTH/A15/OA1I3
DVSS
P4.5/TB2/A14/OA0I3
1TEST/SBWTCK
2DVCC
3P2.5/ROSC
4
XOUT/P2.7 5
XIN/P2.6 6
RST/NMI/SBWTDIO 7
P2.0/ACLK/A0 8
P2.1/TAINCLK/SMCLK/A1 9
P2.2/TA0/A2 10
P3.0/UCB0STE/UCA0CLK/A5 11
P3.1/UCB0SIMO/UCB0SDA 12
P3.2/UCB0SOMI/UCB0SCL 13
P3.3/UCB0CLK/UCA0STE 14
P4.0/TB0
15
P4.1/TB1
16
P4.2/TB2
17
P4.3/TB0/A12
18 P4.4/TB1/A13
19
38 P1.7/TA2/TDO/TDI
37 P1.6/TA1/TDI
36 P1.5/TA0/TMS
35 P1.4/SMCLK/TCK
34 P1.3/TA2
33 P1.2/TA1
32 P1.1/TA0
31 P1.0/TACLK/ADC10CLK
30 P2.4/TA2/A4/VREF+/VeREF+
29 P2.3/TA1/A3/VREF−/VeREF−
28 P3.7/A7
27 P3.6/A6
26 P3.5/UCA0RXD/UCA0SOMI
25 P3.4/UCA0TXD/UCA0SIMO
24
23AVCC
22
AVSS
21
P4.7/TBCLK
20
P4.6/TBOUTH/A15
DVSS
P4.5/TB2/A14
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
MSP430F22x2 Device Pinout, DA Package
MSP430F22x4 Device Pinout, DA Package
Copyright © 2006–2012, Texas Instruments Incorporated 3
1DVSS
P1.5/TA0/TMS
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
13
P2.4/TA2/A4/VREF+/VeREF+
P2.5/ROSC
DVCC
TEST/SBWTCK
P1.6/TA1/TDI/TCLK
2
3
4
5
6
7
8
10
9
12 14 15 16 17 18 19
30
29
28
27
26
25
24
23
21
22
3839 37 36 35 34 33 32
XOUT/P2.7
XIN/P2.6
DVSS
RST/NMI/SBWTDIO
P2.0/ACLK/A0
P2.1/TAINCLK/SMCLK/A1
P2.2/TA0/A2
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
DVCC
P1.7/TA2/TDO/TDI
P2.3/TA1/A3/VREF−/VeREF−
P3.7/A7
P3.6/A6
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
AVCC
AVSS
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB0/A12
P4.4/TB1/A13
P4.5/TB2/A14
P4.6/TBOUTH/A15
P4.7/TBCLK
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
MSP430F22x2 Device Pinout, RHA Package
4Copyright © 2006–2012, Texas Instruments Incorporated
1DVSS
P1.5/TA0/TMS
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
13
P2.4/TA2/A4/VREF+/VeREF+/OA1I0
P2.5/ROSC
DVCC
TEST/SBWTCK
P1.6/TA1/TDI/TCLK
2
3
4
5
6
7
8
10
9
12 14 15 16 17 18 19
30
29
28
27
26
25
24
23
21
22
3839 37 36 35 34 33 32
XOUT/P2.7
XIN/P2.6
DVSS
RST/NMI/SBWTDIO
P2.0/ACLK/A0/OA0I0
P2.1/TAINCLK/SMCLK/A1/OA0O
P2.2/TA0/A2/OA0I1
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
DVCC
P1.7/TA2/TDO/TDI
P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O
P3.7/A7/OA1I2
P3.6/A6/OA0I2
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
AVCC
AVSS
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB0/A12/OA0O
P4.4/TB1/A13/OA1O
P4.5/TB2/A14/OA0I3
P4.6/TBOUTH/A15/OA1I3
P4.7/TBCLK
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
MSP430F22x4 Device Pinout, RHA Package
Copyright © 2006–2012, Texas Instruments Incorporated 5
A1 A2 A4A3 A5 A6 A7
TOP VIEW
B1 B2 B4B3 B5 B6 B7
C1 C2 C4C3 C5 C6 C7
D1 D2 D4D3 D5 D6 D7
E1 E2 E4E3 E5 E6 E7
F1 F2 F4F3 F5 F6 F7
G1 G2 G4G3 G5 G6 G7
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
MSP430F22x4, MSP430F22x2 Device Pinout, YFF Package
Package Dimensions
The package dimensions for this YFF package are shown in Table 2. See the package drawing at the end of this
data sheet for more details.
Table 2. YFF Package Dimensions
PACKAGED DEVICES D E
MSP430F22x2 3.33 ± 0.03 mm 3.49 ± 0.03 mm
MSP430F22x4
6Copyright © 2006–2012, Texas Instruments Incorporated
Basic Clock
System+
RAM
1kB
512B
512B
Brownout
Protection
RST/NMI
VCC VSS
MCLK
SMCLK
Watchdog
WDT+
15/16−Bit
Timer_A3
3 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
XOUT
JTAG
Interface
Flash
32kB
16kB
8kB
ACLK
XIN
MDB
MAB
Spy−Bi Wire
Timer_B3
3 CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
OA0, OA1
2 Op Amps
ADC10
10−Bit
12
Channels,
Autoscan,
DTC
Ports P1/P2
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
Ports P3/P4
2x8 I/O
pull−up/down
resistors
P1.x/P2.x
2x8
P3.x/P4.x
2x8
Basic Clock
System+
RAM
1kB
512B
512B
Brownout
Protection
RST/NMI
VCC VSS
MCLK
SMCLK
Watchdog
WDT+
15/16−Bit
Timer_A3
3 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
XOUT
JTAG
Interface
Flash
32kB
16kB
8kB
ACLK
XIN
MDB
MAB
Spy−Bi Wire
Timer_B3
3 CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
ADC10
10−Bit
12
Channels,
Autoscan,
DTC
Ports P1/P2
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
Ports P3/P4
2x8 I/O
pull−up/down
resistors
P1.x/P2.x
2x8
P3.x/P4.x
2x8
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
MSP430F22x2 Functional Block Diagram
MSP430F22x4 Functional Block Diagram
Copyright © 2006–2012, Texas Instruments Incorporated 7
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 3. Terminal Functions, MSP430F22x2
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK F2 31 29 I/O Timer_A, clock signal TACLK input
ADC10, conversion clock
General-purpose digital I/O pin
P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output
BSL transmit
General-purpose digital I/O pin
P1.2/TA1 E2 33 31 I/O Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
P1.3/TA2 G1 34 32 I/O Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
P1.4/SMCLK/TCK F1 35 33 I/O SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin
P1.5/TA0/TMS E1 36 34 I/O Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin
P1.6/TA1/TDI/TCLK E3 37 35 I/O Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin
P1.7/TA2/TDO/TDI(1) D2 38 36 I/O Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin
P2.0/ACLK/A0 A4 8 6 I/O ACLK output
ADC10, analog input A0
General-purpose digital I/O pin
Timer_A, clock signal at INCLK
P2.1/TAINCLK/SMCLK/A1 B4 9 7 I/O SMCLK signal output
ADC10, analog input A1
General-purpose digital I/O pin
P2.2/TA0/A2 A5 10 8 I/O Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2
General-purpose digital I/O pin
Timer_A, capture CCI1B input, compare: OUT1 output
P2.3/TA1/A3/VREF-/ VeREF- F3 29 27 I/O ADC10, analog input A3
Negative reference voltage input
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
P2.4/TA2/A4/VREF+/ VeREF+ G3 30 28 I/O ADC10, analog input A4
Positive reference voltage output or input
General-purpose digital I/O pin
P2.5/ROSC C2 3 40 I/O Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
XIN/P2.6 A2 6 3 I/O General-purpose digital I/O pin
(1) TDO or TDI is selected via JTAG instruction.
8Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Table 3. Terminal Functions, MSP430F22x2 (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
Output terminal of crystal oscillator
XOUT/P2.7 A1 5 2 I/O General-purpose digital I/O pin(2)
General-purpose digital I/O pin
USCI_B0 slave transmit enable
P3.0/UCB0STE/UCA0CLK/ B5 11 9 I/O
A5 USCI_A0 clock input/output
ADC10, analog input A5
General-purpose digital I/O pin
P3.1/UCB0SIMO/ A6 12 10 I/O USCI_B0 SPI mode: slave in/master out
UCB0SDA USCI_B0 I2C mode: SDA I2C data
General-purpose digital I/O pin
P3.2/UCB0SOMI/UCB0SCL A7 13 11 I/O USCI_B0 SPI mode: slave out/master in
USCI_B0 I2C mode: SCL I2C clock
General-purpose digital I/O pin
P3.3/UCB0CLK/UCA0STE B6 14 12 I/O USCI_B0 clock input/output
USCI_A0 slave transmit enable
General-purpose digital I/O pin
P3.4/UCA0TXD/ G6 25 23 I/O USCI_A0 UART mode: transmit data output
UCA0SIMO USCI_A0 SPI mode: slave in/master out
General-purpose digital I/O pin
P3.5/UCA0RXD/ G5 26 24 I/O USCI_A0 UART mode: receive data input
UCA0SOMI USCI_A0 SPI mode: slave out/master in
General-purpose digital I/O pin
P3.6/A6 F4 27 25 I/O ADC10 analog input A6
General-purpose digital I/O pin
P3.7/A7 G4 28 26 I/O ADC10 analog input A7
General-purpose digital I/O pin
P4.0/TB0 D6 17 15 I/O Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
P4.1/TB1 D7 18 16 I/O Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
P4.2/TB2 E6 19 17 I/O Timer_B, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
P4.3/TB0/A12 E7 20 18 I/O Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
General-purpose digital I/O pin
P4.4/TB1/A13 F7 21 19 I/O Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
General-purpose digital I/O pin
P4.5/TB2/A14 F6 22 20 I/O Timer_B, compare: OUT2 output
ADC10 analog input A14
General-purpose digital I/O pin
P4.6/TBOUTH/A15 G7 23 21 I/O Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
Copyright © 2006–2012, Texas Instruments Incorporated 9
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 3. Terminal Functions, MSP430F22x2 (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
P4.7/TBCLK F5 24 22 I/O Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
RST/NMI/SBWTDIO B3 7 5 I Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
TEST/SBWTCK D1 1 37 I Spy-Bi-Wire test clock input during programming and test
C1,
D3,
DVCC 2 38, 39 Digital supply voltage
D4,
E4, E5
C6,
AVCC C7, 16 14 Analog supply voltage
D5
A3,
B1,
DVSS B2, 4 1, 4 Digital ground reference
C3,
C4
B7,
AVSS 15 13 Analog ground reference
C5
QFN Pad NA NA Pad NA QFN package pad; connection to DVSS recommended.
10 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Table 4. Terminal Functions, MSP430F22x4
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK F2 31 29 I/O Timer_A, clock signal TACLK input
ADC10, conversion clock
General-purpose digital I/O pin
P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output
BSL transmit
General-purpose digital I/O pin
P1.2/TA1 E2 33 31 I/O Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
P1.3/TA2 G1 34 32 I/O Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
P1.4/SMCLK/TCK F1 35 33 I/O SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin
P1.5/TA0/TMS E1 36 34 I/O Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin
P1.6/TA1/TDI/TCLK E3 37 35 I/O Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin
P1.7/TA2/TDO/TDI(1) D2 38 36 I/O Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin
ACLK output
P2.0/ACLK/A0/OA0I0 A4 8 6 I/O ADC10, analog input A0
OA0, analog input IO
General-purpose digital I/O pin
Timer_A, clock signal at INCLK
P2.1/TAINCLK/SMCLK/ B4 9 7 I/O SMCLK signal output
A1/OA0O ADC10, analog input A1
OA0, analog output
General-purpose digital I/O pin
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
P2.2/TA0/A2/OA0I1 A5 10 8 I/O ADC10, analog input A2
OA0, analog input I1
General-purpose digital I/O pin
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3
P2.3/TA1/A3/ VREF-/VeREF-/F3 29 27 I/O
OA1I1/OA1O Negative reference voltage input
OA1, analog input I1
OA1, analog output
(1) TDO or TDI is selected via JTAG instruction.
Copyright © 2006–2012, Texas Instruments Incorporated 11
MSP430F22x2
MSP430F22x4
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Table 4. Terminal Functions, MSP430F22x4 (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
P2.4/TA2/A4/ G3 30 28 I/O ADC10, analog input A4
VREF+/VeREF+/OA1I0 Positive reference voltage output or input
OA1, analog input I/O
General-purpose digital I/O pin
P2.5/ROSC C2 3 40 I/O Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
XIN/P2.6 A2 6 3 I/O General-purpose digital I/O pin
Output terminal of crystal oscillator
XOUT/P2.7 A1 5 2 I/O General-purpose digital I/O pin(2)
General-purpose digital I/O pin
USCI_B0 slave transmit enable
P3.0/UCB0STE/UCA0CLK/ B5 11 9 I/O
A5 USCI_A0 clock input/output
ADC10, analog input A5
General-purpose digital I/O pin
P3.1/UCB0SIMO/ A6 12 10 I/O USCI_B0 SPI mode: slave in/master out
UCB0SDA USCI_B0 I2C mode: SDA I2C data
General-purpose digital I/O pin
P3.2/UCB0SOMI/UCB0SCL A7 13 11 I/O USCI_B0 SPI mode: slave out/master in
USCI_B0 I2C mode: SCL I2C clock
General-purpose digital I/O pin
P3.3/UCB0CLK/UCA0STE B6 14 12 I/O USCI_B0 clock input/output
USCI_A0 slave transmit enable
General-purpose digital I/O pin
P3.4/UCA0TXD/ G6 25 23 I/O USCI_A0 UART mode: transmit data output
UCA0SIMO USCI_A0 SPI mode: slave in/master out
General-purpose digital I/O pin
P3.5/UCA0RXD/ G5 26 24 I/O USCI_A0 UART mode: receive data input
UCA0SOMI USCI_A0 SPI mode: slave out/master in
General-purpose digital I/O pin
P3.6/A6/OA0I2 F4 27 25 I/O ADC10 analog input A6
OA0 analog input I2
General-purpose digital I/O pin
P3.7/A7/OA1I2 G4 28 26 I/O ADC10 analog input A7
OA1 analog input I2
General-purpose digital I/O pin
P4.0/TB0 D6 17 15 I/O Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
P4.1/TB1 D7 18 16 I/O Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
P4.2/TB2 E6 19 17 I/O Timer_B, capture: CCI2A input, compare: OUT2 output
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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Table 4. Terminal Functions, MSP430F22x4 (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
P4.3/TB0/A12/OA0O E7 20 18 I/O ADC10 analog input A12
OA0 analog output
General-purpose digital I/O pin
Timer_B, capture: CCI1B input, compare: OUT1 output
P4.4/TB1/A13/OA1O F7 21 19 I/O ADC10 analog input A13
OA1 analog output
General-purpose digital I/O pin
Timer_B, compare: OUT2 output
P4.5/TB2/A14/OA0I3 F6 22 20 I/O ADC10 analog input A14
OA0 analog input I3
General-purpose digital I/O pin
Timer_B, switch all TB0 to TB3 outputs to high impedance
P4.6/TBOUTH/A15/OA1I3 G7 23 21 I/O ADC10 analog input A15
OA1 analog input I3
General-purpose digital I/O pin
P4.7/TBCLK F5 24 22 I/O Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
RST/NMI/SBWTDIO B3 7 5 I Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
TEST/SBWTCK D1 1 37 I Spy-Bi-Wire test clock input during programming and test
C1,
D3,
DVCC 2 38, 39 Digital supply voltage
D4,
E4, E5
C6,
AVCC C7, 16 14 Analog supply voltage
D5
A3,
B1,
DVSS B2, 4 1, 4 Digital ground reference
C3,
C4
B7,
AVSS 15 13 Analog ground reference
C5
QFN Pad NA NA Pad NA QFN package pad; connection to DVSS recommended.
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General-PurposeRegister
ProgramCounter
StackPointer
StatusRegister
ConstantGenerator
General-PurposeRegister
General-PurposeRegister
General-PurposeRegister
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-PurposeRegister
General-PurposeRegister
R6
R7
General-PurposeRegister
General-PurposeRegister
R8
R9
General-PurposeRegister
General-PurposeRegister
R10
R11
General-PurposeRegister
General-PurposeRegister
R14
R15
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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SHORT-FORM DESCRIPTION
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 5 shows examples of the three types of
instruction formats; Table 6 shows the address
modes.
Table 5. Instruction Word Formats
INSTRUCTION FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 →R5
Single operands, destination only CALL R8 PC →(TOS), R8 →PC
Relative jump, unconditional/conditional JNE Jump-on-equal bit = 0
Table 6. Address Mode Descriptions
ADDRESS MODE S (1) D(2) SYNTAX EXAMPLE OPERATION
Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 →R11
Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) →M(6+R6)
Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) →M(TONI)
Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) →M(TCDAT)
Indirect ✓MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) →M(Tab+R6)
M(R10) →R11
Indirect autoincrement ✓MOV @Rn+,Rm MOV @R10+,R11 R10 + 2 →R10
Immediate ✓MOV #X,TONI MOV #45,TONI #45 →M(TONI)
(1) S = source
(2) D = destination
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Operating Modes
The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active. MCLK is disabled.
• Low-power mode 1 (LPM1)
– CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.
– DCO dc-generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator remains enabled.
– ACLK remains active.
• Low-power mode 3 (LPM3)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– ACLK remains active.
• Low-power mode 4 (LPM4)
– CPU is disabled.
– ACLK is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– Crystal oscillator is stopped.
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 7. Interrupt Vector Addresses
SYSTEM
INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY
INTERRUPT
Power-up PORIFG
External reset RSTIFG
Watchdog Reset 0FFFEh 31, highest
WDTIFG
Flash key violation KEYV(2)
PC out-of-range(1)
NMI NMIIFG (non)-maskable,
Oscillator fault OFIFG (non)-maskable, 0FFFCh 30
Flash memory access violation ACCVIFG(2)(3) (non)-maskable
Timer_B3 TBCCR0 CCIFG(4) maskable 0FFFAh 29
TBCCR1 and TBCCR2 CCIFGs,
Timer_B3 maskable 0FFF8h 28
TBIFG(2)(4)
0FFF6h 27
Watchdog Timer WDTIFG maskable 0FFF4h 26
Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25
TACCR1 CCIFG
Timer_A3 TACCR2 CCIFG maskable 0FFF0h 24
TAIFG(2)(4)
USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG(2) maskable 0FFEEh 23
USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG(2) maskable 0FFECh 22
ADC10 ADC10IFG(4) maskable 0FFEAh 21
0FFE8h 20
I/O Port P2 P2IFG.0 to P2IFG.7(2)(4) maskable 0FFE6h 19
(eight flags)
I/O Port P1 P1IFG.0 to P1IFG.7(2)(4) maskable 0FFE4h 18
(eight flags) 0FFE2h 17
0FFE0h 16
(5) 0FFDEh 15
(6) 0FFDCh to 0FFC0h 14 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
(4) Interrupt flags are located in the module.
(5) This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
(6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw Bit can be read and written.
rw-0, 1 Bit can be read and written. It is Reset or Set by PUC.
rw-(0), (1) Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 8. Interrupt Enable 1
Address 7 6 5 4 3 2 1 0
00h ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0
WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
OFIE Oscillator fault interrupt enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Table 9. Interrupt Enable 2
Address 7 6 5 4 3 2 1 0
01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw-0 rw-0 rw-0 rw-0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
Table 10. Interrupt Flag Register 1
Address 7 6 5 4 3 2 1 0
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw-0 rw-(0) rw-(1) rw-1 rw-(0)
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
PORIFG Power-on reset interrupt flag. Set on VCC power up.
NMIIFG Set via RST/NMI pin
Table 11. Interrupt Flag Register 2
Address 7 6 5 4 3 2 1 0
03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
rw-1 rw-0 rw-1 rw-0
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
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Memory Organization
Table 12. Memory Organization
MSP430F223x MSP430F225x MSP430F227x
Memory Size 8KB Flash 16KB Flash 32KB Flash
Main: interrupt vector Flash 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h
Main: code memory Flash 0FFFFh-0E000h 0FFFFh-0C000h 0FFFFh-08000h
Size 256 Byte 256 Byte 256 Byte
Information memory Flash 010FFh-01000h 010FFh-01000h 010FFh-01000h
Size 1KB 1KB 1KB
Boot memory ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h
512 Byte 512 Byte 1KB
RAM Size 03FFh-0200h 03FFh-0200h 05FFh-0200h
16-bit 01FFh-0100h 01FFh-0100h 01FFh-0100h
Peripherals 8-bit 0FFh-010h 0FFh-010h 0FFh-010h
8-bit SFR 0Fh-00h 0Fh-00h 0Fh-00h
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap
Loader User’s Guide (SLAU319).
Table 13. BSL Function Pins
BSL FUNCTION DA PACKAGE PINS RHA PACKAGE PINS YFF PACKAGE PINS
Data transmit 32 - P1.1 30 - P1.1 G3 - P1.1
Data receive 10 - P2.2 8 - P2.2 A5 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and
a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in
less than 1 µs. The basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal very-
low-power LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 14. DCO Calibration Data
(Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY CALIBRATION REGISTER SIZE ADDRESS
CALBC1_1MHZ byte 010FFh
1 MHz CALDCO_1MHZ byte 010FEh
CALBC1_8MHZ byte 010FDh
8 MHz CALDCO_8MHZ byte 010FCh
CALBC1_12MHZ byte 010FBh
12 MHz CALDCO_12MHZ byte 010FAh
CALBC1_16MHZ byte 010F9h
16 MHz CALDCO_16MHZ byte 010F8h
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and
write data is ignored.
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 15. Timer_A3 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT
BLOCK
DA RHA YFF DA RHA YFF
SIGNAL NAME SIGNAL
31 - P1.0 29 - P1.0 F2 - P1.0 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
9 - P2.1 7 - P2.1 B4 - P2.1 TAINCLK INCLK
32 - P1.1 30 - P1.1 G2 - P1.1 TA0 CCI0A CCR0 TA0 32 - P1.1 30 - P1.1 G2 - P1.1
10 - P2.2 8 - P2.2 A5 - P2.2 TA0 CCI0B 10 - P2.2 8 - P2.2 A5 - P2.2
VSS GND 36 - P1.5 34 - P1.5 E1 - P1.5
VCC VCC
33 - P1.2 31 - P1.2 E2 - P1.2 TA1 CCI1A CCR1 TA1 33 - P1.2 31 - P1.2 E2 - P1.2
29 - P2.3 27 - P2.3 F3 - P2.3 TA1 CCI1B 29 - P2.3 27 - P2.3 F3 - P2.3
VSS GND 37 - P1.6 35 - P1.6 E3 - P1.6
VCC VCC
34 - P1.3 32 - P1.3 G1 - P1.3 TA2 CCI2A CCR2 TA2 34 - P1.3 32 - P1.3 G1 - P1.3
ACLK CCI2B 30 - P2.4 28 - P2.4 G3 - P2.4
(internal)
VSS GND 38 - P1.7 36 - P1.7 D2 - P1.7
VCC VCC
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Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 16. Timer_B3 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT
BLOCK
DA RHA YFF DA RHA YFF
SIGNAL NAME SIGNAL
24 - P4.7 22 - P4.7 F5 - P4.7 TBCLK TBCLK Timer NA
ACLK ACLK
SMCLK SMCLK
24 - P4.7 22 - P4.7 F5 - P4.7 TBCLK INCLK
17 - P4.0 15 - P4.0 D6 - P4.0 TB0 CCI0A CCR0 TB0 17 - P4.0 15 - P4.0 D6 - P4.0
20 - P4.3 18 - P4.3 E7 - P4.3 TB0 CCI0B 20 - P4.3 18 - P4.3 E7 - P4.3
VSS GND
VCC VCC
18 - P4.1 16 - P4.1 D7 - P4.1 TB1 CCI1A CCR1 TB1 18 - P4.1 16 - P4.1 D7 - P4.1
21 - P4.4 19 - P4.4 F7 - P4.4 TB1 CCI1B 21 - P4.4 19 - P4.4 F7 - P4.4
VSS GND
VCC VCC
19 - P4.2 17 - P4.2 E6 - P4.2 TB2 CCI2A CCR2 TB2 19 - P4.2 17 - P4.2 E6 - P4.2
ACLK CCI2B 22 - P4.5 20 - P4.5 F6 - P4.5
(internal)
VSS GND
VCC VCC
Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.
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Operational Amplifier (OA) (MSP430F22x4 only)
The MSP430F22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input and
output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA
op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
Table 17. OA0 Signal Connections
ANALOG INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME
DA RHA YFF
8 - A0 6 - A0 B4 - A0 OA0I0 OAxI0
10 - A2 8 - A2 B5 - A2 OA0I1 OA0I1
10 - A2 8 - A2 B5 - A2 OA0I1 OAxI1
27 - A6 25 - A6 F4 - A6 OA0I2 OAxIA
22 - A14 20 - A14 F6 - A14 OA0I3 OAxIB
Table 18. OA1 Signal Connections
ANALOG INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME
DA RHA YFF
30 - A4 28 - A4 G3 - A4 OA1I0 OAxI0
10 - A2 8 - A2 B5 - A2 OA0I1 OA0I1
29 - A3 27 - A3 F3 - A3 OA1I1 OAxI1
28 - A7 26 - A7 G4 - A7 OA1I2 OAxIA
23 - A15 21 - A15 G7 - A15 OA1I3 OAxIB
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Peripheral File Map
Table 19. Peripherals With Word Access
MODULE REGISTER NAME SHORT NAME ADDRESS
OFFSET
ADC10 ADC data transfer start address ADC10SA 1BCh
ADC memory ADC10MEM 1B4h
ADC control register 1 ADC10CTL1 1B2h
ADC control register 0 ADC10CTL0 1B0h
ADC analog enable 0 ADC10AE0 04Ah
ADC analog enable 1 ADC10AE1 04Bh
ADC data transfer control register 1 ADC10DTC1 049h
ADC data transfer control register 0 ADC10DTC0 048h
Timer_B Capture/compare register TBCCR2 0196h
Capture/compare register TBCCR1 0194h
Capture/compare register TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control TBCCTL2 0186h
Capture/compare control TBCCTL1 0184h
Capture/compare control TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A Capture/compare register TACCR2 0176h
Capture/compare register TACCR1 0174h
Capture/compare register TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control TACCTL2 0166h
Capture/compare control TACCTL1 0164h
Capture/compare control TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash Memory Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
Watchdog Timer+ Watchdog/timer control WDTCTL 0120h
Copyright © 2006–2012, Texas Instruments Incorporated 23
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 20. Peripherals With Byte Access
MODULE REGISTER NAME SHORT NAME ADDRESS
OFFSET
OA1 (MSP430F22x4 only) Operational Amplifier 1 control register 1 OA1CTL1 0C3h
Operational Amplifier 1 control register 1 OA1CTL0 0C2h
OA0 (MSP430F22x4 only) Operational Amplifier 0 control register 1 OA0CTL1 0C1h
Operational Amplifier 0 control register 1 OA0CTL0 0C0h
USCI_B0 USCI_B0 transmit buffer UCB0TXBUF 06Fh
USCI_B0 receive buffer UCB0RXBUF 06Eh
USCI_B0 status UCB0STAT 06Dh
USCI_B0 bit rate control 1 UCB0BR1 06Bh
USCI_B0 bit rate control 0 UCB0BR0 06Ah
USCI_B0 control 1 UCB0CTL1 069h
USCI_B0 control 0 UCB0CTL0 068h
USCI_B0 I2C slave address UCB0SA 011Ah
USCI_B0 I2C own address UCB0OA 0118h
USCI_A0 USCI_A0 transmit buffer UCA0TXBUF 067h
USCI_A0 receive buffer UCA0RXBUF 066h
USCI_A0 status UCA0STAT 065h
USCI_A0 modulation control UCA0MCTL 064h
USCI_A0 baud rate control 1 UCA0BR1 063h
USCI_A0 baud rate control 0 UCA0BR0 062h
USCI_A0 control 1 UCA0CTL1 061h
USCI_A0 control 0 UCA0CTL0 060h
USCI_A0 IrDA receive control UCA0IRRCTL 05Fh
USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh
USCI_A0 auto baud rate control UCA0ABCTL 05Dh
Basic Clock System+ Basic clock system control 3 BCSCTL3 053h
Basic clock system control 2 BCSCTL2 058h
Basic clock system control 1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
Port P4 Port P4 resistor enable P4REN 011h
Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 resistor enable P3REN 010h
Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 resistor enable P2REN 02Fh
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
24 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Table 20. Peripherals With Byte Access (continued)
MODULE REGISTER NAME SHORT NAME ADDRESS
OFFSET
Port P1 Port P1 resistor enable P1REN 027h
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Function SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h
Copyright © 2006–2012, Texas Instruments Incorporated 25
4.15 MHz
12 MHz
16 MHz
1.8 V 2.2 V 2.7 V 3.3 V 3.6 V
Supply Voltage −V
System Frequency −MHz
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Legend:
7.5 MHz
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Absolute Maximum Ratings(1)
Voltage applied at VCC to VSS -0.3 V to 4.1 V
Voltage applied to any pin (2) -0.3 V to VCC + 0.3 V
Diode current at any device terminal ±2 mA
Unprogrammed device -55°C to 150°C
Storage temperature, Tstg (3) Programmed device -55°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions(1)(2)
MIN NOM MAX UNIT
During program 1.8 3.6 V
execution
VCC Supply voltage AVCC = DVCC = VCC During program/erase 2.2 3.6 V
flash memory
VSS Supply voltage AVSS = DVSS = VSS 0 V
I version -40 85
TAOperating free-air temperature °C
T version -40 105
VCC = 1.8 V, Duty cycle = 50% ±10% dc 4.15
Processor frequency
fSYSTEM (maximum MCLK frequency)(1)(2) VCC = 2.7 V, Duty cycle = 50% ±10% dc 12 MHz
(see Figure 1)VCC ≥3.3 V, Duty cycle = 50% ±10% dc 16
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Operating Area
26 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Active Mode Supply Current (into DVCC + AVCC) Excluding External Current (1)(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz, 2.2 V 270 390
fACLK = 32768 Hz,
Program executes in flash,
Active mode (AM)
IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µA
current (1 MHz) 3 V 390 550
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 1 MHz, 2.2 V 240
fACLK = 32768 Hz,
Program executes in RAM,
Active mode (AM)
IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µA
current (1 MHz) 3.3 V 340
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK = fACLK = 32768 Hz/8 = -40°C to 5 9
4096 Hz, 85°C 2.2 V
fDCO = 0 Hz, 105°C 18
Active mode (AM) Program executes in flash,
IAM,4kHz µA
-40°C to
current (4 kHz) SELMx = 11, SELS = 1, 6 10
85°C
DIVMx = DIVSx = DIVAx = 11, 3 V
CPUOFF = 0, SCG0 = 1, SCG1 = 0, 105°C 20
OSCOFF = 0 -40°C to 60 85
85°C
fMCLK = fSMCLK = fDCO(0, 0) ≈100 kHz, 2.2 V
fACLK = 0 Hz, 105°C 95
Active mode (AM)
IAM,100kHz Program executes in flash, µA
current (100 kHz) -40°C to
RSELx = 0, DCOx = 0, CPUOFF = 0, 72 95
85°C 3 V
SCG0 = 0, SCG1 = 0, OSCOFF = 1 105°C 105
(1) All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Copyright © 2006–2012, Texas Instruments Incorporated 27
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
1.5 2.0 2.5 3.0 3.5 4.0
VCC − Supply Voltage − V
Active Mode Current − mA
fDCO = 1 MHz
fDCO = 8 MHz
fDCO = 12 MHz
fDCO = 16 MHz
0.0
1.0
2.0
3.0
4.0
5.0
0.0 4.0 8.0 12.0 16.0
fDCO − DCO Frequency − MHz
Active Mode Current − mA
TA= 25 °C
TA= 85 °C
VCC = 2.2 V
VCC = 3 V
TA= 25 °C
TA= 85 °C
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC)
ACTIVE-MODE CURRENT
vs ACTIVE-MODE CURRENT
SUPPLY VOLTAGE vs
TA= 25°C DCO FREQUENCY
Figure 2. Figure 3.
28 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current (1)(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
fMCLK = 0 MHz, 2.2 V 75 90
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 0
ILPM0,1MHz BCSCTL1 = CALBC1_1MHZ, µA
(LPM0) current(3) 3 V 90 120
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
fMCLK = 0 MHz, 2.2 V 37 48
fSMCLK = fDCO(0, 0) ≈100 kHz,
Low-power mode 0 fACLK = 0 Hz,
ILPM0,100kHz µA
(LPM0) current(3) RSELx = 0, DCOx = 0, 3 V 41 65
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 1 -40°C to
fMCLK = fSMCLK = 0 MHz, 22 29
85°C
fDCO = 1 MHz, 2.2 V
fACLK = 32768 Hz, 105°C 31
Low-power mode 2
ILPM2 BCSCTL1 = CALBC1_1MHZ, µA
(LPM2) current(4) -40°C to
DCOCTL = CALDCO_1MHZ, 25 32
85°C 3 V
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0 105°C 34
-40°C 0.7 1.4
25°C 0.7 1.4
2.2 V
85°C 2.4 3.3
fDCO = fMCLK = fSMCLK = 0 MHz, 105°C 5 10
Low-power mode 3 fACLK = 32768 Hz,
ILPM3,LFXT1 µA
(LPM3) current(4) CPUOFF = 1, SCG0 = 1, -40°C 0.9 1.5
SCG1 = 1, OSCOFF = 0 25°C 0.9 1.5
3 V
85°C 2.6 3.8
105°C 6 12
-40°C 0.4 1
25°C 0.5 1
2.2 V
85°C 1.8 2.9
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator 105°C 4.5 9
Low-power mode 3
ILPM3,VLO (VLO), µA
current, (LPM3)(4) -40°C 0.5 1.2
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0 25°C 0.6 1.2
3 V
85°C 2.1 3.3
105°C 5.5 11
-40°C 0.1 0.5
fDCO = fMCLK = fSMCLK = 0 MHz, 25°C 0.1 0.5
Low-power mode 4 fACLK = 0 Hz, 2.2 V/
ILPM4 µA
(LPM4) current(5) CPUOFF = 1, SCG0 = 1, 3 V
85°C 1.5 3
SCG1 = 1, OSCOFF = 1 105°C 4.5 9
(1) All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
Copyright © 2006–2012, Texas Instruments Incorporated 29
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
0.45 VCC 0.75 VCC
VIT+ Positive-going input threshold voltage 2.2 V 1 1.65 V
3 V 1.35 2.25
0.25 VCC 0.55 VCC
VIT- Negative-going input threshold voltage 2.2 V 0.55 1.20 V
3 V 0.75 1.65
2.2 V 0.1 1
Vhys Input voltage hysteresis (VIT+ - VIT-) V
3 V 0.3 1
For pullup: VIN = VSS,
RPull Pullup/pulldown resistor 3 V 20 35 50 kΩ
For pulldown: VIN = VCC
CIInput capacitance VIN = VSS or VCC 5 pF
Inputs (Ports P1, P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Port P1, P2: P1.x to P2.x, External trigger
t(int) External interrupt timing 2.2 V, 3 V 20 ns
pulse width to set interrupt flag(1)
(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int) .
Leakage Current (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Ilkg(Px.y) High-impedance leakage current (1) (2) 2.2 V, 3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
30 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Outputs (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
IOH(max) = -1.5 mA (1) VCC - 0.25 VCC
2.2 V
IOH(max) = -6 mA (2) VCC - 0.6 VCC
VOH High-level output voltage V
IOH(max) = -1.5 mA(1) VCC - 0.25 VCC
3 V
IOH(max) = -6 mA(2) VCC - 0.6 VCC
IOL(max) = 1.5 mA(1) VSS VSS + 0.25
2.2 V
IOL(max) = 6 mA(2) VSS VSS + 0.6
VOL Low-level output voltage V
IOL(max) = 1.5 mA(1) VSS VSS + 0.25
3 V
IOL(max) = 6 mA(2) VSS VSS + 0.6
(1) The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2.2 V 10
P1.4/SMCLK, CL= 20 pF,
fPx.y Port output frequency (with load) MHz
RL= 1 kΩagainst VCC/2(1)(2) 3 V 12
2.2 V 12
fPort_CLK Clock output frequency P2.0/ACLK, P1.4/SMCLK, CL= 20 pF(2) MHz
3 V 16
(1) Alternatively, a resistive divider with two 2-kΩresistors between VCC and VSS is used as load. The output is connected to the center tap
of the divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Copyright © 2006–2012, Texas Instruments Incorporated 31
VOH − High-Level Output V oltage − V
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P4.5
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
VOH − High-Level Output V oltage − V
−50.0
−40.0
−30.0
−20.0
−10.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P4.5
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
VOL − Low-Level Output V oltage − V
0.0
5.0
10.0
15.0
20.0
25.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P4.5
TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
VOL − Low-Level Output V oltage − V
0.0
10.0
20.0
30.0
40.0
50.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P4.5 TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Typical Characteristics - Outputs
One output loaded at a time.
TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT
vs vs
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
Figure 4. Figure 5.
TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs vs
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
Figure 6. Figure 7.
32 Copyright © 2006–2012, Texas Instruments Incorporated
0
1
td(BOR)
VCC
V(B_IT−)
Vhys(B_IT−)
VCC(start)
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
POR/Brownout Reset (BOR) (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
0.7 ×
VCC(start) See Figure 8 dVCC /dt ≤3 V/s V
V(B_IT-)
V(B_IT-) See Figure 8 through Figure 10 dVCC /dt ≤3 V/s 1.71 V
Vhys(B_IT-) See Figure 8 dVCC /dt ≤3 V/s 70 130 210 mV
td(BOR) See Figure 8 2000 µs
Pulse length needed at RST/NMI pin
t(reset) 3 V 2 µs
to accepted reset internally
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-) is ≤1.8 V.
(2) During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-) . The default DCO settings
must not be changed until VCC ≥VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
Copyright © 2006–2012, Texas Instruments Incorporated 33
VCC
0
0.5
1
1.5
2
VCC(drop)
tpw
tpw − Pulse Width − µs
VCC(drop) − V
3 V
0.001 1 1000 tftr
tpw − Pulse Width − µs
tf= tr
Typical Conditions
VCC = 3 V
VCC(drop)
VCC
3 V
tpw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1 ns 1 ns
tpw − Pulse Width − µs
VCC(drop) − V
tpw − Pulse Width − µs
VCC = 3 V
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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Typical Characteristics - POR/Brownout Reset (BOR)
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
34 Copyright © 2006–2012, Texas Instruments Incorporated
DCO(RSEL,DCO) DCO(RSEL,DCO+1)
average DCO(RSEL,DCO) DCO(RSEL,DCO+1)
32 × f × f
f = MOD × f + (32 – MOD) × f
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Main DCO Characteristics
• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
• DCO control bits DCOx have a step size as defined by parameter SDCO .
• Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
RSELx < 14 1.8 3.6
VCC Supply voltage range RSELx = 14 2.2 3.6 V
RSELx = 15 3.0 3.6
fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V, 3 V 0.06 0.14 MHz
fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 2.2 V, 3 V 0.07 0.17 MHz
fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 2.2 V, 3 V 0.10 0.20 MHz
fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 2.2 V, 3 V 0.14 0.28 MHz
fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 2.2 V, 3 V 0.20 0.40 MHz
fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 2.2 V, 3 V 0.28 0.54 MHz
fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 2.2 V, 3 V 0.39 0.77 MHz
fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 2.2 V, 3 V 0.54 1.06 MHz
fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 2.2 V, 3 V 0.80 1.50 MHz
fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 2.2 V, 3 V 1.10 2.10 MHz
fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 2.2 V, 3 V 1.60 3.00 MHz
fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 2.2 V, 3 V 2.50 4.30 MHz
fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 2.2 V, 3 V 3.00 5.50 MHz
fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 2.2 V, 3 V 4.30 7.30 MHz
fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 2.2 V, 3 V 6.00 9.60 MHz
fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 2.2 V, 3 V 8.60 13.9 MHz
fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3 V 12.0 18.5 MHz
fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3 V 16.0 26.0 MHz
Frequency step between
SRSEL SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO) 2.2 V, 3 V 1.55 ratio
range RSEL and RSEL+1
Frequency step between tap
SDCO SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO) 2.2 V, 3 V 1.05 1.08 1.12 ratio
DCO and DCO+1
Duty cycle Measured at P1.4/SMCLK 2.2 V, 3 V 40 50 60 %
Copyright © 2006–2012, Texas Instruments Incorporated 35
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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Calibrated DCO Frequencies - Tolerance at Calibration
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
Frequency tolerance at calibration 25°C 3 V -1 ±0.2 +1 %
BCSCTL1 = CALBC1_1MHZ,
fCAL(1MHz) 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 25°C 3 V 0.990 1 1.010 MHz
Gating time: 5 ms
BCSCTL1 = CALBC1_8MHZ,
fCAL(8MHz) 8-MHz calibration value DCOCTL = CALDCO_8MHZ, 25°C 3 V 7.920 8 8.080 MHz
Gating time: 5 ms
BCSCTL1 = CALBC1_12MHZ,
fCAL(12MHz) 12-MHz calibration value DCOCTL = CALDCO_12MHZ, 25°C 3 V 11.88 12 12.12 MHz
Gating time: 5 ms
BCSCTL1 = CALBC1_16MHZ,
fCAL(16MHz) 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 25°C 3 V 15.84 16 16.16 MHz
Gating time: 2 ms
Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
1-MHz tolerance over 0°C to 85°C 3 V -2.5 ±0.5 +2.5 %
temperature
8-MHz tolerance over 0°C to 85°C 3 V -2.5 ±1.0 +2.5 %
temperature
12-MHz tolerance over 0°C to 85°C 3 V -2.5 ±1.0 +2.5 %
temperature
16-MHz tolerance over 0°C to 85°C 3 V -3 ±2.0 +3 %
temperature 2.2 V 0.97 1 1.03
BCSCTL1 = CALBC1_1MHZ,
fCAL(1MHz) 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 0°C to 85°C 3 V 0.975 1 1.025 MHz
Gating time: 5 ms 3.6 V 0.97 1 1.03
2.2 V 7.76 8 8.4
BCSCTL1 = CALBC1_8MHZ,
fCAL(8MHz) 8-MHz calibration value DCOCTL = CALDCO_8MHZ, 0°C to 85°C 3 V 7.8 8 8.2 MHz
Gating time: 5 ms 3.6 V 7.6 8 8.24
2.2 V 11.7 12 12.3
BCSCTL1 = CALBC1_12MHZ,
fCAL(12MHz) 12-MHz calibration value DCOCTL = CALDCO_12MHZ, 0°C to 85°C 3 V 11.7 12 12.3 MHz
Gating time: 5 ms 3.6 V 11.7 12 12.3
BCSCTL1 = CALBC1_16MHZ, 3 V 15.52 16 16.48
fCAL(16MHz) 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 0°C to 85°C MHz
3.6 V 15 16 16.48
Gating time: 2 ms
36 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
1-MHz tolerance over VCC 25°C 1.8 V to 3.6 V -3 ±2 +3 %
8-MHz tolerance over VCC 25°C 1.8 V to 3.6 V -3 ±2 +3 %
12-MHz tolerance over VCC 25°C 2.2 V to 3.6 V -3 ±2 +3 %
16-MHz tolerance over VCC 25°C 3 V to 3.6 V -6 ±2 +3 %
BCSCTL1 = CALBC1_1MHZ,
fCAL(1MHz) 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 25°C 1.8 V to 3.6 V 0.97 1 1.03 MHz
Gating time: 5 ms
BCSCTL1 = CALBC1_8MHZ,
fCAL(8MHz) 8-MHz calibration value DCOCTL = CALDCO_8MHZ, 25°C 1.8 V to 3.6 V 7.76 8 8.24 MHz
Gating time: 5 ms
BCSCTL1 = CALBC1_12MHZ,
fCAL(12MHz) 12-MHz calibration value DCOCTL = CALDCO_12MHZ, 25°C 2.2 V to 3.6 V 11.64 12 12.36 MHz
Gating time: 5 ms
BCSCTL1 = CALBC1_16MHZ,
fCAL(16MHz) 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 25°C 3 V to 3.6 V 15 16 16.48 MHz
Gating time: 2 ms
Calibrated DCO Frequencies - Overall Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
1-MHz tolerance I: -40°C to 85°C 1.8 V to 3.6 V -5 ±2 +5 %
overall T: -40°C to 105°C
8-MHz tolerance I: -40°C to 85°C 1.8 V to 3.6 V -5 ±2 +5 %
overall T: -40°C to 105°C
12-MHz I: -40°C to 85°C 2.2 V to 3.6 V -5 ±2 +5 %
tolerance overall T: -40°C to 105°C
16-MHz I: -40°C to 85°C 3 V to 3.6 V -6 ±3 +6 %
tolerance overall T: -40°C to 105°C
BCSCTL1 = CALBC1_1MHZ,
1-MHz I: -40°C to 85°C
fCAL(1MHz) DCOCTL = CALDCO_1MHZ, 1.8 V to 3.6 V 0.95 1 1.05 MHz
calibration value T: -40°C to 105°C
Gating time: 5 ms
BCSCTL1 = CALBC1_8MHZ,
8-MHz I: -40°C to 85°C
fCAL(8MHz) DCOCTL = CALDCO_8MHZ, 1.8 V to 3.6 V 7.6 8 8.4 MHz
calibration value T: -40°C to 105°C
Gating time: 5 ms
BCSCTL1 = CALBC1_12MHZ,
12-MHz I: -40°C to 85°C
fCAL(12MHz) DCOCTL = CALDCO_12MHZ, 2.2 V to 3.6 V 11.4 12 12.6 MHz
calibration value T: -40°C to 105°C
Gating time: 5 ms
BCSCTL1 = CALBC1_16MHZ,
16-MHz I: -40°C to 85°C
fCAL(16MHz) DCOCTL = CALDCO_16MHZ, 3 V to 3.6 V 15 16 17 MHz
calibration value T: -40°C to 105°C
Gating time: 2 ms
Copyright © 2006–2012, Texas Instruments Incorporated 37
TA− Temperature − °C
0.97
0.98
0.99
1.00
1.01
1.02
1.03
−50.0 −25.0 0.0 25.0 50.0 75.0 100.0
Frequency − MHz
VCC = 1.8 V
VCC = 2.2 V
VCC = 3.0 V
VCC = 3.6 V
VCC − Supply Voltage − V
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.5 2.0 2.5 3.0 3.5 4.0
Frequency − MHz
TA= −40 °C
TA= 25 °C
TA= 85 °C
TA= 105 °C
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Typical Characteristics - Calibrated 1-MHz DCO Frequency
CALIBRATED 1-MHz FREQUENCY CALIBRATED 1-MHz FREQUENCY
vs vs
TEMPERATURE SUPPLY VOLTAGE
Figure 11. Figure 12.
38 Copyright © 2006–2012, Texas Instruments Incorporated
DCO Frequency − MHz
0.10
1.00
10.00
0.10 1.00 10.00
RSELx = 0...11
RSELx = 12...15
DCO Wake-Up Time − µs
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
BCSCTL1 = CALBC1_1MHZ, 2
DCOCTL = CALDCO_1MHZ
BCSCTL1 = CALBC1_8MHZ, 2.2 V, 3 V 1.5
DCOCTL = CALDCO_8MHZ
DCO clock wake-up time
tDCO,LPM3/4 µs
from LPM3/4 (1) BCSCTL1 = CALBC1_12MHZ, 1
DCOCTL = CALDCO_12MHZ
BCSCTL1 = CALBC1_16MHZ, 3 V 1
DCOCTL = CALDCO_16MHZ
CPU wake-up time from 1 / fMCLK +
tCPU,LPM3/4 LPM3/4 (2) tClock,LPM3/4
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
CLOCK WAKE-UP TIME FROM LPM3
vs
DCO FREQUENCY
Figure 13.
Copyright © 2006–2012, Texas Instruments Incorporated 39
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
−50.0 −25.0 0.0 25.0 50.0 75.0 100.0
TA− Temperature − C
DCO Frequency − MHz
ROSC = 100k
ROSC = 270k
ROSC = 1M
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.0 2.5 3.0 3.5 4.0
VCC − Supply Voltage − V
DCO Frequency − MHz
ROSC = 100k
ROSC = 270k
ROSC = 1M
0.01
0.10
1.00
10.00
10.00 100.00 1000.00 10000.00
ROSC − External Resistor − kW
DCO Frequency − MHz
RSELx = 4
0.01
0.10
1.00
10.00
10.00 100.00 1000.00 10000.00
ROSC − External Resistor − kW
DCO Frequency − MHz
RSELx = 4
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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DCO With External Resistor ROSC(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
DCOR = 1, 2.2 V 1.8
fDCO,ROSC DCO output frequency with ROSC RSELx = 4, DCOx = 3, MODx = 0, MHz
3 V 1.95
TA= 25°C
DCOR = 1,
DTTemperature drift 2.2 V, 3 V ±0.1 %/°C
RSELx = 4, DCOx = 3, MODx = 0
DCOR = 1,
DVDrift with VCC 2.2 V, 3 V 10 %/V
RSELx = 4, DCOx = 3, MODx = 0
(1) ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK= ±50 ppm/°C.
Typical Characteristics - DCO With External Resistor ROSC
DCO FREQUENCY DCO FREQUENCY
vs vs
ROSC ROSC
VCC = 2.2 V, TA= 25°C VCC = 3 V, TA= 25°C
Figure 14. Figure 15.
DCO FREQUENCY DCO FREQUENCY
vs vs
TEMPERATURE SUPPLY VOLTAGE
VCC = 3 V TA= 25°C
Figure 16. Figure 17.
40 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Crystal Oscillator LFXT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
LFXT1 oscillator crystal
fLFXT1,LF XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz
frequency, LF mode 0, 1
LFXT1 oscillator logic level
fLFXT1,LF,logic square wave input frequency, XTS = 0, LFXT1Sx = 3 1.8 V to 3.6 V 10000 32768 50000 Hz
LF mode XTS = 0, LFXT1Sx = 0, 500
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
OALF kΩ
LF crystals XTS = 0, LFXT1Sx = 0, 200
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0 1
XTS = 0, XCAPx = 1 5.5
Integrated effective load
CL,eff pF
capacitance, LF mode(2) XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 11
XTS = 0, Measured at P2.0/ACLK,
Duty cycle, LF mode 2.2 V, 3 V 30 50 70 %
fLFXT1,LF = 32768 Hz
Oscillator fault frequency,
fFault,LF XTS = 0, LFXT1Sx = 3(4) 2.2 V, 3 V 10 10000 Hz
LF mode(3)
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the crystal that is used.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TAVCC MIN TYP MAX UNIT
-40°C to 85°C 4 12 20
fVLO VLO frequency 2.2 V, 3 V kHz
105°C 22
I: -40°C to 85°C
dfVLO/dT VLO frequency temperature drift (1) 2.2 V, 3 V 0.5 %/°C
T: -40°C to 105°C
dfVLO/dVCC VLO frequency supply voltage drift (2) 25°C 1.8 V to 3.6 V 4 %/V
(1) Calculated using the box method:
I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
T version: [MAX(-40...105°C) - MIN(-40...105°C)]/MIN(-40...105°C)/[105°C - (-40°C)]
(2) Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
Copyright © 2006–2012, Texas Instruments Incorporated 41
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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Crystal Oscillator LFXT1, High-Frequency Mode(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
LFXT1 oscillator crystal
fLFXT1,HF0 XTS = 1, LFXT1Sx = 0 1.8 V to 3.6 V 0.4 1 MHz
frequency, HF mode 0
LFXT1 oscillator crystal
fLFXT1,HF1 XTS = 1, LFXT1Sx = 1 1.8 V to 3.6 V 1 4 MHz
frequency, HF mode 1 1.8 V to 3.6 V 2 10
LFXT1 oscillator crystal
fLFXT1,HF2 XTS = 1, LFXT1Sx = 2 2.2 V to 3.6 V 2 12 MHz
frequency, HF mode 2 3 V to 3.6 V 2 16
1.8 V to 3.6 V 0.4 10
LFXT1 oscillator logic-level
fLFXT1,HF,logic square-wave input frequency, HF XTS = 1, LFXT1Sx = 3 2.2 V to 3.6 V 0.4 12 MHz
mode 3 V to 3.6 V 0.4 16
XTS = 1, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz, 2700
CL,eff = 15 pF
Oscillation allowance for HF XTS = 1, LFXT1Sx = 1,
OAHF crystals (see Figure 18 and fLFXT1,HF = 4 MHz, 800 Ω
Figure 19) CL,eff = 15 pF
XTS = 1, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz, 300
CL,eff = 15 pF
Integrated effective load
CL,eff XTS = 1(3) 1 pF
capacitance, HF mode(2)
XTS = 1,
Measured at P2.0/ACLK, 40 50 60
fLFXT1,HF = 10 MHz
Duty cycle, HF mode 2.2 V, 3 V %
XTS = 1,
Measured at P2.0/ACLK, 40 50 60
fLFXT1,HF = 16 MHz
fFault,HF Oscillator fault frequency(4) XTS = 1, LFXT1Sx = 3(5) 2.2 V, 3 V 30 300 kHz
(1) To improve EMI on the XT1 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
(3) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
(5) Measured with logic-level input frequency, but also applies to operation with crystals.
42 Copyright © 2006–2012, Texas Instruments Incorporated
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
800.0
0.0 4.0 8.0 12.0 16.0 20.0
Crystal Frequency − MHz
XT Oscillator Supply Current − uA
LFXT1Sx = 1
LFXT1Sx = 3
LFXT1Sx = 2
Crystal Frequency − MHz
10.00
100.00
1000.00
10000.00
100000.00
0.10 1.00 10.00 100.00
Oscillation Allowance − Ohms
LFXT1Sx = 1
LFXT1Sx = 3
LFXT1Sx = 2
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
OSCILLATION ALLOWANCE OSCILLATOR SUPPLY CURRENT
vs vs
CRYSTAL FREQUENCY CRYSTAL FREQUENCY
CL,eff = 15 pF, TA= 25°C CL,eff = 15 pF, TA= 25°C
Figure 18. Figure 19.
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK 2.2 V 10
fTA Timer_A clock frequency External: TACLK, INCLK MHz
3 V 16
Duty cycle = 50% ± 10%
tTA,cap Timer_A capture timing TA0, TA1, TA2 2.2 V, 3 V 20 ns
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK 2.2 V 10
fTB Timer_B clock frequency External: TACLK, INCLK MHz
3 V 16
Duty cycle = 50% ± 10%
tTB,cap Timer_B capture timing TB0, TB1, TB2 2.2 V, 3 V 20 ns
Copyright © 2006–2012, Texas Instruments Incorporated 43
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
fBITCLK 2.2 V, 3 V 1 MHz
(equals baud rate in MBaud) 2.2 V 50 150 600
tτUART receive deglitch time(1) ns
3 V 50 100 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 20 and Figure 21)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SMCLK, ACLK
fUSCI USCI input clock frequency fSYSTEM MHz
Duty cycle = 50% ± 10% 2.2 V 110
tSU,MI SOMI input data setup time ns
3 V 75
2.2 V 0
tHD,MI SOMI input data hold time ns
3 V 0
2.2 V 30
UCLK edge to SIMO valid,
tVALID,MO SIMO output data valid time ns
CL= 20 pF 3 V 20
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
USCI (SPI Slave Mode)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 22 and Figure 23)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tSTE,LEAD STE lead time, STE low to clock 2.2 V, 3 V 50 ns
tSTE,LAG STE lag time, Last clock to STE high 2.2 V, 3 V 10 ns
tSTE,ACC STE access time, STE low to SOMI data out 2.2 V, 3 V 50 ns
STE disable time, STE high to SOMI high
tSTE,DIS 2.2 V, 3 V 50 ns
impedance 2.2 V 20
tSU,SI SIMO input data setup time ns
3 V 15
2.2 V 10
tHD,SI SIMO input data hold time ns
3 V 10
2.2 V 75 110
UCLK edge to SOMI valid,
tVALID,SO SOMI output data valid time ns
CL= 20 pF 3 V 50 75
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
44 Copyright © 2006–2012, Texas Instruments Incorporated
UCLK
CKPL=0
CKPL=1
SIMO
1/fUCxCLK
tLO/HI tLO/HI
SOMI
tSU,MI
tHD,MI
tVALID,MO
UCLK
CKPL=0
CKPL=1
SIMO
1/fUCxCLK
tLO/HI tLO/HI
SOMI
tSU,MI
tHD,MI
tVALID,MO
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Figure 20. SPI Master Mode, CKPH = 0
Figure 21. SPI Master Mode, CKPH = 1
Copyright © 2006–2012, Texas Instruments Incorporated 45
STE
UCLK
CKPL=0
CKPL=1
tSTE,LEAD tSTE,LAG
tSTE,ACC tSTE,DIS
tLO/HI tLO/HI
tSU,SI
tHD,SI
tVALID,SO
SOMI
SIMO
1/fUCxCLK
STE
UCLK
CKPL=0
CKPL=1
SOMI
tSTE,ACC tSTE,DIS
1/fUCxCLK
tLO/HI tLO/HI
SIMO
tSU,SI
tHD,SI
tVALID,SO
tSTE,LEAD tSTE,LAG
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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Figure 22. SPI Slave Mode, CKPH = 0
Figure 23. SPI Slave Mode, CKPH = 1
46 Copyright © 2006–2012, Texas Instruments Incorporated
SDA
SCL
1/fSCL
tHD,DAT
tSU,DAT
tHD,STA tSU,STA tHD,STA
tSU,STO
tSP
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MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
Duty cycle = 50% ± 10%
fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz
fSCL ≤100 kHz 4
tHD,STA Hold time (repeated) START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
fSCL ≤100 kHz 4.7
tSU,STA Setup time for a repeated START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 2.2 V, 3 V 0 ns
tSU,DAT Data setup time 2.2 V, 3 V 250 ns
tSU,STO Setup time for STOP 2.2 V, 3 V 4 µs
2.2 V 50 150 600
tSP Pulse width of spikes suppressed by input filter ns
3 V 50 100 600
Figure 24. I2C Mode Timing
Copyright © 2006–2012, Texas Instruments Incorporated 47
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
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10-Bit ADC, Power Supply and Input Range Conditions(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
Analog supply voltage
VCC VSS = 0 V 2.2 3.6 V
range All Ax terminals,
Analog input voltage
VAx Analog inputs selected in 0 VCC V
range(2) ADC10AE register
fADC10CLK = 5 MHz, 2.2 V 0.52 1.05
ADC10ON = 1, REFON = 0, I: -40°C to 85°C
IADC10 ADC10 supply current(3) ADC10SHT0 = 1, mA
T: -40°C to 105°C 3 V 0.6 1.2
ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 0, 2.2 V, 3 V 0.25 0.4
Reference supply REFON = 1, REFOUT = 0 I: -40°C to 85°C
IREF+ current, reference buffer mA
T: -40°C to 105°C
fADC10CLK = 5 MHz,
disabled(4) ADC10ON = 0, REF2_5V = 1, 3 V 0.25 0.4
REFON = 1, REFOUT = 0
fADC10CLK = 5 MHz -40°C to 85°C 2.2 V, 3 V 1.1 1.4
Reference buffer supply ADC10ON = 0, REFON = 1,
IREFB,0 current with mA
REF2_5V = 0, REFOUT = 1, 105°C 2.2 V, 3 V 1.8
ADC10SR = 0(4) ADC10SR = 0
fADC10CLK = 5 MHz, -40°C to 85°C 2.2 V, 3 V 0.5 0.7
Reference buffer supply ADC10ON = 0, REFON = 1,
IREFB,1 current with mA
REF2_5V = 0, REFOUT = 1, 105°C 2.2 V, 3 V 0.8
ADC10SR = 1(4) ADC10SR = 1
Only one terminal Ax selected at I: -40°C to 85°C
CIInput capacitance 27 pF
a time T: -40°C to 105°C
Input MUX ON I: -40°C to 85°C
RI0 V ≤VAx ≤VCC 2.2 V, 3 V 2000 Ω
resistance T: -40°C to 105°C
(1) The leakage current is defined in the leakage current table with Px.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR-for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC10.
(4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
48 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IVREF+ ≤1 mA, REF2_5V = 0 2.2
Positive built-in
VCC,REF+ reference analog IVREF+ ≤0.5 mA, REF2_5V = 1 2.8 V
supply voltage range IVREF+ ≤1 mA, REF2_5V = 1 2.9
IVREF+ ≤IVREF+max, REF2_5V = 0 2.2 V, 3 V 1.41 1.5 1.59
Positive built-in
VREF+ V
reference voltage IVREF+ ≤IVREF+max, REF2_5V = 1 3 V 2.35 2.5 2.65
2.2 V ±0.5
Maximum VREF+
ILD,VREF+ mA
load current 3 V ±1
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈0.75 V, 2.2 V, 3 V ±2
REF2_5V = 0
VREF+ load LSB
regulation IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈1.25 V, 3 V ±2
REF2_5V = 1
IVREF+ = 100 µA to 900 µA, ADC10SR = 0 400
VREF+ load VAx ≈0.5 x VREF+,
regulation response 3 V ns
Error of conversion result ADC10SR = 1 2000
time ≤1 LSB
Maximum IVREF+ ≤±1 mA,
CVREF+ capacitance at pin 2.2 V, 3 V 100 pF
REFON = 1, REFOUT = 1
VREF+(1)
Temperature IVREF+ = constant with
TCREF+ 2.2 V, 3 V ±100 ppm/°C
coefficient(2) 0 mA ≤IVREF+ ≤1 mA
Settling time of IVREF+ = 0.5 mA, REF2_5V = 0,
tREFON internal reference 3.6 V 30 µs
REFON = 0 to 1
voltage(3)
IVREF+ = 0.5 mA, ADC10SR = 0 1
REF2_5V = 0, 2.2 V
REFON = 1, ADC10SR = 1 2.5
REFBURST = 1
Settling time of
tREFBURST µs
reference buffer(3) IVREF+ = 0.5 mA, ADC10SR = 0 2
REF2_5V = 1, 3 V
REFON = 1, ADC10SR = 1 4.5
REFBURST = 1
(1) The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA 2/A4/VREF+/ VeREF+ (REFOUT = 1),
must be limited; the reference buffer may become unstable otherwise.
(2) Calculated using the box method:
I temperature: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
T temperature: (MAX(-40 to 105°C) – MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C – (–40°C))
(3) The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
Copyright © 2006–2012, Texas Instruments Incorporated 49
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
10-Bit ADC, External Reference(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VeREF+ > VeREF-,1.4 VCC
SREF1 = 1, SREF0 = 0
Positive external reference input
VeREF+ V
voltage range(2) VeREF-≤VeREF+ ≤VCC - 0.15 V, 1.4 3
SREF1 = 1, SREF0 = 1(3)
Negative external reference input
VeREF- VeREF+ > VeREF- 0 1.2 V
voltage range(4)
Differential external reference
ΔVeREF input voltage range VeREF+ > VeREF-(5) 1.4 VCC V
ΔVeREF = VeREF+ - VeREF- 0 V ≤VeREF+ ≤VCC,±1
SREF1 = 1, SREF0 = 0
IVeREF+ Static input current into VeREF+ 2.2 V, 3 V µA
0 V ≤VeREF+ ≤VCC - 0.15 V ≤3 V, 0
SREF1 = 1, SREF0 = 1(3)
IVeREF- Static input current into VeREF- 0 V ≤VeREF-≤VCC 2.2 V, 3 V ±1 µA
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
ADC10SR = 0 0.45 6.3
ADC10 input clock For specified performance of
fADC10CLK 2.2 V, 3 V MHz
frequency ADC10 linearity parameters ADC10SR = 1 0.45 1.5
ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,
fADC10OSC 2.2 V, 3 V 3.7 6.3 MHz
frequency fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0, 2.2 V, 3 V 2.06 3.51
fADC10CLK = fADC10OSC
tCONVERT Conversion time µs
fADC10CLK from ACLK, MCLK or SMCLK, 13 × ADC10DIVx ×
ADC10SSELx ≠0 1 / fADC10CLK
Turn on settling time of
tADC10ON 100 ns
the ADC(1)
(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
50 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
EIIntegral linearity error 2.2 V, 3 V ±1 LSB
EDDifferential linearity error 2.2 V, 3 V ±1 LSB
EOOffset error Source impedance RS< 100 Ω2.2 V, 3 V ±1 LSB
SREFx = 010, unbuffered external reference, 2.2 V ±1.1 ±2
VeREF+ = 1.5 V
SREFx = 010, unbuffered external reference, 3 V ±1.1 ±2
VeREF+ = 2.5 V
EGGain error LSB
SREFx = 011, buffered external reference(1),2.2 V ±1.1 ±4
VeREF+ = 1.5 V
SREFx = 011, buffered external reference(1),3 V ±1.1 ±3
VeREF+ = 2.5 V
SREFx = 010, unbuffered external reference, 2.2 V ±2 ±5
VeREF+ = 1.5 V
SREFx = 010, unbuffered external reference, 3 V ±2 ±5
VeREF+ = 2.5 V
ETTotal unadjusted error LSB
SREFx = 011, buffered external reference(1),2.2 V ±2 ±7
VeREF+ = 1.5 V
SREFx = 011, buffered external reference(1),3 V ±2 ±6
VeREF+ = 2.5 V
(1) The reference buffer offset adds to the gain and total unadjusted error.
10-Bit ADC, Temperature Sensor and Built-In VMID (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2.2 V 40 120
Temperature sensor supply REFON = 0, INCHx = 0Ah,
ISENSOR µA
current(1) TA= 25°C 3 V 60 160
TCSENSOR ADC10ON = 1, INCHx = 0Ah(2) 2.2 V, 3 V 3.44 3.55 3.66 mV/°C
VOffset,Sensor Sensor offset voltage ADC10ON = 1, INCHx = 0Ah(2) -100 100 mV
Temperature sensor voltage at 1265 1365 1465
TA= 105°C (T version only)
Temperature sensor voltage at TA= 85°C 1195 1295 1395
VSENSOR Sensor output voltage(3) 2.2 V, 3 V mV
Temperature sensor voltage at TA= 25°C 985 1085 1185
Temperature sensor voltage at TA= 0°C 895 995 1095
Sample time required if ADC10ON = 1, INCHx = 0Ah,
tSENSOR(sample) 2.2 V, 3 V 30 µs
channel 10 is selected(4) Error of conversion result ≤1 LSB 2.2 V N/A
Current into divider at
IVMID ADC10ON = 1, INCHx = 0Bh µA
channel 11(4) 3 V N/A
2.2 V 1.06 1.1 1.14
ADC10ON = 1, INCHx = 0Bh,
VMID VCC divider at channel 11 V
VMID ≈0.5 × VCC 3 V 1.46 1.5 1.54
2.2 V 1400
Sample time required if ADC10ON = 1, INCHx = 0Bh,
tVMID(sample) ns
channel 11 is selected(5) Error of conversion result ≤1 LSB 3 V 1220
(1) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high).When REFON = 1, ISENSOR is included in IREF+.When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
(2) The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA= 0°C) [mV]
(3) Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
(4) No additional current is needed. The VMID is used during sampling.
(5) The on time, tVMID(on), is included in the sampling time, tVMID(sample); no additional on time is needed.
Copyright © 2006–2012, Texas Instruments Incorporated 51
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Operational Amplifier (OA) Supply Specifications (MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC Supply voltage range 2.2 3.6 V
Fast Mode 180 290
ICC Supply current(1) Medium Mode 2.2 V, 3 V 110 190 µA
Slow Mode 50 80
PSRR Power-supply rejection ratio Noninverting 2.2 V, 3 V 70 dB
(1) Corresponding pins configured as OA inputs and outputs, respectively.
Operational Amplifier (OA) Input/Output Specifications (MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VI/P Input voltage range -0.1 VCC - 1.2 V
TA= -40 to +55°C -5 ±0.5 5
Input leakage
Ilkg TA= +55 to +85°C 2.2 V, 3 V -20 ±5 20 nA
current(1) (2) TA= +85 to +105°C -50 50
Fast Mode 50
Medium Mode fV(I/P) = 1 kHz 80
Slow Mode 140
Voltage noise
VnnV/√Hz
density, I/P Fast Mode 30
Medium Mode fV(I/P) = 10 kHz 50
Slow Mode 65
VIO Offset voltage, I/P 2.2 V, 3 V ±10 mV
Offset temperature 2.2 V, 3 V ±10 µV/°C
drift, I/P(3)
Offset voltage drift 0.3 V ≤VIN ≤VCC - 1.0 V 2.2 V, 3 V ±1.5 mV/V
with supply, I/P ΔVCC ≤±10%, TA= 25°C
Fast Mode, ISOURCE ≤-500 µA VCC - 0.2 VCC
High-level output
VOH 2.2 V, 3 V V
voltage, O/P Slow Mode, ISOURCE ≤-150 µA VCC - 0.1 VCC
Fast Mode, ISOURCE ≤500 µA VSS 0.2
Low-level output
VOL 2.2 V, 3 V V
voltage, O/P Slow Mode, ISOURCE ≤150 µA VSS 0.1
RLoad = 3 kΩ, CLoad = 50 pF, 150 250
VO/P(OAx) < 0.2 V
Output resistance(4) RLoad = 3 kΩ, CLoad = 50 pF,
RO/P(OAx) 2.2 V, 3 V 150 250 Ω
(see Figure 25) VO/P(OAx) > VCC - 1.2 V
RLoad = 3 kΩ, CLoad = 50 pF, 0.1 4
0.2 V ≤VO/P(OAx) ≤VCC - 0.2 V
Common-mode
CMRR Noninverting 2.2 V, 3 V 70 dB
rejection ratio
(1) ESD damage can degrade input current leakage.
(2) The input bias current is overridden by the input leakage current.
(3) Calculated using the box method
(4) Specification valid for voltage-follower OAx configuration
52 Copyright © 2006–2012, Texas Instruments Incorporated
Input Frequency − kHz
−250
−200
−150
−100
−50
0
1 10 100 1000 10000 100000
Phase − degrees
Slow Mode
Fast Mode
Medium Mode
Input Frequency − kHz
−80
−60
−40
−20
0
20
40
60
80
100
120
140
1 10 100 1000 10000 100000
Slow Mode
Fast Mode
Gain − dB
Medium Mode
RO/P(OAx)
Max
0.2V AVCC
AVCC−0.2V VOUT
Min
RLoad
AVCC
CLoad
2
ILoad
OAx
O/P(OAx)
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Figure 25. OAx Output Resistance Tests
Operational Amplifier (OA) Dynamic Specifications (MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Fast Mode 1.2
SR Slew rate Medium Mode 0.8 V/µs
Slow Mode 0.3
Open-loop voltage gain 100 dB
φm Phase margin CL= 50 pF 60 deg
Gain margin CL= 50 pF 20 dB
Noninverting, Fast Mode, 2.2
RL= 47 kΩ, CL= 50 pF
Gain-bandwidth product Noninverting, Medium Mode,
GBW 2.2 V, 3 V 1.4 MHz
(see Figure 26 and Figure 27) RL= 300 kΩ, CL= 50 pF
Noninverting, Slow Mode, 0.5
RL= 300 kΩ, CL= 50 pF
ten(on) Enable time on ton, noninverting, Gain = 1 2.2 V, 3 V 10 20 µs
ten(off) Enable time off 2.2 V, 3 V 1 µs
TYPICAL OPEN-LOOP GAIN TYPICAL PHASE
vs vs
FREQUENCY FREQUENCY
Figure 26. Figure 27.
Copyright © 2006–2012, Texas Instruments Incorporated 53
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Operational Amplifier OA Feedback Network, Resistor Network (MSP430F22x4 Only)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Rtotal Total resistance of resistor string 76 96 128 kΩ
Runit Unit resistor of resistor string(2) 4.8 6 8 kΩ
(1) A single resistor string is composed of 4 Runit + 4 Runit + 2 Runit + 2 Runit + 1 Runit + 1 Runit + 1 Runit + 1 Runit = 16 Runit = Rtotal.
(2) For the matching (that is, the relative accuracy) of the unit resistors on a device, see the gain and level specifications of the respective
configurations.
Operational Amplifier (OA) Feedback Network, Comparator Mode (OAFCx = 3) (MSP430F22x4
Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
OAFBRx = 1, OARRIP = 0 0.245 0.25 0.255
OAFBRx = 2, OARRIP = 0 0.495 0.5 0.505
OAFBRx = 3, OARRIP = 0 0.619 0.625 0.631
OAFBRx = 4, OARRIP = 0 N/A(1)
OAFBRx = 5, OARRIP = 0 N/A(1)
OAFBRx = 6, OARRIP = 0 N/A(1)
OAFBRx = 7, OARRIP = 0 N/A(1)
VLevel Comparator level 2.2 V, 3 V VCC
OAFBRx = 1, OARRIP = 1 0.061 0.0625 0.065
OAFBRx = 2, OARRIP = 1 0.122 0.125 0.128
OAFBRx = 3, OARRIP = 1 0.184 0.1875 0.192
OAFBRx = 4, OARRIP = 1 0.245 0.25 0.255
OAFBRx = 5, OARRIP = 1 0.367 0.375 0.383
OAFBRx = 6, OARRIP = 1 0.495 0.5 0.505
OAFBRx = 7, OARRIP = 1 N/A(1)
Fast Mode, Overdrive 10 mV 40
Fast Mode, Overdrive 100 mV 4
Fast Mode, Overdrive 500 mV 3
Medium Mode, Overdrive 10 mV 60
tPLH, Propagation delay Medium Mode, Overdrive 100 mV 2.2 V, 3 V 6 µs
tPHL (low-high and high-low) Medium Mode, Overdrive 500 mV 5
Slow Mode, Overdrive 10 mV 160
Slow Mode, Overdrive 100 mV 20
Slow Mode, Overdrive 500 mV 15
(1) The level is not available due to the analog input voltage range of the operational amplifier.
54 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Operational Amplifier (OA) Feedback Network, Noninverting Amplifier Mode (OAFCx = 4)
(MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
OAFBRx = 0 0.998 1 1.002
OAFBRx = 1 1.328 1.334 1.340
OAFBRx = 2 1.985 2.001 2.017
OAFBRx = 3 2.638 2.667 2.696
G Gain 2.2 V, 3 V
OAFBRx = 4 3.94 4 4.06
OAFBRx = 5 5.22 5.33 5.44
OAFBRx = 6 7.76 7.97 8.18
OAFBRx = 7 15 15.8 16.6
2.2 V -60
THD Total harmonic distortion/nonlinearity All gains dB
3 V -70
tSettle Settling time(1) All power modes 2.2 V, 3 V 7 12 µs
(1) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
Operational Amplifier (OA) Feedback Network, Inverting Amplifier Mode (OAFCx = 6)
(MSP430F22x4 Only)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
OAFBRx = 1 -0.345 -0.335 -0.325
OAFBRx = 2 -1.023 -1.002 -0.979
OAFBRx = 3 -1.712 -1.668 -1.624
G Gain OAFBRx = 4 2.2 V, 3 V -3.1 -3 -2.9
OAFBRx = 5 -4.51 -4.33 -4.15
OAFBRx = 6 -7.37 -6.97 -6.57
OAFBRx = 7 -16.3 -14.8 -13.1
2.2 V -60
THD Total harmonic distortion/nonlinearity All gains dB
3 V -70
tSettle Settling time(2) All power modes 2.2 V, 3 V 7 12 µs
(1) This includes the 2 OA configuration "inverting amplifier with input buffer". Both OA needs to be set to the same power mode OAPMx.
(2) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
Copyright © 2006–2012, Texas Instruments Incorporated 55
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC (PGM/ERASE) Program and erase supply voltage 2.2 3.6 V
fFTG Flash timing generator frequency 257 476 kHz
IPGM Supply current from VCC during program 2.2 V, 3.6 V 1 5 mA
IERASE Supply current from VCC during erase 2.2 V, 3.6 V 1 7 mA
tCPT Cumulative program time(1) 2.2 V, 3.6 V 10 ms
tCMErase Cumulative mass erase time 2.2 V, 3.6 V 20 ms
Program/Erase endurance 104105cycles
tRetention Data retention duration TJ= 25°C 100 years
tWord Word or byte program time (2) 30 tFTG
tBlock, 0 Block program time for first byte or word (2) 25 tFTG
Block program time for each additional
tBlock, 1-63 (2) 18 tFTG
byte or word
tBlock, End Block program end-sequence wait time (2) 6 tFTG
tMass Erase Mass erase time (2) 10593 tFTG
tSeg Erase Segment erase time (2) 4819 tFTG
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V(RAMh) RAM retention supply voltage (1) CPU halted 1.6 V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
56 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs
Spy-Bi-Wire enable time
tSBW,En 2.2 V, 3 V 1 µs
(TEST high to acceptance of first clock edge(1))
tSBW,Ret Spy-Bi-Wire return to normal operation time 2.2 V, 3 V 15 100 µs
2.2 V 0 5 MHz
fTCK TCK input frequency(2) 3 V 0 10 MHz
RInternal Internal pulldown resistance on TEST 2.2 V, 3 V 25 60 90 kΩ
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA= 25°C 2.5 V
VFB Voltage level on TEST for fuse blow 6 7 V
IFB Supply current into TEST during fuse blow 100 mA
tFB Time to blow fuse 1 ms
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
Copyright © 2006–2012, Texas Instruments Incorporated 57
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
1
0
DVSS
DVCC
P1REN.x Pad Logic
1
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
Table 21. Port P1 (P1.0 to P1.3) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x
P1.0(1) I: 0; O: 1 0
P1.0/TACLK/ADC10CLK 0 Timer_A3.TACLK 0 1
ADC10CLK 1 1
P1.1(1) (I/O) I: 0; O: 1 0
P1.1/TA0 1 Timer_A3.CCI0A 0 1
Timer_A3.TA0 1 1
P1.2(1) (I/O) I: 0; O: 1 0
P1.2/TA1 2 Timer_A3.CCI1A 0 1
Timer_A3.TA1 1 1
P1.3(1) (I/O) I: 0; O: 1 0
P1.3/TA2 3 Timer_A3.CCI2A 0 1
Timer_A3.TA2 1 1
(1) Default after reset (PUC/POR)
58 Copyright © 2006–2012, Texas Instruments Incorporated
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
1
0
DVSS
DVCC
P1REN.x
To JTAG
From JTAG
1
Pad Logic
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access
Features
Table 22. Port P1 (P1.4 to P1.6) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x 4-Wire JTAG
P1.4(2) (I/O) I: 0; O: 1 0 0
P1.4/SMCLK/TCK 4 SMCLK 1 1 0
TCK X X 1
P1.5(2) (I/O) I: 0; O: 1 0 0
P1.5/TA0/TMS 5 Timer_A3.TA0 1 1 0
TMS X X 1
P1.6(2) (I/O) I: 0; O: 1 0 0
P1.6/TA1/TDI/TCLK 6 Timer_A3.TA1 1 1 0
TDI/TCLK(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Function controlled by JTAG
Copyright © 2006–2012, Texas Instruments Incorporated 59
From JTAG
From JTAG (TDO)
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.7
1
0
P1DIR.7
P1IN.7
P1IRQ.7
D
EN
Module X IN
1
0
Module X OUT
P1OUT.7
Interrupt
Edge
Select
Q
EN
Set
P1SEL.7
P1IES.7
P1IFG.7
P1IE.7
P1.7/TA2/TDO/TDI
1
0
DVSS
DVCC
P1REN.7
To JTAG
From JTAG
1
Pad Logic
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features
Table 23. Port P1 (P1.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x 4-Wire JTAG
P1.7(2) (I/O) I: 0; O: 1 0 0
P1.7/TA2/TDO/TDI 7 Timer_A3.TA2 1 1 0
TDO/TDI(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Function controlled by JTAG
60 Copyright © 2006–2012, Texas Instruments Incorporated
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
P2.0/ACLK/A0/OA0I0
P2.2/TA0/A2/OA0I1
1
0
DVSS
DVCC
P2REN.x
ADC10AE0.y
Pad Logic
INCHx = y
To ADC 10
1
OA0
+
−
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger
Table 24. Port P2 (P2.0, P2.2) Pin Functions
CONTROL BITS/SIGNALS(1)
Pin Name (P2.x) x y FUNCTION P2DIR.x P2SEL.x ADC10AE0.y
P2.0(2) (I/O) I: 0; O: 1 0 0
P2.0/ACLK/A0/OA0I0 0 0 ACLK 1 1 0
A0/OA0I0(3) X X 1
P2.2(2) (I/O) I: 0; O: 1 0 0
Timer_A3.CCI0B 0 1 0
P2.2/TA0/A2/OA0I1 2 2 Timer_A3.TA0 1 1 0
A2/OA0I1(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated 61
1
OAFCx
OAPMx
OAADCx
To OA0 Feedback Network 1
(OAADCx = 10 or OAFCx = 000) and OAPMx > 00
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.1
1
0
P2DIR.1
P2IN.1
P2IRQ.1
D
EN
Module X IN
1
0
Module X OUT
P2OUT.1
Interrupt
Edge
Select
Q
EN
Set
P2SEL.1
P2IES.1
P2IFG.1
P2IE.1
P2.1/TAINCLK/SMCLK/
A1/OA0O
1
0
DVSS
DVCC
P2REN.1
ADC10AE0.1
Pad Logic
INCHx = 1
To ADC 10
1
OA0
+
−
1
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger
Table 25. Port P2 (P2.1) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x) x y FUNCTION P2DIR.x P2SEL.x ADC10AE0.y
P2.1(2) (I/O) I: 0; O: 1 0 0
Timer_A3.INCLK 0 1 0
P2.1/TAINCLK/SMCLK/ 1 1
A1/OA0O SMCLK 1 1 0
A1/OA0O(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
62 Copyright © 2006–2012, Texas Instruments Incorporated
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.3
1
0
P2DIR.3
P2IN.3
P2IRQ.3
D
EN
Module X IN
1
0
Module X OUT
P2OUT.3
Interrupt
Edge
Select
Q
EN
Set
P2SEL.3
P2IES.3
P2IFG.3
P2IE.3
1
0
DVSS
DVCC
P2REN.3
ADC10AE0.3
Pad Logic
INCHx = 3
To ADC 10
1
OA1
+
−
1
OAFCx
OAPMx
OAADCx
To OA1 Feedback Network
To ADC 10 V
R− 1
0
SREF2
VSS
P2.3/TA1/
A3/VREF−/VeREF−/
OA1I1/OA1O
1
(OAADCx = 10 or OAFCx = 000) and OAPMx > 00
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger
Copyright © 2006–2012, Texas Instruments Incorporated 63
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 26. Port P2 (P2.3) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x) x y FUNCTION P2DIR.x P2SEL.x ADC10AE0.y
P2.3(2) (I/O) I: 0; O: 1 0 0
Timer_A3.CCI1B 0 1 0
P2.3/TA1/A3/VREF- 3 3
/VeREF-/ OA1I1/OA1O Timer_A3.TA1 1 1 0
A3/VREF-/VeREF-/OA1I1/OA1O(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
64 Copyright © 2006–2012, Texas Instruments Incorporated
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.4
1
0
P2DIR.4
P2IN.4
P2IRQ.4
D
EN
Module X IN
1
0
Module X OUT
P2OUT.4
Interrupt
Edge
Select
Q
EN
Set
P2SEL.4
P2IES.4
P2IFG.4
P2IE.4
P2.4/TA2/
A4/VREF+/VeREF+/
OA1I0
1
0
DVSS
DVCC
P2REN.4
ADC10AE0.4
Pad Logic
INCHx = 4
To ADC 10
1
To/from ADC10
positive reference
OA1
+
−
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger
Table 27. Port P2 (P2.4) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x) x y FUNCTION P2DIR.x P2SEL.x ADC10AE0.y
P2.4(2) (I/O) I: 0; O: 1 0 0
P2.4/TA2/A4/VREF+/4 4 Timer_A3.TA2 1 1 0
VeREF+/ OA1I0 A4/VREF+/VeREF+/OA1I0(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated 65
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
P2.5/ROSC
1
0
DVSS
DVCC
P2REN.x
DCOR
Pad Logic
To DCO
1
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
Table 28. Port P2 (P2.5) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.x DCOR
P2.5(2) (I/O) I: 0; O: 1 0 0
N/A(3) 010
P2.5/ROSC 5DVSS 110
ROSC X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) N/A = Not available or not applicable
66 Copyright © 2006–2012, Texas Instruments Incorporated
LFXT1 off
P2SEL.7
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.6
1
0
P2DIR.6
P2IN.6
P2IRQ.6
D
EN
Module X IN
1
0
Module X OUT
P2OUT.6
Interrupt
Edge
Select
Q
EN
Set
P2SEL.6
P2IES.6
P2IFG.6
P2IE.6
P2.6/XIN
1
0
DVSS
DVCC
P2REN.6
Pad Logic
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
0
1
1
LFXT1CLK
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input
Table 29. Port P2 (P2.6) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.x
P2.6 (I/O) I: 0; O: 1 0
P2.6/XIN 6 XIN(2) X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
Copyright © 2006–2012, Texas Instruments Incorporated 67
LFXT1 off
P2SEL.6
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.7
1
0
P2DIR.7
P2IN.7
P2IRQ.7
D
EN
Module X IN
1
0
Module X OUT
P2OUT.7
Interrupt
Edge
Select
Q
EN
Set
P2SEL.7
P2IES.7
P2IFG.7
P2IE.7
P2.7/XOUT
1
0
DVSS
DVCC
P2REN.7
Pad Logic
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
0
1
1
LFXT1CLK From P2.6/XIN P2.6/XIN
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output
Table 30. Port P2 (P2.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.x
P2.7 (I/O) I: 0; O: 1 0
XOUT/P2.7 7 XOUT(2) (3) X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this
pin after reset.
68 Copyright © 2006–2012, Texas Instruments Incorporated
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.0
1
0
P3DIR.0
P3IN.0
D
EN
Module X IN
1
0
Module X OUT
P3OUT.0
1
0
DVSS
DVCC
P3REN.0
ADC10AE0.5
Pad Logic
INCHx = 5
To ADC 10
1
USCI Direction
Control
P3.0/UCB0STE/UCA0CLK/A5
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger
Table 31. Port P3 (P3.0) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x) x y FUNCTION P3DIR.x P3SEL.x ADC10AE0.y
P3.0(2) (I/O) I: 0; O: 1 0 0
P3.0/UCB0STE/ 0 5 UCB0STE/UCA0CLK(3) (4) X 1 0
UCA0CLK/A5 A5(5) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) The pin direction is controlled by the USCI module.
(4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(5) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated 69
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
D
EN
Module X IN
1
0
Module X OUT
P3OUT.x
1
0
DVSS
DVCC
P3REN.x
Pad Logic
1
USCI Direction
Control
DVSS
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger
Table 32. Port P3 (P3.1 to P3.5) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P3.x) x FUNCTION P3DIR.x P3SEL.x
P3.1(2) (I/O) I: 0; O: 1 0
P3.1/UCB0SIMO/UCB0SDA 1 UCB0SIMO/UCB0SDA(3) X 1
P3.2(2) (I/O) I: 0; O: 1 0
P3.2/UCB0SOMI/UCB0SCL 2 UCB0SOMI/UCB0SCL(3) X 1
P3.3(2) (I/O) I: 0; O: 1 0
P3.3/UCB0CLK/UCA0STE 3 UCB0CLK/UCA0STE(3) (4) X 1
P3.4(2) (I/O) I: 0; O: 1 0
P3.4/UCA0TXD/UCA0SIMO 4 UCA0TXD/UCA0SIMO(3) X 1
P3.5(2) (I/O) I: 0; O: 1 0
P3.5/UCA0RXD/UCA0SOMI 5 UCA0RXD/UCA0SOMI(3) X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) The pin direction is controlled by the USCI module.
(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode even if 4-wire SPI mode is selected.
70 Copyright © 2006–2012, Texas Instruments Incorporated
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
D
EN
Module X IN
1
0
Module X OUT
P3OUT.x
P3.6/A6/OA0I2
P3.7/A7/OA1I2
1
0
DVSS
DVCC
P3REN.x
ADC10AE0.y
Pad Logic
INCHx = y
To ADC 10
1
OA0/1
+
−
DVSS
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger
Table 33. Port P3 (P3.6, P3.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P3.x) x y FUNCTION P3DIR.x P3SEL.x ADC10AE0.y
P3.6(2) (I/O) I: 0; O: 1 0 0
P3.6/A6/OA0I2 6 6 A6/OA0I2(3) X X 1
P3.7(2) (I/O) I: 0; O: 1 0 0
P3.7/A7/OA1I2 7 7 A7/OA1I2(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated 71
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
P4.0/TB0
P4.1/TB1
P4.2/TB2
1
0
DVSS
DVCC
P4REN.x
Pad Logic
1
P4DIR.6
P4SEL.6
ADC10AE1.7
P4.6/TBOUTH/A15/OA1I3
Timer_B Output Tristate Logic
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger
Table 34. Port P4 (P4.0 to P4.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P4.x) x FUNCTION P4DIR.x P4SEL.x
P4.0(1) (I/O) I: 0; O: 1 0
P4.0/TB0 0 Timer_B3.CCI0A 0 1
Timer_B3.TB0 1 1
P4.1(1) (I/O) I: 0; O: 1 0
P4.1/TB1 1 Timer_B3.CCI1A 0 1
Timer_B3.TB1 1 1
P4.2(1) (I/O) I: 0; O: 1 0
P4.2/TB2 2 Timer_B3.CCI2A 0 1
Timer_B3.TB2 1 1
(1) Default after reset (PUC/POR)
72 Copyright © 2006–2012, Texas Instruments Incorporated
OAPMx
OAADCx
To OA0/1 Feedback Network 1
OAADCx = 01 and OAPMx > 00
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
P4.3/TB0/A12/OA0O
P4.4/TB1/A13/OA1O
1
0
DVSS
DVCC
P4REN.x
ADC10AE1.y
Pad Logic
INCHx = 8+y
To ADC 10
1
OA0/1
+
−
1
P4DIR.6
P4SEL.6
ADC10AE1.7
P4.6/TBOUTH/A15/OA1I3
Timer_B Output Tristate Logic
†
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger
†If OAADCx = 11 and not OAFCx = 000, the ADC input A12 or A13 is internally connected to the OA0 or OA1 output,
respectively, and the connections from the ADC and the operational amplifiers to the pad are disabled.
Copyright © 2006–2012, Texas Instruments Incorporated 73
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Table 35. Port P4 (P4.3 to P4.4) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P4.x) x y FUNCTION P4DIR.x P4SEL.x ADC10AE1.y
P4.3(2) (I/O) I: 0; O: 1 0 0
Timer_B3.CCI0B 0 1 0
P4.3/TB0/A12/OA0O 3 4 Timer_B3.TB0 1 1 0
A12/OA0O(3) X X 1
P4.4(2) (I/O) I: 0; O: 1 0 0
Timer_B3.CCI1B 0 1 0
P4.4/TB1/A13/OA1O 4 5 Timer_B3.TB1 1 1 0
A13/OA1O(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
74 Copyright © 2006–2012, Texas Instruments Incorporated
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.5
1
0
P4DIR.5
P4IN.5
D
EN
Module X IN
1
0
Module X OUT
P4OUT.5
P4.5/TB3/A14/OA0I3
1
0
DVSS
DVCC
P4REN.5
ADC10AE1.6
Pad Logic
INCHx = 14
To ADC 10
1
P4DIR.6
P4SEL.6
ADC10AE1.7
P4.6/TBOUTH/A15/OA1I3
Timer_B Output Tristate Logic
OA0
+
−
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger
Table 36. Port P4 (P4.5) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P4.x) x y FUNCTION P4DIR.x P4SEL.x ADC10AE1.y
P4.5(2) (I/O) I: 0; O: 1 0 0
P4.5/TB3/A14/OA0I3 5 6 Timer_B3.TB2 1 1 0
A14/OA0I3(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Copyright © 2006–2012, Texas Instruments Incorporated 75
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.6
1
0
P4DIR.6
P4IN.6
D
EN
Module X IN
1
0
Module X OUT
P4OUT.6
1
0DVSS
DVCC
P4REN.6
ADC10AE1.7
Pad Logic
INCHx = 15
To ADC 10
1
OA1
+
−
P4.6/TBOUTH/
A15/OA1I3
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger
Table 37. Port P4 (P4.6) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P4.x) x y FUNCTION P4DIR.x P4SEL.x ADC10AE1.y
P4.6(2) (I/O) I: 0; O: 1 0 0
TBOUTH 0 1 0
P4.6/TBOUTH/A15/OA1I3 6 7 DVSS 110
A15/OA1I3(3) X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
76 Copyright © 2006–2012, Texas Instruments Incorporated
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
P4.7/TBCLK
1
0
DVSS
DVCC
P4REN.x
Pad Logic
1
DVSS
MSP430F22x2
MSP430F22x4
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SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger
Table 38. Port P4 (Pr.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P4.x) x FUNCTION P4DIR.x P4SEL.x
P4.7(1) (I/O) I: 0; O: 1 0
P4.7/TBCLK 7 Timer_B3.TBCLK 0 1
DVSS 1 1
(1) Default after reset (PUC/POR)
Copyright © 2006–2012, Texas Instruments Incorporated 77
Time TMS Goes Low After POR
TMS
ITF
ITEST
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012
www.ti.com
JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Figure 28. Fuse Check Mode Current
NOTE
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit
bootloader access key is used. Also, see the Bootstrap Loader section for more
information.
78 Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
www.ti.com
SLAS504G –JULY 2006–REVISED AUGUST 2012
REVISION HISTORY
Literature Summary
Number
SLAS504 Preliminary data sheet release
SLAS504A Production data sheet release
Updated specification and added characterization graphs
Updated/corrected port pin schematics
SLAS504B Maximum low-power mode supply current limits decreased
Added note concerning fUCxCLK to USCI SPI parameters
SLAS504C Added Development Tool Support section (page 2)
Changed Tstg for programmed devices from "-40°C to 105°C" to "-55°C to 105°C" (page 23)
SLAS504D Corrected pin names in "Port P3 pin schematic: P3.0" and "Port P3 (P3.0) pin functions" (page 68)
Corrected pin names in "Port P3 pin schematic: P3.1 to P3.5" and "Port P3 (P3.1 to P3.5) pin functions" (page 69)
Corrected signal names in "Port P2 pin schematic: P2.5, input/output" (page 65) (D1)
Corrected values in "x" column in "Port P3 (P3.1 to P3.5) pin functions" (page 69) (D2)
SLAS504E Added information for YFF package
SLAS504F Correct signal names for P3.6 and P3.7 in MSP430F22x2 pinouts – DA package,RHA package
Changed Storage temperature range limit in Absolute Maximum Ratings
Corrected Test Conditions in Crystal Oscillator LFXT1, High-Frequency Mode
Corrected signal names in Port P1 (P1.0 to P1.3) Pin Functions
Corrected typo in note 1 on Crystal Oscillator LFXT1, High-Frequency Mode table
SLAS504G Terminal Functions tables, Corrected description of VREF-/VeREF-pins.
Added note on TCREF+ in 10-Bit ADC, Built-In Voltage Reference.
Copyright © 2006–2012, Texas Instruments Incorporated 79
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F2232IDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2232IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2232IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2232IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2232IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2232IYFFT PREVIEW DSBGA YFF 49 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2232TDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2232TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2232TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2232TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2234IDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2234IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2234IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2234IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2234IYFFR PREVIEW DSBGA YFF 49 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2234IYFFT PREVIEW DSBGA YFF 49 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2234TDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jul-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F2234TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2234TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2234TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2252IDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2252IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2252IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2252IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2252IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2252IYFFT PREVIEW DSBGA YFF 49 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2252TDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2252TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2252TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2252TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2254IDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2254IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2254IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2254IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2254IYFFR PREVIEW DSBGA YFF 49 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
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Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F2254IYFFT PREVIEW DSBGA YFF 49 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2254TDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2254TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2254TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2254TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2272IDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2272IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2272IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2272IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2272IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2272IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2272TDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2272TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2272TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2272TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2274IDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2274IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2274IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
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Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F2274IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2274IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2274IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
MSP430F2274TDA ACTIVE TSSOP DA 38 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2274TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430F2274TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F2274TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
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Addendum-Page 5
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430F2232, MSP430F2234, MSP430F2252, MSP430F2254, MSP430F2272, MSP430F2274 :
•Automotive: MSP430F2232-Q1, MSP430F2234-Q1, MSP430F2252-Q1, MSP430F2254-Q1, MSP430F2272-Q1, MSP430F2274-Q1
•Enhanced Product: MSP430F2274-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430F2232IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
MSP430F2232IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2232IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2232TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2232TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2234IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
MSP430F2234IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2234IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2234TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2252IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
MSP430F2252IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2252IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2252TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2252TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2254IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
MSP430F2254IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2254IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2254TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430F2254TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2272IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
MSP430F2272IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2272IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2272TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2272TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2274IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2274IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2274TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
MSP430F2274TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F2232IDAR TSSOP DA 38 2000 367.0 367.0 45.0
MSP430F2232IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2232IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2232TRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2232TRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2234IDAR TSSOP DA 38 2000 367.0 367.0 45.0
MSP430F2234IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F2234IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2234TRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2252IDAR TSSOP DA 38 2000 367.0 367.0 45.0
MSP430F2252IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2252IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2252TRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2252TRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2254IDAR TSSOP DA 38 2000 367.0 367.0 45.0
MSP430F2254IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2254IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2254TRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2254TRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2272IDAR TSSOP DA 38 2000 367.0 367.0 45.0
MSP430F2272IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2272IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2272TRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2272TRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2274IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2274IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430F2274TRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430F2274TRHAT VQFN RHA 40 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2012
Pack Materials-Page 3
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