FST3245MTCX_NL - Fairchild Semiconductor

June 1997

Revised March 2005

FST3245 8-Bit Bus Switch

FST3245

8-Bit Bus Switch

General Descript ion

The Fairchild Switch FST3245 provides 8-bits of high-

speed CMOS TTL-compatible bus switching in a standard

’245 pin-out. The low on resistance of the switch allows

inputs to be con nected to outp uts without add ing propaga-

tion delay or generating additional ground bounce noise.

The device is organized as an 8-bit switch. When OE is

LOW, the switch is ON and Por t A is connecte d to Port B.

When OE is HIGH, the switch is OPEN and a high-imped-

ance state exists between the two ports.

Features

■4

switch connection between two ports.

■Minimal propagation delay through the switch.

■Low lCC.

■Zero bounce in flow-through mode.

■Control inputs compatible with TTL level.

Ordering Code:

Devices also available in Tape and R eel. Specif y by append ing the suffix let t er “X” to th e ordering co de.

Note 1: “_NL” indicates Pb-Fre e pac k age (per JE D EC J -STD-0 20B). Devic e availa ble in Tape and Reel only.

Logic Diagram

Pin Descriptions

Connection Diagram

Truth Table

Order Number Package Package Description

Number

FST3245WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

FST3245QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

FST3245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

FST3245MTCX_NL

(Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Name Description

OE Bus Switch Enable

ABus A

BBus B

Input OE Function

L Connect

H Disconnect

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FST3245

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions (Note 4)

Note 2: The Absolute Maximum Ratings are those values beyond which

the saf ety of the device cannot be guarante ed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Charact eristic s tables are no t guarant eed at the ab solute maximu m rating.

The “R ecomm ended Ope rating Condition s” tabl e will d efine th e cond itions

for actu al device operation.

Note 3: The input and output negative voltage ratings may be exceeded if

the input and output diode current ratings are observed.

Note 4: Unused control inputs must be held HIGH or LOW. They may not

float.

DC Electrical Characteristi cs

Note 5: Typical v alues are at VCC

5.0V and TA



Note 6: Measured by the v olt age drop be t w een A and B pins at t he indicat ed curre nt th rough the s w it ch . On resistanc e is determin ed by the lower of the

voltages on the tw o (A or B) pins.

Supply Voltage (VCC)



0.5V to



7.0V

DC Switch Voltage (VS)



0.5V to



7.0V

DC Input Voltage (VIN) (Note 3)



0.5V to



7.0V

DC Input Diode Current (lIK) VIN





50mA

DC Output (IOUT) Sink Current 128mA

DC VCC/GND Current (ICC/IGND)





100mA

Storage Temperature Range (TSTG)



C to



150

Power Supply Operating (VCC) 4.0V to 5.5V

Input Voltage (VIN)0V to 5.5V

Output Voltage (VOUT)0V to 5.5V

Input Rise and Fall Time (tr, tf)

Switch Control Input 0nS/V to 5nS/V

Switch I/O 0nS/V to DC

Free Air Operating Temperature (TA)



C to



Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ

(Note 5) Max

VIK Clamp Diode Voltage 4.5



1.2 V IIN



18 mA

VIH HIGH Level Input Voltage 4.0–5.5 2.0 V

VIL LOW Level Input Voltage 4.0–5.5 0.8 V

IIInput Leakage Current 5.5

1.0

VIN

5.5V

IOZ OFF-STATE Leakage Current 5.5

1.0

A, B

VCC

RON Switch On Resistance 4.5 4 7

VIN

0V, IIN

64 mA

(Note 6) 4.5 4 7

VIN

0V, IIN

30 mA

4.5 8 15

VIN

2.4V, IIN

15 mA

4.0 11 20

VIN

2.4V, IIN

15 mA

ICC Quiescent Supply Current 5.5 3

VCC or GND, IOUT

ICC Increase in ICC per Input 5.5 2.5 mA One Input at 3.4V

Other Inputs at VCC or GND

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FST3245

AC Electrical Characteristics

Note 7: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On

resistance of the switch and th e 50pF load c apacitanc e, w hen driven by an ideal voltage the source (zero out put impe dance) .

Capacitance (Note 8)

Note 8: TA



C, f

1 MHz, Ca pacitance is c haracte riz ed but not tes t ed.

AC Loading and Waveforms

Note: Input driven by 50

source terminated in 50

Note: CL includes load and stray capacitance

Note: Input PRR

1.0 MH z t W

500 ns

FIGURE 1. AC Test Circuit

FIGURE 2. AC Waveforms

Symbol Parameter



C to



50pF, RU

500

Units Conditions Figure

Number

VCC

4.5 – 5.5V VCC

4.0V

Min Max Min Max

tPHL,tPLH Propagation Delay Bus to Bus

(Note 7) 0.25 0.25 ns VI

OPEN Figures

1, 2

tPZH, tPZL Output Enable Time 1.5 5.9 6.4 ns VI

7V for tPZL Figures

1, 2

OPEN for tPZH

tPHZ, tPLZ Output Disable Time 1.5 6.0 5.7 ns VI

7V for tPLZ Figures

1, 2

OPEN for tPHZ

Symbol Parameter Typ Max Units Conditions

CIN Control Pin Input Capacitance 3 pF VCC

5.0V

CI/O Input/Output Capacitance 5 pF VCC, OE

5.0V

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FST3245

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

Package Number MQA20

5 www.fairchildsemi.com

FST3245 8-Bit Bus Switch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

Technology Description

The Fairchild Switch family derives fr om and embodies Fairchild’s proven switch technology used fo r several years in its

74LVX3L384 (FST3384) bus switch product.

Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses ar e implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.