NJU26202
-
1
-
Ver.2007-02-26
Digital Signal Processor for Car Audio
General Description
The NJU26202 is a digital signal processor that provides the function of
Circle Surround Automotive, Hall Simulator, 7Band PEQ / GEQ, and Time Alignment.
The applications of NJU26202 are suitable for multi-channel products such as Car Audio
small speakers system.
Features
-Software
SRS Circle Surround Automotive
TruBass
FOCUS
Hall Simulator
7Band PEQ / GEQ
Time Alignment
Sampling Frequency
- 16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz (Stereo Input Mode and Multi Input Mode)
- 32kHz/44.1kHz/48kHz (CS Auto Mode)
-Hardware
24bit Fixed-point Digital Signal Processing
Maximum Clock Frequency : 12.288MHz(Standard), built-in PLL Circuit
Digital Audio Interface : 4 Input ports / 3 Output ports
Digital Audio Format : I2S 24bit, left-justified, right-justified, BCK : 32fs/64fs
Master / Slave Mode
Microcomputer Interface
- I2C Bus (Standard-mode/100kbps, Fast-mode/400kbps)
- 4 -Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data)
Operating Voltage : VDD = VDDPLL = 1.8V
: VDDIO = 3.3V
Input Terminal : 5.0V Input tolerant
Package : QFP48-N2 (Pb-Free)
* The detail hardware specification of the NJU26202 is described in the “ NJU26200 Series Hardware Data Sheet”.
■Package
NJU26202FN2
NJU26202
-
2
-Ver.2007-02-26
Block Diagram
TIMING
GENERATOR
/ PLL
PROGRAM
CONTROL
ALU
24-BIT x 24-BI T
MULTIPLIER
ADDRESS GENERAT ION UNIT
FIRMWARE
ROM
DATA
RAM
SERIAL
HOST
INTERFACE
General I/O
INTERFACE
SDO2
SDO3
SCL/SCK
SDA/SDOUT
AD1/SDIN AD2/SSb
CLK
CLKOUT
RESETb
24bit Fixed-point DSP Core
LRI
BCKI
MCK
BCKO
LRO
C/SW
RL/RR
SERIAL AUDIO
INTERFACE
NJU26202
SDO1
FL/FR
WDC
SEL
MUTEb
PROC
SDIO-3
Fig. 1 NJU26202 Hard ware Block Diagram
Function Block Diagram
Fig. 2 NJU26202 Block Diagram
IN
S
DI1
S
DI
0
S
DI
2
S
DI
3
In
put
Trim
CS
A
u
t
o
L
/R
C/S
W
L
S/
R
S
PE
Q/G
E
Q
7B
a
n
d
Tr
u
B
ass
F
OCUS
Tim
e
*
A
li
g
nm
e
n
t
M
as
t
er
V
o
l
u
m
e
&
C
h
a
nn
e
l
Trim
&
S
m
oo
th
F
r
o
nt L
/
R
(
L
/
R
)
C/S
W
R
ea
r L
/
R
(
L
S/
R
S)
Ph
a
nt
o
m
Ce
nt
er
M
u
lti In
pu
t M
ode
L
/
R
,
C/S
W
,
L
S/
R
S
OU
T
* H
a
ll
S
im
u
l
a
t
o
r
a
n
d
Tim
e
Ali
g
nm
e
nt
do
n
o
t w
o
rk
a
t th
e
sa
m
e
tim
e
.
S
DI
0
o
r
S
DI1
L
/R
C/S
W
L
S/
R
S
Tim
e
A
li
g
nm
e
n
t
L
/R
L
S/
R
S
S
D
O
1
S
D
O2
S
D
O3
S
DI
0
o
r
S
DI1
,
S
DI2
,
S
DI
3
CS Auto Mode
S
t
e
r
eo
In
pu
t
M
ode
o
r
S
DI1
H
a
ll *
S
im
u
l
a
t
or
C/S
W
(
L
/
R
)
R
ea
r L
/
R
Fr
o
nt L
/
R
(
L
/
R
)
R
e
a
r L
/R
(
L
S/
R
S)
In
put
Trim
CS
A
u
t
o
PE
Q/G
E
Q
7B
a
n
d
Tr
u
B
ass
F
OCUS
Tim
e
*
A
li
g
nm
e
n
t
M
as
t
er
V
o
l
u
m
e
&
C
h
a
nn
e
l
Trim
&
S
m
oo
th
Ph
a
nt
o
m
Ce
nt
er
* H
a
ll
S
im
u
l
a
t
o
r
a
n
d
Tim
e
Ali
g
nm
e
nt
do
n
o
t w
o
rk
a
t th
e
sa
m
e
tim
e
.
Tim
e
A
li
g
nm
e
n
t
S
D
O2
S
D
O3
S
DI
0
o
r
S
DI1
,
S
DI
0
S
DI1
H
a
ll *
S
im
u
l
a
t
or
S
W
Front L/R
(
L
S/
R
S)
NJU26202
-
3
-
Ver.2007-02-26
Pin Configuration
48
1
2
3
4
5
6
7
8
9
10
11
12
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
RESETb
TEST
VDDPLL
VSSPLL
VSS
VDD
CLKOUT
CLK
VDDIO
VSSIO
TEST
TEST
LRI
SDI0
SDI1
SDI2
SDI3
VDD
VSS
VDDIO
TEST
SDO1
SDO2
SEL
VSSIO
VDDIO
PROC
WDC
MUTEb
TEST
VDD
VSS
VSSIO
BCKI
VDDIO
AD1/SDIN
AD2/SSb
SCL/SCK
SDA/SDOUT
VDD
VSS
VSSIO
VDDIO
MCK
BCKO
LRO
SDO3
NJU26202
VSSIO
Fig. 3 NJU26202 Pin Configuration
NJU26202
-
4
-Ver.2007-02-26
Pin Description
Table 1 Pin Description
Pin No. Symbol I/O Function
1,11,20,32,40 VDDIO - I/O Power Supply +3.3V
2 BCKI I Bit Clock Input
3,10,19,31,41 VSSIO - I/O GND
4,15,30,42 VSS - Core GND
5,16,29,43 VDD - Core Power Supply +1.8V
6 TEST I for test (connected to VSSIO through 3.3kΩ resistance.)
7 MUTEb * I Master Volume level, After Reset DSP (“1” : 0dB “0” : Mute)
8 WDC * OD Clock for Watch Dog Timer (Open Drain Output)
9 PROC * I After Reset DSP. ( “1” : Normal “0” : Wait from Command )
12 SEL I Select I2C or Serial bus ( ‘1’ : Serial / ‘0’ : I2C-Bus)
13 VDDPLL - PLL Analog Power Supply +1.8V
14 VSSPLL - PLL Analog GND
17 CLKOUT O OSC Output
18 CLK I X’tal Clock Input (12.288MHz)
21 RESETb I Reset (RESETb=’0’ : DSP Reset)
22 TEST I for Test (Connect to VDDIO)
23,24 TEST I for Test (Connect to VSSIO)
25 AD1/SDIN I I2C Address / Serial Input
26 AD2/SSb I I2C Address / Serial Enable
27 SCL/SCK I I2C Clock / Serial Clock
28 SDA/SDOUT I/O
I2C I/O (Open Drain output) / Serial Output (CMOS output)
I2C Bus mode : SDA pin requires a pull-up resistance.
4-wire Serial mode : SDOUT does not require a pull-up resistance.
33 MCK O Master Clock Output (CLK Terminal=27pin Buffer Out)
34 BCKO O Bit Clock Output
35 LRO O LR Clock Output
36 SDO3 O Audio Data Output 3 ( Rear Lch / Rch )
37 SDO2 O Audio Data Output 2 ( Center / Subwoofer )
38 SDO1 O Audio Data Output 1 ( Front Lch / Rch )
39 TEST O for Test ( No connect : OPEN )
44 SDI3 I Audio Data Input 3 ( SL / SR )
45 SDI2 I Audio Data Input 2 ( Center / Subwoofer)
46 SDI1 I Audio Data Input 1 ( Front Lch / Rch )
47 SDI0 I Audio Data Input 0 ( Front Lch / Rch )
48 LRI I LR Clock Input
Note : I : Input
O : Output
OD : Open Drain Output
I/O : Bi-directional
Pins symbol with * : Connect with VDDIO or VSSIO through 3.3kΩ resistance
NJU26202
-
5
-
Ver.2007-02-26
Audio Interface
The NJU26202 audio interface provides industry serial data formats of I2S, MSB-first Left-justified or MSB-first
Right-justified. The NJU26202 audio interface provides two data inputs, SDI0 and SDI1, and three data outputs,
SDO0, SDO1 and SDO2, as shown in table 2 and 3. The input serial data is selected by the firmware command.
Table 2 Serial Audio Input Pin
Pin No. Symbol Description
47 SDI0 Lch / Rch Audio Data Input 0
46 SDI1 Lch / Rch Audio Data Input 1
45 SDI2 Cch / SWch Audio Data Input 2
44 SDI3 LSch / RSch Audio Data Input 3
Table 3 Serial Audio Output Pin
Pin No. Symbol Description
38 SDO1 Front Lch/Rch Audio Data Output 1
37 SDO2 Cch / SWch Audio Data Output 2
36 SDO3 Rear Lch/Rch Audio Data Output 3
Host Interface
The NJU26202 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I2C bus or
4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a
SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates
data transfers, regardless of the chosen communication protocol.
The detail I2C bus and 4-Wire Serial bus information are described in the ‘NJU26200 Series Hardware Data
Sheet’.
Table 4 Serial Host Interf ace Pin Descriptions
Pin No. Symbol Setting Host Interface
Low I2C Bus Interface
12 SEL High 4-Wire Serial Interface
Table 5 Serial Host Interface Pin Desc ription
Pin No. Symbol
(I2C /Serial)
I2C bus Interface 4-Wire Serial Interface
25 AD1/SDIN I2C Address Select Bit1 Serial data input
26 AD2/SSb I2C Address Select Bit2 Slave select
27 SCL/SCK Serial Clock Serial Clock
28 SDA/SDOUT Serial Data Input/Output
(Open Drain output)
Serial data output
(CMOS Output)
Note: When 4-Wire Serial bus is selected, The SDA/SDOUT pin is CMOS output. The SDOUT pin does not require a
pull-up resistance.
When I2C Bus is selected, this pin is a bi-directional Open Drain output. This pin, which is assigned for I2C Bus,
requires a pull-up resistance.
The SDA/SDOUT pin isn’t 5.0V Input tolerant.
NJU26202
-
6
-Ver.2007-02-26
I2C Bus
When the NJU26202 is configured for I2C bus communication in SEL=”Low”, the serial host interface transfers
data on the SDA pin and clocks data on the SCL pin. SDA is an open drain pin requiring a pull-up resistance. Pins
AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6)
Table 6 I2C-Bus Interface Slav e address
* SLAVE address is 0 when AD1/2 is “Low”. SLAVE address is 1 when AD1/2 is “High”.
Note: The serial host interface supports “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” I2C bus data
transfer. Moreover, after sending S ("START" condition), Sr (repeated "START" condition) is not received
but it becomes the waiting for the P ("STOP" condition). Therefore, please be sure to send P ("STOP"
condition).
4-Wire Serial Interface
The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1=”High” during the
Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the
same time that a read byte is shifted out of the SDOUT pin.
Data transfers are MSB first and are enabled by setting SSb = “Low”. Data is clocked into SDIN on rising
transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is
latched on the falling transitions of SSb. The SDOUT pin is always CMOS output. This pin does not require a pull-up
resistance.
Fig. 4 4-Wire Serial Inter face Timing
Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the
transition of SSb=”High”.
When the data-clock is more than 8 clocks, the last 8 bit data becomes valid.
After sending LSB data, SDOUT transmits the MSB data that is received via SDIN until SSb becomes “High”.
bit7 bit6 bit5 bit4 bit3
AD2
bit2
AD1
bit1
R/W
bit0
0 0 1 1 1 0 0
0 0 1 1 1 0 1
0 0 1 1 1 1 0
0 0 1 1 1 1 1
R/W
Start
bit
R/W
bit ACK
Slave Add
r
ess
(
7bi
t
)
SDIN
SDOU
T
SCK
SS
b
bit5 bit1
bit7 bit0
bit6
bit1bit7 bit0bit6 bit5 unstable
unstable
MSB LSB
NJU26202
-
7
-
Ver.2007-02-26
Pin setting
The NJU26202 operates default command setting after resetting the NJU26202. In addition, the NJU26202
restricts operation at power on by setting PROC pin and MUTEb pin (Table 7). These pins are input pin. However,
these pins operate as bi-directional pins. Connect with VDDIO or VSSIO through 3.3kΩ resistance.
Table 7 Pin setting
Pin No. Symbol Setting Function
“High” The NJU26202 operates default setting after reset.
9
PROC “Low” The NJU26202 does not operate after reset. Sending start
command is required for starting operation.
“High” Master volume is set 0dB after reset. 7 MUTEb
“Low” Master volume is set mute after reset.
W atchDog Clock
The NJU26202 outputs clock pulse through WDC (Pin No.8) during normal operation. The WDC clock is useful to check
the status of the NJU26202 operation. For example, a microcomputer monitors the WDC clock and checks the status of
the NJU26202. When the WDC clock pulse is lost or not normal clock cycle, the NJU26202 does not operate correctly.
Then reset the NJU26202 and set up the NJU26202 again.
The output toggle cycle from a WDC pin is set as about 100ms.
The WDC pin is open drain output. The WDC pin setting (Table 8)
Table 8 WDC pin setting
Note: The cycle of WDC output is rough. Because WDC output inserts in the process of sound processing.
In slave mode, when there is no input of BCKI/LRI, the WDC pin can’t output.
It is required to set up a sampling rate correctly.
Pin No. Symbol Setting
WDC pin is used. Connect with VDDIO through 3.3kΩ resistance
8
WDC WDC pin is not used. Connect with VSSIO through 3.3kΩ resistance.
Do not open WDC pin.
NJU26202
-
8
-Ver.2007-02-26
Firmware Command Table
Table 9 NJU26202 Command
No. Command No. Command
1 Set Task 22 Hall Simulator Surround
2 Circle Surround Config 23 Hall Simulator Effect Output Trim
3 Circle Surround Automotive Config 24 Hall Simulator Balance Trim
4 TruBass Config 25 EQ Mode Select
5 TruBass Size Select 26 EQ f0 Control
6 TruBass Gain Control 27 EQ Q Control
7 FOCUS Config 28 EQ Gain Control
8 FOCUS Gain Control 29 Time Alignment
9 Input Trim Control 30 SW LPF fc
10 Master Volume Control 31 Sample rate Select
11 Channel Trim Control 32 Smooth Control Config
12 Delay Control 33 Input Select
13 Stereo Input Mode Config 34 Phantom Center Config
14 Hall Simulator Input Select 35 TruBass Input Select
15 Hall Simulator HPF fc 36 Input Mode Config
16 Hall Simulator LPF fc 37 System State
17 Hall Simulator Early Reflection Start Time 38 Firmware Version Number Request
18 Hall Simulator Early Reflection End Time 39 DSP Reset
19 Hall Simulator Reverb Start Time 40 Start
20 Hall Simulator HF Dump
41 Nop
21 Hall Simulator Reverb Time
Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a licenser
(SRS Labs. Inc.) is required.
NJU26202
-
9
-
Ver.2007-02-26
Package Dimensions ( QFP48-N2, Pb-Free )
BA
S
E
O
F M
O
LDIN
G
M
O
LD MATERIAL : EP
O
XY RE
S
IN
NJU26202
-
10
-Ver.2007-02-26
License Information
1. The “Circle Surround Automotive”, ”FOCUS”, “TruBass” technology rights incorporated in the NJU26202 are owned
by SRS Labs, a U.S. Corporation and licensed to New Japan Radio Co., Ltd.. Purchaser of NJU26202 must sign a
license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the NJU26202 must
be send to SRS Labs for review. “Circle Surround Automotive”, ”FOCUS”, “TruBass” are protected under US and
foreign patents issued and/or pending. “Circle Surround Automotive”, ”FOCUS”, “TruBass”, SRS and symbol
are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the
NJU26202, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized
recordings made with any SRS technology. SRS Labs requires all set marks to comply with all rules and regulations
as outlined in the SRS Trademark Usage Manual separately provided.
For further information, please contact::
SRS Labs, Inc.
2909 Daimler Street.
Santa Ana, CA 92705 USA
Tel: 949-442-1070 Fax: 949-852-1099 http://www.srslabs.com
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
