DATA SH EET
Product specification
File under Integrated Circuits, IC04 January 1995
INTEGRATED CIRCUITS
HEF4082B
gates
Dual 4-input AND gate
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Dual 4-input AND gate HEF4082B
gates
DESCRIPTION
The HEF4082B provides the positive dual 4-input AND
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.1 Functional diagram.
HEF4082BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4082BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4082BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
Fig.3 Logic diagram (one gate).
January 1995 3
Philips Semiconductors Product specification
Dual 4-input AND gate HEF4082B
gates
AC CHARACTERISTICS
VSS =0V; T
amb =25°C; CL= 50 pF; input transition times ≤20 ns
VDD
VSYMBOL TYP. MAX. TYPICAL EXTRAPOLATION
FORMULA
Propagation delays 5 tPHL; tPLH
65 125 ns 38 ns +(0,55 ns/pF) CL
In→On10 30 60 ns 19 ns +(0,23 ns/pF) CL
15 25 45 ns 17 ns +(0,16 ns/pF) CL
Output transition times 5 tTHL
60 120 ns 10 ns +(1,0 ns/pF) CL
HIGH to LOW 10 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
5 60 120 ns 10 ns +(1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 1500 fi+∑(foCL) ×VDD 2where
dissipation per 10 6700 fi+∑(foCL) ×VDD 2fi= input freq. (MHz)
package (P) 15 16 800 fi+∑(foCL) ×VDD 2fo= output freq. (MHz)
CL= load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
