1
®
FN8196.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9421
Low Noise/Low Power/SPI Bus
Single Digitally Controlled (XDCP™)
Potentiometer
Description
The X9421 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using 63
resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled
by the user through the SPI bus interface. The potentiometer
has associated with it a volatile Wiper Counter Register
(WCR) and a four non-volatile Data Registers that can be
directly written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor array
though the switches . Power-up recalls the contents of the
default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Single Voltage Potentiometer
• 64 Resistor Taps
• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Wiper Resistance, 150Ω Typical at 5V
• 4 Non-Vol atile Da ta Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 5µA Max
•V
CC : 2.7V to 5.5V Operation
•2.5kΩ, 10kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes per Bit per Register
• 14 Ld TSSOP, 16 Ld SOIC
• Low Power CMOS
• Pb-Free Available (RoHS Compliant)
Block Diagram
64-TAPS
10kΩ
INC / DEC
RH/VH
RL/VL
RW/VW
POT
VCC
VSS
SPI
BUS
ADDRESS
DATA
STATUS
WRITE
READ
WIPER
TRANSFER POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
4 BYTES
CONTROL
INTERFACE
BUS
INTERFACE &
CONTROL
Data Sheet January 14, 2009
NOT RECOMMENDED FOR NEW DESIGNS
POSSIBLE SUBSTITUTE PRODUCT
ISL22416, ISL22419
2FN8196.4
January 14, 2009
Ordering Information
PART
NUMBER PART
MARKING VCC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(kΩ)TEMP
RANGE (°C) PACKAGE
X9421YS16* X9421YS 5 ±10% 2.5 0 to +70 16 Ld SOIC (300 mil)
X9421YS16Z* (Note) X9421YS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-Free)
X9421YS16I* X9421YS I -40 to +85 16 Ld SOIC (300 mil)
X9421YS16IZ* (Note) X9421YS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-Free)
X9421YV14* X9421 YV 0 to +70 14 Ld TSSOP (4.4mm)
X9421YV14Z* (Note) X9421 YVZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free)
X9421YV14I* X9421 YV I -40 to +85 14 Ld TSSOP (4.4mm)
X9421YV14IZ* (Note) X9421 YVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free)
X9421WS16* X9421WS 10 0 to +70 16 Ld SOIC (300 mil)
X9421WS16Z* (Note) X9421WS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-Free)
X9421WS16I* X9421WS I -40 to +85 16 Ld SOIC (300 mil)
X9421WS16IZ* (Note) X9421WS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-Free)
X9421WV14* X9421 WV 0 to +70 14 Ld TSSOP (4.4mm)
X9421WV14Z* (Note) X9421 WV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free)
X9421WV14I* X9421 WV I -40 to +85 14 Ld TSSOP (4.4mm)
X9421WV14IZ* (Note) X9421 WVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free)
X9421YS16-2.7* X9421YS F 2.7 to 5.5 2.5 0 to +70 16 Ld SOIC (300 mil)
X9421YS16Z-2.7* (Note) X9421YS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-Free)
X9421YS16I-2.7* X9421 YS G -40 to +85 16 Ld SOIC (300 mil)
X9421YS16IZ-2.7* (Note) X9421 YS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-Free)
X9421YV14-2.7* X9421 YVF 0 to +70 14 Ld TSSOP (4.4mm)
X9421YV14Z-2.7* (Pb-free) X9421 YVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free)
X9421YV14I-2.7* X9421 YVG -40 to +85 14 Ld TSSOP (4.4mm)
X9421YV14IZ-2.7* (Pb-free) X9421 YVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free)
X9421WS16-2.7* X9421WS F 10 0 to +70 16 Ld SOIC (300 mil)
X9421WS16Z-2.7* (Note) X9421WS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-Free)
X9421WS16I-2.7* X9421WS G -40 to +85 16 Ld SOIC (300 mil)
X9421WS16IZ-2.7* (Note) X9421WS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-Free)
X9421WV14-2.7* X9421 WVF 0 to +70 14 Ld TSSOP (4.4mm)
X9421WV14Z-2.7* (Pb-free) X9421 WVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free)
X9421WV14I-2.7* X9421 WVG -40 to +85 14 Ld TSSOP (4.4mm)
X9421WV14IZ-2.7* (Pb-free) X9421 WVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free)
*Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
X9421
3FN8196.4
January 14, 2009
Detailed Functional Diagrams
Circuit Level Applications
• Vary the Gain of a Voltage Amplifier
• Provide Programmable DC Reference Voltages for
Comparators and Detectors
• Control the V olume in Audio Circuits
• Trim Out the Offset Voltage Error in a Voltage Amplifier
Circuit
• Set the Output Voltage of a Voltage Regulator
• Trim the Resistance in Wheatstone Bridge Circuits
• Control the Gain, Characteristic Frequen cy and
Q-factor in Fi lter Circuits
• Set the Scale Factor and Zero Point in Sensor Signal
Conditioning Circuits
• Vary the Frequency and Duty Cycle of Timer ICs
• Vary the DC Biasing of a Pin Diode Attenuator in RF
Circuits
• Provide a Control Variable (I, V, or R) in Feedback Circuits
System Level Applications
• Adjust the contrast in LCD displays
• Control the Power Level of LED Transmitters in
Communication Systems
• Set and Regulate the DC Biasing Point in an RF Power
Amplifier in Wireless Systems
• Control the Gain in Audio and Home Entertainment
Systems
• Provide the Variable DC Bias for Tuners in RF Wireless
Systems
• Set the Operating Points in Temperature Control Systems
• Control the Operating Point for Sensors in Industrial
Systems
• Trim Of fset and Gain Errors in Artificial Intelligent Systems
WIPER
COUNTER
REGISTER
(WCR)
RH/VH
RL/VL
DATA
RW/VW
INTERFACE
AND
CONTROL
CIRCUITRY
VCC
VSS
CS
SCK
A0
SO
SI
HOLD
WP
CONTROL
64-taps
10kΩ
POWER-ON RECALL
DR0 DR1
DR2 DR3
X9421
4FN8196.4
January 14, 2009
X9421
(14 LD TSSOP)
TOP VIEW
X9421
(16 LD SOIC)
TOP VIEW
Pin Assignments
Pin Descriptions
Host Interface Pins
SERIAL OUTPUT (SO)
SO is a push/pull serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by the
falling edge of the serial clock.
SERIAL INPUT
SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the potentiometer and pot register
are input on this pin. Data is latched by the rising edge of the
serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9421.
CHIP SELECT (CS)
When CS is HIGH, the X9421 is deselected and the SO pin
is at high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state. CS LOW
enables the X9421, placing it in the active power mo de. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the se rial
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
SCK is LOW. To resume communication, HOLD is brought
HIGH, again while SCK is LOW. If the pause feature is not
used, HOLD should be held HIGH at all times.
RW/VW
NC
VCC
A0
HOLD
CS
S0
SI
NC
SCK
RL/VL
RH/VH
WP
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
NC
SO
NC
CS
SCK
SI
VSS
NC
VCC
RL/VL
RH/VH
RW/VW
ISEN
AO
WP
NC
TSSOP
PIN NO. SOIC
PIN NO. SYMBOL DESCRIPTION
1 2 SO Serial Data Output
2, 3 3, 1, 7, 5 NC No Connect
44CS
Chip Select
5 5 SCK Serial Clock
6 6 SI Serial Data Input
7 8 VSS System Ground
89WP
Hardware Write Protect
9 10 A0 Device Address
10 HOLD Device select. Pause the serial bus.
11 12 RW/VWWiper Terminal of the Potentiometer.
12 13 RH/VHHigh Terminal of the Potentiometer.
13 14 RL/VLLow Terminal of the Potentiometer.
14 16 VCC System Supply Voltage
X9421
5FN8196.4
January 14, 2009
DEVICE ADDRESS (A0)
The address input is used to set the least significant bit of
the 8-bit slave address. A match in the slave address serial
data stream must be made with the address input in order to
initiate communication with the X94 21. A maximum of two
devices may occupy the SPI serial bus.
Potentiometer Pins
VH/RH, VL/RL
The VH/RH and VL/RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
VW/RW
The wiper output is equivale nt to the wiper output of a
mechanical potentiometer.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to the
Data Registers. Writing to the Wiper Counter Register is not
restricted.
SYSTEM/DIGITAL SUPPLY (VCC)
VCC is the supply voltage for the system/digit al section. VSS
is the system ground.
Principles of Operation
The X9421 is a highly integrated microcircuit incorporating a
resistor array and associated registers and counter and the
serial interface logic providing direct communication
between the host and the XDCP potentiometer.
Serial Interface
The X9421 supports the SPI interface hardware
conventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW and the
HOLD and WP pins must be HIGH during the entire
operation.
The SO and SI pins can be connected together, since they
have three state output s. This can help to reduce system pin
count.
Array Description
The X9421 is comprised of one re sistor array containing 63
discrete resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (V H/RH and VL/RL
inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper (VW/RW)
output. Within the individual array only one switch may be
turned on at a time .
These switches are controlled by a Wiper Counter Register
(WCR). The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches. The block diagram of the
potentiometer is shown in Figure 1.
Wiper Counter Register (WCR)
The X9421 contains a Wiper Counter Register. The WCR
can be envisioned as a 6-bit parallel and serial load counter
with its outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can be
altered in four ways: it may be written directly by the host via
the Write Wiper Counter Register instruction (serial load); it
may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decrement instruction. Finally, it is
loaded with the contents of its dat a register zero (DR0) upon
power-up.
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9421 is powered-down.
Although the register is automatically loaded with th e value
in DR0 upon power-up, this may be different from the value
present at power-down.
Data Registers
The potentiometer has four 6-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can
also be transferred between any of the four Data Registers
and the WCR. It should be noted all operations changing
data in one of the Data Registers is a nonvolatile operation
and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Register Descriptions
TABLE 1. DATA REGISTERS, (6-BIT), NONVOLATILE
There are four 6-bit Data Registers associated with the
potentiometer.
• {D5~D0}: These bits are for general purpose Nonvolatile
data storage or for storage of up to four different wiper
values.
TABLE 2. WIPER COUNTER REGISTER, (6-BIT), VOLATILE
• {WP5~WP0}: These bits specif y the wiper position of the
potentiometer.
0 0 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
0 0 WP5WP4WP3WP2WP1WP0
(MSB) (LSB)
X9421
6FN8196.4
January 14, 2009
Write In Process
The contents of the Dat a Reg isters are saved to nonvo latile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can b e monitored by a
Write In Process bit (WIP). The WIP bi t is read with a Read
St atus command.
Instructions
Address/Identification (ID) Byte
The first byte sent to the X9421 from the host, following a CS
going HIGH to LOW, is called the Address or Identificati on
byte. The most significant four bits of the slave address are a
device type identifier, for the X9421 this is fixed as 0101[B]
(refer to Figure 2).
The least significant bit in the ID byte selects one of two
devices on the bus. The physical device address is defined
by the state of the A0 input pi n. The X9421 compares the
serial data stream with the address input state; a successful
compare of the address bit is required for the X9421 to
successfully continue the command sequence. The A0 input
can be actively driven by a CMOS input signal or tied to VCC
or VSS.
The remaining three bits in the ID byte must be set to 110.
Instruction Byte
The next byte sent to the X9421 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next two bits point to one of four Data
Registers. The fo rmat is shown below in Figure 3.
The four high order bits of the instruction byte specify the
operation. The next two bits (R1 and R0) select one of the
four registers that is to be acted upon when a register
oriented instruction is issued. The last two bits are defined
as 0.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0 REGISTER 1
REGISTER 2 REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
VH
VL
VW
8 6
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN VW = VL
IF WCR = 3F[H] THEN VW = VH
WIPER
(WCR)
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
10 0 11 0A0
DEVICE TYPE
IDENTIFIER
DEVICE ADDRESS
1
FIGURE 2. ADDRESS/IDENTIFICATION BYTE FORMAT
I1I2I3 I0 R1 R0 0 0
REGISTER
SELECT
INSTRUCTIONS
FIGURE 3. INSTRUCTION BYTE FORMAT
X9421
7FN8196.4
January 14, 2009
Two of the eight instructions are two bytes in length and end
with the transmissi on of the instruction byte. These
instructions are:
• XFR Data Register to Wiper Counter Register —This
instruction transfers the contents of one specified Data
Register to the Wiper Counter Register.
• XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper Counter
Register to the specified associated Data Register.
The basic sequence of the two by te instructions is illu strated
in Figure 4. These two-byte instructions exchange dat a
between the WCR and one of the D at a Reg isters. A transfer
from a Data Register to a WCR is essentially a write to a static
RAM, with the static RAM controlling the wiper posi tion. The
response of the wiper to this action will be delayed by tWRL. A
transfer from the WCR (current wiper position), to a Dat a
Register is a write to nonvolatile memory and t akes a
minimum of tWR to complete. The transfer can occur between
the potentiometer and one of its associated registers.
Five instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9421; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are:
• Read Wiper Counter Register—read the current wiper
position of the pot,
• Write Wiper Counter Register—change current wiper
position of the pot,
• Read Data Register—read the contents of the selected
data register;
• Write Data Register—write a new value to the selected
data register.
• Read Status—This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
The sequence of these operations is shown in Figure 5 and
Figure 6.
The final command is Increment/Decrement. It is different
from the other commands, because it’s length is
indeterminate. Once the command is issued, the master can
clock the wiper up and/or down in one resistor segment step;
thereby, providing a fine tuning capability to the host. For
each SCK clock pulse (tHIGH) while SI is HIGH, the selected
wiper will move one resistor segment towards the VH/RH
terminal. Similarly, for each SCK clock pulse while SI is
LOW, the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in Figure 7
and 8.
0101110A0I3 I2 I1 I0 R1 R0 0 0
SCK
SI
CS
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
0 101 0A0 I3 I2 I1 I0 R1 R0 0 0
SCL
SI
0 0 D5 D4 D3 D2 D1 D0
CS
11
FIGURE 5. THREE-BYTE INSTRUCT ION SEQUENCE (WRITE)
X9421
8FN8196.4
January 14, 2009
0 101 0A0 I3 I2 I1 I0 R1 R0 0 0
SCL
SI
CS
11
S0
0 0 D5 D4 D3 D2 D1 D0
DON’T CARE
FIGURE 6. THREE-BYTE INSTRUCTION SEQUENCE (READ)
0101110A0 I3 I2 I1 I0 0 0 0
SCK
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
CS
FIGURE 7. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
SCK
SI
VW
INC/DEC CMD ISSUED
tWRID
VOLTAGE OUT
FIGURE 8. INCREMENT/DECREMENT TIMING LIMITS
X9421
9FN8196.4
January 14, 2009
TABLE 3. INSTRUCTION SET
Instruction Format
NOTES:
1. “A0”: stands for the device addresses sent by the master.
2. WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during
active SCK phase (high).
3. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Read the contents of the Register pointed to by R1 - R0.
Write Data Register (DR)
Write a new value to the Register pointed to by R1 - R0.
INSTRUCTION
INSTRUCTION SET
OPERATIONI3I2I1I0R1R0
Read Wiper Counter Register 1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register
Write Wiper Counter Register 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register
Read Data Register 1 0 1 1 1/0 1/0 0 0 Read the contents of the Data Register pointed to by R1 - R0
Write Data Register 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to by R1 - R0
XFR Data Register to Wiper
Counter Regis ter 1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to by R1 -
R0 to the Wiper Counter Register
XFR Wiper Counter Register to Data
Register 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by R1 - R0
Increment/Decrement Wiper
Counter Regis ter 0 0 1 0 0 0 0 0 Enable Increment/decrement of the Wiper Counter Register
Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by checking the WIP
bit.
CS
FALLING
EDGE
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES INSTRUCTION
OPCODE WIPER POSITION
(SENT BY X9421 ON SO) CS
RISING
EDGE0101110A0 1 0 0 1000000WP5WP4WP3WP2WP1WP0
CS
FALLING
EDGE
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES INSTRUCTION
OPCODE DATA BYTE
(SENT BY HOST ON SI) CS
RISING
EDGE0101110A0 1 010000000WP5WP4WP3WP2WP1WP0
CS
FALLING
EDGE
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES INSTRUCTION
OPCODE REGISTER
ADDRESSES DATA BYTE
(SENT BY X9421 ON SO) CS
RISING
EDGE0101110A01011R1R00000WP5WP4WP3WP2WP1WP0
CS
FALLING
EDGE
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES INSTRUCTION
OPCODE REGISTER
ADDRESSES DATA BYTE
(SENT BY HOST ON SI) CS
RISING
EDGE HIGH-VOLTAGE
WRITE CYCLE
0101110A
01100R
1R
00000WP
5WP
4WP
3WP
2WP
1WP
0
X9421
10 FN8196.4
January 14, 2009
Transfer Data Register (DR) to Wiper Counter Register (WCR)
T ransfer the contents of the Register pointed to by R1 - R0 to the WCR.
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Increment/Decrement Wiper Counter Register (WCR)
Read Status
CS
FALLING
EDGE
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES INSTRUCTION
OPCODE REGISTER
ADDRESSES CS
RISING
EDGE0101110 A0 1 101R1R000
CS
FALLIN
G EDGE
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES INSTRUCTION
OPCODE REGISTER
ADDRESSES CS
RISING
EDGE HIGH-VOLTAGE
WRITE CYCLE0101110A01110R1R000
CS
FALLING
EDGE
DEVICE TYPE
IDENTIFIER DEVICE
ADDRESSES INSTRUCTION
OPCODE INCREMENT/DECREMENT
(SENT BY MASTER ON SDA) CS
RISING
EDGE0101110A000100000I/DI/D....I/DI/D
CS
FALLING
EDGE
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES INSTRUCTION
OPCODE DATA BYTE
(SENT BY X9421 ON SO) CS
RISING
EDGE
0101110A0010100010000000W
IP
X9421
11 FN8196.4
January 14, 2009
Analog Specificatio n s (Over recommended operating conditions unless otherwise stated.)
Absolute Maximum Ratings Thermal Information
Supply Voltage (VCC Limits)
X9421. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
X9421-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Voltage on SCK, SDA any address input
with respect to VSS: . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
ΔV = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Any VH/RH, VL/RL, VW/RW . . . . . . . . . . . . . . . . . . . . . VSS to VCC
Thermal Resistance (Typical, Note 1) θJA (°C/W)
14 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
16 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN.
(Note 5) TYP.
(Note 6) MAX.
(Note 5) UNITS
Rtotal End to End Resistance
Tolerance -20 +20 %
Power Rating +25°C, each pot 50 mW
RWWiper Resistance Wiper Current
Iw = (VH - VL)/RTOTAL, VCC = 5V 150 250 Ω
Wiper Current
Iw = (VH - VL)/RTOTAL, VCC = 3V 400 1000 Ω
VTERM Voltage on any VH/RH, VL/RL,
VW/RWVSS = 0V VSS VCC V
Noise Ref: 1kHz -120 dBV
Resolution (Note 4) (Note 5) 1.6 %
Absolute Linearity (Note 1) Vw(n)(actual) - Vw(n)(expected) -1 +1 MI (Note 3)
Relative Linearity (Note 2) Vw ( n + 1) - [Vw(n) + MI] -0.2 +0.2 MI (Note 3)
Temperature Coefficient of
RTOTAL (Note 5) ±300 ppm/°C
Ratio metric Temperature
Coefficient (Note 5) ±20 ppm/°C
CH/CL/CWPotentiometer Capacitances See “Circuit #3 SPICE Macro Model” on
page 13 10/10/25 pF
IAL Rh, RI, Rw leakage current VIN = VSS to VCC. Device is in stand-by
mode. 0.1 10 µA
X9421
12 FN8196.4
January 14, 2009
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Power-up Requirements
(Power-up sequencing can affect correct recall of the wiper
registers) The preferred power-on sequence is as follows:
First VCC and then the potentiometer pins, RH, RL, and RW.
Voltage should not be applied to the potentiometer pins
before VCC is applied. The VCC ramp rate specification
should be met, and any glitches or slope changes in the VCC
line should be held to <100mV if possible. Also, VCC should
not reverse polarity by more than 0.5V. Recall of wiper
position will not be complete until VCC reaches its final
value.
DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified).
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN
(Note 5) TYP
(Note 6) MAX
(Note 5) UNITS
ICC1 VCC Supply Current
(Active) fSCK = 2MHz, SO = Open,
Other Inputs = VSS 400 µA
ICC2 VCC Supply Current
(Nonvolatile Write) fSCK = 2MHz, SO = Open,
Other Inputs = VSS 3.5 mA
ISB VCC Current (Standby) SCK = SI = VSS, Addr. = VSS 3µA
ILI Input Leakage Current VIN = VSS to VCC 10 µA
ILO Output Leakage Current VOUT = VSS to VCC 10 µA
VIH Input HIGH Voltage VCC x 0.7 VCC + 0.3 V
VIL Input LOW Voltage -0.5 VCC x 0.1 V
VOL Output LOW Voltage IOL = 3mA 0.4 V
PARAMETER MIN UNITS
Minimum Endurance 100,000 Data Changes per Bit per Register
Data Retention 100 Years
SYMBOL TEST TYP UNITS TEST CONDITIONS
COUT (Note 5) Output Capacitance (SO) 8 pF VOUT = 0V
CIN (Note 5) Input Capacitance (A0, SI, and SCK) 6 pF VIN = 0V
SYMBOL PARAMETER MIN MAX UNITS
tRVCC(Note 5) VCC Power-up Ramp 0.2 50 V/msec
NOTES:
1. Absolute Linearity is utilized to determine actual wiper voltage versus expected volt age as determined by wiper position when used as a
potentiometer.
2. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = RTOT/63 or (VH - VL)/63, single pot
4. Typical = Individual array resolution.
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization
and are not production tested.
6. Limits should be considered typical and are not production tested.
7. This parameter is not production tested. Parameter established by characterization.
X9421
13 FN8196.4
January 14, 2009
AC Test Conditions
Equivalent AC Load Circuit
Circuit #3 SPICE Macro Model
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
5V
1533Ω
100pF
SDA Output
2.7V
100pF
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
X9421
14 FN8196.4
January 14, 2009
AC Timing
High-Voltage Write Cycle Timing
XDCP Timing
SYMBOL PARAMETER MIN
(Note 5) TYP
(Note 6) MAX
(Note 5) UNITS
fSCK SSI/SPI Clock Frequency 2.0 MHz
tCYC SSI/SPI Clock Cycle Time 500 ns
tWH SSI/SPI Clock High Time 200 ns
tWL SSI/SPI Clock Low Time 200 ns
tLEAD Lead Time 250 ns
tLAG Lag Time 250 ns
tSU SI, SCK, HOLD and CS Input Setup Time 50 ns
tHSI, SCK, HOLD and CS Input Hold Time 50 ns
tRI(7) SI, SCK, HOLD and CS Input Rise Time 2 µs
tFI(7) SI, SCK, HOLD and CS Input Fall Time 2 µs
tDIS SO Output Disable Time 0 500 ns
tVSO Output Valid Time 150 ns
tHO SO Output Hold Time 0 ns
tRO SO Output Rise Time 50 ns
tFO SO Output Fall Time 50 ns
tHOLD HOLD Time 400 ns
tHSU HOLD Setup Time 100 ns
tHH HOLD Hold Time 100 ns
tHZ HOLD Low to Output in High Z 100 ns
tLZ HOLD High to Output in Low Z 100 ns
TINoise Suppression Time Constant at SI, SCK, HOLD and CS inputs 20 ns
tCS CS Deselect Time 2 µs
tWPASU WP, A0 and A1 Setup Time 0 ns
tWPAH WP, A0 and A1 Hold Time 0 ns
SYMBOL PARAMETER TYP
(NOTE 6) MAX
(NOTE 5) UNITS
tWR High-voltage Write Cycle Time (Store Instructions) 5 10 ms
SYMBOL PARAMETER MIN
(NOTE 5) MAX
(NOTE 5) UNITS
tWRPO Wiper Response Time After The Power Supply Is Stable 10 µs
tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 10 µs
tWRID Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction) 10 µs
X9421
15 FN8196.4
January 14, 2009
Symbol Table
Timing Diagrams
Input Timing
Output Timing
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM LOW TO
HIGH
WILL CHANGE
FROM LOW TO
HIGH
MAY CHANGE
FROM HIGH TO
LOW
WILL CHANGE
FROM HIGH TO
LOW
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A CENTER LINE
IS HIGH
IMPEDANCE
...
CS
SCK
SI
SO
MSB LSB
HIGH IMPEDANCE
tLEAD
tH
tSU tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
...
CS
SCK
SO
SI ADDR
MSB LSB
tDIS
tHO
tV
...
X9421
16 FN8196.4
January 14, 2009
Hold Timing
XDCP Timing (for All Load Instructions)
XDCP Timing (f or Increment/Decrement Instruction)
...
CS
SCK
SO
SI
HOLD
tHSU tHH
tLZ
tHZ
tHOLD
tRO tFO
...
CS
SCK
SI MSB LSB
VW
tWRL
...
SO HIGH IMPEDANCE
...
CS
SCK
SO
SI ADDR
tWRID
HIGH IMPEDANCE
VW
...
INC/DEC INC/DEC
...
X9421
17 FN8196.4
January 14, 2009
Write Protect and Device Address Pins Timing
Applications information
1. Electronic potentiometers provide three powerful
application advantages: The variability and reliability of a
solid-state potentiometer,
2. The flexibility of computer-bas ed digital controls)
3. the retentivity of nonvolatile memory used for the storage
of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
CS
WP
A0
A1
tWPASU tWPAH
(ANY INSTRUCTION)
VR
VW
VR
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
VH
VL
X9421
18 FN8196.4
January 14, 2009
Application Circuits
NONINVERTING AMPLIFIER
VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERITISIS
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/CR1+R2} VO(max)
VLL = {R1/CR1+R2} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
VS
VO
R2
R1
}
}
+5V
-5V
LM308A
CASCADING TECHNIQUESBUFFERED REFERENCE VOLTAGE
–
+
+5V
R1
+V
-5V
VW
VWVOUT = VW
OP-07
VW
VW
+V
+V +V
X
(a) (b)
X9421
19 FN8196.4
January 14, 2009
X9421
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
α0o8o0o8o-
Rev. 2 4/06
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8196.4
January 14, 2009
X9421
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
