ST70134A - STMicroelectronics - Datasheet.Directory

1/22January 2001

■FULLY INTEGRATED AFE FOR CPE ADSL

■OVERA LL 12 B IT RESOLUTION , 1.1MHz

SIGNAL BANDW IDTH IN Rx

■8.8M S/s ADC

■8.8MS /s DAC

■THD: -60dB @FULL SCALE

■4-BIT DIGI TAL INT ER FACE TO/ FROM THE

DMT MODEM

■1V FULL SCALE INPUT

■DIFFERENTIAL ANALOG I/O

■ACCURA TE CONTINUOUS-TIME CHANNEL

FILTERING

■3rd & 4th ORDER TUNABLE CONTINUOUS

TI ME L P FI LT E R S

■0.5 WATT AT 3.3V

■0.5mm HCMOS5 LA TECHNOLO GY

■64 PIN TQF P PACKAGE

DESCRIPTION

ST 70134 i s the Anal og Front End of the STM icro-

electronics ASCOTTM ADSL chipset and when

coupled with ST70135A or ST70235 (DMT

mode m) allows to g et a T1.413 Issue 2 or G.dmt

compliant so l ut i on.

The ST70134 analog front end handles 2 trans-

mission channels on a balanced 2 wire intercon-

nection; a 16 to 640Kbit/s upstream transmit

channel and a 1.536Mbit/s to 8.192Mbit/s down-

stream receive channel.

This asymmetrical data transmissi on system uses

high resolution, high speed analog to digital and

digital to analog conversion and high order analog

filtering to reduce the echo and noise in both

receive rs and transmitters.

External low noise driver and input stage used

with ST70134 guarante e low noise performances .

The filters, with a programm able cutoff freque ncy,

use automatic Continuous Time Tuning to avoid

time varying phase c haracteristic which can be of

dramatic co nsequence f or DMT modem .

It requi res few ex ternal compon ents, uses a 3.3V

supply. It is packaged in a 64- pi n TQ FP in order to

reduce PCB area.

TQFP64

ORDERING NUMBER:

ST7 0134 (TQFP 64)

ST 70134A (TQF P 64)

ST70134 - ST70134A

ASCOTTM INTEGRATED ADSL CMOS

ANALOG FRONT-END CIRCUIT

ST70134A

2/22

Fi gure 1 : Blo ck Diagram

The Receiver (RX) Part

The DMT signal coming from the line to the

ST70134 is first filtered by two external filters,

Pots HP and channel filters.

An analog multiplexer allows the selection

between two input ports which can be used to

select an attenuated (0, 10dB for ex.) version of

the signal in case of short loop or large echo.

The sig nal is amplified by a l ow noise gain stage

(0-31dB) then low-pass filtered to avoid aliasing

and to ease further digital processing by r emoving

unwanted high frequency out-of-band noise.A

13-bit A/D converter samples the data at

8.832MS/s (or 4.416MS/s in alternative mode),

transforms the signal into a digital representation

and sends it to the DMT signal processor via the

digital interface.

The Transmi tte r (TX) part

The 12 -b it data words at 8 .832MS/ s (or 4.41 6MS/

s) com ing from the DMT signal process or through

the digital interface are transformed by D/A con-

verter int o a analog signal.

This sign al is then filtered to dec rease DMT si de-

lobes level and meet the ANSI transmi tter spectr al

response but also to reduce the out-of-band noise

(which can be echoed to the RX path) to an

accep table level . The pre-driver buffers th e signa l

for the external line driver and in case of short

loop provide at tenuation (-15...0d B).

The VCXO Part

The VCXO is divided in a XTAL dr iver and a aux il-

iary 8 bits DAC for timing recovery.The XTAL

driver is able to operate at 35. 328MHz.

The DAC which is driven by the CTRLIN pin pro-

vides a current output with 8-bit resolution and

can be used to tune the XTAL frequency with the

help of external comp onent s.

A time constant between DAC input and VCXO

output can be in troduced (via the CTLIN i nterface)

and programmed with the help of an external

capacitor (on VCOC pin).See chapter ’VCXO’ for

the external circuit related to the VCXO.

The Digi tal Interface Part

The digital part of the ST70134 can be divided in 2

sections:

– The data i nterfac e conv erts the multiplexed data

from/to the DMT signal processor into valid

representation for the TX DAC and RX ADC.

– The control i nterface allows the board processor

to configure the STL70 134 pat hs (RX/TX gains,

filter band, ...) or settings (OSR, vcodac enable,

digital / ana log loopb ack,...).

R-MOS-C

TUNING I/V-REF XTAL-DRIVER

VCXO DAC

G = -1 5...0dB

st ep = 1d B

AGCtx

TXP

TXN

1.1MHz

HC2

1.1MHz

HC1

138kHz

SC2

DIGITAL

DAC

AGCrx

G = 0...31dB

st ep = 1d B

RXP(0:1)

RXN(0:1)

ADC

13 B its

12 B its

Rx (0:3)

Tx ( 0:3)

ST70134A

3/22

DMT Signal (Done by the DMT companion

chip)

A DMT signal is basically the sum of N indepen-

dentl y QA M m odu lat ed si gnals, each carried ov er

a distinct carrier. The frequency separation of

each carrier is 4.3125kHz with a total number of

256 carri ers ( ANSI) . For N large, the signal can be

modelled by a gaussian process with a certain

amplitude probability density function. Since the

maximum amplitude is expected to arise very

rarely, we decide to clip the signal and to trade-off

the resulting SNR loss against AD/DA dy nam ic. A

clipping factor (Vpeak/V rms = "crest factor") of 5.3

will be used resulting in a maximum SNR of 75dB.

ADSL DM T sig nals are nominally sent at an aver-

age of -3 8dBmHz (-1.65dBm /carrier) with a m axi-

mal power of 15.7mW for the transmitter

(upstream for ADSL over Pots, DMT carriers are

from 7 to 31, for ADSL over ISDN DMT carriers

are from 31 to 64).

Maxi mum / Minim um Signal Levels

The following table gives the transmitted and

received signal levels for CPE (ATU-R) and, for

reference, at ATU-C. All the levels are referred to

the line voltages (i.e. after hybrid and transform-

ers in TX direction, before hybrid and trans form er

in RX direction).

Note that signal amplitudes shown below are for

illustration purpose and depending on the t ransmi t

power an d line impedance signal amplitudes can

differ from these values.

The ref erence line im ped anc e for all po wer calcu-

lations is 100Ω.

Package

The ST70134 is packaged in a 64-pin TQFP pack-

age (body size 10x10mm , pitch 0.5mm ).

* Power cut back software co facility.

Table 1 : Target Sign al Levels (on the line)

Parameter ATU - R ATU - C (for reference)

RX TX RX TX

Max level 3.95 Vpdif * 6.8 Vpdif 1.66 mVpdif 15.8 Vpdif *

Max RMS level 791 mVrms 671 mVrms 168 mVrms 3.16 Vrms

Min level 42 mVpdif 839 mVpdif 54 mVpdif 3.95 Vpdif

Min RMS level 8 mVrms 168 mVrms 11 mVrms 791 mVrms

ST70134A

4/22

Fi gure 2 : Pin Connection

58 57 56 55 54 53 52 51 50 4964 63 62 61 60 59

23 24 25 26 27 28 29 30 31 3217 18 19 20 21 22

TX2

TX3

DVSS2

AVSS1

XTALO

XTALI

AVDD1

RES

VCXO

IVCO

AVDD2

IREF

AVSS2

AVSS6

RXIP1

RXIN1

DVDD2

PDOWN

RES

RESETN

RES

GP0

AVSS3

VRAP

VREF

VRAN

AVDD3

AVDD4

NC0

NC1

TXP

TXN

RXIP0

RXIN0

GC1

GC0

VCOC

GP2

AVDD6

AVDD5

RES

AGND

RES

AVSS5

AVSS4

GP1

TX1

TX0

NU3

NU2

NU1

NU0

CTRLIN

DVSS1

CLKM

CLNIB

CLWD

RX3

RX2

RX1

RX0

DVDD1

ST70134

ST70134A

5/22

Table 2 : Pin Functions

Numbers Name Function PCB connection Supply

ANALOG INTERFACE

24 VRAP Positive Voltage Reference ADC Decoupling network AVDD3

25 VREF Ground Reference ADC Decoupling network AVDD3

26 VRAN Negativ e Voltage Refer ence ADC Decoup ling networ k AVDD3

31 TXP Pre Driver Output Line driver input AVDD4

32 TXN Pre Driver Output Line driver input AVDD4

38 AGND Virtual Analog Ground (AVDD/2 = 1.65V) Decoupling network AVDD5

44 VCOC VCODAC Time Constant Capacitor VCODAC cap. AVDD5

45 GC0 External Gain Control Output LSB - AVDD5

46 GC1 External Gain Control Output MSB - AVDD5

47 RXN0 Analog Receive Negative Input Gain 0 Echo filter output AVDD5

48 RXP0 Analog Receive Positive Input Gain 0 Echo filter output AVDD5

49 RXN1 Analog Receive Negative Input Gain 1

(Most Sensitive Input) Echo filter output AVDD5

50 RXP1 Analog Receive Positive Input Gain 1

(Most Sensitive Input) Echo filter output AVDD5

53 IREF Current Reference TX DAC/DACE Decoupling network AVDD2

55 IVCO Current Reference VCO DAC VCO bias network AVDD1

56 VCXO VXCO Control Current VCXO filter AVDD1

59 XTALI XTAL Oscillator Input Pin Crystal + varicap AVDD1

60 XTALO XTAL Oscillator Output Pin Crystal + varicap AVDD1

DIGITAL INTERFACE

1 TX1 Digital Transmit Input, Parallel Data - DVDD2

2 TX0 Digital Transmit Input, Parallel Data - DVDD2

7 CTRLIN Serial Data Input (Settings) Async Interface DVDD2

9 CLKM Master Clock Output, f = 35.328MHz Load = CL<30pF DVDD2

10 CLNIB Nibble Clock Output, f = 17.664MHz

(OSR = 2) or ground (OSR = 4) Load = CL<30pF DVDD2

11 CLWD Word Clock Output, f = 8.832/4.416MHz Load = CL<30pF DVDD2

12 RX3 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2

13 RX2 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2

14 RX1 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2

15 RX0 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2

18 PDOWN Power Down Select, "1" = Power Down Power Down Input DVDD2

20 RESETN Reset Pin (Active Low) RC- Reset DVDD2

22 GP0 General Purpose Output 0 (on AVDD 1) Echo filter output AVDD

33 GP1 General Purpose Output 1 (on AVDD 1) Echo filter output AVDD

43 GP2 General Purpose Output 2 (on AVDD 1) Echo filter output AVDD

63 TX3 Digital Transmit Input, Parallel Data Load = CL<30pF DVDD2

64 TX2 Digital Transmit Input, Parallel Data Load = CL<30pF DVDD2

19, 21 RES RESERVED Must Be Connected to DVSS (Input) -

36, 37, 39,

40, 57 RES RESERVED Must Be Connected to AVSS (Input) -

ST70134A

6/22

SUPPLY VOLTAGES

8 DVSS1 - DVSS -

16 DVDD1 Digital I/O Supply Voltage DVDD -

17 DVDD2 Digital Internal Supply Voltage DVDD -

23 AVSS3 - AVSS -

27 AVDD3 ADC Supply Voltage AVDD -

28 AVDD4 TX Pre - Drivers Supply AVDD -

34 AVSS4 - AVSS -

35 AVSS5 - AVSS -

41 AVDD5 CT Filter Supply AVDD -

42 AVDD6 LNA Supply AVDD -

51 AVSS6 - AVSS -

52 AVSS2 - AVSS -

54 AVDD2 DAC and Support Circuit AVDD -

58 AVDD1 XTAL Oscillator Supply Voltage AVDD -

61 AVSS1 - AVSS -

62 DVSS2 - DVSS -

SPARES

3 NU3 Not Used Inputs DVSS -

4 NU2 Not Used Inputs DVSS -

5 NU1 Not Used Inputs DVSS -

6 NU0 Not Used Inputs DVSS -

29 NC0 - - -

30 NC1 - - -

Fi gure 3 : Grounding and Decoupling Net works

Numbers Name Function PCB connection Supply

F 100nF 10

F 100nF

VRAP Pin VRAN Pin

F 100nF 10

VREF Pin IREF Pin

100nF

Analog

VDD

4.7

F100nF 100nF

AVDD

(Each pin

100nF 10

F10

AGND PinVCOC Pin

must have its

own capacitor)

ST70134A

7/22

BLOCK DIAGRAM

Appl ication principl e is described in Figure 4.

A LP f ilter may be used on th e TX path to reduce

DMT sidelobes and out of band noi se influence on

the receiver. On the RX path, a HP filter must be

use d in order to reduce the echo signal le ve l and

to avoid saturation of the input stage of the

receiver. The POTS filter is used in both directions

to reduce crosstalk between ADSL signals and

PO TS speech an d signalling. Low p ass POTS fi l-

ter can be very s imple for Lite - ADSL appli cation

(see Figure 4).

RX Path

Speech Filter

An external bi-directional LC filter for up and

downstream POTS service splits the speech sig-

nal from the ADSL signal to the POTS circuits.

The ADSL analog front end i ntegrated circuit does

not contain an y circuitry for the POTS service but

it guarantees that bandwidth is not disturbed by

spurious signals from the ADSL-spectrum.

Channel Filt e r s

The external analog circuits provide partial echo

cancellation by an analog filtering of the transmit

upstream signal. This is feasible because the

upstream and the downstream data are modu-

lated on separate carriers (F DM) (see Figure 4).

Si gn a l to Noi se P erf ormance

RX- PA TH SENSITIVITY AT MAXIMUM GA IN

The RX path sensitivity at the maximal RX-AGC of

the receiver is defined at -140dBm/Hz (for 100Ω

ref) on the line. This figure corresponds to the

equivalent input noise of 31nVHz-1/2 seen on the

line.

The maximum n oise d ensity within the pass band

can exceed the average value as follows:

RX path (max AGC setting):

<100nV Hz-1/2 @ 138kHz

<31 nV Hz-1/2 for 250kHz < f

* Fo r A DSL over IS DN, instead of SC2, HC2 1. 1M Hz LP fi l ter is programme d.

Fi gure 4 : Blo ck Diagram

VCODAC XTAL DRIVER

VCXOUT

60 59

35.328MHz

RXN(0:1)

RXP(0:1)

LP 1.1MH z

HC1

13 Bits A/D

Converter

LNA

LP 138KH z

SC2 * 12 Bits D/A

Converter

-15.0dB

TXP

TXN

LPF

GRX

50k

Ω

2R2R

GTX

LINE

DRIVER

2TXn

HP POTSFILTER

LP POTSFILTER

POTS

1.1

Line

Zo = 100

Ω

M aster Clock

35.328MHz

Nibbles

17.664MHz

Word

8.832/4.416MHz

RXn

CTRLIN

RESETN

To ST70135

50k

Ω

HPF + Attenuator

ST70134A

8/22

RX-PATH NOISE AT MINIMUM GAI N

At the minimum AGC the total average thermal

noise of the analog RX-path at the ADC input

sho uld be lower than the A DC qua ntisa tion noise.

The maximum n oise d ensity within the pass band

can exceed the average value as follows:

RX path (min AGC setting) <500nVHz-1/2 @

138kHz < f

These noise specifications correspond to 10bit

resolution of the complete RX-path.

AGC of RX Path

The AGC gain in the RX-path is controlled t hrough

a 5-bits digital code.

Four inputs are provided for RX input and the

selection is made with the RXMUX bits of the

CTRLIN interface.

This can be used to make lower gain paths in

case of high input signal.

RX Filters

The combination of the external filter (an LC lad-

der filter typically) with the integrated lowpass fil-

ter must provide:

– Echo reduct ion to improve dynam ic range.

– DMT sidelobe and out of band (anti-aliasing) at-

tenuation.

– Anti a lias f ilt er (60 dB reje ction @ i mage fr equenc y).

RX Filters

The integrated filter have the following character-

istics:

Table 3 : RX Common-mode Volt age

Description Value/Unit

Common mode signal VCM

at RXIN1 and RXIN2: 1.6V < VCM <1.7V

Table 4 : AGC Characteristics

Description Value/Unit

Input referred noise(max. gain) 31nVHz-1/2

Max. input level 1Vpd

Max. output level 1Vpd

Gain range 0 to 31dB with

step = 1dB

Gain and step accuracy ± 0.3dB

Table 5 : Integrated HC Filter Characteristics

Description Value / Unit

Maximum input level 1Vpd

Maximum output level 1Vpd

Type 3rd order butterworth

Frequency band 1.104MHz (0% setting, see below)

Frequency tuning -43.75% -> +0%

Max. in-band ripple 1dB

Matlab Model

Default cut off frequency @ -3dB

Actual cut off @ -3dB

HC Freq. selection register

[B, A] = butter (3, w0, 's')

F0 = 1560KHz

w0 = 2 * pi * F0/((20 + n)/16)

n = -4,..,3 see (AFE settings,Table 19)

Table 6 : Phase Characteristic

Description Value / Unit

Total RX filter group delay < 50µs @ 138kHz < f < 1.104MHz

Total RX filter group delay distortion < 15µs @ 138kHz < f < 1.104MHz

ST70134A

9/22

Fi gure 5 : HC Filter Mask for RX

Note: The total RX path (incl uding ADC) group delay distortion is 16µs (i.e . = 15 µs + 1 µs of AD C)

Lineari ty of R X

Linearity of t he RX analog path is defined by the IM3 product of two sinusoidal signals with frequencies f1

and f2 and each with 0.5Vpd amplitude (total

≤

1Vpd) at the output of the RX - AGC amplifier (i.e: before

the ADC) for the cas e of minimal AGC se tting.

Table 7 lists the RX path intermodulation distortion (as S/IM3 ratio) in downstream and upstream band-

width.

Power Supply Rejection

The n oise on the power supplies for the RX pa th must be lower than the following: <50mVrms in band

white noise for any AVDD.

In t his case, PSR (power supply rejection) of ST70134 RX path i s lower t h an -43dB .

Table 7 : Linearity of RX

f1 (0.5Vpd)

f2 (0.5Vpd) 300kHz

200kHz 500kHz

400kHz 700kHz

600kHz

S/IM3

(AGC = 0dB) 59.5dB @ 100kHz

53.5dB @ 400kHz

43.5dB @ 700kHz

42.5dB @ 800kHz

59.5dB @ 300kHz

48.0dB @ 600kHz 48.0dB @ 500kHz

42.5dB @ 800kHz

Table 8 : RX Filter to A/D Interface

RX filter to A/D maximal level: 1Vpd = full scale of A/D

Table 9 : A/D Converters

Numbers of bits: 12bits

Minimum resolution of the A/D converter 11bits

Linearity error of the A/D converter <1LSB (out of 12bits)

Full scale input range: 1 Vpdif ±5%

Sampling rate: 8.832MHz (or 4.416MHz in OSR = 2 mode)

Maximum attenuation at 1.1MHz: <0.5dB without in-band ripple

Maximum group delay: <3µs

Maximum group delay distortion: <1µs

5dB 36dB 50dB

±1dB

0dB

30 1104 2208 7728 16

560

kHz

Amplitude

ST70134A

10/22

TX Pre-driver Capability

The pre-driver drives an external line power amplifier which t ransmits the required power to the line.

TX Filter

The TX filter acts not only to suppress the DMT sidebands but al so as smoothing fi l ter on the D/A conver-

tor’s output to suppress the image spectrum. For this reason it must be realized in a continuous time

approach.

ATU-R TX Filter

The purpos e of this filter is to remove out-of-band noi se of the TX path echoed to the RX path. In order to

meet the transmitter spectral response, an additional filtering must be (digitally) performed. The inte-

grated filter has the foll owing charact eristics:

Note: The total TX path (including DAC) group delay distortion i s 16µs ( i.e. = 1 5 µs + 1µs of DAC).

Table 10 : TX Pre-driver

TX drive level to the external line

driver for max. AGC setting 1.5 Vpdif

External line driver input impedance: resistive

capacitive > 500Ω

< 30pF

Pre-driver characteristics:

Closed loop gain: -15dB...0dB with step = 1dB

Output characteristics

Output offset voltage (0dB) < 10mV

Output noise voltage (0dB) < 150nVHz-1/2 @ f > 250kHz

< 500nVHz-1/2 @ 34.5kHz < f < 138kHz 0dB

Output common mode voltage: 1.6V < Vcm < 1.7V

Table 11 : Integrated SC Filter Characteristics

Description Value/Unit

Maximum input level 1Vpd

Maximum output level 1Vpd

Type 4th order chebytchef

Frequency band 138kHz (0% setting see below)

Frequency tuning -25% -> +25%

Max. in-band ripple 1dB

Matlab Model

Default cut-off frequency @ -3dB

Actual cut-off @ -3dB

SC Frequency selection register

[B,A] = cheby1 (4,0.5,W0,’s’) {ripple = 0.5}

F0 = 151.8kHz

W0 = 2*pi*F0/((17+n)/16)

n = -4,..,3 see (AFE settings, Table 19)

Total TX filter group delay < 50µs @ 34.5kHz < f < 138kHz

Total TX filter group delay distortion < 20µs @ 34.5kHz < f < 138kHz

ST70134A

11/22

Fi gure 6 : SC Filter Mask for TX

Linearity in TX

Linearity of the T X is defined by t he IM3 prod uc t of two sinusoida l signals wi th frequencies f1 and f2 and

each with 0.5Vpd amplitude (total ≤ 1Vpd) at the output of the pre-driver for the case of a total

AGC = 0dB.

TX Idle Channel Noise

The idle channel noise specifications correspond with 11bit resolution of the complete TX-path. TX idle

channel output noise on TXP, TXN.

Power Supply Rejection

The noise on the power supplies for the TX-path must be lower than the following:

< 50mVrms in-band white noise for AV DD.

< 15mVrms in-band white noise for Pre-driver AVDD.

VCXO

A voltage controlled crystal oscillator driver is integrated in ST70134. The nominal frequency is

35.328MHz. The quartz crystal is connected between the pins XTALI and XTALO. The principle of the

VCXO control i s shown in Figure 7.

Table 12 : D/A Converter (A current steering architecture is used)

Description Value / Unit

Numbers of bits: 12bits

Minimum resolution of the D/A converters 11bits

Linearity error of the A/D converter <1LSB (out of 12bits)

Full scale input range: 1 Vpdif ±5%

Sampling rate: 8.832MHz (or 4.416MHz in compatible mode)

Maximum group delay: <3µs

Maximum group delay distortion: <1µs

Table 13 : Linearity in TX

f1 (0.5Vpd) 80kHz

f2 (0.5Vpd) 70kHz

S/IM3 (AGC = 0 dB) 59.5dB (@ 60KHz, 90KHz)

Table 14 : TX idle channel noise

For max AGC setting (0dB)

In-band noise

Out-of-band noise 1.6µVHz-1/2

150nVHz-1/2 @ 34.5kHz -138kHz

@ 250kHz -1.104MHz

For min AGC setting (=-15dB)

In-band noise 500nVHz-1/2 @ 34kHz -138kHz

Amplitude

0dB ±1dB 20dB

30 138 250 kHz

ST70134A

12/22

The information coming from the digital processor via the CTRLIN path is used to drive an 8-bit DAC

which generates a control current. This current is externally converted and filtered to generate the

required c ontrol vol tage (range :-15V to 0.5V) f or the varicap. T he V CXO circui t c haracteristics a re given

in Tabl e 15.

N.B: frequency tuning range is proportional to the crystal dyna mi c capacitance Cm .

Fi gure 7 : Principle of VCXO co ntrol

The tuning must be monotonic with 8-bit resolution with the worst-case tuning step of <2ppm/ LSB (8-bit ).

The time constant of the tuning must be variable from 5s to 10s through an external capacitor Cs (R =

1MΩ ±30%). This determines the speed of the VCXO in normal operation (slow speed in "show time")

with filtered VCXO. For faster tracking, the previous filter is not used and the speed depends on CtRt.

DIGITAL INTERFACE

Co ntrol Interface

The digital setting codes for the ST70134 configuration are sent over a serial line (CTRLIN) using the

word clock (CLWD).

The data burst is composed of 16 bits from which the first bi t is used as start bit ('0'), the three LSBs being

used to identify the data contained in the 12 remaining bits.

Table 15 : VCXO circuit Characteristic s

Symbol Parameter Minimum Nominal Maximum Note

fabs Absolute frequency accuracy -15ppm 35.328MHz +15ppm

frange Frequency Tuning Range ±50ppm

IO VCXO Output Current 100µA Rref = 16.5kΩ

AVDD = 3.3V

Ii Reference Input Current 100µA 1mA AVDD = 3.3V

DAC

8 Bits 1M

Ω

30%

Filtered VCXO

(see CTRLIN table)

VCOC

AVDD

CTRLIN

55 IVCO AVDD

Rref

AVDD/22 ÷ AVDD/2

56 VCXO

Clk35 60

XTALI

XTALO

Ct Rt

AGND

Io = l i

-15V

ST70134A

13/22

Note 1. Aft er i ni tialization, this bi t ha s t o be clear ed (0) to make the de vice properly operate.

Table 16 : Control Interface Bit Mapping

MSB LSB RX SETTINGS

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

0X 0 0 0 External Ga in Control GC1 (init = 0)

0 X 0 0 0 External Ga in Control GC0 (init = 0)

0 0 0 0 0 Rx input selected = RXIN0, RXIP0 (init)

0 1 0 0 0 Rx input selected = RXIN1, RXIP1

0 0 0 0 0 0 0 0 0 AGC RX Gain setting 0dB (init)

0 00001 0 00AGC RX Gain setting 1dB

0 XXXXX 000AGC RX Gain setting XdB

0 1 1 1 1 1 0 0 0 AGC RX Gain setting 31dB

0 0 0 0 0 0 Normal mode Filter selection (init)

0 0 1 0 0 0 Force HC2 for R X path, T X grounded

0 1 0 0 0 0 Force HC1 for RX path

0 1 1 0 0 0 Normal mode Filter selection

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TX SETTINGS

0 0 0 0 0 0 0 1 T ra nsmit TX - AGC setting -1 5dB (init)

0 0 0 0 1 0 0 1 Transmit TX - AGC setting -14dB

0 X X X X 0 0 1 T rans m i t TX - A G C s ettin g (X - 15) dB

0 1 1 1 1 0 0 1 Transmit TX - AGC setting 0dB

0 0 0 0 0 0 0 1 Not used (i ni t)

0 X X X 0 0 1 Gene ral Pur pose Ou t put (GPO) setting (i n i t = 000)

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AFE SE TTINGS

00 0 1 0 Normal M ode (Di gi tal path) (i ni t)

01 0 1 0 Digital Loopback (di g i t al T X to digi tal RX - DA C n ot u sed)

0 0 0 1 0 Normal Mode (Analog path)

01 010

Analog loop back (RXi to TXi - ADC not used)

(init)

0 0 0 1 0 VCO DAC di sabled

0 1 0 1 0 VCO DAC enabled (i ni t)

0 0 0 1 0 HC2 filt er disabl ed (i ni t)

0 1 0 1 0 HC2 filt er enabled

ST70134A

14/22

* F or each f i l ter, 8 possible frequency values (see Table 5 and Tabl e 11). Notati on i s 2’s compl ement range from -4 = 100b +3 = 011b. Fc is

the frequency band (-1dB)

Table 17 : Control Interface Bit Mapping (continued)

MSB LSB AFE SET T INGS

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 1 0 OSR set to 4 (init)

0 1 0 1 0 OSR set to 2

0 1 1 1 0 1 0 SC freq. selec tion: Fc = 138kHz (init) *

0 0 1 1 0 1 0 SC freq . s el ection: F c ~ 110 kHz *

0 1 0 1 0 1 0 SC freq . s el ection: F c ~ 170kHz *

0 1 0 0 0 1 0 HC freq. selec tion: Fc = 1. 104MHz (init) *

0 0 1 1 0 1 0 HC freq. selection: Fc ~ 768 kHz *

00 0 1 0 VCX O output NOT fil tered ("show-t i me") (init )

01 0 1 0 VCXO output fil tered

b15 b14 b1 3 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 VCO DAC VALUE S ETTINGS

0 0 0 0 0 0 0 0 0 0 1 1 VCO DAC CURRENT value @ MINIMUM

0 XXXXX XXX 01 1VCO DAC CURRENT value @ X

0 11111111 011VCO DAC CURRENT value @ MAXIMUM

b15 b14 b1 3 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PO WER DOWN ANALO G BLO CK SETTIN GS

0 000000000000100Init

00 1 0 0 TXD Active

01 100TXD in powerdown

00 100N.U.

01 100N.U.

00 100ADC Active

01 100ADC in powerdown

001 100HFC2 Active

0 1 1 1 0 0 HFC2 in powerdown

001 100HFC1 Active

0 1 1 1 0 0 HFC1 in powerdown

0 0 1 1 0 0 SCF2 Act ive

011100SCF2 in powerdown

0 0 1 0 0 LNA Active

0 1 1 0 0 L NA i n po werdown

001100DAC Active

0 1 1 1 0 0 D AC i n po werdo wn

0 0 1 0 0 V CODAC Active

0 1 1 0 0 V CODAC in powerdown

00 1 0 0 XTAL Active

0 1 1 0 0 XTAL in powe r down

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RESERVED

0 X X X X X X X X X X X X 1 0 1 RESERVED

0 X X X X X X X X X X X X 1 1 0 RESERVED

0 X X X X X X X X X X X X 1 1 1 RESERVED

ST70134A

15/22

Control Interface Timing

The wo rd clock (CLWD) is used to sample at negative going edge the control information. The start bit

b15 is transmitted first fol lowed by bits b[14: 0] and at least 16 stop bits need to be provided to validate the

data.

Data set-up and hold time versus falling e dge CLWD must be greater than 10nsec.

Receive / Transmit I nterface

RECEIVE / TR ANSMIT PROTOCOL

The digital interface is based on 4 x 8.832M Hz (35.328MHz) data lines in the following manner:

If OSR = 2 (OSR bit set to 1) is selected, CLKNIB is used as nibble clock (17.664MHz, disabled in normal

mode), and all the RXi, TXi, CLKWD periods are twice as long as in normal mode. This ensures a

compat ibility with lower speed products.

TX Signal Dynamic

The d yn amic of dat a sig nal for both TX DACs i s 12 b its extracted f rom the av ailable s igned 16 b it repre-

sen tation com ing from the digital processor.

The maximal positive nu mber is 214-1, the most neg ative num ber is -214, the 3 LSBs are filled with ’0’.

Any signal exceedi ng these limits is clamped to the maximu m value.

The two sign bits must be identical.

Fi gure 8 : Cont ro l Inte rface

Table 18 : TX Data Bit Map

BIT MAP/NIBBLE N0 N1 N2 N3

TXD0 not used data bit 1 data bit 5 data bit 9

TXD1 not used data bit 2 data bit 6 data bit 10

TXD2 not used data bit 3 data bit 7 data SIGN

TXD3 d0 = data bit 0 (LSB) data bit 4 data bit 8 data SIGN

Table 19 : TX Nibble Bit Ma p

N3 N2 N1 N0

sign sign d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 n.u. n.u. n.u.

Data

CLWD

CTRLIN

Start

Bit ID.

>=16 Stop

Bits = High

ST70134A

16/22

RX Signal Dynamic

The dynamic of the signal from the ADC is limited to 13bits. Those bits are converted to a signed (2’s

comple men t) representation with a m axim al posi tive numbe r of 214 -1 and a most negative num ber -214.

The 2 LSBs are filled with ’0’.

The two sign bits must be identical.

Table 20 : RX Data Bit Map

BIT MAP/NIBBLE N0 N1 N2 N3

RXD0 0 data bit 2 data bit 6 data bit 10

RXD1 0 data bit 3 data bit 7 data bit 11

RXD2 d0 = data bit 0 (LSB) data bit 4 data bit 8 data SIGN

RXD3 data bit 1 data bit 5 data bit 9 data SIGN

Table 21 : RX Nibble Bit M ap

N3 N2 N1 N0

sign sign d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0

Fi gure 9 : TX/ RX Digital Interface Timing

CLKM

35.328MHz

CLWD

8.832MHz

TXDx/RXDx

N0 N1 N2 N3

OSR = 4

CLKNIB

17.664MHz

CLWD

4.4162MHz

TXDx/RXDx

N0 N1 N2 N3

OSR = 2

ST70134A

17/22

Recei ve / Transm it Interface Timing

The interface is a quadruple (RX, TX) nibble -

serial interface running at 8.8MHz sampling (nor-

mal mode). The data are represented in 16bits

format, and transferred in groups of 4 bits (nib-

bles). The LSBs are transferred first. The

ST 70134 generates a nibble clock (CLKM master

clock in normal mode , CLKNI B in OS R = 2 mo de)

and word signals shared by t he three interf aces.

Data is transmitt ed on the rising e dge of t he m as-

ter clock (CLKM/CLKNIB) and sampled on the

falling edge of CLKM/CLKNIB. This holds for the

data stream from ST70134 and from the digital

processor.

Data, CLWD setup and hold times are 5ns with

reference to the falling edge of CLKM/CLKNIB.

(not floating).

Data is transmitt ed on the rising e dge of t he m as-

ter cloc k (CLKM/CLKNIB) and sampled on the low

going edge of CLKM/CLKNIB. This holds for the

data stream from ST70134 and from the digital

processor.Data, CLWD setup and hold times are

5ns with reference to the falling edge of CLKM/

CLKNIB . (not floating).

Power Down

When pin Pdown = "1", the chip is set in power

down mode. As the Pdown signal is synchro-

nous ly sampl ed, mini mum durat ion is 2 periods of

the 35MHz clock. In this mode all analog func-

tional blocks are deact ivated except: preamplifiers

(TX), clock circuits for ou tput clock CLKM. Pdown

will not affect the digital part of the chip. Anyway,

after a Pdow n transit ion, the di gital part status, is

updated after 3 cl ock periods (worst case).

The chip is activated when Pd own = "0".

In power down mode the following conditions

hold:

– Output voltages at TXP/TXN = AGND

– Preamplifier is on with maximum gain setting

(0dB), (d igital gain setting coef ficient s are over-

ruled)

– The XTAL output clock on pin CLKM keeps ru nning.

– All digital setting are retained.

– Digital output on pins RXDx don't care(not floating).

In power-down mode the power consumption is

100mW.

Foll owing external condit ions are added:

– Clock pin CLW is running.

– CTRLIN signals can still be allowed.

– AGND remains at AV DD/2 (circuit is po wered up)

– Input signal at TXDx inputs are not strobed.

The Pdown signal controls asynchronously the

power-down of each analog module:

– A f te r a fe w µs the analog channel is functional

– After about 100ms the analog channel delivers

full performance

Reset Func tion

The reset function is implied when the RESETN

pin is at a l ow voltage input level. In t his condition,

the reset func tion can be easily used for power up

reset condit ions.

Detailed Desc ription

During reset: (reset is asynchronous, tent hs o f ns

are enough to put the IC in reset).

All clock outputs are deactivat ed and put t o l ogical

"1" (except for the XTAL and master clock CLKM).

After reset: (4 clock periods after reset transition,

as worst case).

– OSR = 4

– All analog gains (RX, TX) are set to minim um value

– Nominal filter frequency bands (138kHz,

1.104MHz)

– LNA input = "11" (max. attenuation)

– VCO dac disabled

Digital outputs are placed in don't care condition

(non-floating).

N.B. If a Xtal oscillator is used, the RESET must

be released at last 10µs after power-on, t o ensure

a correct duty cycl e for the clk35 clock signal.

ST70134A

18/22

ELECTRICAL RATINGS AND CHARACTERISTICS

Absol ut e Maximu m Ratings

Ther mal Data

Oper ating Conditions

(Unless specified, the characteristic limits of ’Static Characteristics’ in this document apply over an

Top = -40 to 80°C; VDD wi thin the range 3 to 3.6V ref. to substrate.

STATIC CHARACTERISTICS

Digita l In pu t s

Schm itt-trigger inputs: TXi, CTRLIN, PDOW N, RESETN

Symbol Parameter Minimum Maximum Unit

VDD Any VDD Supply Voltage, related to substrate - 0.5 5 V

Vin Voltage at any input pin -0.5 VDD +0.5 V

Tstg Storage Temperature -40 125 ×C

TLLead Temperature (10 second soldering) 300 ×C

ILU Latch - up current @80°C 100 mA

IAVDD Analog Supply Current @ 3.6V - normal operation 165 mA

IAVDD Analog Supply Current @ 3.6V - power down 30 mA

IDVDD Analog Supply Current @ 3.6V - normal operation 56 mA

IDVDD Analog Supply Current @ 3.6V - power down 50 mA

Symbol Parameter Value Unit

Rth j-amb Thermal and Junction ambient 50 °C/W

Symbol Parameter Minimum Maximum Unit

AVDD AVDD Supply Voltage, related to substrate 3.0 3.6 V

DVDD DVDD Supply Voltage, related to substrate 2.7 3.6 V

Vin /Vout Voltage at any input and output pin 0 VDD V

PdPower Dissip ation 0.4 0.6 W

Tamb Ambient Temperature -40 80 °C

TjJunction Temperature -40 110 °C

Symbol Parameter Test Condition Minimum Typical Maximum Unit

VIL Low Level Input Voltage 0.3 x DVDD V

VIH High Level Input Voltage 0.7 x DVDD V

VHHysteresis 1.0 1.3 V

Cimp Input Capacitance 3 pF

ST70134A

19/22

Digital Ou tputs

Hard Driven Out p uts: RXi

Clock Driver Output: CLKM, CLNIB, CLKWD

Symbol Parameter Test Condition Minimum Typical Maximum Unit

VOL Low Level Output Voltage Iout = -4mA 0.15 x DVDD V

VOH High Level Output Voltage Iout = 4mA 0.85 x DVDD V

Cload Load Capacitance 30 pF

Symbol Parameter Test Condition Minimum Typical Maximum Unit

VOL Low Level Output Voltage Iout = -4mA 0.15 x DVDD V

VOH High Level Output Voltage Iout = 4mA 0.85 x DVDD V

Cload Load Capacitance 30 pF

DC Duty Cycle 45 55 %

ST70134A

20/22

PACKAGE MECHANICAL DATA

Fi gure 10 : P ackage Out line TQFP64

Dimension Millimeter Inch

Minimum Typical Maximum Minimum Typical Maximum

A 1.60 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.18 0.23 0.28 0.007 0.009 0.011

C 0.12 0.16 0.20 0.0047 0.0063 0.0079

D 12.00 0.472

D1 10.00 0.394

D3 7.50 0.295

e 0.50 0.0197

E 12.00 0.472

E1 10.00 0.394

E3 7.50 0.295

L 0.40 0.60 0.75 0.0157 0.0236 0.0295

L1 1.00 0.0393

K0° (minimum), 7° (maximum)

64 49

17 32

A1 A2

0,25 mm

.010 inch

GAGE PLANE

0,10 mm

.004 inch

SEATING PLANE

ST70134A

21/22

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its use. No licens e is granted by i mp lication or otherwise under any pat ent or patent righ ts of S TMic roelec tronic s. S pec ificat ions

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems with out expres s written approval of STMicroelec tronics .

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