25LC080C-H/SN - MICROCHIP TECHNOLOGY

25LC080C 25LC320A

25LC080D 25LC640A

25LC160C 25LC128

25LC160D 25LC256

Features:

• Max. Clock 5 MHz

• Low-power CMOS Technology:

- Max. Write Current: 5 mA at 5.5V, 5 MHz

- Read Current: 5 mA at 5.5V, 5 MHz

- Standby Current: 10 μA at 5.5V

• 1024 x 8 through 32768 x 8-bit Organization

• Byte and Page-level Write Operations

• Self-timed Erase and Write Cycles (6 ms max.)

• Block Write Protection:

- Protect none, 1/4, 1/2 or all of array

• Built-in Write Protection:

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential Read

• High Reliability:

- Endurance: >1M erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• Temperature Range Supported:

• Package is Pb-free and RoHS Compliant

Pin Function Table

Description:

Microchip Technology Inc. 25 LCXXX* devi ces are Mi d-

density 8 through 256 Kbit Serial Electrically Erasable

PROMs (EEPROM). The devices are organized in

blocks of x 8-b it m emory and su pport the Seri al Periph-

eral Interface (SPI) compatible serial bus architecture.

Byte-level and page-level functions are supported.

The bus signals required are a clock input (SCK) plus

separate data in (SI) and data out (SO) lines. Access to

the device is controlled through a Chip Select (CS)

input.

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused, transi-

tions on its inputs will be ignored, with the exception of

Chip Select, allowing the host to service higher priority

interrupts.

The 25LCXXX is available in a standard 8-lead SOIC

package. The package is Pb-free.

Package Types (not to scale)

- Extended (H): -40°C to +150°C

Name Function

CS Chip Select Inpu t

SO Serial Data Outpu t

WP Write-Protect

VSS Ground

SI Serial Data Inp ut

SCK Serial Cloc k Inpu t

HOLD Hold Input

VCC Supply Voltage

HOLD

SCK

SOIC

(SN)

8K-256K SPI Serial EEPROM High Temp Family Data Sheet

*25LCXXX is used in this document as a generic part number for the 25 series devices.

25LCXXX

Device Selection Table

Part Number Density

(bits) Organization VCC Range Max Speed

(MHz) Page Size

(Bytes) Temp.

Range Package

25LC080C 8K 1,024 x 8 2.5V - 5.5V 5 16 H SN

25LC080D 8K 1,024 x 8 2.5V - 5.5V 5 32 H SN

25LC160C 16K 2,048 x 8 2.5V - 5.5V 5 16 H SN

25LC160D 16K 2,048 x 8 2.5V - 5.5V 5 32 H SN

25LC320A 32K 4,096 x 8 2.5V - 5.5V 5 32 H SN

25LC640A 64K 8,192 x 8 2.5V - 5.5V 5 32 H SN

25LC128 128K 16,384 x 8 2.5V - 5.5V 5 64 H SN

25LC256 256K 32,768 x 8 2.5V - 5.5V 5 64 H SN

25LCXXX

1.0 ELECTRICAL CHARAC TERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 155°C

Ambient temperature under bias....................................................................................................... .... -40°C to 150°C(1)

ESD protection on all pins..........................................................................................................................................4 kV

TABLE 1-1: DC CHARACTERISTICS

Note 1: AEC-Q100 re liability testing fo r devices intended to operate at 150°C is 1,0 00 hours. Any design in whic h

the total operating ti me bet ween 125°C and 150°C will be g r eat er th an 1 ,00 0 hours is not warrant ed wi th-

out prior written approval from Micr ochip Technology Inc.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This i s a stres s ratin g only and functio nal operati on of the devic e at thos e or any other co nditio ns abov e thos e

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

DC CHARACTERISTICS Extended (H): TA = -40°C to +150°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

D001 VIH1High-level input

voltage .7 VCC VCC+1 V

D002 VIL1Low-level input

voltage -0.3 0.3VCC VVCC ≥ 2.7V

D003 VIL2-0.3 0.2VCC VVCC < 2.7V

D004 VOL1Low-level output

voltage —0.4VIOL = 2.1 mA

D005 VOL2—0.2VIOL = 1.0 mA

D006 VOH High-level output

voltage VCC -0.5 — V IOH = -400 μA

D007 ILI Input leakage current — ±2 μACS = VCC, VIN = VSS OR VCC

D008 ILO Output lea kage

current —±2μACS = VCC, VOUT = VSS OR VCC

D009 CINT Intern al Cap acitance

(all inputs and

outputs)

—7pFTA = 25°C, CLK = 1.0 MHz,

VCC = 5.0V (Note)

D010 ICC Read

Operating Current

—

—5

2.5

VCC = 5.5V; FCLK = 5.0 MHz;

SO = Open

VCC = 2.5V; FCLK = 3.0 MHz;

SO = Open

D011 ICC Write —

—5

3mA

mA VCC = 5.5V

VCC = 2.5V

D012 ICCS Standby Current — 10 μACS = VCC = 5.5V, Inputs tied to VCC or

VSS, 150°C

Note: This parameter is periodically sampled and not 100% tested.

25LCXXX

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS Extended (H): TA = -40°C to +150°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

1FCLK Clock Frequency —

—5

3MHz

MHz 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

2TCSS CS Setup Time 100

150 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

3TCSH CS Hold Time 200

250 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

4TCSD CS Disable Time 50 — ns —

5 Tsu Data S etup Time 20

30 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

HD Data Hold Time 40

50 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

7TRCLK Rise Time — 2 μs(Note 1)

FCLK Fall Time — 2 μs(Note 1)

HI Clock Hig h Time 100

150 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

10 TLO Clock Low Time 100

150 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

11 TCLD Clock Delay Time 50 — ns —

12 TCLE Clock En able Time 50 — ns —

13 TVOutput Valid from Clock

Low —

—100

160 ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

14 THO Output Hold Time 0 — ns (Note 1)

15 TDIS Output Disable Time —

—80

160 ns

ns 4.5V ≤ Vcc ≤ 5.5V(Note 1)

2.5V ≤ Vcc ≤ 4.5V(Note 1)

16 THS HOLD Setup Time 40

80 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

17 THH HOLD Hold Time 40

80 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

18 THZ HOLD Low to Output

High-Z 60

160 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V(Note 1)

2.5V ≤ Vcc < 4.5V(Note 1)

19 THV HOLD High to Output

Valid 60

160 —

—ns

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

20 TWC In ternal Write C y cle Time — 6 ms (Note 2)

21 — Endurance 1,000,000 — E/W

Cycles Page Mode, 25°C, VCC = 5.5V (Note 3)

Note 1: This parameter is periodically sampled and not 100% tested.

2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete.

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site:

www.microchip.com.

25LCXXX

TABLE 1-3: AC TEST CONDITIONS

AC Wave f orm:

VLO = 0.2V —

VHI = VCC – 0.2V (Note 1)

VHI = 4.0V (Note 2)

CL = 50 pF —

Timing Measurem ent Refere nce Lev el

Input 0.5 VCC

Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For VCC > 4.0V

25LCXXX

FIGURE 1-1: HOLD TIM ING

FIGURE 1-2: SERIAL INPUT TIMING

FIGURE 1-3: SERIAL OUTPUT TIMING

SCK

HOLD

16 16 17

Don’t Care 5

High-Impedance

n + 2 n + 1 n n - 1

n + 2 n + 1 n nn - 1

SCK

711

LSB in

MSB in

High-Impedance

Mode 1,1

Mode 0,0

SCK

MSB out ISB out

Don’t Care

Mode 1,1

Mode 0,0

25LCXXX

2.0 PIN DESCRIPTIONS

The desc riptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in progress w il l be co mpl ete d, re gard le ss of

the CS input signal. If CS is brought high during a

progra m cycle, t he device wil l go into Sta ndby mo de as

soon as the programming cycle is complete. When the

device is deselected, SO goes to the high-im pedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low lev el on CS is required prior to any se quence

being initiated.

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the

25LCXXX. During a read cycle, data is shifted out on

this pin after the falling edge of the serial clock.

2.3 Write-Protect (WP)

This pin is used in conjunction with the WPEN bit in the

STATUS register to prohibit writes to the nonvolatile

bits in the STATUS register. When WP is low and

WPEN is high, wr iting to the nonvolat ile bits in the STA-

TUS register is disabled. All other operations function

normally. When WP is high, all functions, including

writes to the nonvolatile bits in the STATUS register

operate no rmally. If the WPEN bit is set, WP low during

a STATUS register write sequence will disable writing

to the STATUS register. If an internal write cycle has

already begun, WP go ing low w ill h ave no ef fect on the

write.

The WP pin function is blocked when the WPEN bit in

the STATUS register is low. This allows the user to

inst all the 25LCXXX in a system with WP p in grou nded

and still be able to write to the STATUS register. The

WP pin functi ons will be enabl ed when the WPEN bit is

set high.

2.4 Seria l In p u t (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication

between a master and the 25LCXXX. Instructions,

address es or data present on the SI pin are latched on

the risin g edge of the clo ck in put, while data on the SO

pin is updated after the falling edge of the clock input.

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the

25LCXXX while in the middle of a serial sequence

without having to retransmit the entire sequence

again. It must be held high any time this function is not

being used. Once the devic e is selected a nd a serial

sequence is underway, the HOLD pin may be pulled

low to pause further serial communication without

resetting t he se ria l sequ ence. The HOLD pi n must b e

brought low while SCK is low, otherwise the HOLD

function will not be invoked until the next SCK high-to-

low transition. The 25LCXXX must remain selected

during this sequence. The SI, SCK and SO pins are in

a high-impedance state during the time the device is

paused and transi tions on these pins will be ignor ed.

To resume serial communication, HOLD must be

brought high while the SCK pin is low , otherwise serial

communication will not resume. Lowering the HOLD

line at any time will tri-state the SO line.

Name Pin Number Function

CS 1 Chip Select Input

SO 2 Serial Data Output

WP 3 Write-Protect Pin

VSS 4 Ground

SI 5 Serial Data Input

SCK 6 Serial Clock Input

HOLD 7 Hold Input

VCC 8 Supply Voltage

25LCXXX

3.0 FUNCTIONAL DESCRIPTION

3.1 Principles of Operation

The 25LCXXX are Mid-Density Serial EEPROMs

design ed to interface di rec tly with the Seri al Peripheral

Interface (SPI) port of many of today’s popular micro-

controller families, including Microchip’s PIC® micro-

controllers. It may also interface with microcontrollers

that do not have a built-in SPI port by using discrete I/

O lines programmed properly in firmware to match the

SPI protocol.

The 25LCXXX contains an 8-bit instruction register.

The d evic e is acce sse d via the SI pin, w ith data bei ng

clocked in on the rising edge of SC K. Th e CS pin mus t

be low and the HOLD pin must be high for the entire

operation.

Table 3-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses, and data are transferred MSB first, LSB

last.

Data (SI) is sampled on the first rising edge of SCK

after CS goes low. If th e c loc k li ne is s hare d wi th other

peripher al d evices on t he SPI bus , the u ser ca n asse rt

the HOLD input and place the 25LCXXX in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.

Block Diagram

SCK

HOLD

STATUS

I/O Contr ol Memory

Control

Logic

Dec

HV Genera to r

EEPROM

Array

Page Latches

Y Decoder

Sense Amp.

R/W Control

Logic

VCC

VSS

TABLE 3-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ 0000 0011 Read data from memory array beginning at selected address

WRITE 0000 0010 Write data to memory array beginning at selected address

WRDI 0000 0100 Reset the write enable latch (disable write operations)

WREN 0000 0110 Set the write enable latch (enable write operations)

RDSR 0000 0101 Read STATUS register

WRSR 0000 0001 Write STATUS re gister

25LCXXX

3.2 Read Sequence

The device is selected by pulling CS low. The 8-bit

READ instruction is transmitted to the 25LCXXX fol-

lowed by the 16-bit address. After the correct READ

instruc tio n a nd address are sent, the data s tore d i n th e

memory at the selected address is shifted out on the

SO pin. The data stored in the memory at the next

address can be read sequentially by continuing to pro-

vide cl ock puls es. The inter nal Addr ess Pointe r is auto-

matically incremented to the next higher address after

each byte of data is shifted out. When the highest

address is reached, the address counter rolls over to

address 00 00h all ow in g th e rea d c yc le to b e co nti nue d

indefin itely. The read operati on is term inated by rai sing

the CS pin (Figure 3-1 ).

3.3 Write Sequence

Prior to any attempt to write data to the 25LCXXX, the

write enable latch must be set by issuing the WREN

instruction (Figure 3-4). This is done by setting CS low

and then clocking out the proper instruction into the

25LCXXX. After all eight bits of the instruction are

transmitted, the CS must be brought high to set the

write enable latch. If the write operation is initiated

immediately after the WREN instruction without CS

being brought high, the data will not be written to the

array bec ause the write enable latc h will not hav e been

properly set.

Once the write enable latch is set, the user may

proceed by settin g the CS low , issuing a WRITE instruc-

tion, followed by the 16-bit address, and then the data

to be written. Depending upon the density, a page of

dat a that rang es from 16 by tes to 64 b yte s c an be sent

to the de vice before a write cycle is necessary. The only

restriction is that all of the bytes must reside in the

same page.

For the data to be actually written to the array, the CS

must be brought high a fter the Leas t Significant bit (D0)

of the nth data byte has been clocked in. If CS is

brought high at any other time, the write operation will

not be completed. Refer to Figure 3-2 and Figure 3-3

for more detailed illustrations on the byte write

sequence and the page write sequence, respectively.

While the write is in progress, the ST A TUS register may

be read to check the status of the WPEN, WIP, WEL,

BP1 and BP0 bits (Figure 3-6). A read attempt of a

memory array location will not be possible during a

write cycle. When the write cycle is completed, the

write enab le latc h is res et.

FIGURE 3-1: READ SEQUENCE

Note: Page write opera tions are l imited to wri ting

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘pag e size’) an d, end at addresses tha t are

integer multiples of page size – 1. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being w ritte n to the next page as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

SCK

0 234567891011 21222324252627282930311

0100000115 14 13 12 210

76543210

Instruction 16-bit Address

Data Out

High-Impedance

25LCXXX

FIGURE 3-2: BYTE WRITE SEQUENCE

FIGURE 3-3: PAGE WRITE SEQUENCE

91011 2122232425262728293031

0000000115 14 13 12 21076543210

Instructio n 16-bit Address Data Byte

High-Impedance

SCK 0 23456718 Twc

9 1011 2122232425262728293031

0000000115 14 13 12 21076543210

Instructi on 16-bit Addre ss Data Byte 1

SCK 0 23456718

41 42 43 46 47

76543210

Data Byte n (16/32/64 max)

SCK 32 34 35 36 37 38 3933 40

76543210

Data Byte 3

76543210

Data Byte 2

44 45

25LCXXX

3.4 Wr ite Enable (WREN) and Write

Disable (WRDI)

The 25LCXXX contains a write enable latch. See

Table 5-1 for the write-protect functionality matrix. This

latch must be set before any write operation will be com-

pleted internally. The WREN instruction will set the latch,

and the WRDI will reset the latch.

The following is a list of conditions under which the

write enab le latc h wi ll be reset:

• Power-up

•WRDI instruction successfully executed

•WRSR instruction successfully executed

•WRITE instruction successfully executed

FIGURE 3-4: WRITE ENABLE SEQUENCE (WREN)

FIGURE 3-5: WRITE DISABLE SEQUENCE (WRDI)

SCK

0 2345671

High-Impedance

010000 01

SCK

0 2345671

High-Impedance

010000 01

25LCXXX

3.5 Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provid es

access to the STATUS register. The STATUS register

may be rea d at any time, ev en during a write cy cle. The

STATUS register is formatted as follows:

TABLE 3-2: STATUS REGISTER

The Write-In-Process (WIP) bit indicates whether the

25LCXXX is bus y with a write opera tion. Whe n set to a

‘1’, a write is in progress, when set to a ‘0’, no write is

in progress. This bit is read-only.

The Writ e Enable Latch (WEL ) bit in dicates th e statu s

of th e wri te e nabl e lat ch an d is r ead -onl y. When set to

a ‘1’, the latch allows writes to the array, when set to a

‘0’, the latch prohibits writes to the array. The state of

this bit can always be updated via the WREN or WRDI

commands regardless of the state of write protection

on the STATUS register. These commands are shown

in Figure 3-4 and Figure 3-5.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user i ss ui ng the WRSR in stru ction . These

bits are nonvolatile, and are shown in Table 3-3.

See Figure 3-6 for the RDSR timing sequence.

FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)

7 654 3 2 1 0

W/R –––W/RW/R R R

WPEN X X X BP1 BP0 WEL WIP

W/R = writable/readable. R = read-only.

9101112131415

11000000

7654 210

Instruction

Data from STATUS Register

High-Impedance

SCK

0 23456718

25LCXXX

3.6 Wr ite Status Register Inst ruction

(WRSR)

The W rite S t atus Regis ter instruc tion (WRSR) allows the

user to write to the nonvolatile bits in the STATUS

select one of four levels of protection for the array by

writing to the appropriate bits in the STATUS register.

The array is divided up into four segments. The user

has the abilit y to write -protec t none, one, tw o or all fo ur

of the segments of the array. The partitioning is

controlled as shown in Table 3-3.

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is availabl e as an enabl e bit for the WP pi n. The

Write-Protect (WP) pin and the Write-Protect Enable

(WPEN) bit in the STATUS register control the

programmable hardware write-protect feature. Hard-

ware write protection is enabled when WP pin is low

and the WPEN bit is high. Hardware write protection is

disabled when either the WP pi n is hi gh or t he WPE N

bit is low. When the chip is hardware write-protected,

only writes to nonvolatile bits in the STATUS register

are di sa ble d. Se e Table 5-1 for a matrix of func ti onality

on the WPEN bit.

See Figure 3-7 for the WRSR timing sequence.

TABLE 3-3: ARRAY PROTECTION

TABLE 3-4: ARRAY PROTECTED ADDRESS LOCATIONS

FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

BP1 BP0 Array Addresses

Write-Protected Array Addresses

Unprotected

None All

Upper 1/4 Lower 3/4

Upper 1/2 Lower 1/2

All None

Density Upper 1/4 Uppe r 1/2 All

8K 300h - 3FFh 200h - 3FFh 000h - 3FFh

16K 600h - 7FFh 400h - 7FFh 000h - 7FFh

32K C00h - FFFh 800h - FFFh 000h - FFFh

64K 1800h - 1FFFh 1000h - 1FFFh 0000h - 1FFFh

128K 3000h - 3FFFh 2000h - 3FFFh 0000h - 3FFFh

256K 6000h - 7FFFh 4000h - 7FFFh 0000h - 7FFFh

9101112131415

01000000

7654 210

Instruction Data to STATUS Register

High-Impedance

SCK

0 23456718

Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register

sequence.

25LCXXX

4.0 DA TA PROTECTIO N

The following protection has been implemented to

prevent inadve rtent writes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

•CS

must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal w rite cycle

is ignored and programming is continued

5.0 POWER-ON STATE

The 25LCXXX powers on in the following state:

• The device is in low-power Standby mode

(CS=1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter activ e st ate

TABLE 5-1: WRITE-PROTECT FUNCTIONALITY MATRIX

WEL

(SR bit 1) WPEN

(SR bit 7) WP

(pin 3) Protected Blocks Unprotected Blocks STATUS Register

0xxProtected Protected Protected

10xProtected Writable Writable

110 (low) Protected Writable Protected

111 (high) Protected Writable Writable

x = don’t care

25LCXXX

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Note: Custom marking available.

8-Lead SOIC

XXXXYYWW

XXXXXXXT

NNN

Example:

SN 0728

25LC32AH

1L7

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In th e event the ful l Micro chip p ar t numbe r canno t be marke d on one li ne, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

8-Lead SOIC Package Marking (Pb-Free)

Device Line 1 Marking

25LC080C 25LC80CT

25LC080D 25LC80DT

25LC160C 25LC16CT

25LC160D 25LC16DT

25LC320A 25LC32AT

25LC640A 25L640AT

25LC128 25LC128T

25LC256 25LC256T

Note 1: T = Temperature Grade (H).

25LCXXX

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 *$%+% %

, &  "-"%!"&"$ %!  "$ %!   %#".&& "

 & "%-/.

0+1 0 & %#%! ))%!%% 

-21 $& '! !)%!%%'$$&%!  

& 2%& %!%3") '  %3$%%"%

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5% 66--

& 6&% 7 78 9

7!&($ 7 :

%  0+

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""33  . < <

%"$$*  < .

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""3="% - ,0+

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2%6% 6  < 

2%% 6 -2

2% A < :A

6"3   < .

6"="% ( , < .

"$% .A < .A

"$%0%%& .A < .A

NOTE 1

12 3

  ) +.0

25LCXXX

 !"#$%

%%144)))&&43

25LCXXX

REVISION HISTORY

Revision A (01/2009)

Original Release.

Revision B (04/2009)

Revised part number from 25XX to 25LCXXX; Added

Note 1 to Electrical Characteristics.

Revision C (06/2009)

Revised Features: Endurance and Package; Revised

Table 1-2, Para. 21.

25LCXXX

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.mic roc hi p.c om . Thi s web si te i s us ed as a m ean s

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Local sales offices are also available to help custom-

ers. A l isting of sal es offic es and locat ions is inc luded in

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Technic al suppo rt is avail able throug h the web si te

at: http://support.microchip.com

25LCXXX

READER RESP ONSE

It is ou r intention to pro vi de you with the bes t do cu me nt ation possib le to e ns ure suc c es sfu l u se of y ou r M ic roc hip pro d-

uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, su bject matter, and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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Device: Literature Number:

Questions:

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DS22131C25LCXXX

1. What are the best features of this docu ment?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

25LCXXX

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTape & Reel

Device

Device: 25LC080C =

25LC080D =

25LC160C =

25LC160D =

25LC320A =

25LC640A =

25LC128 =

25LC256 =

8k-bit, 2.5V, 16 Byte Page, SPI Serial EEPROM

8k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM

16k-bit, 2.5V, 16 Byte Page, SPI Serial EEPROM

16k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM

32k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM

64k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM

128k-bit, 2.5V, 64 Byte Page, SPI Serial EEPROM

256k-bit, 2.5V, 64 Byte Page, SPI Serial EEPROM

Tape & Reel: Blank =

T= Standa rd packag i ng

Tape & Reel

Temperature

Range: H= -40°C to+150°C

Package: SN = Plastic SOIC (3.90 mm body), 8-lead

Examples:

a) 25LC080CT-H/SN = 8k-bit, 16-byte page, 2.5V

Serial EEPROM, Extended temp., Tape &

Reel, SOIC package

b) 25LC080D-H/SN = 8k-bit, 32-byte page, 2.5V

Serial EEPRO M, Extended temp., SOIC pack-

age

c) 25LC160CT-H/SN = 16k-bit, 16-byte page,

2.5V Seria l EEPROM, Ex tende d temp ., Tape &

Reel, SOIC package

d) 25LC160D-H/SN = 16k-bit, 32-byte page, 2.5V

Serial EEPRO M, Extended temp., SOIC pack-

age

e) 25LC320AT-H/SN = 32k-bit, 32-byte page,

2.5V Seria l EEPROM, Ex tende d temp ., Tape &

Reel, SOIC package

f) 25LC64 0A -H/SN = 64k- bit, 32 -byte page, 2.5V

Serial EEPRO M, Extended temp., SOIC pack-

age

g) 25LC128T-H/SN = 128k-bit, 64-byte page,

2.5V Seria l EEPROM, Ex tende d temp ., Tape &

Reel, SOIC package

h) 25LC256-H/ SN = 256k- bit, 64-b yte page, 2.5 V

Serial EEPRO M, Extended temp., SOIC pack-

age

–

Temp Range

25LCXXX

NOTES:

Information contained in this publication regarding device

applications a nd t he lik e is provid ed only for your convenience

and may be su perseded by updates. I t is y our respo ns i bil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC , PIC mi cro, PI C START,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSens e, HI-TIDE, In-Circuit Serial

Prog ra m ming, IC SP, ICE PIC, Min d i , MiW i , MPASM, MPL AB

Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,

Omniscient Code Generation, PICC, PICC-18, PICkit,

PICDEM, PICDEM.net, PICtail, PIC32 log o, REAL ICE, r fLAB,

Select Mode, Total Endurance, TSHARC, WiperLock and

ZENA are trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellec tual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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