Low Noise, 2:8 Differential
Fanout Buffer
Data Sheet HMC6832
Rev. C Document Feedback
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FEATURES
Ultralow noise floor: −165.9 dBc/Hz or −165.2 dBc/Hz
(LVPECL or LVDS) at 2000 MHz
Configurable to LVPECL or pseudo LVDS outputs
2.5 V or 3.3 V LVPECL operation (LVDS 2.5 V only)
Wideband: 10 MHz to 3500 MHz operating frequency range
Flexible input interface
LVPECL, LVDS, CML, and CMOS compatible
AC or dc coupling
On-chip 50 kΩ pull-up/pull-down resistors to VDD and
GND
Multiple output drivers
Up to 8 differential or 16 single-ended LVPECL or LVDS
outputs
Low speed digital control via the IN_SEL and CONFIG pins
28-lead, 5 mm × 5 mm, LFCSP package, 25 mm2
APPLICATIONS
SONET, Fibre Channel, GigE clock distribution
ADC/DAC clock distribution
Low skew and jitter clocks
Wireless/wired communications
Level translation
High performance instrumentation
Medical imaging
Single-ended to differential conversions
GENERAL DESCRIPTION
The HMC6832 is an input selectable, 2:8 differential fanout
buffer designed for low noise clock distribution. The IN_SEL
control pin selects one of the two differential inputs. This input
is then buffered to all eight differential outputs. The low jitter
outputs of the HMC6832 lead to synchronized low noise
switching of downstream circuits, such as mixers, analog-to-
digital converters (ADCs)/digital-to-analog converters (DACs),
or serializer/deserializer (SERDES) devices. The device is capable
of low voltage, positive emitter-coupled logic (LVPECL) or low
voltage differential signaling (LVDS) configurations by pulling
the CONFIG pin low for LVPECL or high or open (internally
pulled high) for pseudo LVDS.
PRODUCT HIGHLIGHTS
1. Multiple Output Configurations.
The CONFIG pin allows the user to select LVPECL or
LVDS output termination.
2. Multiple Supply Voltage Operation.
The HMC6832 operates at 2.5 V or 3.3 V for LVPECL
terminations (2.5 V only for LVDS).
3. Low Noise.
The HMC6832 noise is low, typically from −168 dBc/Hz to
−162 dBc/Hz up to 3000 MHz.
4. Low Propagation Delay.
The HMC6832 displays a low delay, less than 207 ps,
typical. Channel skew is also low, ±5 ps, typical.
5. Low Core Current.
The HMC6832 has a low core current of 56 mA, typical.
HMC6832 Data Sheet
Rev. C | Page 2 of 23
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
AC Output Characteristics .......................................................... 4
Output Gain and Power Characteristics ................................... 5
Timing Characteristics ................................................................ 8
Timing Specifications .................................................................. 8
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 12
Test Circuits ..................................................................................... 18
Theory of Operation ...................................................................... 19
Input Stage ................................................................................... 19
LVPECL Output Stage ............................................................... 19
Applications Information .............................................................. 21
Recommended Solder Reflow Profile ...................................... 21
Evaluation Printed Circuit Board (PCB) ................................ 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
1/2018—Rev. B to Rev. C
Added Figure 24; Renumbered Sequentially .............................. 15
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
9/2016—Rev. A to Rev. B
Changes to Features Section and General Description Section . 1
Changes to Figure 1 .......................................................................... 3
Changes to Tabl e 1 and Table 2 ....................................................... 4
Changes Table 3 ................................................................................ 5
Changes to Floor Density Jitter Parameter, Test Conditions/
Comments Column Only, Tabl e 4 and Integrated RMS Jitter,
Test Conditions/Comments Column Only, Table 4..................... 6
Changes to Single-Sideband (SSB Phase Noise Floor) Parameter,
Test Conditions/Comments Column Only, Tabl e 5..................... 8
Changes to Figure 11 Caption and Figure 15 Caption .............. 13
Changes to Figure 16 Caption to Figure 18 Caption and
Figure 20 Caption ........................................................................... 14
Changes to Figure 19 and Figure 21............................................. 14
Added Figure 23; Renumbered Sequentially ...................................... 15
Changes to Figure 22 Caption and Figure 24 Caption to
Figure 27 Caption ........................................................................... 15
Changes to Figure 28 Caption ...................................................... 16
Changes to Figure 38 Caption, Figure 40 Caption, and Figure 42 . 18
Changes to Input Stage Section and Figure 44 ........................... 19
Changes to Figure 45 ...................................................................... 20
Changes to Figure 50 Caption and Figure 51 Caption .............. 21
3/2016—Revision A: Initial Version
Data Sheet HMC6832
Rev. C | Page 3 of 23
FUNCTIONAL BLOCK DIAGRAM
IN_SEL
HIG H: IN1
LOW: IN0
VDD
VDD
VDD
VDD
50kΩ
VDD
LVDS
100kΩ
CONFIGURATION
CONTROL
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
OUTP7
INP1
INN1
100pF
100pF
100pF
100pF
INP0
INN0
VAC_REF
CONFIG
HIGH: LVDS
LOW: LVPECL
4mA4mA
OUTN7
LVDS
OUTP6
4mA4mA
OUTN6
LVDS
OUTP5
4mA4mA
OUTN5
LVDS
OUTP4
4mA4mA
OUTN4
LVDS
OUTP3
4mA4mA
OUTN3
LVDS
OUTP2
4mA4mA
OUTN2
LVDS
OUTP1
4mA4mA
2mA
OUTN1
LVDS
OUTP0
4mA4mA
OUTN0
LVDS
LVPECL
13201-001
Figure 1.
HMC6832 Data Sheet
Rev. C | Page 4 of 23
SPECIFICATIONS
Typical is given as fINPUT = 1.25 GHz (ac-coupled), differential input power = 7.5 dBm, TNOMINAL = 25°C, unless otherwise noted. All outputs
captured using 50 Ω scope termination. 50 Ω board termination on inputs used to minimize reflections.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
VDD
LVPECL 2.375 2.5 2.625 V 2.5 V operation
3.0 3.3 3.6 V 3.3 V operation
LVDS 2.375 2.5 2.625 V
Input Common-Mode Voltage GND + 0.2 VDD/2 VDD − 0.2 V Guaranteed by design
SELECTION PINS
IN_SEL Pin GND = IN0, VDD = IN1
Input Voltage Low (V
IL
)
VDD/2 − 0.4
V
Input Voltage High (VIH) VDD/2 + 0.4 V
CONFIG Pin GND = LVPECL, VDD = LVDS
Input Voltage Low (VIL) 2VDD/3 − 0.3 V
Input Voltage High (VIH) 2VDD/3 + 0.3 V
TEMPERATURE RANGE, TA −40 +25 +85 °C
SUPPLY CURRENT
Outputs unterminated
Core Current 56 mA VDD = 2.5 V
56 mA VDD = 3.3 V
Full Load Current
LVPECL Termination 301 mA RTERM1 = 86 Ω, VDD = 2.5 V
283 mA RTERM = 150 Ω, VDD = 3.3 V
LVDS Termination 125 mA RTERM = 100 Ω
RF INPUT CHARACTERISTICS
Operating Frequency Range 10 3500 MHz
Input Swing (Single-Ended) 0.1 2 V
Input Capacitance 3.6 pF
Pull-Up/Pull-Down Resistance 50 kΩ See Figure 1
1 For LVPECL termination, RTERM is the single-ended termination resistance to GND. For LVDS termination, RTERM is the differential termination resistance.
AC OUTPUT CHARACTERISTICS
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DIFFERENTIAL OUTPUT VOLTAGE SWING Differential inputs and outputs; adjusted for impedance
mismatch and printed circuit board (PCB) losses; see Figure 41
and Figure 42 for ac measurement test circuits
LVPECL Termination 652 mV p-p RTERM = 86 Ω, VDD = 2.5 V
721
mV p-p
R
TERM
= 150 Ω, VDD = 3.3 V
LVDS Termination 462 mV p-p RTERM = 100 Ω, VDD = 2.5 V
OUTPUT VOLTAGE, HIGH LEVEL Differential inputs and outputs
LVPECL Termination 1.63 V RTERM = 86 Ω, VDD = 2.5 V
2.51 V RTERM = 150 Ω, VDD = 3.3 V
LVDS Termination 1.65 V RTERM = 100 Ω, VDD = 2.5 V
OUTPUT VOLTAGE, COMMON LEVEL Differential inputs and outputs; see Figure 39 and Figure 40
for dc measurement test circuits
LVPECL Termination 1.30 V RTERM = 86 Ω, VDD = 2.5 V
2.15 V RTERM = 150 Ω, VDD = 3.3 V
LVDS Termination 1.42 V RTERM = 100 Ω, VDD = 2.5 V
Data Sheet HMC6832
Rev. C | Page 5 of 23
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT VOLTAGE, LOW LEVEL Differential inputs and outputs
LVPECL Termination 0.97 V RTERM = 86 Ω, VDD = 2.5 V
1.79 V RTERM = 150 Ω, VDD = 3.3 V
LVDS Termination 1.19 V RTERM = 100 Ω, VDD = 2.5 V
AC PERFORMANCE See Figure 41 and Figure 42 for ac measurement test
circuits
3 dB Bandwidth Adjusted for impedance mismatch and PCB losses; refer to
Figure 19 and Figure 21
LVPECL Differential Input 1600 MHz Differential input = 100 mV p-p; VDD = 2.5 V
2500 MHz Differential input = 200 mV p-p; VDD = 2.5 V
3200 MHz Differential input = 400 mV p-p; VDD = 2.5 V
LVDS Differential Input 1750 MHz Differential input = 100 mV p-p; VDD = 2.5 V
2550 MHz Differential input = 200 mV p-p; VDD = 2.5 V
4100
MHz
Differential input = 400 mV p-p; VDD = 2.5 V
Output Rise Time (20% to 80%) Differential inputs and outputs
LVPECL Termination 56 ps RTERM = 86 Ω, VDD = 2.5 V
57 ps RTERM = 150 Ω, VDD = 3.3 V
LVDS Termination 45 ps RTERM = 100 Ω, VDD = 2.5 V
Output Fall Time (20% to 80%) Differential inputs and outputs
LVPECL Termination 59 ps RTERM = 86 Ω, VDD = 2.5 V
59 ps RTERM = 150 Ω, VDD = 3.3 V
LVDS Termination 46 ps RTERM = 100 Ω, VDD = 2.5 V
Duty Cycle Variation Differential inputs and outputs
LVPECL Termination 50 % RTERM = 86 Ω, VDD = 2.5 V
50
%
R
TERM
= 150 Ω, VDD = 3.3 V
LVDS Termination 50 % RTERM = 100 Ω, VDD = 2.5 V
Power Supply Rejection Ratio 50 kHz, 100 mV p-p sinusoidal signal modulated onto VDD;
single-ended 1 GHz, 0 dBm input; outputs measured
differentially
LVPECL Termination −55 dBc RTERM = 86 Ω, VDD = 2.5 V
−59 dBc RTERM = 150 Ω, VDD = 3.3 V
LVDS Termination −52 dBc RTERM = 100 Ω, VDD = 2.5 V
OUTPUT GAIN AND POWER CHARACTERISTICS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DIFFERENTIAL SMALL SIGNAL GAIN (S21) Adjusted for impedance mismatch and
printed circuit board (PCB) losses
LVPECL Termination
25 dB RTERM = 86 Ω, VDD = 2.5 V
26 dB RTERM = 150 Ω, VDD = 3.3 V
LVDS Termination 22 dB RTERM = 100 Ω, VDD = 2.5 V
INPUT 1 dB COMPRESSION POINT (P1dB) 1250 MHz, adjusted for impedance
mismatch and PCB losses
LVPECL Termination −25 dBm RTERM = 86 Ω, VDD = 2.5 V
−25 dBm RTERM = 150 Ω, VDD = 3.3 V
LVDS Termination −26 dBm RTERM = 100 Ω, VDD = 2.5 V
SATURATED POWER IN FUNDAMENTAL
TONE (SINGLE-ENDED)
VDD = 2.5 V, adjusted for impedance
mismatch and PCB losses
LVPECL Termination
1000 MHz −4 dBm −4 dBm = 399 mV p-p
2000 MHz −2 dBm −2 dBm = 502 mV p-p
3000 MHz
−5
dBm
−5 dBm = 356 mV p-p
HMC6832 Data Sheet
Rev. C | Page 6 of 23
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS Termination
1000 MHz −7 dBm −7 dBm = 283 mV p-p
2000 MHz −7 dBm −7 dBm = 283 mV p-p
3000 MHz −7 dBm −7 dBm = 283 mV p-p
HARMONICS VDD = 2.5 V, adjusted for impedance
mismatch and PCB losses, fINPUT = 2 GHz
LVPECL Termination
f
OUT
−2
dBm
−2 dBm = 502 mV p-p
2 × fOUT −28 dBc
3 × fOUT −17 dBc
4 × fOUT −38 dBc
5 × fOUT −24 dBc
LVDS Termination
fOUT −7 dBm −7 dBm = 283 mV p-p
2 × fOUT −22 dBc
3 × fOUT −16 dBc
4 × fOUT −38 dBc
5 × fOUT −29 dBc
OUTPUT RETURN LOSS < 10 dB <6 GHz LVDS termination
Table 4. Jitter
Parameter Min Typ Max Unit Test Conditions/Comments
FLOOR DENSITY JITTER Single-ended input; differential output; measured with
saturated amplifier to remove amplitude modulation (AM)
noise (only affects 100 MHz data); LVPECL RTERM = 150 Ω;
LVDS RTERM = 100 Ω; VDD = 2.5 V; see Figure 43 and Figure 44
for phase noise measurement test circuits
Input Carrier Frequency
LVPECL Termination
100 MHz 13.09 as/√Hz
622 MHz
1.61
as/√Hz
1000 MHz 1.26 as/√Hz
1600 MHz 0.91 as/√Hz
1750 MHz 0.81 as/√Hz
2000 MHz 0.64 as/√Hz
3000 MHz 0.51 as/√Hz
LVDS Termination
100 MHz 15.55 as/√Hz
622 MHz 1.63 as/√Hz
1000 MHz 1.21 as/√Hz
1600 MHz 0.80 as/√Hz
1750 MHz
0.72
as/√Hz
2000 MHz 0.69 as/√Hz
3000 MHz 0.64 as/√Hz
INTEGRATED RMS JITTER
Single-ended input; differential output; measured with
saturated amplifier to remove AM noise (only affects
100 MHz data); LVPECL RTERM = 150 Ω; LVDS RTERM = 100 Ω;
VDD = 2.5 V; see Figure 43 and Figure 44 for phase noise
measurement test circuits
100 MHz Carrier Frequency
LVPECL Termination
60 kHz to 10 MHz 37 fs rms
60 kHz to 20 MHz 52 fs rms
60 kHz to 40 MHz 74 fs rms
Data Sheet HMC6832
Rev. C | Page 7 of 23
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS Termination
60 kHz to 10 MHz 44 fs rms
60 kHz to 20 MHz 62 fs rms
60 kHz to 40 MHz 88 fs rms
622.06 MHz Carrier Frequency
LVPECL Termination
10 MHz to 80 MHz 12 fs rms
10 MHz to 100 MHz 14 fs rms
LVDS Termination
10 MHz to 80 MHz 12 fs rms
10 MHz to 100 MHz
14
fs rms
1000 MHz Carrier Frequency
LVPECL Termination
10 MHz to 80 MHz 9 fs rms
10 MHz to 100 MHz 11 fs rms
LVDS Termination
10 MHz to 80 MHz 10 fs rms
10 MHz to 100 MHz 10 fs rms
1600 MHz Carrier Frequency
LVPECL Termination
10 MHz to 80 MHz 7 fs rms
10 MHz to 100 MHz
8
fs rms
LVDS Termination
10 MHz to 80 MHz 6 fs rms
10 MHz to 100 MHz 7 fs rms
2000 MHz Carrier Frequency
LVPECL Termination
10 MHz to 80 MHz
5
fs rms
10 MHz to 100 MHz 6 fs rms
LVDS Termination
10 MHz to 80 MHz 5 fs rms
10 MHz to 100 MHz 6 fs rms
3000 MHz Carrier Frequency
LVPECL Termination
10 MHz to 80 MHz 3 fs rms
10 MHz to 100 MHz 4 fs rms
LVDS Termination
10 MHz to 80 MHz 4 fs rms
10 MHz to 100 MHz
5
fs rms
HMC6832 Data Sheet
Rev. C | Page 8 of 23
Table 5. Phase Noise Floor
Parameter Min Typ Max Unit Test Conditions/Comments
SINGLE-SIDEBAND (SSB PHASE NOISE
FLOOR)
Single-ended input; differential output;
measured with saturated amplifier to remove
AM noise (only affects 100 MHz data); LVPECL
RTERM = 150 Ω; LVDS RTERM = 100 Ω; VDD = 2.5 V;
see Figure 43 and Figure 44 for phase noise
measurement test circuits
Input Carrier Frequency
LVPECL Termination
100 MHz −165.7 dBc/Hz
622 MHz
−168.0
dBc/Hz
1000 MHz −166.0 dBc/Hz
1600 MHz −164.8 dBc/Hz
1750 MHz −165.0 dBc/Hz
2000 MHz −165.9 dBc/Hz
3000 MHz −164.4 dBc/Hz
LVDS Termination
100 MHz −164.2 dBc/Hz
622 MHz −167.9 dBc/Hz
1000 MHz −166.4 dBc/Hz
1600 MHz −165.9 dBc/Hz
1750 MHz −166.0 dBc/Hz
2000 MHz −165.2 dBc/Hz
3000 MHz −162.4 dBc/Hz
TIMING CHARACTERISTICS
TA = 25°C, unless otherwise noted. Minimum/maximum values are guaranteed by design and characterization.
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
TYPICAL CHANNEL SKEW ±5 ps Relative to OUTP5, VDD = 2.5 V or 3.3 V
TYPICAL PROPAGATION DELAY
LVPECL Termination 201 ps VDD = 2.375 V to 3.6 V
LVDS Termination 207 ps VDD = 2.375 V to 2.625 V
TYPICAL DELAY VARIATION
At TA = 25°C
LVPECL Termination ±5 ps VDD = 2.375 V to 3.6 V, measurement uncertainty = ±2 ps
LVDS Termination ±5 ps VDD = 2.375 V to 2.625 V, measurement uncertainty = ±2 ps
At TA = −40°C to +85°C
LVPECL Termination ±13 ps VDD = 2.375 V to 3.6 V, measurement uncertainty = ±4 ps
LVDS Termination ±13 ps VDD = 2.375 V to 2.625 V, measurement uncertainty = ±4 ps
PROCESS PROPAGATION DELAY VARIATION −18 +18 ps Process simulation, VDD = 2.5 V
TIMING SPECIFICATIONS
VDD = 2.5 V or 3.3 V, TA = 25°C, unless otherwise noted.
Table 7.
Parameter
Typical
Unit
Description
tSKEW ±5 ps Output skew
t
R
57/45
ps
Output rise/fall time (LVPECL/LVDS)
tF 59/46 ps Output rise/fall time (LVPECL/LVDS)
tD 201/207 ps Propagation delay (LVPECL/LVDS)
HMC6832 Data Sheet
Rev. C | Page 10 of 23
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Rating
Maximum Voltage Between VDD Pins
and EPAD
−0.3 V to +4 V
Maximum RF Power to INPx and INNx 15 dBm, single-ended
INPx and INNx −0.3 V to +3.6 V
Minimum Output Load Resistor
LVPECL (VDD = 2.5 V) 75 Ω to GND
LVPECL (VDD = 3.3 V) 100 Ω to GND
LVPECL Output Load Current
40 mA/single-ended
output channel
Input Select Voltage Range −0.3 V to +3.6 V
Maximum VAC_REF Load Current 2 mA
Maximum Reflow Temperature
(MSL3 Rating)
260°C
ESD Sensitivity
Human Body Model (HBM) Class 1C
Field Induced Charged Device Model
(FICDM)
Class C4
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 9. Thermal Resistance
Package Type θJC Unit
28-Lead LFCSP 10.6 °C/W
ESD CAUTION
Data Sheet HMC6832
Rev. C | Page 11 of 23
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13201-003
15
1
3
2
8
GND
OUTP7
OUTN7 4
5
IN_SEL
INP1 6
INN1 7
VAC_REF
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE CO NNE CTED TO GND.
VDD
16 OUTP1
17 OUTN1
18 OUTP2
19 OUTN2
20 OUTP3
21 OUTN3
VDD
11
CONFIG
10
INN0
9
INP0
12
OUTP0
13
OUTN0
14
GND
22
OUTP4
23
OUTN4
24
OUTP5
25
OUTN5
26
OUTP6
27
OUTN6
28
VDD
HMC6832
TOP VIEW
(No t t o Scal e)
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Description
1
GND
Ground.
2 OUTP7 Differential Signal Output 7, Positive.
3 OUTN7 Differential Signal Output 7, Negative.
4 IN_SEL Input Select. Logic 0 = INP0/INN0 and Logic 1 = INP1/INN1.
5 INP1 Differential Signal Input 1, Positive.
6 INN1 Differential Signal Input 1, Negative.
7 VAC_REF Output Reference Voltage.
8 VDD Power Supply.
9 INP0 Differential Signal Input 0, Positive.
10 INN0 Differential Signal Input 0, Negative.
11 CONFIG Output Termination Configuration Input. Logic 0 = LVPECL and Logic 1 = LVDS.
12
OUTP0
Differential Signal Output 0, Positive.
13 OUTN0 Differential Signal Output 0, Negative.
14 GND Ground.
15 VDD Power Supply.
16 OUTP1 Differential Signal Output 1, Positive.
17 OUTN1 Differential Signal Output 1, Negative.
18 OUTP2 Differential Signal Output 2, Positive.
19 OUTN2 Differential Signal Output 2, Negative.
20 OUTP3 Differential Signal Output 3, Positive.
21 OUTN3 Differential Signal Output 3, Negative.
22 OUTP4 Differential Signal Output 4, Positive.
23
OUTN4
Differential Signal Output 4, Negative.
24 OUTP5 Differential Signal Output 5, Positive.
25 OUTN5 Differential Signal Output 5, Negative.
26 OUTP6 Differential Signal Output 6, Positive.
27 OUTN6 Differential Signal Output 6, Negative.
28 VDD Power Supply.
EPAD Exposed Pad. The exposed pad must be connected to GND.
HMC6832 Data Sheet
Rev. C | Page 12 of 23
TYPICAL PERFORMANCE CHARACTERISTICS
Typical is given as fINPUT = 1.25 GHz (ac-coupled), differential input power = 7.5 dBm, TNOMINAL = 25°C, unless otherwise noted. All outputs
captured using 50 Ω scope termination. Used 50 Ω board termination on inputs to minimize reflections.
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–800 –600 –400 –200 0200 400 600 800
OUTPUT VOLTAGE (V)
TIME (ps)
1GHz
2GHz
3GHz
13201-004
Figure 4. LVPECL Differential Output Voltage, 86 Ω, 2.5 V vs. Carrier
Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and
Measurement Band Limited by the Trace Bandwidth
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–800 –600 –400 –200 0200 400 600 800
OUTPUT VOLTAGE (V)
TIME (ps)
1GHz
2GHz
3GHz
13201-005
Figure 5. LVPECL Differential Output Voltage, 150 Ω, 3.3 V vs. Carrier
Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and
Measurement Band Limited by the Trace Bandwidth
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–800 –600 –400 –200 0200 400 600 800
OUTPUT VOLTAGE (V)
TIME (ps)
1GHz
2GHz
3GHz
13201-006
Figure 6. LVDS Differential Output Voltage, 100 Ω, 2.5 V vs. Carrier Frequency
over Time, 2 dBm Input, Uncorrected for Board Loss, and
Measurement Band Limited by the Trace Bandwidth
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–60 –40 –20 020 40 60
OUTPUT VOLTAGE (V)
TIME (ps)
1GHz
2GHz
3GHz
13201-007
Figure 7. LVPECL Differential Output Voltage, 86 Ω, 2.5 V vs. Carrier
Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and
Measurement Band Limited by the Trace Bandwidth
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–60 –40 –20 020 40 60
OUTPUT VOLTAGE (V)
TIME (ps)
1GHz
2GHz
3GHz
13201-008
Figure 8. LVPECL Differential Output Voltage, 150 Ω, 3.3 V vs. Carrier
Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and
Measurement Band Limited by the Trace Bandwidth
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–60 –40 –20 020 40 60
OUTPUT VOLTAGE (V)
TIME (ps)
1GHz
2GHz
3GHz
13201-009
Figure 9. LVDS Differential Output Voltage, 100 Ω, 2.5 V vs. Carrier Frequency
over Time, 2 dBm Input, Uncorrected for Board Loss, and
Measurement Band Limited by the Trace Bandwidth
Data Sheet HMC6832
Rev. C | Page 13 of 23
0
50
100
150
200
250
300
350
400
450
500
012 3 4 5 6 7 8
OUTPUT CURRE NT (mA)
LOADED BANKS
86Ω
150Ω
13201-010
Figure 10. 3.3 V Current Consumption vs. Loaded Banks
for Given LVPECL RTERM Values
0
50
100
150
200
250
300
350
0 1 2 3 4 5 6 7 8
LOADED BANKS
13201-011
OUTPUT CURRE NT (mA)
86Ω
150Ω
Figure 11. 2.5 V Current Consumption vs. Loaded Banks
for Given LVPECL RTERM Values
–5
0
1
2
3
4
–4
–3
–2
–1
5
01234567
RELATI VE DELAY (ps)
OUT P UT CHANNEL
13201-012
Figure 12. Skew of Outputs Relative to Average Delay, Characterized at 1.25 GHz;
Effects of Customer Evaluation Board Skew and Loss Are De-Embedded
–25
–20
–15
–10
–5
0
–22 –17 –12 –7 –2
OUTPUT P OW E R ( dBm)
INPUT POW E R ( dBm)
13201-013
LVDS, 100Ω
LVPECL, 150Ω
LVPECL, 86Ω
Figure 13. 1.25 GHz Fundamental Differential Output Power vs. Differential
Input Power, Uncorrected for Impedance Mismatch
–6
–5
–4
–3
–2
–1
0
1
10M 100M 1G 10G
OUTPUT TRACE LOSS (dB)
CARRIER FREQUENCY (Hz)
13201-014
BOARD LOSS
200Ω TERMINATION
150Ω TERMINATION
86Ω TERMINATION
Figure 14. LVPECL Evaluation Board Output Trace Loss and Distortion from
Impedance Mismatch vs. Carrier Frequency
10M 100M 1G 10G
CARRIER FREQUENCY (Hz)
13201-015
–20
–15
–10
–5
0
5
10
OUTPUT P OW E R ( dBm)
+25°C
–40°C
+85°C
Figure 15. LVPECL 2.5 V Differential Output Power vs. Carrier Frequency for
Various Temperatures, 0 dBm Input, Network Analyzer Gating Used to
Remove Input and Output Impedance Mismatch and Board Loss
HMC6832 Data Sheet
Rev. C | Page 14 of 23
10M 100M 1G 10G
CARRIER FREQUENCY (Hz)
13201-017
–20
–15
–10
–5
0
5
10
OUTPUT P OW E R ( dBm)
+25°C
–40°C
+85°C
Figure 16. LVPECL 3.3 V Differential Output Power vs. Carrier Frequency for
Various Temperatures, 0 dBm Input, Network Analyzer Gating Used to
Remove Input and Output Impedance Mismatch and Board Loss
10M 100M 1G 10G
CARRIER FREQUENCY (Hz)
13201-019
–20
–15
–10
–5
0
5
10
OUTPUT P OW E R ( dBm)
2.375V
2.500V
2.625V
3.000V
3.300V
3.600V
Figure 17. LVPECL Differential Output Power vs. Carrier Frequency for Various
Supplies, 0 dBm Input, Network Analyzer Gating Used to Remove Input and
Output Impedance Mismatch and Board Loss
10M 100M 1G 10G
CARRIER FREQUENCY (Hz)
13201-021
–20
–15
–10
–5
0
5
10
OUTPUT P OW E R ( dBm)
2.5V, 200Ω
2.5V, 150Ω
2.5V, 86Ω
Figure 18. LVPECL Differential Output Power vs. Carrier Frequency for
Various Terminations, 0 dBm Input, Network Analyzer Gating Used to
Remove Input and Output Impedance Mismatch and Board Loss
10M 100M 1G 10G
CARRIER FREQUENCY (Hz)
13201-023
GAI N (dB)
–15
–10
–5
0
5
10
15
20
25
30
35
–16dBm
–10dBm
–4dBm
0dBm
+2dBm
+8dBm
Figure 19. LVPECL 2.5 V, 150 Ω Differential Gain vs. Carrier Frequency for
Various Input Powers, Network Analyzer Gating Used to Remove Input and
Output Impedance Mismatch and Board Loss
10M 100M 1G 10G
CARRIER FREQUENCY (Hz)
13201-024
–20
–15
–10
–5
0
5
10
OUTPUT P OW E R ( dBm)
2.625V
2.500V
2.375V
Figure 20. LVDS Differential Output Power vs. Carrier Frequency for Various
Supplies, 0 dBm Input, Network Analyzer Gating Used to Remove Input and
Output Impedance Mismatch and Board Loss
10M 100M 1G 10G
CARRIER FREQUENCY (Hz)
13201-026
GAI N (dB)
–15
–20
–10
–5
0
5
10
15
20
25
30
–16dBm
–10dBm
–4dBm
0dBm
+2dBm
+8dBm
Figure 21. LVDS Differential Gain vs. Carrier Frequency for Various Input
Powers with 100 Ω, Network Analyzer Gating Used to Remove Input and
Output Impedance Mismatch and Board Loss
Data Sheet HMC6832
Rev. C | Page 15 of 23
–180
–170
–160
–150
–140
–130
–120
–110
–100
–90
1k 10k 100k 1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
HMC830
SINGLE–ENDED
DIFFERENTIAL
13201-027
Figure 22. Phase Noise Performance at 2 GHz, 2.5 V Supply, HMC830 Used as
Signal Source; Driving 9 dBm Single-Ended Through Balun
–160
–150
–140
–130
–120
–110
–100
–90
1k 10k 100k 1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
13201-123
REFERENCE PHASE NOISE
REF ERE NCE + HM C6832 P HAS E NOI S E
Figure 23. Phase Noise Performance at 2 GHz, Agilent E8257D (UNY Option)
Used as Signal Source, 0 dBm Single-Ended Input Signal, Single-Ended
Output, Depicts Residual Phase Noise Much Better than Reference Source
–125
–120
100 1k 10k 100k 1M
ADDITIV E P HAS E NOIS E ( dBc/ Hz )
FREQUENCY OFFSET (Hz)
–130
–135
–140
–145
–150
–155
–160
–165
–170
–175
–180
SINGLE-ENDED LVPECL
DIFFERENTIAL LVDS
13201-124
Figure 24. Additive Phase Noise at 2 GHz, 0 dBm Single-Ended Input Signal,
Differential LVDS Output and Single-Ended LVPECL Output
–170
–168
–166
–164
–162
–160
–158
–156
–154
0246810 12 14 16
PHASE NOISE FLOOR (dBc/Hz)
SLEW RATE (V/ n s)
3000MHz LVPECL
3000MHz LVDS
2000MHz LVPECL
2000MHz LVDS
1000MHz LVPECL
1000MHz LVDS
100MHz LVPECL
100MHz LVDS
13201-028
Figure 25. Phase Noise Floor vs. Slew Rate for Carrier Frequencies and Output
Configurations, LVPECL RTERM = 150 Ω; LVDS RTERM = 100 Ω
–166
–165
–164
–163
–162
–161
–160
–159
–158
–157
–15 –10 –5 0 5 10 15
PHASE NOISE FLOOR (dBc/Hz)
INPUT POW E R ( dBm)
LVDS
13201-029
LVPECL
Figure 26. Phase Noise Floor at 1.6 GHz vs. Input Power,
LVPECL RTERM = 150 Ω; LVDS RTERM = 100 Ω
0500 1000 1500 2000 2500 3000
FOM (dBc/Hz)
SINUSOIDAL INP UT F RE QUENCY (MHz)
LVPECL
LVDS
13201-030
–260
–258
–256
–254
–252
–250
–248
–246
–244
–242
Figure 27. Phase Noise Performance with Low Frequency Sinusoidal Inputs,
Input Power = 10 dBm Single-Ended, LVPECL RTERM = 150 Ω;
LVDS RTERM = 100 Ω, Phase Noise Floor (dBc/Hz) =
Figure of Merit (FOM) (dBc/Hz)) + 10 log(fOUT (Hz))
HMC6832 Data Sheet
Rev. C | Page 16 of 23
–170
–169
–168
–167
–166
–165
–164
–163
–162
–161
–160
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
PHASE NOISE FLOOR (dBc/Hz)
13201-031
SUPPLY VOLTAGE (V)
LVDS
LVPECL
Figure 28. Phase Noise Floor vs. Supply Voltage for LVPECL and LVDS,
LVPECL RTERM = 150 Ω; LVDS RTERM = 100 Ω
–170
–169
–168
–167
–166
–165
–164
–163
–162
–161
–160
PHASE NOISE FLOOR (dBc/Hz)
13201-032
–60 –40 –20 020 40 60 80 100
TEMPERATURE (°C)
3GHz
2GHz
1GHz
Figure 29. LVPECL 2.5 V, 150 Ω, Phase Noise Floor vs. Temperature for
Various Carrier Frequencies
–170
–169
–168
–167
–166
–165
–164
–163
–162
–161
–160
PHASE NOISE FLOOR (dBc/Hz)
13201-033
–60 –40 –20 020 40 60 80 100
TEMPERATURE (°C)
2GHz
1GHz
3GHz
Figure 30. LVDS Phase Noise Floor vs. Temperature for Various Carrier Frequencies
–35
–30
–25
–20
–15
–10
–5
0
02 4 6 8 10
S11 (d B)
FREQUENCY (GHz)
DIFFERENTIAL, 2.5V
SINGLE-ENDED, 2.5V
DIFFERENTIAL, 3.3V
SINGLE-ENDED, 3.3V
13201-034
Figure 31. LVDS/LVPECL S Parameters (S11), Network Analyzer Gating Used
to Remove Input and Output Impedance Mismatch and Board Loss
–110
–100
–90
–80
–60
–70
–50
–40
–30
0246810
S12 (d B)
FREQUENCY (GHz)
DIFFERENTIAL, 2.5V
SINGLE-ENDED, 2.5V
DIFFERENTIAL, 3.3V
SINGLE-ENDED, 3.3V
13201-035
Figure 32. LVPECL S Parameters (S12), Network Analyzer Gating Used to
Remove Input and Output Impedance Mismatch and Board Loss
–110
–100
–90
–80
–60
–70
–50
–40
–30
0246810
S12 (d B)
FREQUENCY (GHz)
13201-036
DIFFERENTIAL, 2.5V
SINGLE-ENDED, 2.5V
Figure 33. LVDS S Parameters (S12), Network Analyzer Gating Used to
Remove Input and Output Impedance Mismatch and Board Loss
Data Sheet HMC6832
Rev. C | Page 17 of 23
–30
–25
–20
–15
–10
–5
0
02 4 6 8 10
S22 (dB)
FREQUENCY (GHz)
DIFFERENTIAL, 2.5V
SINGLE-ENDED, 2.5V
DIFFERENTIAL, 3.3V
SINGLE-ENDED, 3.3V
13201-037
Figure 34. LVPECL S Parameters (S22), Network Analyzer Gating Used to
Remove Input and Output Impedance Mismatch and Board Loss
–30
–25
–20
–15
–10
–5
0
0246810
S22 (dB)
FREQUENCY (GHz)
13201-038
DIFFERENTIAL, 2.5V
SINGLE-ENDED, 2.5V
Figure 35. LVDS S Parameters (S22), Network Analyzer Gating Used to
Remove Input and Output Impedance Mismatch and Board Loss
13201-039
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
OUTPUT P OW E R ( dBm)
SUPPLY VOLTAGE (V)
+85°C
+25°C
–40°C
NO LOAD
600Ω
Figure 36. VAC_REF Output Power vs. Supply Voltage for Various
Temperatures and Current Loads; 600 Ω Signifies 2 mA Output Load
0
50
100
150
200
250
300
350
400
2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
SUPPLY CURRENT ( mA)
SUPPLY VOLTAGE (V)
86Ω
150Ω
200Ω
13201-040
CORE
+85°C
+25°C
–40°C
Figure 37. LVPECL Supply Current vs. Supply Voltage for Various
Temperatures and RTERM Values
100
104
108
112
116
120
124
128
132
136
140
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
SUPPLY CURRENT ( mA)
SUPPLY VOLTAGE (V)
+25°C
–40°C
+85°C
13201-041
Figure 38. LVDS Supply Current vs. Supply Voltage for Various Temperatures
HMC6832 Data Sheet
Rev. C | Page 18 of 23
TEST CIRCUITS
50Ω 50Ω
VDD = 2. 5V /3. 3V
HMC6832
SOURCE
GENERATOR
+
–
86Ω/150Ω 86Ω/150Ω
HIG H IMP E DANCE
PROBE
HIGH-Z
HIGH-Z
13201-042
Figure 39. Test Circuit for DC LVPECL Measurements, 86 Ω Termination Used for VDD = 2.5 V; 150 Ω Termination Used for VDD = 3.3 V
50Ω 50Ω
VDD = 2. 5V
HMC6832
SOURCE
GENERATOR
+
–
100Ω
HIG H IMP E DANCE
PROBE
HIGH-Z
HIGH-Z
13201-043
Figure 40. Test Circuit for DC LVDS Measurements
50Ω 50Ω
VDD = 2. 5V /3. 3V
DC BLOCKING
CAPACITORS
HMC6832
SOURCE
GENERATOR
+
–
86Ω/150Ω 86Ω/150Ω
OSCILLOSCOPE
13201-044
50Ω 50Ω
Figure 41. Test Circuit for Transient (AC) LVPECL Measurements, 86 Ω Termination Used for VDD = 2.5 V; 150 Ω Termination Used for VDD = 3.3 V
50Ω 50Ω
VDD = 2. 5V
HMC6832
SOURCE
GENERATOR
+
–
OSCILLOSCOPE
13201-045
50Ω 50Ω
100Ω
DC BLOCKING
CAPACITORS
Figure 42. Test Circuit for Transient (AC) LVDS Measurements
50Ω 50Ω
VDD = 2. 5V
HMC6832
SSA
13201-046
50Ω
150Ω 150Ω
BALUN
SATURATED
AMPLIFIER
DC BLO CKING
CAPACITORS
Figure 43. Test Circuit for Phase Noise LVPECL Measurements
50Ω 50Ω
VDD = 2. 5V
HMC6832
SSA
13201-047
50Ω
BALUN
SATURATED
AMPLIFIER
100Ω
DC BLO CKING
CAPACITORS
Figure 44. Test Circuit for Phase Noise LVDS Measurements
Data Sheet HMC6832
Rev. C | Page 19 of 23
THEORY OF OPERATION
INPUT STAGE
The input stage shown in Figure 45 is flexible. It can be driven
single-ended or differential with LVPECL, LVDS, or CML signals.
If driven single-ended, place a large ac-coupled capacitor between
the undriven input and a nearby GND pin. There are pull-up and
pull-down resistors on each single-ended input to set the nominal
dc voltage to VDD/2. The input is selectable by the input select
pin (IN_SEL), a digital pin that can be set to either GND (INx0)
or VDD (INx1). To select t he output termination, use the
configuration pin (CONFIG), a digital pin that can be set to
either GND (LVPECL) or to VDD (LVDS). When left floating,
the CONFIG pin is internally pulled to VDD (LVDS).
LVPECL OUTPUT STAGE
The LVPECL output driver produces up to 0.8 V p-p differential
swing into 100 Ω differential loads. LVPECL drivers are terminated
with off-chip resistors that provide the dc current through the
emitter-follower output stage. If unused, LVPECL outputs can
be left floating. VAC_REF is an output reference voltage capable
of sourcing 2 mA at 1.25 V.
VDD
LVDS
100kΩ
CONFIGURATION
CONTROL
CONFIG
HIGH: LVDS
LOW: LVPECL LVPECL
13201-048
IN_SEL
HIG H: IN1
LOW: IN0
VDD
VDD
VDD
VDD
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
INP1
INN1
100pF
100pF
100pF
100pF
INP0
INN0
Figure 45. Input Stage Block Diagram
HMC6832 Data Sheet
Rev. C | Page 20 of 23
13201-049
OUTP7
VAC_REF
4mA4mA
OUTN7
LVDS
OUTP6
4mA4mA
OUTN6
LVDS
OUTP5
4mA4mA
OUTN5
LVDS
OUTP4
4mA4mA
OUTN4
LVDS
OUTP3
4mA4mA
OUTN3
LVDS
OUTP2
4mA4mA
OUTN2
LVDS
OUTP1
4mA4mA
2mA
OUTN1
LVDS
OUTP0
4mA4mA
OUTN0
LVDS
Figure 46. Output Stage Block Diagram
A number of choices are available for connecting the LVPECL
drivers and receivers. There are compromises between matching
performance, common-mode levels, and signal swing. For clocking
applications, the user often has the option of using ac coupling,
unlike in many datapath situations. Figure 47 shows a simplified
interface schematic between an LVPECL output and an input
stage, where various options and trade-offs for the termination
components are provided (see Table 11). The Analog Devices,
Inc., evaluation board has a great deal of flexibility in how the
inputs/outputs are configured. Several configurations are shown
in the Applications Information section.
VDD = 2. 5V /3. 3V
OUTP
OUTN
LVPECL
HMC6832
R
L
R
L
C
AC
C
AC
13201-050
Figure 47. Recommended Interface Diagram
Table 11. Interface Values
Interface Value Description
Load Resistor (RL) DC current termination for LVPECL
output stage
150 Ω Analog Devices evaluation board
default, standard LVPECL termination
voltages
200 Ω Reduced current, no performance
degradation
300 Ω Further reduced current, lower output
power but flatter frequency response
Open If using internal dc termination
network at the receiver
AC-Coupled Capacitor (CAC)
Large Capacitor Analog Devices evaluation board
default, when ac coupling is used
Data Sheet HMC6832
Rev. C | Page 21 of 23
APPLICATIONS INFORMATION
Figure 48 to Figure 50 illustrate the common input interface
configurations. Figure 48 shows how to interface a LVCMOS
input to the HMC6832. A capacitor is needed between the
LVCMOS driver and the HMC6832 to ac couple the input. In
addition, add a capacitor between the inverted input of the
HMC6832 and a nearby GND pin to reduce noise in the system.
The series resistance (RSERIES) provides impedance matching and
signal attenuation. The RSERIES value is the difference between
the LVCMOS driver output impedance and the transmission
line impedance. Position RSERIES near the LVCMOS driver.
VDD = 2. 5V OR 3. 3V
LVCMOS
HMC6832
13201-051
R
SERIES
DC BLO CKING
CAPACITORS
Figure 48. LVCMOS AC-Coupled Input Interface
VDD = 2. 5V
LVDS
HMC6832
13201-052
100Ω
Figure 49. LVDS DC-Coupled Input Interface
VDD = 2. 5V OR 3. 3V
DIFFERENTIALHMC6832
13201-053
DC BLO CKING
CAPACITORS
Figure 50. Differential Input AC-Coupled Interface
Figure 51 and Figure 52 illustrate the common output interface
configurations.
VDD = 2. 5V OR 3. 3V
LVPECL
HMC6832
13201-054
86Ω/150Ω 86Ω/150Ω
Figure 51. LVPECL Output DC Termination Interface (86 Ω Termination Can
Be Used at 2.5 V Only)
VDD = 2. 5V OR 3. 3V
LVPECL
HMC6832
13201-055
86Ω/150Ω 86Ω/150Ω
DC BLO CKING
CAPACITORS
Figure 52. LVPECL Output AC Termination Interface (86 Ω Termination Can
Be Used at 2.5 V Only)
RECOMMENDED SOLDER REFLOW PROFILE
The typical Pb-free reflow solder profile shown in Figure 53 is
based on JEDEC J-STD-20C.
60 SECO NDS
TO
180 SECO NDS
20 SECO NDS
TO 40 SECONDS
480 SECO NDS M AX
TEMPERATURE (°C)
TIME (Seconds)
260°C –5°C/+ 0°C
150°C TO 200°C
RAMP DOWN
6°C/SECOND
MAX
217°C
RAMP UP
3°C/SECOND MAX
60 SECO NDS
TO
150 SECO NDS
13201-100
Figure 53. LFCSP Pb-Free Reflow Profile
HMC6832 Data Sheet
Rev. C | Page 22 of 23
EVALUATION PRINTED CIRCUIT BOARD (PCB)
An easy to use evaluation PCB is available from Analog Devices
upon request. Top and bottom view layouts of the evaluation
board are given in Figure 54 and Figure 55. For the circuit board
in this application, use RF circuit design techniques.
Ensure that signal lines have 50 Ω impedance. Connect the
package ground leads and exposed paddle directly to the
ground plane similarly to that shown in Figure 54 (top view)
and Figure 55 (bottom view). Use a sufficient number of via
holes to connect the top and bottom ground planes.
13201-101
Figure 54. Evaluation PCB (Top View)
13201-102
Figure 55. Evaluation PCB (Bottom View)
Data Sheet HMC6832
Rev. C | Page 23 of 23
OUTLINE DIMENSIONS
0.50
BSC
0.65
0.55
0.45
COMPLIANT
TO
JEDEC ST ANDARDS M O - 220-V HHD-1.
BOT TOM VI EW
TOP VIEW
SI DE VIEW
5.10
5.00 SQ
4.90
0.90
0.85
0.80 0.05 M AX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
28
814
15
21
22
7
11-29-2017-B
0.30
0.25
0.18
0.20 M IN
3.25
3.15 S Q
3.05
EXPOSED
PAD
PKG-005229
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95 )
SEATING
PLANE
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURAT IO N AND
FUNCT I O N DES CRI P T I ONS
SECTION OF THIS DATA SHEET.
Figure 56. 28-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.85 mm Package Height
(HCP-28-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description Package Option
HMC6832ALP5LE −40°C to +85°C MSL3 28-Lead Lead Frame Chip Scale Package [LFCSP] HCP-28-1
HMC6832ALP5LETR −40°C to +85°C MSL3 28-Lead Lead Frame Chip Scale Package [LFCSP] HCP-28-1
EV1HMC6832ALP5L Evaluation Board (LVPECL Configuration)
EV2HMC6832ALP5L Evaluation Board (LVDS Configuration)
1 All models are RoHS Compliant Parts.
2 The maximum peak reflow temperature is 260°C for the HMC6832ALP5LE and HMC6832ALP5LETR. See the Absolute Maximum Ratings section, Table 8.
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13201-0-1/18(C)
