Low Noise, 2:8 Differential Fanout Buffer HMC6832 Data Sheet FEATURES GENERAL DESCRIPTION Ultralow noise floor: -165.9 dBc/Hz or -165.2 dBc/Hz (LVPECL or LVDS) at 2000 MHz Configurable to LVPECL or pseudo LVDS outputs 2.5 V or 3.3 V LVPECL operation (LVDS 2.5 V only) Wideband: 10 MHz to 3500 MHz operating frequency range Flexible input interface LVPECL, LVDS, CML, and CMOS compatible AC or dc coupling On-chip 50 k pull-up/pull-down resistors to VDD and GND Multiple output drivers Up to 8 differential or 16 single-ended LVPECL or LVDS outputs Low speed digital control via the IN_SEL and CONFIG pins 28-lead, 5 mm x 5 mm, LFCSP package, 25 mm2 The HMC6832 is an input selectable, 2:8 differential fanout buffer designed for low noise clock distribution. The IN_SEL control pin selects one of the two differential inputs. This input is then buffered to all eight differential outputs. The low jitter outputs of the HMC6832 lead to synchronized low noise switching of downstream circuits, such as mixers, analog-todigital converters (ADCs)/digital-to-analog converters (DACs), or serializer/deserializer (SERDES) devices. The device is capable of low voltage, positive emitter-coupled logic (LVPECL) or low voltage differential signaling (LVDS) configurations by pulling the CONFIG pin low for LVPECL or high or open (internally pulled high) for pseudo LVDS. PRODUCT HIGHLIGHTS 1. APPLICATIONS SONET, Fibre Channel, GigE clock distribution ADC/DAC clock distribution Low skew and jitter clocks Wireless/wired communications Level translation High performance instrumentation Medical imaging Single-ended to differential conversions 2. 3. 4. 5. Rev. C Multiple Output Configurations. The CONFIG pin allows the user to select LVPECL or LVDS output termination. Multiple Supply Voltage Operation. The HMC6832 operates at 2.5 V or 3.3 V for LVPECL terminations (2.5 V only for LVDS). Low Noise. The HMC6832 noise is low, typically from -168 dBc/Hz to -162 dBc/Hz up to 3000 MHz. Low Propagation Delay. The HMC6832 displays a low delay, less than 207 ps, typical. Channel skew is also low, 5 ps, typical. Low Core Current. The HMC6832 has a low core current of 56 mA, typical. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2016-2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC6832 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution................................................................................ 10 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions........................... 11 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 12 Product Highlights ........................................................................... 1 Test Circuits ..................................................................................... 18 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 19 Functional Block Diagram .............................................................. 3 Input Stage ................................................................................... 19 Specifications..................................................................................... 4 LVPECL Output Stage ............................................................... 19 AC Output Characteristics .......................................................... 4 Applications Information .............................................................. 21 Output Gain and Power Characteristics ................................... 5 Recommended Solder Reflow Profile...................................... 21 Timing Characteristics ................................................................ 8 Evaluation Printed Circuit Board (PCB) ................................ 22 Timing Specifications .................................................................. 8 Outline Dimensions ....................................................................... 23 Absolute Maximum Ratings.......................................................... 10 Ordering Guide .......................................................................... 23 Thermal Resistance .................................................................... 10 REVISION HISTORY 1/2018--Rev. B to Rev. C Added Figure 24; Renumbered Sequentially .............................. 15 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 9/2016--Rev. A to Rev. B Changes to Features Section and General Description Section . 1 Changes to Figure 1 .......................................................................... 3 Changes to Table 1 and Table 2 ....................................................... 4 Changes Table 3 ................................................................................ 5 Changes to Floor Density Jitter Parameter, Test Conditions/ Comments Column Only, Table 4 and Integrated RMS Jitter, Test Conditions/Comments Column Only, Table 4..................... 6 Changes to Single-Sideband (SSB Phase Noise Floor) Parameter, Test Conditions/Comments Column Only, Table 5..................... 8 Changes to Figure 11 Caption and Figure 15 Caption .............. 13 Changes to Figure 16 Caption to Figure 18 Caption and Figure 20 Caption ........................................................................... 14 Changes to Figure 19 and Figure 21............................................. 14 Added Figure 23; Renumbered Sequentially ......................................15 Changes to Figure 22 Caption and Figure 24 Caption to Figure 27 Caption ........................................................................... 15 Changes to Figure 28 Caption ...................................................... 16 Changes to Figure 38 Caption, Figure 40 Caption, and Figure 42 . 18 Changes to Input Stage Section and Figure 44 ........................... 19 Changes to Figure 45...................................................................... 20 Changes to Figure 50 Caption and Figure 51 Caption .............. 21 3/2016--Revision A: Initial Version Rev. C | Page 2 of 23 Data Sheet HMC6832 FUNCTIONAL BLOCK DIAGRAM VDD 50k IN_SEL HIGH: IN1 LOW: IN0 OUTP7 INP1 50k OUTN7 100pF LVDS OUTP6 VDD OUTN6 100pF INN1 OUTN5 50k 4mA 4mA LVDS OUTP4 OUTN4 4mA LVDS OUTP5 50k 4mA 4mA 4mA LVDS 4mA 4mA OUTP3 VDD OUTN3 50k INP0 50k OUTN2 100pF OUTN1 100pF OUTN0 50k 4mA 4mA 4mA LVDS OUTP0 50k INN0 4mA LVDS OUTP1 VDD LVDS OUTP2 4mA 4mA LVDS 4mA 4mA VAC_REF VDD 100k CONFIGURATION CONTROL LVDS 2mA LVPECL Figure 1. Rev. C | Page 3 of 23 13201-001 CONFIG HIGH: LVDS LOW: LVPECL HMC6832 Data Sheet SPECIFICATIONS Typical is given as fINPUT = 1.25 GHz (ac-coupled), differential input power = 7.5 dBm, TNOMINAL = 25C, unless otherwise noted. All outputs captured using 50 scope termination. 50 board termination on inputs used to minimize reflections. Table 1. Parameter DC INPUT CHARACTERISTICS VDD LVPECL LVDS Input Common-Mode Voltage SELECTION PINS IN_SEL Pin Input Voltage Low (VIL) Input Voltage High (VIH) CONFIG Pin Input Voltage Low (VIL) Input Voltage High (VIH) TEMPERATURE RANGE, TA SUPPLY CURRENT Core Current Min Typ Max Unit Test Conditions/Comments 2.375 3.0 2.375 GND + 0.2 2.5 3.3 2.5 VDD/2 2.625 3.6 2.625 VDD - 0.2 V V V V 2.5 V operation 3.3 V operation VDD/2 - 0.4 V V 2VDD/3 - 0.3 V V C GND = IN0, VDD = IN1 VDD/2 + 0.4 GND = LVPECL, VDD = LVDS 2VDD/3 + 0.3 -40 Full Load Current LVPECL Termination LVDS Termination RF INPUT CHARACTERISTICS Operating Frequency Range Input Swing (Single-Ended) Input Capacitance Pull-Up/Pull-Down Resistance 1 Guaranteed by design +25 +85 56 56 mA mA Outputs unterminated VDD = 2.5 V VDD = 3.3 V 301 283 125 mA mA mA RTERM1 = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 MHz V pF k See Figure 1 10 0.1 3500 2 3.6 50 For LVPECL termination, RTERM is the single-ended termination resistance to GND. For LVDS termination, RTERM is the differential termination resistance. AC OUTPUT CHARACTERISTICS Table 2. Parameter DIFFERENTIAL OUTPUT VOLTAGE SWING LVPECL Termination LVDS Termination OUTPUT VOLTAGE, HIGH LEVEL LVPECL Termination LVDS Termination OUTPUT VOLTAGE, COMMON LEVEL LVPECL Termination LVDS Termination Min Typ Max Unit 652 721 462 mV p-p mV p-p mV p-p 1.63 2.51 1.65 V V V 1.30 2.15 1.42 V V V Rev. C | Page 4 of 23 Test Conditions/Comments Differential inputs and outputs; adjusted for impedance mismatch and printed circuit board (PCB) losses; see Figure 41 and Figure 42 for ac measurement test circuits RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V Differential inputs and outputs RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V Differential inputs and outputs; see Figure 39 and Figure 40 for dc measurement test circuits RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V Data Sheet Parameter OUTPUT VOLTAGE, LOW LEVEL LVPECL Termination HMC6832 Min LVDS Termination AC PERFORMANCE Typ Max Unit 0.97 1.79 1.19 V V V 1600 2500 3200 1750 2550 4100 MHz MHz MHz MHz MHz MHz 56 57 45 ps ps ps 59 59 46 ps ps ps 50 50 50 % % % -55 -59 -52 dBc dBc dBc 3 dB Bandwidth LVPECL Differential Input LVDS Differential Input Output Rise Time (20% to 80%) LVPECL Termination LVDS Termination Output Fall Time (20% to 80%) LVPECL Termination LVDS Termination Duty Cycle Variation LVPECL Termination LVDS Termination Power Supply Rejection Ratio LVPECL Termination LVDS Termination Test Conditions/Comments Differential inputs and outputs RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V See Figure 41 and Figure 42 for ac measurement test circuits Adjusted for impedance mismatch and PCB losses; refer to Figure 19 and Figure 21 Differential input = 100 mV p-p; VDD = 2.5 V Differential input = 200 mV p-p; VDD = 2.5 V Differential input = 400 mV p-p; VDD = 2.5 V Differential input = 100 mV p-p; VDD = 2.5 V Differential input = 200 mV p-p; VDD = 2.5 V Differential input = 400 mV p-p; VDD = 2.5 V Differential inputs and outputs RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V Differential inputs and outputs RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V Differential inputs and outputs RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V 50 kHz, 100 mV p-p sinusoidal signal modulated onto VDD; single-ended 1 GHz, 0 dBm input; outputs measured differentially RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V OUTPUT GAIN AND POWER CHARACTERISTICS Table 3. Parameter DIFFERENTIAL SMALL SIGNAL GAIN (S21) Min Typ Max Unit Test Conditions/Comments Adjusted for impedance mismatch and printed circuit board (PCB) losses 25 26 22 dB dB dB -25 -25 -26 dBm dBm dBm RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V 1250 MHz, adjusted for impedance mismatch and PCB losses RTERM = 86 , VDD = 2.5 V RTERM = 150 , VDD = 3.3 V RTERM = 100 , VDD = 2.5 V VDD = 2.5 V, adjusted for impedance mismatch and PCB losses -4 -2 -5 dBm dBm dBm LVPECL Termination LVDS Termination INPUT 1 dB COMPRESSION POINT (P1dB) LVPECL Termination LVDS Termination SATURATED POWER IN FUNDAMENTAL TONE (SINGLE-ENDED) LVPECL Termination 1000 MHz 2000 MHz 3000 MHz Rev. C | Page 5 of 23 -4 dBm = 399 mV p-p -2 dBm = 502 mV p-p -5 dBm = 356 mV p-p HMC6832 Data Sheet Parameter LVDS Termination 1000 MHz 2000 MHz 3000 MHz HARMONICS Min Typ LVPECL Termination fOUT 2 x fOUT 3 x fOUT 4 x fOUT 5 x fOUT LVDS Termination fOUT 2 x fOUT 3 x fOUT 4 x fOUT 5 x fOUT OUTPUT RETURN LOSS < 10 dB Max Unit Test Conditions/Comments -7 -7 -7 dBm dBm dBm -7 dBm = 283 mV p-p -7 dBm = 283 mV p-p -7 dBm = 283 mV p-p VDD = 2.5 V, adjusted for impedance mismatch and PCB losses, fINPUT = 2 GHz -2 -28 -17 -38 -24 dBm dBc dBc dBc dBc -2 dBm = 502 mV p-p -7 -22 -16 -38 -29 <6 dBm dBc dBc dBc dBc GHz -7 dBm = 283 mV p-p LVDS termination Table 4. Jitter Parameter FLOOR DENSITY JITTER Input Carrier Frequency LVPECL Termination 100 MHz 622 MHz 1000 MHz 1600 MHz 1750 MHz 2000 MHz 3000 MHz LVDS Termination 100 MHz 622 MHz 1000 MHz 1600 MHz 1750 MHz 2000 MHz 3000 MHz INTEGRATED RMS JITTER 100 MHz Carrier Frequency LVPECL Termination 60 kHz to 10 MHz 60 kHz to 20 MHz 60 kHz to 40 MHz Min Typ Max Unit 13.09 1.61 1.26 0.91 0.81 0.64 0.51 as/Hz as/Hz as/Hz as/Hz as/Hz as/Hz as/Hz 15.55 1.63 1.21 0.80 0.72 0.69 0.64 as/Hz as/Hz as/Hz as/Hz as/Hz as/Hz as/Hz Test Conditions/Comments Single-ended input; differential output; measured with saturated amplifier to remove amplitude modulation (AM) noise (only affects 100 MHz data); LVPECL RTERM = 150 ; LVDS RTERM = 100 ; VDD = 2.5 V; see Figure 43 and Figure 44 for phase noise measurement test circuits Single-ended input; differential output; measured with saturated amplifier to remove AM noise (only affects 100 MHz data); LVPECL RTERM = 150 ; LVDS RTERM = 100 ; VDD = 2.5 V; see Figure 43 and Figure 44 for phase noise measurement test circuits 37 52 74 fs rms fs rms fs rms Rev. C | Page 6 of 23 Data Sheet Parameter LVDS Termination 60 kHz to 10 MHz 60 kHz to 20 MHz 60 kHz to 40 MHz 622.06 MHz Carrier Frequency LVPECL Termination 10 MHz to 80 MHz 10 MHz to 100 MHz LVDS Termination 10 MHz to 80 MHz 10 MHz to 100 MHz 1000 MHz Carrier Frequency LVPECL Termination 10 MHz to 80 MHz 10 MHz to 100 MHz LVDS Termination 10 MHz to 80 MHz 10 MHz to 100 MHz 1600 MHz Carrier Frequency LVPECL Termination 10 MHz to 80 MHz 10 MHz to 100 MHz LVDS Termination 10 MHz to 80 MHz 10 MHz to 100 MHz 2000 MHz Carrier Frequency LVPECL Termination 10 MHz to 80 MHz 10 MHz to 100 MHz LVDS Termination 10 MHz to 80 MHz 10 MHz to 100 MHz 3000 MHz Carrier Frequency LVPECL Termination 10 MHz to 80 MHz 10 MHz to 100 MHz LVDS Termination 10 MHz to 80 MHz 10 MHz to 100 MHz HMC6832 Min Typ Max Unit 44 62 88 fs rms fs rms fs rms 12 14 fs rms fs rms 12 14 fs rms fs rms 9 11 fs rms fs rms 10 10 fs rms fs rms 7 8 fs rms fs rms 6 7 fs rms fs rms 5 6 fs rms fs rms 5 6 fs rms fs rms 3 4 fs rms fs rms 4 5 fs rms fs rms Rev. C | Page 7 of 23 Test Conditions/Comments HMC6832 Data Sheet Table 5. Phase Noise Floor Parameter SINGLE-SIDEBAND (SSB PHASE NOISE FLOOR) Min Typ Input Carrier Frequency LVPECL Termination 100 MHz 622 MHz 1000 MHz 1600 MHz 1750 MHz 2000 MHz 3000 MHz LVDS Termination 100 MHz 622 MHz 1000 MHz 1600 MHz 1750 MHz 2000 MHz 3000 MHz Max Unit -165.7 -168.0 -166.0 -164.8 -165.0 -165.9 -164.4 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -164.2 -167.9 -166.4 -165.9 -166.0 -165.2 -162.4 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Test Conditions/Comments Single-ended input; differential output; measured with saturated amplifier to remove AM noise (only affects 100 MHz data); LVPECL RTERM = 150 ; LVDS RTERM = 100 ; VDD = 2.5 V; see Figure 43 and Figure 44 for phase noise measurement test circuits TIMING CHARACTERISTICS TA = 25C, unless otherwise noted. Minimum/maximum values are guaranteed by design and characterization. Table 6. Parameter TYPICAL CHANNEL SKEW TYPICAL PROPAGATION DELAY LVPECL Termination LVDS Termination TYPICAL DELAY VARIATION At TA = 25C LVPECL Termination LVDS Termination At TA = -40C to +85C LVPECL Termination LVDS Termination PROCESS PROPAGATION DELAY VARIATION Min Typ 5 Unit ps Test Conditions/Comments Relative to OUTP5, VDD = 2.5 V or 3.3 V 201 207 ps ps VDD = 2.375 V to 3.6 V VDD = 2.375 V to 2.625 V 5 5 ps ps VDD = 2.375 V to 3.6 V, measurement uncertainty = 2 ps VDD = 2.375 V to 2.625 V, measurement uncertainty = 2 ps 13 13 ps ps ps VDD = 2.375 V to 3.6 V, measurement uncertainty = 4 ps VDD = 2.375 V to 2.625 V, measurement uncertainty = 4 ps Process simulation, VDD = 2.5 V -18 Max +18 TIMING SPECIFICATIONS VDD = 2.5 V or 3.3 V, TA = 25C, unless otherwise noted. Table 7. Parameter tSKEW tR tF tD Typical 5 57/45 59/46 201/207 Unit ps ps ps ps Description Output skew Output rise/fall time (LVPECL/LVDS) Output rise/fall time (LVPECL/LVDS) Propagation delay (LVPECL/LVDS) Rev. C | Page 8 of 23 Data Sheet HMC6832 Timing Diagram INP0 1 2 3 4 5 6 INN0 1 2 3 4 5 6 tD OUTN0 1 2 3 4 5 6 OUTP0 1 2 3 4 5 6 tSKEW 1 2 3 OUTN7 1 2 3 4 80% 20% 6 5 6 80% 4 tR Figure 2. Timing Diagram Rev. C | Page 9 of 23 5 20% tF 13201-002 OUTP7 HMC6832 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Maximum Voltage Between VDD Pins and EPAD Maximum RF Power to INPx and INNx INPx and INNx Minimum Output Load Resistor LVPECL (VDD = 2.5 V) LVPECL (VDD = 3.3 V) LVPECL Output Load Current Input Select Voltage Range Maximum VAC_REF Load Current Maximum Reflow Temperature (MSL3 Rating) ESD Sensitivity Human Body Model (HBM) Field Induced Charged Device Model (FICDM) Table 9. Thermal Resistance Rating -0.3 V to +4 V 15 dBm, single-ended -0.3 V to +3.6 V Package Type 28-Lead LFCSP ESD CAUTION 75 to GND 100 to GND 40 mA/single-ended output channel -0.3 V to +3.6 V 2 mA 260C Class 1C Class C4 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 10 of 23 JC 10.6 Unit C/W Data Sheet HMC6832 23 OUTN4 22 OUTP4 GND 1 OUTP7 2 OUTN7 3 IN_SEL 4 INP1 5 HMC6832 TOP VIEW (Not to Scale) OUTP0 12 17 OUTN1 16 OUTP1 15 VDD OUTN0 13 GND 14 VDD 8 INP0 9 INN0 10 CONFIG 11 INN1 6 VAC_REF 7 21 OUTN3 20 OUTP3 19 OUTN2 18 OUTP2 NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO GND. 13201-003 27 26 25 24 28 VDD OUTN6 OUTP6 OUTN5 OUTP5 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic GND OUTP7 OUTN7 IN_SEL INP1 INN1 VAC_REF VDD INP0 INN0 CONFIG OUTP0 OUTN0 GND VDD OUTP1 OUTN1 OUTP2 OUTN2 OUTP3 OUTN3 OUTP4 OUTN4 OUTP5 OUTN5 OUTP6 OUTN6 VDD EPAD Description Ground. Differential Signal Output 7, Positive. Differential Signal Output 7, Negative. Input Select. Logic 0 = INP0/INN0 and Logic 1 = INP1/INN1. Differential Signal Input 1, Positive. Differential Signal Input 1, Negative. Output Reference Voltage. Power Supply. Differential Signal Input 0, Positive. Differential Signal Input 0, Negative. Output Termination Configuration Input. Logic 0 = LVPECL and Logic 1 = LVDS. Differential Signal Output 0, Positive. Differential Signal Output 0, Negative. Ground. Power Supply. Differential Signal Output 1, Positive. Differential Signal Output 1, Negative. Differential Signal Output 2, Positive. Differential Signal Output 2, Negative. Differential Signal Output 3, Positive. Differential Signal Output 3, Negative. Differential Signal Output 4, Positive. Differential Signal Output 4, Negative. Differential Signal Output 5, Positive. Differential Signal Output 5, Negative. Differential Signal Output 6, Positive. Differential Signal Output 6, Negative. Power Supply. Exposed Pad. The exposed pad must be connected to GND. Rev. C | Page 11 of 23 HMC6832 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Typical is given as fINPUT = 1.25 GHz (ac-coupled), differential input power = 7.5 dBm, TNOMINAL = 25C, unless otherwise noted. All outputs captured using 50 scope termination. Used 50 board termination on inputs to minimize reflections. 0.4 0.4 1GHz 2GHz 3GHz 0.3 0.2 0 -0.1 -0.1 -0.2 -0.3 -0.3 -600 -400 -200 0 200 400 600 800 -0.4 -60 0 20 40 60 0.4 1GHz 2GHz 3GHz 0.3 1GHz 2GHz 3GHz 0.3 0.2 0 -0.1 0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -400 -200 0 200 400 600 800 TIME (ps) -0.4 -60 13201-005 -600 Figure 5. LVPECL Differential Output Voltage, 150 , 3.3 V vs. Carrier Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and Measurement Band Limited by the Trace Bandwidth -40 -20 0 20 40 60 TIME (ps) 13201-008 OUTPUT VOLTAGE (V) 0.2 0.1 Figure 8. LVPECL Differential Output Voltage, 150 , 3.3 V vs. Carrier Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and Measurement Band Limited by the Trace Bandwidth 0.4 0.4 1GHz 2GHz 3GHz 0.3 1GHz 2GHz 3GHz 0.3 0.2 0.1 0 -0.1 0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -400 -200 0 TIME (ps) 200 400 600 800 -0.4 -60 13201-006 -600 Figure 6. LVDS Differential Output Voltage, 100 , 2.5 V vs. Carrier Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and Measurement Band Limited by the Trace Bandwidth -40 -20 0 TIME (ps) 20 40 60 13201-009 OUTPUT VOLTAGE (V) 0.2 -0.4 -800 -20 Figure 7. LVPECL Differential Output Voltage, 86 , 2.5 V vs. Carrier Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and Measurement Band Limited by the Trace Bandwidth 0.4 -0.4 -800 -40 TIME (ps) Figure 4. LVPECL Differential Output Voltage, 86 , 2.5 V vs. Carrier Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and Measurement Band Limited by the Trace Bandwidth OUTPUT VOLTAGE (V) 0 -0.2 TIME (ps) OUTPUT VOLTAGE (V) 0.1 13201-007 OUTPUT VOLTAGE (V) 0.1 13201-004 OUTPUT VOLTAGE (V) 0.2 -0.4 -800 1GHz 2GHz 3GHz 0.3 Figure 9. LVDS Differential Output Voltage, 100 , 2.5 V vs. Carrier Frequency over Time, 2 dBm Input, Uncorrected for Board Loss, and Measurement Band Limited by the Trace Bandwidth Rev. C | Page 12 of 23 Data Sheet HMC6832 500 0 LVPECL, 150 450 350 OUTPUT POWER (dBm) OUTPUT CURRENT (mA) LVPECL, 86 -5 400 86 300 250 200 150 150 LVDS, 100 -10 -15 -20 100 0 2 1 3 5 4 6 7 8 LOADED BANKS Figure 10. 3.3 V Current Consumption vs. Loaded Banks for Given LVPECL RTERM Values -7 -2 Figure 13. 1.25 GHz Fundamental Differential Output Power vs. Differential Input Power, Uncorrected for Impedance Mismatch 350 1 300 0 250 -12 -17 INPUT POWER (dBm) OUTPUT TRACE LOSS (dB) 86 200 150 150 100 -1 -2 -3 BOARD LOSS 200 TERMINATION 150 TERMINATION 86 TERMINATION -4 -5 50 0 1 2 3 4 5 LOADED BANKS 6 7 8 -6 10M 13201-011 0 Figure 11. 2.5 V Current Consumption vs. Loaded Banks for Given LVPECL RTERM Values 100M 1G 10G CARRIER FREQUENCY (Hz) 13201-014 OUTPUT CURRENT (mA) -25 -22 13201-010 0 13201-013 50 Figure 14. LVPECL Evaluation Board Output Trace Loss and Distortion from Impedance Mismatch vs. Carrier Frequency 5 10 4 5 OUTPUT POWER (dBm) RELATIVE DELAY (ps) 3 2 1 0 -1 -2 -40C +25C +85C 0 -5 -10 -3 -15 0 1 2 3 4 OUTPUT CHANNEL 5 6 7 -20 10M 13201-012 -5 100M 1G CARRIER FREQUENCY (Hz) Figure 12. Skew of Outputs Relative to Average Delay, Characterized at 1.25 GHz; Effects of Customer Evaluation Board Skew and Loss Are De-Embedded 10G 13201-015 -4 Figure 15. LVPECL 2.5 V Differential Output Power vs. Carrier Frequency for Various Temperatures, 0 dBm Input, Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss Rev. C | Page 13 of 23 HMC6832 Data Sheet 10 35 30 25 20 -40C +25C +85C 0 GAIN (dB) OUTPUT POWER (dBm) 5 -5 -10 15 10 5 0 -16dBm -10dBm -4dBm 0dBm +2dBm -5 -15 +8dBm 100M 1G 10G CARRIER FREQUENCY (Hz) Figure 16. LVPECL 3.3 V Differential Output Power vs. Carrier Frequency for Various Temperatures, 0 dBm Input, Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss 10 5 5 2.375V 2.500V 2.625V 3.000V 3.300V 3.600V -5 -10 10G 2.375V 2.500V 2.625V 0 -5 -10 1G 10G CARRIER FREQUENCY (Hz) -20 10M 13201-019 100M Figure 17. LVPECL Differential Output Power vs. Carrier Frequency for Various Supplies, 0 dBm Input, Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss 100M 1G 10G CARRIER FREQUENCY (Hz) 13201-024 -15 -15 -20 10M 1G Figure 19. LVPECL 2.5 V, 150 Differential Gain vs. Carrier Frequency for Various Input Powers, Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss 10 0 100M CARRIER FREQUENCY (Hz) OUTPUT POWER (dBm) OUTPUT POWER (dBm) -15 10M 13201-017 -20 10M 13201-023 -10 Figure 20. LVDS Differential Output Power vs. Carrier Frequency for Various Supplies, 0 dBm Input, Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss 30 10 25 0 20 15 2.5V, 200 2.5V, 150 2.5V, 86 GAIN (dB) -5 -10 10 -16dBm -10dBm 5 -4dBm 0 0dBm -5 +2dBm -10 -15 -15 100M 1G CARRIER FREQUENCY (Hz) 10G -20 10M 13201-021 -20 10M Figure 18. LVPECL Differential Output Power vs. Carrier Frequency for Various Terminations, 0 dBm Input, Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss +8dBm 100M 1G CARRIER FREQUENCY (Hz) 10G 13201-026 OUTPUT POWER (dBm) 5 Figure 21. LVDS Differential Gain vs. Carrier Frequency for Various Input Powers with 100 , Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss Rev. C | Page 14 of 23 Data Sheet HMC6832 -154 -100 -156 PHASE NOISE FLOOR (dBc/Hz) -90 -120 -130 -140 HMC830 SINGLE-ENDED DIFFERENTIAL -150 -160 -160 -162 -164 -166 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M -170 13201-027 -180 Figure 22. Phase Noise Performance at 2 GHz, 2.5 V Supply, HMC830 Used as Signal Source; Driving 9 dBm Single-Ended Through Balun 0 4 6 8 10 12 14 16 SLEW RATE (V/ns) Figure 25. Phase Noise Floor vs. Slew Rate for Carrier Frequencies and Output Configurations, LVPECL RTERM = 150 ; LVDS RTERM = 100 -157 -90 -158 PHASE NOISE FLOOR (dBc/Hz) -100 -110 REFERENCE PHASE NOISE REFERENCE + HMC6832 PHASE NOISE -120 -130 -140 -150 -159 -160 -161 LVPECL -162 LVDS -163 -164 -165 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) -166 -15 13201-123 -160 -10 -5 0 5 10 15 INPUT POWER (dBm) Figure 23. Phase Noise Performance at 2 GHz, Agilent E8257D (UNY Option) Used as Signal Source, 0 dBm Single-Ended Input Signal, Single-Ended Output, Depicts Residual Phase Noise Much Better than Reference Source Figure 26. Phase Noise Floor at 1.6 GHz vs. Input Power, LVPECL RTERM = 150 ; LVDS RTERM = 100 -120 -242 -125 -244 -130 -246 -135 -248 -140 FOM (dBc/Hz) ADDITIVE PHASE NOISE (dBc/Hz) 2 13201-028 -168 -170 PHASE NOISE (dBc/Hz) -158 13201-029 PHASE NOISE (dBc/Hz) -110 3000MHz LVPECL 3000MHz LVDS 2000MHz LVPECL 2000MHz LVDS 1000MHz LVPECL 1000MHz LVDS 100MHz LVPECL 100MHz LVDS -145 -150 SINGLE-ENDED LVPECL -155 -250 -252 -254 -160 LVPECL DIFFERENTIAL LVDS -165 -256 -170 LVDS -258 100 1k 10k 100k FREQUENCY OFFSET (Hz) 1M -260 13201-124 -180 Figure 24. Additive Phase Noise at 2 GHz, 0 dBm Single-Ended Input Signal, Differential LVDS Output and Single-Ended LVPECL Output 0 500 1000 1500 2000 2500 SINUSOIDAL INPUT FREQUENCY (MHz) 3000 13201-030 -175 Figure 27. Phase Noise Performance with Low Frequency Sinusoidal Inputs, Input Power = 10 dBm Single-Ended, LVPECL RTERM = 150 ; LVDS RTERM = 100 , Phase Noise Floor (dBc/Hz) = Figure of Merit (FOM) (dBc/Hz)) + 10 log(fOUT (Hz)) Rev. C | Page 15 of 23 HMC6832 Data Sheet -160 0 DIFFERENTIAL, 2.5V SINGLE-ENDED, 2.5V DIFFERENTIAL, 3.3V SINGLE-ENDED, 3.3V -161 -162 -10 -163 -164 S11 (dB) PHASE NOISE FLOOR (dBc/Hz) -5 LVDS -165 LVPECL -15 -20 -166 -167 -25 -168 -30 -35 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 SUPPLY VOLTAGE (V) 13201-031 -170 2.2 Figure 28. Phase Noise Floor vs. Supply Voltage for LVPECL and LVDS, LVPECL RTERM = 150 ; LVDS RTERM = 100 4 6 8 10 Figure 31. LVDS/LVPECL S Parameters (S11), Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss -30 -161 DIFFERENTIAL, 2.5V SINGLE-ENDED, 2.5V DIFFERENTIAL, 3.3V SINGLE-ENDED, 3.3V -40 -162 -50 -163 3GHz -60 -164 S12 (dB) -165 2GHz -166 -70 -80 1GHz -167 -90 -168 -100 -169 -110 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 13201-032 -170 -60 Figure 29. LVPECL 2.5 V, 150 , Phase Noise Floor vs. Temperature for Various Carrier Frequencies 0 2 4 6 8 10 FREQUENCY (GHz) 13201-035 PHASE NOISE FLOOR (dBc/Hz) 2 FREQUENCY (GHz) -160 Figure 32. LVPECL S Parameters (S12), Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss -160 -30 -161 -40 -162 -50 -163 3GHz SINGLE-ENDED, 2.5V -60 -164 S12 (dB) PHASE NOISE FLOOR (dBc/Hz) 0 13201-034 -169 2GHz -165 -166 -70 DIFFERENTIAL, 2.5V -80 -167 -90 1GHz -168 -100 -110 -40 -20 0 20 40 TEMPERATURE (C) 60 80 100 13201-033 -170 -60 Figure 30. LVDS Phase Noise Floor vs. Temperature for Various Carrier Frequencies 0 2 4 6 FREQUENCY (GHz) 8 10 13201-036 -169 Figure 33. LVDS S Parameters (S12), Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss Rev. C | Page 16 of 23 Data Sheet HMC6832 400 0 350 86 +85C +25C -40C SUPPLY CURRENT (mA) -5 S22 (dB) -10 -15 DIFFERENTIAL, 2.5V SINGLE-ENDED, 2.5V DIFFERENTIAL, 3.3V SINGLE-ENDED, 3.3V -20 300 150 250 200 200 150 100 -25 50 4 6 8 10 FREQUENCY (GHz) 0 2.3 13201-037 2 0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 SUPPLY VOLTAGE (V) Figure 34. LVPECL S Parameters (S22), Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss 13201-040 CORE -30 Figure 37. LVPECL Supply Current vs. Supply Voltage for Various Temperatures and RTERM Values 140 0 136 -5 132 SUPPLY CURRENT (mA) DIFFERENTIAL, 2.5V S22 (dB) -10 -15 SINGLE-ENDED, 2.5V -20 128 124 120 116 -40C +25C +85C 112 108 -25 0 2 4 6 8 10 FREQUENCY (GHz) 100 2.30 13201-038 -30 Figure 35. LVDS S Parameters (S22), Network Analyzer Gating Used to Remove Input and Output Impedance Mismatch and Board Loss OUTPUT POWER (dBm) +85C +25C -40C 1.5 NO LOAD 1.4 1.3 1.2 600 2.7 2.9 3.1 SUPPLY VOLTAGE (V) 3.3 3.5 3.7 13201-039 1.1 2.5 2.45 2.50 2.55 2.60 2.65 2.70 Figure 38. LVDS Supply Current vs. Supply Voltage for Various Temperatures 1.7 1.0 2.3 2.40 SUPPLY VOLTAGE (V) 1.8 1.6 2.35 13201-041 104 Figure 36. VAC_REF Output Power vs. Supply Voltage for Various Temperatures and Current Loads; 600 Signifies 2 mA Output Load Rev. C | Page 17 of 23 HMC6832 Data Sheet TEST CIRCUITS VDD = 2.5V/3.3V HIGH IMPEDANCE PROBE SOURCE GENERATOR HIGH-Z + HMC6832 HIGH-Z - 86/150 50 86/150 13201-042 50 Figure 39. Test Circuit for DC LVPECL Measurements, 86 Termination Used for VDD = 2.5 V; 150 Termination Used for VDD = 3.3 V VDD = 2.5V SOURCE GENERATOR HIGH IMPEDANCE PROBE + HIGH-Z 100 HMC6832 - HIGH-Z 50 13201-043 50 Figure 40. Test Circuit for DC LVDS Measurements VDD = 2.5V/3.3V SOURCE GENERATOR DC BLOCKING CAPACITORS OSCILLOSCOPE + HMC6832 50 86/150 50 86/150 50 50 13201-044 - Figure 41. Test Circuit for Transient (AC) LVPECL Measurements, 86 Termination Used for VDD = 2.5 V; 150 Termination Used for VDD = 3.3 V VDD = 2.5V SOURCE GENERATOR DC BLOCKING CAPACITORS OSCILLOSCOPE + 100 HMC6832 50 50 50 50 13201-045 - Figure 42. Test Circuit for Transient (AC) LVDS Measurements VDD = 2.5V SATURATED AMPLIFIER DC BLOCKING CAPACITORS HMC6832 SSA BALUN 50 50 150 150 13201-046 50 Figure 43. Test Circuit for Phase Noise LVPECL Measurements VDD = 2.5V DC BLOCKING CAPACITORS HMC6832 100 SATURATED AMPLIFIER SSA BALUN 50 50 13201-047 50 Figure 44. Test Circuit for Phase Noise LVDS Measurements Rev. C | Page 18 of 23 Data Sheet HMC6832 THEORY OF OPERATION INPUT STAGE LVPECL OUTPUT STAGE The input stage shown in Figure 45 is flexible. It can be driven single-ended or differential with LVPECL, LVDS, or CML signals. If driven single-ended, place a large ac-coupled capacitor between the undriven input and a nearby GND pin. There are pull-up and pull-down resistors on each single-ended input to set the nominal dc voltage to VDD/2. The input is selectable by the input select pin (IN_SEL), a digital pin that can be set to either GND (INx0) or VDD (INx1). To select the output termination, use the configuration pin (CONFIG), a digital pin that can be set to either GND (LVPECL) or to VDD (LVDS). When left floating, the CONFIG pin is internally pulled to VDD (LVDS). The LVPECL output driver produces up to 0.8 V p-p differential swing into 100 differential loads. LVPECL drivers are terminated with off-chip resistors that provide the dc current through the emitter-follower output stage. If unused, LVPECL outputs can be left floating. VAC_REF is an output reference voltage capable of sourcing 2 mA at 1.25 V. VDD 50k IN_SEL HIGH: IN1 LOW: IN0 INP1 50k 100pF VDD 100pF 50k INN1 50k VDD 50k INP0 50k 100pF VDD 100pF 50k INN0 50k VDD CONFIGURATION CONTROL Figure 45. Input Stage Block Diagram Rev. C | Page 19 of 23 LVDS LVPECL 13201-048 100k CONFIG HIGH: LVDS LOW: LVPECL HMC6832 Data Sheet OUTP7 OUTN7 LVDS OUTP6 OUTN6 OUTN5 4mA 4mA 4mA LVDS OUTP4 OUTN4 4mA LVDS OUTP5 4mA 4mA LVDS 4mA 4mA OUTP3 OUTN3 LVDS OUTP2 OUTN2 OUTP1 OUTN1 4mA 4mA 4mA LVDS OUTP0 OUTN0 4mA LVDS 4mA 4mA LVDS 4mA VAC_REF 2mA 13201-049 4mA Figure 46. Output Stage Block Diagram A number of choices are available for connecting the LVPECL drivers and receivers. There are compromises between matching performance, common-mode levels, and signal swing. For clocking applications, the user often has the option of using ac coupling, unlike in many datapath situations. Figure 47 shows a simplified interface schematic between an LVPECL output and an input stage, where various options and trade-offs for the termination components are provided (see Table 11). The Analog Devices, Inc., evaluation board has a great deal of flexibility in how the inputs/outputs are configured. Several configurations are shown in the Applications Information section. Table 11. Interface Values Interface Value Load Resistor (RL) 150 200 300 Open VDD = 2.5V/3.3V OUTP RL AC-Coupled Capacitor (CAC) Large Capacitor CAC HMC6832 LVPECL RL 13201-050 CAC OUTN Figure 47. Recommended Interface Diagram Rev. C | Page 20 of 23 Description DC current termination for LVPECL output stage Analog Devices evaluation board default, standard LVPECL termination voltages Reduced current, no performance degradation Further reduced current, lower output power but flatter frequency response If using internal dc termination network at the receiver Analog Devices evaluation board default, when ac coupling is used Data Sheet HMC6832 APPLICATIONS INFORMATION The series resistance (RSERIES) provides impedance matching and signal attenuation. The RSERIES value is the difference between the LVCMOS driver output impedance and the transmission line impedance. Position RSERIES near the LVCMOS driver. VDD = 2.5V OR 3.3V Figure 51 and Figure 52 illustrate the common output interface configurations. VDD = 2.5V OR 3.3V HMC6832 LVPECL 86/150 86/150 13201-054 Figure 48 to Figure 50 illustrate the common input interface configurations. Figure 48 shows how to interface a LVCMOS input to the HMC6832. A capacitor is needed between the LVCMOS driver and the HMC6832 to ac couple the input. In addition, add a capacitor between the inverted input of the HMC6832 and a nearby GND pin to reduce noise in the system. Figure 51. LVPECL Output DC Termination Interface (86 Termination Can Be Used at 2.5 V Only) VDD = 2.5V OR 3.3V RSERIES DC BLOCKING CAPACITORS DC BLOCKING CAPACITORS LVCMOS HMC6832 LVPECL 86/150 86/150 13201-055 13201-051 HMC6832 Figure 48. LVCMOS AC-Coupled Input Interface Figure 52. LVPECL Output AC Termination Interface (86 Termination Can Be Used at 2.5 V Only) VDD = 2.5V RECOMMENDED SOLDER REFLOW PROFILE The typical Pb-free reflow solder profile shown in Figure 53 is based on JEDEC J-STD-20C. HMC6832 60 SECONDS TO 150 SECONDS RAMP UP 3C/SECOND MAX Figure 49. LVDS DC-Coupled Input Interface VDD = 2.5V OR 3.3V 260C -5C/+0C 217C DC BLOCKING CAPACITORS Figure 50. Differential Input AC-Coupled Interface TEMPERATURE (C) 150C TO 200C HMC6832 13201-053 DIFFERENTIAL RAMP DOWN 6C/SECOND MAX TIME (Seconds) 60 SECONDS TO 180 SECONDS 20 SECONDS TO 40 SECONDS 480 SECONDS MAX Figure 53. LFCSP Pb-Free Reflow Profile Rev. C | Page 21 of 23 13201-100 100 13201-052 LVDS HMC6832 Data Sheet EVALUATION PRINTED CIRCUIT BOARD (PCB) 13201-101 An easy to use evaluation PCB is available from Analog Devices upon request. Top and bottom view layouts of the evaluation board are given in Figure 54 and Figure 55. For the circuit board in this application, use RF circuit design techniques. Ensure that signal lines have 50 impedance. Connect the package ground leads and exposed paddle directly to the ground plane similarly to that shown in Figure 54 (top view) and Figure 55 (bottom view). Use a sufficient number of via holes to connect the top and bottom ground planes. 13201-102 Figure 54. Evaluation PCB (Top View) Figure 55. Evaluation PCB (Bottom View) Rev. C | Page 22 of 23 Data Sheet HMC6832 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) PIN 1 INDICATOR 0.30 0.25 0.18 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 28 22 1 21 0.50 BSC 3.25 3.15 SQ 3.05 EXPOSED PAD 15 0.65 0.55 0.45 TOP VIEW 0.90 0.85 0.80 SIDE VIEW 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PKG-005229 7 14 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-1. 11-29-2017-B 5.10 5.00 SQ 4.90 Figure 56. 28-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.85 mm Package Height (HCP-28-1) Dimensions shown in millimeters ORDERING GUIDE Model1 HMC6832ALP5LE HMC6832ALP5LETR EV1HMC6832ALP5L EV2HMC6832ALP5L 1 2 Temperature Range -40C to +85C -40C to +85C MSL Rating2 MSL3 MSL3 Package Description 28-Lead Lead Frame Chip Scale Package [LFCSP] 28-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board (LVPECL Configuration) Evaluation Board (LVDS Configuration) Package Option HCP-28-1 HCP-28-1 All models are RoHS Compliant Parts. The maximum peak reflow temperature is 260C for the HMC6832ALP5LE and HMC6832ALP5LETR. See the Absolute Maximum Ratings section, Table 8. (c)2016-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13201-0-1/18(C) Rev. C | Page 23 of 23