ATmega162U - Atmel Corporation - Datasheet.Directory

2513H–AVR–04/06

Features

•High-perf ormance, Lo w-p ower AVR® 8-bit Microcontroller

•Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

•Non-volatile Program and Data Memories

– 16K Bytes of In-System Self-programmable Flash

Endurance: 10,000 Wr ite/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K Bytes Internal SRAM

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

•JTAG (IEEE std. 1149 .1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two 16-bit Timer/Counters with Separate Prescalers, Compare Modes, and

Capture Modes

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separ ate On-chip Oscillator

– On-chip Analog Comparator

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interru pt Sou rces

– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby

•I/O and Packages

– 35 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF

•Operating Voltages

– 1.8 - 5.5V for ATmega162V

– 2.7 - 5.5V for ATmega162

•Speed Grades

– 0 - 8 MHz for ATmega162V (see Figure 113 on page 268)

– 0 - 16 MHz for ATmega162 (see Figure 114 on page 268)

8-bit

Microcontroller

with 16K Bytes

In-System

Programmable

Flash

ATmega162

ATmega162V

ATmega162/V

2513H–AVR–04/06

Pin Configurations Figure 1. Pinout ATmega162

Disclaimer Typical values contained in this datasheet are based on simulations and characteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min

and Max values will be available after the device is characterized.

(OC0/T0) PB0

(OC2/T1) PB1

(RXD1/AIN0) PB2

(TXD1/AIN1) PB3

(SS/OC3B) PB4

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

(RXD0) PD0

(TXD0) PD1

(INT0/XCK1) PD2

(INT1/ICP3) PD3

(TOSC1/XCK0/OC3A) PD4

(OC1A/TOSC2) PD5

(WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

VCC

PA0 (AD0/PCINT0)

PA1 (AD1/PCINT1)

PA2 (AD2/PCINT2)

PA3 (AD3/PCINT3)

PA4 (AD4/PCINT4)

PA5 (AD5/PCINT5)

PA6 (AD6/PCINT6)

PA7 (AD7/PCINT7)

PE0 (ICP1/INT2)

PE1 (ALE)

PE2 (OC1B)

PC7 (A15/TDI/PCINT15)

PC6 (A14/TDO/PCINT14)

PC5 (A13/TMS/PCINT13)

PC4 (A12/TCK/PCINT12)

PC3 (A11/PCINT11)

PC2 (A10/PCINT10)

PC1 (A9/PCINT9)

PC0 (A8/PCINT8)

PA4 (AD4/PCINT4)

PA5 (AD5/PCINT5)

PA6 (AD6/PCINT6)

PA7 (AD7/PCINT7)

PE0 (ICP1/INT2)

GND

PE1 (ALE)

PE2 (OC1B)

PC7 (A15/TDI/PCINT15)

PC6 (A14/TDO/PCINT14)

PC5 (A13/TMS/PCINT13)

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

(RXD0) PD0

VCC

(TXD0) PD1

(INT0/XCK1) PD2

(INT1/ICP3) PD3

(TOSC1/XCK0/OC3A) PD4

(OC1A/TOSC2) PD5

(WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

VCC

(A8/PCINT8) PC0

(A9/PCINT9) PC1

(A10/PCINT10) PC2

(A11/PCINT11) PC3

(TCK/A12/PCINT12) PC4

PB4 (SS/OC3B)

PB3 (TXD1/AIN1)

PB2 (RXD1/AIN0)

PB1 (OC2/T1)

PB0 (OC0/T0)

GND

VCC

PA0 (AD0/PCINT0)

PA1 (AD1/PCINT1)

PA2 (AD2/PCINT2)

PA3 (AD3/PCINT3)

PDIP

12 14 16 18 20 22

13 15 17 19 21

44 42 40 38 36 34

43 41 39 37 35

TQFP/MLF

NOTE:

MLF bottom pad should

be soldered to ground.

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Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle,

the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the sys-

tem designer to optimize power consumption versus processin g speed.

Block Diagram Figure 2. Block Diagram

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

OSCILLATOR

TIMERS/

COUNTERS

INTERRUPT

UNIT

STACK

POINTER

EEPROM

SRAM

STATUS

USART0

PROGRAM

COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

PROGRAMMING

LOGIC

SPI

COMP.

INTERFACE

PORTA DRIVERS/BUFFERS

PORTA DIGITAL INTERFACE

GENERAL

PURPOSE

REGISTERS

ALU

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

PORTB DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

XTAL1

XTAL2

RESET

CONTROL

LINES

GND

PA0 - PA7 PC0 - PC7

PD0 - PD7PB0 - PB7

AVR CPU

INTERNAL

CALIBRATED

OSCILLATOR

PORTE

DRIVERS/

BUFFERS

PORTE

DIGITAL

INTERFACE

PE0 - PE2

USART1

ATmega162/V

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The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting ar chitectu re is more code efficient wh ile achieving th roughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega162 provides t he following featur es: 16K bytes of In-System Pro grammable

Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, an

external memory interface, 35 gen eral purpose I/O lines, 32 general purpose working

registers, a JTAG interface for Bou ndary-scan, On-chip Debugging sup port and pro-

gramming, four flexible Timer/Counters with compare modes, internal and external

interrupts, two serial programmable USARTs, a programmable Watchdog Timer with

Internal Oscillator, an SPI serial port, and five software selectable power saving modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and

interrupt system to continue functioning. The Power-down mode saves the register con-

tents but freezes the Oscillator, disabling all other chip functions until the next interrupt

or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,

allowing the user to maintain a timer base while the rest of the device is sleeping. In

Standby mode, the crystal/resonator Oscillator is running whil e the rest of the device is

sleeping. This allows very fast start-up combined with low-power consumption. In

Extended Standby mode, both the main Oscillator and the Asynchronous Timer con-

tinue to run.

The device is manufactured u sing At mel’s hig h de nsity no n- vo latile m emo ry te chno logy.

The On-chip ISP Flash allows th e program memory to be reprogrammed In-System

through an SPI serial interface, by a conventional non-volatile memory programmer, or

by an On-chip Boot Program running on the AVR core. The Boot Program can use any

interface to download the Ap plication Program in the Application F lash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is

updated, providing true R ead-While-Write operation. By combining an 8-b it RISC CPU

with In-System Self- Pro gr amm able Fl ash on a monolit hic chip, th e Atmel ATmeg a16 2 is

a powerful microcontroller that pr ovides a highly flexible and cost effective solution to

many embedded control applications.

The ATmega162 AVR is sup port ed with a fu ll suite of pr ogra m a nd system d evelo pment

tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-

cuit Emulators, and evaluation kits.

ATmega161 and

ATmega162

Compatibility

The ATmega162 is a highly complex microcontroller where the number of I/O locations

supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure back-

ward compatibility with the ATmega161, all I/O locations present in ATmega161 have

the same locations in ATmega162. Some additional I/O locations are added in an

Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM

space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD

instructions only, not by using IN and OUT instructions. The relocation of the internal

RAM space may still be a problem for ATmega161 users. Also, the increased number of

Interrupt Vectors might be a problem if the code uses absolute addresses. To solve

these proble ms, an ATmega161 comp atibility mode can be sele cted by programming

the fuse M161C. In this m ode, none of the functio ns in the Extended I/O space are in

use, so the intern al RAM is located as in ATmeg a161. Also, t he Ext e nded I nter r upt Vec-

tors are removed. Th e ATmega162 is 100% pin compatib le with ATmega161, and can

replace the ATmega161 on current Printed Circuit Boards. However, the location of

Fuse bits and the electrical characteristics differs between the two devices.

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ATmega161 Compatibility

Mode Programming the M161C will change the following functionality:

• The e xtended I/O map will be configured as internal RAM once the M161C Fuse is

programmed.

• The timed sequence for changing the Watchdog Time-out period is disabled. See

“Timed Sequence s for Cha nging the Co nfiguration of th e Watch dog Timer” on page

57 for details.

• The double buffering of the USART Receive Registers is disabled. See “AVR

USART vs. AVR UART – Compatibility” on page 170 for details.

• Pin change interrupts are not supported (Control Registers are located in Extended

I/O).

• One 16 bits Timer/ Counter ( Timer/C ounter1 ) only. Timer/Counter3 is n ot accessible.

Note that the shared UBRRHI Register in ATmega161 is split into two separate registers

in ATmega162, UBRR0H and UBRR1H. The location of these registers will not be

affected by the ATmega161 compatibility fuse.

Pin Descriptions

VCC Digital supply voltage

GND Ground

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A outp ut buf f ers have symmetr ical drive chara cter istics with both high sink

and source capability. When pins PA0 to PA7 are used as inputs and are externally

pulled low, they will source current if the internal pull-up resistors are activated. The Port

A pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Port A also ser ves the funct ions of var ious special features of the ATmega162 as listed

on page 73.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B outp ut buf f ers have symmetr ical drive chara cter istics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also ser ves the funct ions of var ious special features of the ATmega162 as listed

on page 73.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C outp ut buff er s have symmet rica l dr ive cha racte ristics wit h bot h hi gh sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes act ive, even if the clock is not r unning. If the JTAG interface is

enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be acti-

vated even if a Reset occurs.

Port C also serves the functions of the JTAG interface and other special features of the

ATmega162 as listed on page 76.

ATmega162/V

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Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D outp ut buff er s have symmet rica l dr ive cha racte ristics wit h bot h hi gh sink

and source capability. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega162 as listed

on page 79.

Port E(PE2..PE0) Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port E outp ut buf f ers have symmetr ical drive chara cter istics with both high sink

and source capability. As inputs, Port E pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port E also ser ves the funct ions of var ious special features of the ATmega162 as listed

on page 82.

RESET Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a Reset, even if t h e clock is not ru nning. The minim um pulse le ngth is give n in T able

18 on page 49. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the Inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the Inverting Oscillator amplifier.

ATmega162/V

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Resources A comprehens ive set of develo pment tools, ap plication notes and datashee ts are avail-

able for download on http://www.atmel.com/avr.

ATmega162/V

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About Code

Examples This documentation con tains simple code examples t hat briefly show how to use various

parts of the device. These code examples assume that the part specific header file is

included before compilat ion. Be aw are that n ot all C comp iler vend ors include bit defini-

tions in the header files and interrupt handling in C is compiler dependent. Please

confirm with the C compiler documentation for more details.

ATmega162/V

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AVR CPU Core

Introduction This section discusses the AVR core architecture in general. The main function of the

CPU core is to ensure correct program execution. The CPU must therefore be able to

access memories, perform calculat ions, control peripherals, and handle interrupts.

Architectural Overview Figure 3. Block Diagram of the AVR Archit ect ur e

In order to maximize per for man ce and parallelism, the AVR uses a Harvard archit ecture

– with separate memories and buses for program and data. Instructions in the program

memory are executed with a single level pipelining. While one instruction is being exe-

cuted, the next instruction is pre-fetched from the program memory. This concept

enables instructions to be executed in every clock cycle. The program memory is In-

System Reprog ra m m ab le Fla sh me mo r y.

The fast-access Register File contains 32 x 8-bit general purpose working registers with

a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)

operation. In a typical ALU operation, two operands are output from the Register File,

the operation is executed, and the result is stored back in the Register File – in one

clock cycle.

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

ATmega162/V

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Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing – enabling efficient address calculations. One of the these

address pointers can also be used as an addres s poin ter fo r look u p tables in F lash Pro-

gram memory. These added function registers are the 16-bit X-, Y-, and Z-re gister,

described later in this section.

The ALU supports arithmetic and logic operations between registers or between a con-

stant and a register. Single register operations can also be executed in the ALU. After

an arithmetic operation, the Status Register is updated to reflect information about the

result of the ope ratio n.

Program flow is provided by conditional and unconditional jump and call instructions,

able to directly address the whole address space. Most AVR instructions have a single

16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and

the Application Program section. Both sections have dedicated Lock bits for write and

read/write pro tec tio n. The SPM inst ru ction th at wr ite s into th e Applica tion Flash me mor y

section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the Stack. The Stack is effectively allocated in the general data SRAM, and

consequently the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O

space. The data SRAM can easily be accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architectur e are all linear and regular memory maps.

A flexible interrupt modu le has its control registers in the I/O space with an additional

Global Interrupt Enable bit in the Status Register . All interrupts have a sepa rate Interrupt

Vector in the Interrupt Vector table. The interrupts have priority in accordance with their

Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 ad dresses for CPU peripheral functions as Control

Registers, SPI, and o ther I/O fu nctions. Th e I /O memory can be accesse d directly, or as

the Data Space locations following those of the Register File, 0x20 - 0x5F .

ALU – Arithmetic Logic

Unit The high-perfo rmance AVR ALU operates in di rect connection with all th e 32 general

purpose workin g registers. Within a single clock cycle, arithme tic operations between

general purpose registe rs or between a register and an immediate are executed. The

ALU operations are divided int o thre e main cate gor ies – ar ithmet ic, logical, and bi t-f unc-

tions. Some implementations of the architecture also provide a powerful multiplier

supporting both signed/unsigned multiplication and fractional format. See the “Instruc-

tion Set” section for a det ailed description.

Status Register The Status Register contains information about the result of the most recently executed

arithmetic instruction. This information can be used for altering program flow in order to

perform conditional opera tions. Note that the Status Register is updated after all ALU

operations, as specified in the Instruction Set Reference. This will in many cases

remove the need for using the de dicated compare instructions, resulting in faster an d

more compact code.

The Status Register is not automatically stored when entering an interrupt routine and

restored when returning from an interrupt. This must be handled by sof tware.

ATmega162/V

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The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Globa l Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ-

ual interrupt enable control is then performed in separate control registers. If the Global

Interrupt Enable Register is cleared, none of th e interrupts are enabled independent of

the individual interrupt ena ble settings. The I- bit is cleared by hardware aft er an interrupt

has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-

bit can also be set an d cleared by the application with the SEI and CLI instru ctions, as

described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instru ctions BL D (Bit LoaD) an d BST (Bit STo re) u se the T b it as so urce or

destination for the operated bit. A bit from a registe r in the Register File can be copied

into T by the BST instru ction, and a bit in T can be copied into a bit in a register in the

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a half carry in some arithmetic operations. Half Carry is

useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between th e Negative Flag N and the Two’s Comple-

ment Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V sup ports two’s complement arithmetics. See

the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See

the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 0 – C: Ca rry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-

tion Set Description” for detailed information.

Bit 76543210

I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

ATmega162/V

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General Purpose

achieve the required performance and flexibility, the following input/output schemes are

supported by the Register File:

• One 8-bit output op erand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8- bit outp u t op erand s an d on e 16 -b it re su lt inpu t

• One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Work ing Registers

Most of the in structions op erating on the Registe r File have d irect access to all re gisters,

and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping

them directly int o the fir st 3 2 loca t ions o f the user Dat a Space. Althou gh not b eing phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to

index any register in the file.

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-regist er Low Byte

R31 0x1F Z-re gi ster High Byte

ATmega162/V

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The X-register, Y-register, and

Z-register The registers R26..R31 have some added functions to their general purpose usage.

These registers are 16-bit address pointers for indirect addressing of the Data Space.

The three indirect address registers X, Y, and Z are de fined as described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed dis-

placement, automatic increment, and automatic decrement (see the instruction set

reference for details).

Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for

storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis-

ter always points to the to p of the Sta ck. Note that the Stack is imple mente d as growin g

from higher memory locations to lower memory locations. This implies that a Stack

PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-

rupt Stacks are loc ated. This Stack space in th e data SRAM must be defined b y the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above 0x60. The Stack Pointer is decremented by one

when data is pushed ont o the Stac k with the PUSH inst ruct ion, and it is decrement ed by

two when the return address is pushed onto the Stack with subroutine call or interrupt.

The Stack Pointer is incremented by one when data is popped from the Stack with the

POP instruction, and it is incremented by two when data is popped from the Stack with

return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implem ented as two 8- bit re gisters in the I/O space. The n um-

ber of bits actually used is implemen tatio n depen den t . Note th at the data space in some

implementations of the AVR architecture is so small that only SPL is needed. In this

case, the SPH Register will not be present.

15 XH XL 0

X - register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y - register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z - register 7 0 7 0

R31 (0x1F) R30 (0x1E)

Bit 151413121110 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

00000000

ATmega162/V

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Instruction Execution

Timing This section describes the g enera l access timing con cepts for instr uction execut ion. The

AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock

source for the chip. No internal clock division is used.

Figure 6 shows the pa rallel instru ction fetches an d instructio n executions enabled b y the

Harvard archit ecture an d the f ast-access Register File co ncept. Th is is the basic pipelin-

ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 7. Single Cycle ALU Operation

Reset and Interrupt

Handling The AVR provides several differ en t in terr up t sou rces. These in te rrupt s and the sepa ra te

Reset Vector ea ch have a separate program vector in the program memor y space. All

interrupts are assigned individual enable bits which must be written logic one together

with the Global Interrupt En able bit in the Status Re gister in order to enable the interrupt.

Depending on the Program Counter value, interrupts may be automatically disabled

when Boot Lock bits BLB02 or BLB12 ar e program med. Th is feature imp roves so ftware

security. See the section “Memory Programming” on page 233 fo r details.

The lowest addresses in the program memory sp ace are by default defined as th e Reset

and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 58.

The list also determines the priority levels of the different interrupts. The lower the

address the higher is the priority level. RESET has the highest priority, and next is INT0

– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of

the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register

(GICR). Refer to “Interrupts” on page 58 for more information. The Reset Vector can

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

egister Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

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also be moved to the start of the Boot Flash section by programming the BOOTRST

Fuse, see “Boot Loader Support – Read-While-Write Self-programming” on pa ge 219.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts

are disabled. The user software can write logic one to the I-bit to enable nested inter-

rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is

automatically set when a Return from Interrupt instruct ion – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that

sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the

actual Interrupt Vector in order to execute the interrupt handling routine, and hardware

clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a

logic one to th e flag bit posit ion(s) to be clear ed. If an inte rrupt condition occurs while the

corresponding interru pt enable bit is cleared, the Interrupt F lag will be set and remem-

bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or

more interrupt condit ions occu r wh ile t he g l obal int e rrupt e nable bit is clea red, t he co rr e-

sponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable

bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present.

These interrupts do not necessarily have Inte rrupt Flags. If the inte rrupt condition disap-

pears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and exe-

cute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine, nor restored when returning from an interrupt routine. This must be handled by

software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately

disabled. No interrupt will be executed after the CLI instru ction, even if it occurs simulta-

neously with the CLI instruction. The following example shows how this can be used to

avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

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When using the SEI instruction to enable interrupts, the instruction following SEI will be

executed before any pending interrupts, as shown in this example.

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles the program vector address for the actual interrupt

handling routine is executed . During th is four clock cycle period, th e Progra m Counter is

pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this

jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed befo re the interrupt is served. If an interrup t

occurs when the MCU is in sleep mode, the interrupt execution response time is

increased by four clock cycles. This incr ease comes in addition to the start-up time from

the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four

clock cycles, the Progra m Cou nter (two b ytes) is poppe d b ack fr om th e Stack, th e Stack

Pointer is incremented by two, and the I-bit in SREG is set.

Assembly Code Example

sei ; set global interrupt enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set global interrupt enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

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AVR ATmega162

Memories This section describes the different memories in the ATmega162. The AVR architecture

has two main memory spaces, the Data Memory and the Program Memory space. In

addition, the ATmega162 features an EEPROM Memory for data storage. All three

memory spaces are linear and regular.

In-System

Reprogrammable Flash

Program Memory

The ATmega162 contains 16K bytes On-chip In-System Reprogrammable Flash mem-

ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is

organized as 8K x 16. For software security, the Flash Program memory space is

divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega162 Program Cou nter (PC) is 13 bits wide, thus addressing the 8K program

memory locations. The operation of Boot Program section and associated Boot Lock

bits for software protection are described in detail in “Boot Loader Support – Read-

While-Write Self-programming” on page 219. “M emory Programming” on page 233 con-

tains a detailed des cription on Flash data serial down loading using the SPI pins or the

JTAG interface.

Constant tables can be allocated within the entire program memory address space (see

the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “In struction Execu-

tion Timing” on page 14.

Figure 8. Program Memory Map(1)

Note: 1. The address reflects word addresses.

0x0000

0x1FFF

Program Memory

Application Flash Section

Boot Flash Section

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SRAM Data Memory Figure 9 shows how the ATmega162 SRAM Memory is organized. Memory configura-

tion B refers to the ATmega161 compatibility mode, configuration A to the non-

compatible mode.

The ATmega162 is a complex microcontroller with more peripheral units than can be

supported within the 64 location reserve d in the Opcode for the I N and OUT instructions.

For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and

LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the

ATmega162 is in the ATmega161 compatibility mode.

In Normal mode, the first 1280 Data Memory locations address both the Register File,

the I/O Memory, Extended I/O Memory, and the internal data SRAM . The first 32 loca-

tions address the Register File, the next 64 location the standard I/O memory, then 160

locations of Extended I/O memory, and the next 1024 locations address the internal

data SRAM.

In ATmega161 compatibility mode, the lower 1120 Data Memory locations address the

address the Register File and I/O Memory, and the next 1024 locations address the

internal data SRA M.

An optional external data SRAM can be used with the ATmega162. This SRAM will

occupy an area in the remaining address locations in the 64K address space. This area

starts at the address following the internal SRAM. The Register File, I/O, Extended I/O

and Internal SRAM uses the occupies the lowest 1280 bytes in Normal mode, and the

lowest 1120 bytes in the ATmega161 compatibility mode (Extended I/O not present), so

when using 64KB (65,536 bytes) of External Memory, 64,256 Bytes of External Memory

are available in Normal mode, and 64,416 Bytes in ATmega161 compatibility mode. See

“External Memory Interface” on page 26 for details on how to take advantage of the

external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data

memory locations, the external data SRAM is accessed using the same instructions as

for the internal data memory access. When the internal data memories are accessed,

the read and write strobe pins (PD7 and PD6) are inactive during the whole access

cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR

Accessing external SRAM takes one a dditional clock cycle per byte compared to access

of the internal SRAM. This means that the comm ands LD, ST, LDS, STS, LDD, STD,

PUSH, and POP take one additional clock cycle. If the Stack is placed in external

SRAM, interrupts, subroutine calls and re turns take three clock cycles extra because the

2-byte Program Counter is pushed and popped, and external memory access does not

take advantage of the internal pipeline memory access. When external SRAM interface

is used with wait-state, one-byte external access takes two, three, or four additional

clock cycles for one, two, and three wait-states respectively. Interrupt, subroutine calls

and returns will need five, seven, or nine clock cycles more than specified in the instruc-

tion set manual for one, two, and three wait-states.

The five differen t addressing modes f or the data memor y cover: Direct, Indir ect with Dis-

placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In

the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base

address given by the Y- or Z-register.

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When using register indirect addressing modes with automa tic pre-decrement and post-

increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 (+160) I/O Registers, and the 1024 bytes

of internal da ta SRAM in the ATm ega162 are all accessible throug h all these a ddressing

modes. The Register File is described in “General Purpose Register File” on page 12.

Figure 9. Data Memory Map

Data Memory Access Times This section describes the general access timing concepts for internal memory access.

The internal dat a SRAM access is perfor med in two clk CPU cycles as described in Figure

10.

Figure 10. On-chip Data SRAM Access Cycles

32 Registers

64 I/O Registers

Internal SRAM

(1024 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x0460

0x045F

0xFFFF

0x0060

Data Memory

External SRAM

(0 - 64K x 8)

Memory configuration B

32 Registers

64 I/O Registers

Internal SRAM

(1024 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x04FF

0xFFFF

0x0060 - 0x00FF

Data Memory

External SRAM

(0 - 64K x 8)

Memory configuration A

160 Ext I/O Reg.

0x0100

0x0500

clk

Data

ddress Address valid

T1 T2 T3

Compute Address

Read Write

CPU

Memory Access Instruction Next Instruction

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EEPROM Data Memor y The ATmega162 contains 512 bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPRO M has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM

and the CPU is described in the following, specifying the EEPROM Address Registers,

the EEPROM Data Register, and the EEPROM Control Register.

“Memory Programming” on page 233 contains a detailed description on EEPROM Pro-

gramming in SPI, JTAG, or Parallel Programming mode.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A selftiming function, how-

ever, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In

heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up /down. This

causes the device for some period of time to run at a voltage lower than specified as

minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page

24 for details on how to avoid problems in these situations.

In order to prevent unin tentional EEPROM writes, a spe cific write proced ure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next

instruction is executed. When the EEPROM is written, the CPU is halted for two clock

cycles before th e ne xt ins tru ct ion is execu te d .

The EEPROM Address

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega162 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address

in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly

between 0 and 511. The initial va lue o f EEAR is un define d. A pr ope r va lue must b e writ-

ten before the EEPROM may be accessed.

Bit 151413121110 9 8

–––––––EEAR8EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/WriteRRRRRRRR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0000000X

XXXXXXXX

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The EEPROM Data Register –

EEDR

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR R egister contains the data to be written to

the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-

ation, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

The EEPROM Control Register

– EECR

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega162 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.

Writing EERIE to zero disab les t he in te rr upt. Th e EEPROM Rea dy inte rr up t gen er ates a

constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be

written. When EEMWE is set, setting EEWE within four clock cycles will write data to the

EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect.

When EEMWE has been written to on e by software, hard ware clears the bit to zero after

four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable signal EEWE is the write strobe to the EEPROM. When

address and data are correctly set up, the EEWE bit must be written to one to write the

value into the EEPROM. The EEMWE bit must be written to one before a logical one is

written to EEWE, otherwise no EEPROM write takes place. The following procedure

should be followed when writing the EEPROM (the order of steps 3 and 4 is not

essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programm ed during a CPU write to the Flash memory. The

software must check that the F lash programming is completed befor e initiating a new

EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing

the CPU to program the Flas h. If the Flash is never being updat ed by the CPU, step 2

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

––––EERIEEEMWEEEWEEEREEECR

Read/Write R R R R R/W R/W R/W R/W

Initial Value000000X0

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can be omitted. See “Boot Loader Support – Read-While-Write Self-programming” on

page 219 for details about boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be

modified, causing the interrupted EEPROM access to fail. It is recommended to have

the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elap sed, the EEWE bit is cleared by hardware. The

user software can poll this bit and wait for a zero before writing the next byte. When

EEWE has been set, the CPU is halted for two cycles before the next instruction is

executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the

correct address is set up in the EEAR Register, the EERE bit must be written to a logic

one to trigger the EEPROM read. The EEPROM read access takes one instruction, and

the requested data is available immediately. When the EEPROM is read, the CPU is

halted for four cycle s bef or e th e ne xt ins tru ct ion is executed.

The user should poll the EEWE bit bef ore star ting the read ope ration. I f a write operation

is in progress, it is neither possible to read the EEPROM, nor to change the EEAR

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical

programming time for EEPROM access from the CPU.

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings

Table 1. EEPROM Programming Time

Symbol Number of Calibrated RC

Oscillator Cycles(1) Typ Programming Time

EEPROM write (from CPU) 8448 8.5 ms

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The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g., by disabling inter-

rupts globally) so that no interrupts will occur during execution of these functions. The

examples also assume that no Flash Boot Loader is present in the software. If such

code is present, the EEPROM write function must also wait for any ongoing SPM com-

mand to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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The next code examples sh ow assemb ly and C functions for read ing t he EEPROM . The

examples assume that interrupts are controlled so that no interrupts will occur during

execution of these functi ons.

EEPROM Write During Power-

down Sleep Mode When entering Power-down sleep mode while an EEPROM write operation is active, the

EEPROM write operation will cont inue, and will complete before the write access time

has passed. However, when the write operation is complete, the Oscillator continues

running, and as a consequence, the device does not enter Power-down entirely. It is

therefore recommended to verify that the EEPROM write operation is completed before

entering Power-down.

Preventing EEPROM

Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply volt-

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board level systems using EEPROM, and the same design solutions should

be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequen ce to the EEPROM requires a minimum voltage to

operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the

supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design

recommendation:

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

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Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD). If the detection

level of the internal BOD does not match the needed detection level, an external low

VCC Reset Protection circuit can be used. If a Reset occurs while a write operation is in

progress, the write operation will be completed provided that the power supply voltage is

sufficient.

I/O Memory The I/O space definition of the ATmega162 is shown in “Register Summary” on page

306.

All ATmega162 I/Os and peripherals are placed in the I/O space. All I/O locations may

be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data

between the 32 general purpose working registers and the I/O sp ace. I/O Registers

within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI

instructions. In these registers, the value of single bits can be checked by using the

SBIS and SBIC instructions. Refer to the instruction set section for more details. When

using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be

used. When add ressing I/O Re gister s as dat a spac e using LD and ST instructions, 0x20

must be added to these addresses. Th e ATmega162 is a complex microcontroller with

more peripheral units than can be supported within the 64 location reserved in Opcode

for the IN an d OUT inst ruction s. F or the Ext ended I/O sp ace fro m 0x60 - 0xFF in SRAM,

only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O

space is replaced with SRAM locations when the ATmega162 is in the ATmega161

compatibility mode.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logica l one to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O Register, writing a one back into

any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

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External Memory

Interface With all the features the External Memory Interface provides, it is well suited to operate

as an interface to m emo ry d evices such a s exte rn al SRAM and FL ASH, and per iph erals

such as LCD-display, A/D, and D/A. The main features are:

•Four Different Wait-state Settings (Including No Wait-state)

•Independent Wait-state Setting for Different External Memory Sectors (Configurable

Sector Size)

•The Number of Bits Dedicated to Address High Byte is Selectable

•Bus Keepers on Data Lines to Minimize Current Consump ti on (Optional)

Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal

SRAM becomes available using the dedicated external memory pins (see Figure 1 on

page 2, Table 29 on page 7 1, Table 35 on page 76, and Table 41 on pa ge 82). The

memory configurat ion is shown in Figure 11.

Figure 11. External Memory with Sector Select

Note: 1. Address depends on the ATmega161 compatibility Fuse. See “SRAM Data Memory”

on page 18 and Figure 9 on page 19 for details.

Using the External Memory

Interface The interface consists of:

• AD7:0: Multiplexed lo w-order address bus and data bus

• A15:8: High-order address bus (configurable number of bits)

• ALE: Address latch enable

•RD

: Read strobe.

•WR

: Write strobe.

0x0000

0x04FF/0x045F(1)

External Memory

(0-64K x 8)

0xFFFF

Internal Memory

SRL[2..0]

SRW11

SRW10

SRW01

SRW00

Lower Sector

Upper Sector

0x0500/0x0460(1)

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The control bits for the External Memory Interface are located in three registers, the

MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and

the Special Function IO Register – SFIOR.

When the XMEM interface is enabled, it will override the settings in the Data Direction

registers co rresponding to th e ports dedicated to the interface. For details about this port

override, see the alternate functions in section “ I/O-Ports” on page 64. The XMEM inter-

face will autodetect whether an access is inte rnal or external. If the access is external,

the XMEM interface will output address, data, and the control signals on the ports

according to Figure 1 3 (this figure shows the wave forms without wait-states). When

ALE goes from high to low, there is a valid address on AD7:0. ALE is low during a data

transfer. When the XMEM interface is enabled, also an internal access will cause activ-

ity on address-, data- and ALE ports, but the RD and WR strobes will not toggle during

internal access. When the External Memory Interface is disabled, the normal pin and

data direction settings are used. Note that when the XMEM interface is disabled, the

address space above the internal SRAM boundary is not mapped into the internal

SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal

latch (typically “74x573” or equivalent) which is transparent when G is high.

Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be

selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.

When operating at condition s above these f requencies, the typical old style 74HC ser ies

latch becomes inadequate. The external memory interface is designed in compliance to

the 74AHC series latch. However, most latches can be used as long they comply with

the main timing par ameters. The main parameters for the address latch are:

• D to Q propagati on delay (tpd).

• Data setup time bef ore G low (tsu).

• Data (address) hold time after G low (th).

The external memory int erface is designed to gu aranty minimum a ddress hold time af ter

G is asserted low of th = 5 ns (refer to tLAXX_LD/tLLAXX_ST in Table 115 to Table 12 2 on

page 274). The D to Q propagation delay (tpd) m ust be taken into con sideration when

calculating the access time requirement of the external component. The data setup time

before G low (tsu) must not exceed address valid to ALE lo w (tAVLLC) minus PCB wiring

delay (dependent on the capacitive load).

Figure 12. External SRAM Connected to the AVR

D[7:0]

A[7:0]

A[15:8]

SRAM

AD7:0

ALE

A15:8

AVR

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Pull-up and Bus Keeper The pull-up resistors on the AD7:0 ports may be activate d if the corresponding Port reg-

ister is written to one. To reduce power consumption in sleep mode, it is recommended

to disable the pull-ups by writing the Port register to zero before entering sleep.

The XMEM interface also provid es a bus keeper on the AD7:0 lines. The Bus Keeper

can be disabled and ena bled in software as described in “Special Functi on IO Register –

SFIOR” on page 32. When enabled, the Bus Keeper will keep the previous value on the

AD7:0 bus while these lines are tri-stated by the XMEM interface.

Timing External memory devices have various timing requirements. To meet these require-

ments, the ATmega162 XMEM interface provides four different wait-states as shown in

Table 3. It is important to consider the timing specification of the external memory

device before selecting the wait-state. The most important parameters are the access

time for the external memory in conjunction with the set-up requirement of the

ATmega162. The access time for the external memory is defined to be the time from

receiving the chip select/address until the data of this address actually is driven on the

bus. The acces s time cannot exceed the time from the ALE pulse is ass erted low until

data must be stable during a read sequence (tLLRL+ tRLRH - tDVRH in Table 115 to Table

122 on page 274). The different wait-states are set up in software. As an additional fea-

ture, it is possible to divide the external memory space in two se ctors with individual

wait-state settings. This makes it possible to connect two different memory devices with

different timing requirements to the same XMEM interface. For XMEM interface timing

details, please refer to Figure 118 to Figure 121, and Table 115 to Table 122.

Note that the XMEM interface is asynchronous and that the waveforms in the figures

below are related to the internal system clock. The skew between the internal and exter-

nal clock (XTAL1) is not g uaranteed (i t varies between device s, temperatu re, and supply

voltage). Consequently, the XMEM interface is not suited for synchronous operation.

Figure 13. External Data Memory Cycles without Wait-state

(SRWn1 = 0 and SRWn0 =0)(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower secto r), SRWn0 = SRW10 (upper

sector) or SR W00 (lower sector).

The ALE pulse in period T4 is only present if the next instruction accesses the RAM

(internal or external).

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

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Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower secto r), SRWn0 = SRW10 (upper

sector) or SR W00 (lower sector)

The ALE pulse in period T5 is only present if the next instruction accesses the RAM

(internal or external).

Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower secto r), SRWn0 = SRW10 (upper

sector) or SR W00 (lower sector).

The ALE pulse in period T6 is only present if the next instruction accesses the RAM

(internal or external).

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLK

CPU

)

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

T4 T5

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Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower secto r), SRWn0 = SRW10 (upper

sector) or SR W00 (lower sector).

The ALE pulse in period T7 is only present if the next instruction accesses the RAM

(internal or external).

XMEM Register

Description

MCU Control Register –

MCUCR

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,

A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit over-

rides any pin direction settings in the respective Data Direction Registers. Writing SRE

to zero, disables the External Memory Interface and the normal pin and data direction

settings are used.

• Bit 6 – SRW10: Wait State Select Bit

For a detailed description, see common description for the SRWn bits below (EMCUCR

description).

Extended MCU Control

• Bit 6..4 – SRL2 , SRL1, SRL0: Wait State Sector Limit

It is possible to configure different wait-states for different external memory addresses.

The external memory address space can be divided in two sectors that have separate

wait-state bits. The SRL2, SRL1, and SRL0 bits select the splitti ng of th ese sectors, see

Table 2 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and

the entire extern al memory address space is treated a s one sector. When the entire

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

T4 T5 T6

Bit 76543210

SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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SRAM address space is configured as one sector, the wait-states are co nfigure d by the

SRW11 and SRW10 bit s.

• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait-state Select Bits for Upper

Sector

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of

the external memory address space, see Table 3.

• Bit 3..2 – SRW01, SRW00: Wait-state Select Bits for Lower Sector

The SRW01 and SRW00 bits control the number of wait-states for the lower sector of

the external memory address space, see Table 3.

Note: 1. n = 0 or 1 (lower/upper sector).

F or further details of the timing and wait-states of the External Memory Interface, see

Figure 13 to Figure 16 how the setting of the SRW bits affects the timing.

Table 2. Sector Limits with Different Settings of SRL2..0

SRL2 SRL1 SRL0 Sector Limits

000Lower sector = N/A

Upper sector = 0x1100 - 0xFFFF

001Lower sector = 0x1100 - 0x1FFF

Upper sector = 0x2000 - 0xFFFF

010Lower sector = 0x1100 - 0x3FFF

Upper sector = 0x4000 - 0xFFFF

011Lower sector = 0x1100 - 0x5FFF

Upper sector = 0x6000 - 0xFFFF

100Lower sector = 0x1100 - 0x7FFF

Upper sector = 0x8000 - 0xFFFF

101Lower sector = 0x1100 - 0x9FFF

Upper sector = 0xA000 - 0xFFFF

110Lower sector = 0x1100 - 0xBFFF

Upper sector = 0xC000 - 0xFFFF

111Lower sector = 0x1100 - 0xDFFF

Upper sector = 0xE000 - 0xFFFF

Table 3. Wait-states(1)

SRWn1 SRWn0 Wait-states

0 0 No wait-states

0 1 Wait one cycle during read/write strobe

1 0 Wait two cycles during read/write strobe

11Wait two cycles during read/write and wait one cycle before driving out

new address

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Special Function IO Register –

SFIOR

• Bit 6 – XMBK: External Memory Bus Keeper Enable

Writing XMBK to one enable s the Bus Keeper on the AD7:0 lin es. When the Bus Keep er

is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface

has tri-stated the lines. Writing XMBK to zero disables the Bus Keeper. XMBK is not

qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still

activated as long as XMBK is one.

• Bit 6..3 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memo ry is enabled, all Port C pins are used for the high address

byte by default. If the full 60KB address space is not required to access the external

memory, some, or all, Port C pins can be released for normal Port Pin function as

described in Table 4. As descri bed in “Using all 64KB Locations of External Memory” on

page 34, it is p o ssib le to use the XMMn bits to access all 64 KB lo ca tio ns of th e ex te rn al

memory.

Using all Locations of

External Memory Smaller than

64 KB

Since the external memory is mapped after the internal memory as shown in Figure 11,

the external memory is not addressed when addressing the first 1,280 bytes of data

space. It may appear that the first 1,280 bytes of the external memory are inaccessible

(external memory addresses 0x0 000 to 0x04FF). However, when connecting an exter-

nal memory smaller than 64 KB, fo r example 3 2 KB, these locat ions are ea sily accessed

simply by addressing from a ddress 0x8000 to 0x84FF. Since the External Memory

Address bit A15 is not connected to the external memory, addresses 0x8000 to 0x84FF

will appear as addresses 0x0000 to 0x04FF for the external memory. Addressing above

address 0x84FF is not recommended, since this will address an external memory loca-

tion that is already accessed by another (lower) address. To the Application software,

the external 32 KB memory will appear as one linear 32 KB address space from 0x0500

to 0x84FF. This is illustrated in Figure 17. Memory configuration B refers to the

ATmega161 compatibility mode, configuration A to the non-compatible mode.

Bit 7654321 0

TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 4. Port C Pins Released as Normal Port Pins when the External Memory is

Enabled

XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins

0008 (Full 60 KB space) None

0017 PC7

0106 PC7 - PC6

0115 PC7 - PC5

1004 PC7 - PC4

1013 PC7 - PC3

1102 PC7 - PC2

111No Address high bits Full Port C

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When the device is set in ATmega161 compatibility mode, the internal address space is

1,120 bytes. This implies that the first 1,120 bytes of the external memory can be

accessed at addresses 0x8000 to 0x845F. To the Application software, the external 32

KB memory will appear as one linear 32 KB address space from 0x0460 to 0x845F.

Figure 17. Address Map with 32 KB External Memory

0x0000

0x04FF

0xFFFF

0x0500

0x7FFF

0x8000

0x84FF

0x8500

0x0000

0x04FF

0x0500

0x7FFF

Memory Configuration A Memory Configuration B

Internal Memory

(Unused)

AVR Memory Map External 32K SRAM

External

Memory

0x0000

0x045F

0xFFFF

0x0460

0x7FFF

0x8000

0x845F

0x8460

0x0000

0x045F

0x0460

0x7FFF

Internal Memory

(Unused)

AVR Memory Map External 32K SRAM

External

Memory

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Using all 64KB Locations of

External Memor y Since the external memory is mapped after the internal memory as shown in Figure 11,

only 64,256 Bytes of externa l memory are available by default (addres s space 0x0000

to 0x05FF is reserved for internal memory). However, it is possible to take advantage of

the entire external memory by masking the higher address bits to zero. This can be

done by using the XMMn bits and control by software th e most significant bits of the

address. By se tting Por t C to outpu t 0x00 , and releasing the most significan t bit s for no r-

mal Port Pin operation, the Memory Interface will address 0x000 0 - 0x1FFF. See code

example below.

Note: 1. The example code assumes that the part specific header file is included.

Care must be exercised using this option as most of the memory is masked away.

Assembly Code Example(1)

; OFFSET is defined to 0x2000 to ensure

; external memory access

; Configure Port C (address high byte) to

; output 0x00 when the pins are released

; for normal Port Pin operation

ldi r16, 0xFF

out DDRC, r16

ldi r16, 0x00

out PORTC, r16

; release PC7:5

ldi r16, (1<<XMM1)|(1<<XMM0)

out SFIOR, r16

; write 0xAA to address 0x0001 of external

; memory

ldi r16, 0xaa

sts 0x0001+OFFSET, r16

; re-enable PC7:5 for external memory

ldi r16, (0<<XMM1)|(0<<XMM0)

out SFIOR, r16

; store 0x55 to address (OFFSET + 1) of

; external memory

ldi r16, 0x55

sts 0x0001+OFFSET, r16

C Code Example(1)

#define OFFSET 0x2000

void XRAM_example(void)

{

unsigned char *p = (unsigned char *) (OFFSET + 1);

DDRC = 0xFF;

PORTC = 0x00;

SFIOR = (1<<XMM1) | (1<<XMM0);

*p = 0xaa;

SFIOR = 0x00;

*p = 0x55;

}

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System Clock and

Clock Options

Clock Systems and their

Distribution Figure 18 presents the principal clock systems in the AVR and their distribution. All of

the clocks need not be active at a give n time. In order to reduce power con sumption, the

clocks to modules not being used can be halted by using different sleep modes, as

described in “Power Management and Sleep Modes” on page 43. The clock systems

are detailed below.

Figure 18. Clock Distribution

CPU clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR

core. Examples of such modules are th e General Purpose Register File, t he Status Reg-

ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the

core from performing general operations and calculations.

I/O clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and

USART. The I/O clock is also used by the External Interrupt module, but note that some

external interrupts are detected by asynchronous logic, allo wing such interrupts to be

detected even if the I/O clock is halted.

Flash clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually

active simultaneously with the CPU clock.

Asynchronous Timer clock –

clkASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked

directly from an external 32 kHz clock crystal. Th e dedic ated clo ck domain allows using

this Timer/Counter as a realtime counte r even when the device is in sleep mode.

General I/O

Modules

Asynchronous

Timer/Counter CPU Core RAM

clkI/O

clkASY

AVR Clock

Control Unit clkCPU

Flash and

EEPROM

clkFLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Timer/Counter

Oscillator Crystal

Oscillator Low-frequency

Crystal Oscillator

External Clock

ATmega162/V

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Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as

shown below. The clock from the selected source is input to the AVR clock generator,

and routed to the appropriate modules.

Note: For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking o ption is given in the following sections. When the

CPU wakes up from Power-down or Power-save, the selected clock source is used to

time the start-up, ensuring stable Oscillator operation before instruction execution starts.

When the CPU starts from Reset, there is an additional delay allowing the power to

reach a stable level before commencing normal operation. The Watchdog Oscillator is

used for timing this realtime part of the start-up time. The number of WDT Oscillator

cycles used for each Time-out is shown in Table 6. The frequency of the Watchdog

Oscillator is voltage dependent as shown in “ATmega162 Typical Characteristics” on

page 277.

Default Clock Source The device is shipp ed wit h CKSEL = “0010 ”, SUT = “ 10” a nd CKDI V8 pr og ra mmed. The

default clock source setting is therefore the Internal RC Oscillator with longest startup

time and an initial system clock prescaling of 8. This default setting ensures that all

users can make their desired clock source setting using an In-System or Parallel

programmer.

Crystal Oscillator XTAL1 and XTAL2 are input and output , respectively, of an inver ting amplifier which can

be configured for use as an On-chip Oscillator, as shown in Figure 19. Either a quartz

crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value

of the capacitors depends on the crystal or resonator in use, the amount of stray capac-

itance, and the electromagnetic noise of the environmen t. Some initial guidelin es for

choosing capacitors for use with crystals are given in Table 7. For ceram ic resonators,

the capacitor values given by the manufacturer should be used.

Table 5. Device Clocking Options Select

Device Cloc king Option CKSEL3..0

External Crystal/Ceramic Resonator 1111 - 1000

External Low-frequency Crystal 0111 - 0100

Calibrated Internal RC Oscillator 0010

Exter nal Clock 0000

Reserved 0011, 0001

Table 6. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

4.1 ms 4.3 ms 4K (4,096)

65 ms 69 ms 64K (65,536)

ATmega162/V

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Figure 19. Crystal Oscillator Connections

The Oscillator can operate in four different modes, each optimized for a specific fre-

quency range. The operating mode is selected by the fuses CKSEL3:1 as shown in

Table 7.

Note: 1. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown

in Table 8.

Table 7. Crystal Oscillator Operating Modes

CKSEL3:1 Frequency Range

(MHz) Recommended Range for Capacitors C1 and

C2 for Use with Crystals (pF)

100(1) 0.4 - 0.9 –

101 0.9 - 3.0 12 - 22

110 3.0 - 8.0 12 - 22

111 8.0 - 12 - 22

Table 8. Start-up Times for the Crystal Oscillator Clock Selection

CKSEL0 SUT1:0

Start-up Time from

Power-down and

Power-save Additional Delay fr om

Reset (VCC = 5.0V) Recommended

Usage

0 00 258 CK(1) 4.1 ms Ceramic resonator,

fast rising power

0 01 258 CK(1) 65 ms Ceramic resonator,

slowly rising power

010 1K CK

(2) – Ceramic resonator ,

BOD enabled

011 1K CK

(2) 4.1 ms Ceramic resonator,

fast rising power

100 1K CK

(2) 65 ms Ceramic resonator,

slowly rising power

1 01 16K CK – Crystal Oscillator,

BOD enabled

1 10 16K CK 4.1 ms Crystal Oscillator,

fast rising power

1 11 16K CK 65 ms Crystal Oscillator,

slowly rising power

XTAL

GND

ATmega162/V

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Notes: 1. These options should only be used when not operating close to the maximum fre-

quency of the device, and only if frequency stability at start-up is not important for the

application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure fre-

quency stability at star t-up. They can also be used with cr ystals when not operating

close to the maximum frequency of the device, and if frequency stability at start-up is

not important for the application.

Low-frequency Crystal

Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre-

quency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0100”,

“0101”, “0110” or “0111”. The crystal should be connected as shown in Figure 19. If

CKSEL equals “0110” or “0111”, the internal capacitors on XTAL1 and XTAL2 are

enabled, thereby removing the need for external capacitors. The internal capacitors

have a nominal value of 10 pF.

When this Oscillator is selected, start-up times are determined by the SUT Fuses (real

time-out from Reset) and CKSEL0 (number of clock cycles) as shown in Table 9 and

Table 10.

Note: 1. These options should only be used if frequency stability at start-up is not impor tant

for the application.

Calibrated Internal RC

Oscillator The calibrated internal RC Oscillator provides a fix ed 8.0 MHz clock. The frequency is

nominal value at 3V and 25°C. If 8.0 MHz frequency exceed the specification of the

device (depends on VCC), the CKDIV8 Fuse must be programmed in order to divide the

internal frequency by 8 during start- up. See “System Clock Prescaler” on page 41 for

more details. This clock may be selected as the system clock by programming the

CKSEL Fuses as shown in Table 11. If selected, it will operate with no external compo-

nents. During Reset, har dwar e loads the ca libr ati on byte int o the OSCCAL Reg ist er and

thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration gives

a frequency within ±10% of the nominal frequency. Using calibration methods as

described in application notes available at www.atmel.com/avr it is possible to achieve

±2% accuracy at any given VCC and Temperature. When this Oscillator is used as the

chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the

Table 9. Start-up Delay from Reset when Low-frequency Crystal Oscillator is Selected

SUT1:0 Additional Delay from Reset (VCC = 5.0V) Recommended Usage

00 0 ms Fast rising power or BOD enabled

01 4.1 ms Fast r ising power or BOD enabled

10 65 ms Slowly rising power

11 Reserved

Table 10. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

CKSEL1:0 Internal Capacitors

Enabled?

Start-up Time from

Power-dow n and

Power-save Recommended Usage

00(1) No 1K CK

01 No 32K CK Stable Frequency at start-up

10(1) Yes 1K CK

11 Yes 32K CK Stable Frequency at start-up

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Reset Time-out. For more inform ation on the pre-programmed calibration value, see the

section “Calibration Byte ” on page 236.

Note: 1. The device is shipped with this option selected.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as

shown in Table 12. XTAL1 and XTAL2 should be left unconnected (NC).

Note: 1. The device is shipped with this option selected.

Oscillator Calibration Register

– OSCCAL

• Bit 7 – Res: Reserved Bit

This bit is reserved bit in the ATmega162, and will alwa ys read as zero.

• Bits 6..0 – CAL6..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the Internal Oscillator to remove pro-

cess variations from the Oscillator frequ ency. This is done automatically during Chip

Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-

zero values to this register will increase the frequency of the Internal Oscillator. Writing

0x7F to the register gives the highest available frequency. The calibrated Oscillator is

used to time EEPROM and Flash access. If EEPROM or Flash is written, do not cali-

brate to more than 10% abo ve the nominal frequency. Otherwise, the EEPROM or Flash

write may fail.

Table 11. Internal Calibrated RC Oscillator Operating Modes

CKSEL3:0 Nominal Frequency

0010(1) 8.0 MHz

Table 12. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

SUT1:0 Start-up Time from Power-

dow n and Power-sav e Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

00 6 CK – BOD enabled

01 6 CK 4.1 ms Fast rising power

10(1) 6 CK 65 ms Slowly rising power

11 Reserved

Bit 76543210

– CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 Device Specific Calibration Value

ATmega162/V

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External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in

Figure 20. To run the device on an extern al clock, the CKSEL Fuses must be pro-

grammed to “0000”.

Figure 20. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as

shown in Table 14.

When applying an external clock, it is required to avoid sudden change s in the applied

clock frequency to en sure stable operation of the MCU. A variation in frequency of mo re

than 2% from one clock cycle to the next can lead to unpredictable behavior. It is

required to ensure that the MCU is kept in reset during such changes in the clock

frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of

the internal clock frequency while still ensuring stable operation. Refer to “System Clock

Prescaler” on page 41 for details.

Clock output buffer When the CKOUT Fuse is programmed, the system clock will be output on PortB 0. This

mode is suitable when chip clock is used to drive other circuits on th e syst em. Th e clock

Table 13. Internal RC Oscillator Frequency Range.

OSCCAL Value Min Frequency in Percentage of

Nominal Frequency Max Frequency in Percentage of

Nominal Frequency

0x00 50% 100%

0x3F 75% 150%

0x7F 100% 200%

Table 14. Start-up Times for the External Clock Selection

SUT1..0

Start-up Time from

Power-down and

Power-save Additional Delay from

Reset (VCC = 5.0V) Recommend ed Us age

00 6 CK – BOD enabled

01 6 CK 4.1 ms Fast rising power

10 6 CK 65 ms Slowly rising power

11 Reserved

XTERNAL

CLOCK

SIGNAL

ATmega162/V

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will be output also during Reset and the normal operation of PortB will be overridden

when the fuse is programmed. Any clock sources, including Internal RC Oscillator, can

be selected when PortB 0 serves as clock output.

If the system clock prescaler is used, it is the divided system clock that is output when

the CKOUT Fuse is programmed. See “System Clock Prescaler” on page 41. for a

description of the system clock prescaler.

Timer/Counter Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the

crystal is connected directly between the pins. The Oscillator provides internal capaci-

tors on TOSC1 and TO SC2, thereby removing the ne ed for external capacitors. The

internal capacitors have a nominal value of 10 pF. The Oscillator is optimized for use

with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not

recommended.

System Cloc k Prescaler The ATmega162 system clock can be divided by setting the Clock Prescale Register –

CLKPR. This feature can be used to decrease power consumption when the require-

ment for processing power is low. This can be used with all clock source options, and it

will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkCPU,

and clkFLASH are divided by a factor as shown in Table 15. Note that the clock frequency

of clkASY (asynchronously Timer/Counter) only will be scaled if the Timer/Counter is

clocked synchronously.

Clock Prescale Register –

CLKPR

• Bit 7 – CLKPCE: Clock Prescal er Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. CLK-

PCE is cleared by hardware four cycles after it is written or when CLKPS is written.

Setting the CLKPCE bit will disable interrupts, as explained in the CLKPS description

below.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal

system clock. These bits can be written run-time to vary the clock frequency to suit the

application requirements. As the divider divides the master clock input to the MCU, the

speed of all synchronous peripher als is reduced when a division f actor is used. The divi-

sion factors are given i n Table 15.

To avoid unintentional changes of clock frequency, a special write procedure must be

followed to change the CLKPS bits:

1. Write the Cloc k Presca ler Ch ange Enable (CLKPCE) bit to one a nd all ot her bits

in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to

CLKPCE.

Caution: An interrupt between step 1 and step 2 will make the timed sequence fail. It is

recommended to have the Global Interrupt Flag cleared during these steps to avoid this

problem.

Bit 7 6 5 4 3 2 1 0

CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

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The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-

grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits

are reset to “001 1”, giving a d ivision fa ctor of 8 a t start up. This featu re should be u sed if

the selected clock source has a higher frequency than the maximum frequency of the

device at the present operating conditions. Note that any value can be written to the

CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must

ensure that a sufficient division factor is ch osen if the se lected clock source has a high er

frequency than the maximum frequency of the device at the present operating condi-

tions. The device is shipped with the CKDIV8 Fuse programmed.

Table 15. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

00001

00012

00104

00118

010016

010132

011064

0111128

1000256

1001Reserved

1010Reserved

1011Reserved

1100Reserved

1101Reserved

1110Reserved

1111Reserved

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Power Management

and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby

saving power. The AVR provid es various sleep modes allowing the user to tailor the

power consum p tio n to the ap p licat ion ’s re qu ire m en ts.

To enter any of the five sleep modes, the SE bit in MCUCR must be written to logic one

and a SLEEP instr uction must be exec uted. The SM2 bit in M CUCSR, the SM1 bit in

MCUCR, and the SM0 bit in the EMCUCR Register select which sleep mode (Idle,

Power-down, Power-save, Standby, or Extended Standby) will be activated by the

SLEEP instruction. See Table 16 for a summary. If an enabled interrupt occurs while the

MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in

addition to the start- up time , exe cute s the interr up t r outine , a nd r esumes e xe cutio n from

the instruction following SLEEP. The contents of the Register File and SRAM are unal-

tered when the device wakes up from sleep. If a Reset occurs during sleep mode, the

MCU wakes up and ex ec ute s fro m the Reset V ect or .

Figure 18 on page 35 presents the different clock systems in the ATmega162, and their

distribution. The figure is helpful in selecting an appropriate sleep mode.

MCU Control Register –

MCUCR

• Bit 5 – SE: Sleep Enable

The SE bit must be wr itten to logic o ne to make the MCU e nter the sleep mo de when the

SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is

the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one

just before the execution of the SLEEP instruction and to clear it immediately after wak-

ing up.

• Bit 4 – SM1: Sleep Mode Select Bit 1

The Sleep Mode Select bits select between the five available sleep modes as shown in

Table 16.

MCU Control and Status

• Bit 5 – SM2: Sleep Mode Select Bit 2

The Sleep Mode Select bits select between the five available sleep modes as shown in

Table 16.

Bit 76543210

SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

JTD –SM2JTRF WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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Extended MCU Control

• Bit 7 – SM0: Sleep Mode Select Bit 0

The Sleep Mode Select bits select between the five available sleep modes as shown in

Table 16.

Note: 1. Standby mode and Extended Standby mode are only available with external cr ystals

or resonators.

Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter

Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator,

Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode ena bles the MCU to wake up from external triggere d interrupts as well as

internal ones like the Timer Overflow and USART Transmit Complete interrupts. If

wake-up from the Analog Co mparator interrupt is not require d, the Analog Comparator

can be powered down by setting the ACD bi t in the Analog Comparat or Control and Sta-

tus Register – ACSR. This will reduce power consumption in Idle mode.

Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the external Oscillator is stopped, while the external

interrupts and the Watchdog continue operating (if enabled). Only an External Reset, a

Watchdog Reset, a Brown-out Reset, an External Level Interrupt on INT0 or INT1, an

external interrupt on INT2, or a pin change interru pt can wake up the MCU. This sleep

mode bas ically halts all g enerated c locks, allowing operation of asynchronous modules

only.

Note that if a level triggered interr upt is used for wake-up from Power-down mode, the

changed level must be h eld for some t ime t o wake up t he MCU. Ref er t o “ External Inter-

rupts” on page 85 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition

occurs until the wake -up become s effe ct ive. T his allo ws th e clock t o rest ar t and b ecome

stable after having been stopped. The wake-up period is defined by the same CKSEL

Fuses that define the Reset Time-out period, as described in “Clock Sources” on page

36.

Bit 76543210

SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 16. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle

001Reserved

010Power-down

011Power-save

100Reserved

101Reserved

110Standby

(1)

1 1 1 Extended Standby(1)

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Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter

Power-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,

Timer/Counter2 will run during sleep. The device can wake up from either Timer Over-

flow or Output Compare event from Timer/Counter2 if the corresponding

Timer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable

bit in SREG is set.

If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is rec-

ommended instead of Power-save mode because the contents of the registers in the

Asynchronous Timer should be considered undefined after wake-up in Power-save

mode if AS2 is 0.

This sleep mode basically halts all clocks except clkASY, allo wing opera tion only of asyn-

chronous modules, including Timer/Counter 2 if clocked asynchronously.

Standb y Mode When the SM2..0 bit s ar e 110 and a n exter nal cryst al/reson ator clo ck o ption is selecte d,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to

Power-down with the exception that the main Oscillator is kept running. From Standby

mode, the device wakes up in six clock cycles.

Extended Standby Mode When the SM2..0 bit s ar e 111 and a n exter nal cryst al/reson ator clo ck o ption is selecte d,

the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is

identical to Power-save mode with the exception that the main Oscillator is kept running.

From Extended Standby mode, the device wakes up in six clock cycles.

Notes: 1. External Crystal or resonator selected as clock source

2. If AS2 bit in ASSR is set

3. For INT1 and INT0, only level interrupt

Table 17. Active Clock domains and Wake up sources in the different sleep modes

Active Clock domains Oscillators Wake-up Sources

Sleep Mod e clkCPU clkFLASH clkIO clkASY

Main Clock

Source Enabled Timer Osc

Enabled

INT2

INT1

INT0

and Pin Change Timer2

SPM/

EEPROM

Ready Other

I/O

Idle X X X X(2) XXXX

Power-down X(3)

Power-save X(2) X(2) X(3) X(2)

Standby(1) XX

(3)

Extended Standby(1) X(2) XX

(2) X(3) X(2)

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Minimizing Po wer

Consumption There are several issues to consider when trying to minimize the power consumption in

an AVR controlled system. In general, sleep modes should be used as much as possi-

ble, and the sleep mode should be selected so that as few as possible of the device’s

functions are operating. All functions not needed should be disabled. In particular, the

following modules may need special consideration when trying to achieve the lowest

possible power consumption.

Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not needed. In

the other sleep modes, the Analog Comparator is automatically disabled. However, if

the Analog Comp arator is set up to use the Internal Voltage Reference as input, the

Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Volt-

age Reference will be enabled, independent of sleep mode. Refer to “Analog

Comparator” on page 197 for details on how to configure the Analog Comparator.

Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned

off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in

all sleep modes, and hence, always consume power. In the deeper sleep modes, this

will contribute significantly to the total current consumption. R efer to “Brown-out Detec-

tion” on page 51 for details on how to configure the Brown-out Detector.

Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detector

or the Analog Comparator. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming

power. When turned on again, the user must allow the reference to start up before the

output is used. If the reference is kept on in sleep mode, the output can be used imme-

diately. Refer to “Inter nal Volt age Refe rence” on pag e 53 for de tails on the star t-up tim e.

Watchdog Timer If the Wa tchdog Tim er is no t neede d in t he applicat ion, this modu le should be turne d off.

If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,

always consume power. In the deeper sleep modes, this will contribute significantly to

the total current consumption. Refer to “Watchdog Timer” on page 53 for details on how

to configure the Watchdog Timer.

Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.

The most important thing is to ensure that no pins drive resistive loads. In sleep modes

where the I/O clock (clkI/O) is stopped, the input buffers of the device will be disabled.

This ensures that no power is consumed by the input logic when not needed. In some

cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 68 for

details on which pins are enabled. If the input buffer is enabled and the input signal is

left floating or ha ve an an alo g signal le ve l clo se t o V CC/2, the inpu t buf fer wi ll use e xces-

sive power.

JTAG Interface and

On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power

down or Power save sleep mode, the main clock source remains enabled. In these

sleep modes, this will contribute significantly to the total current consumption. There are

three alternative ways to avoid this:

• Disable OCDEN Fuse.

• Disable JTAGEN Fuse.

• Write one to the JTD bit in MCUCSR.

The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP

controller is not shifting data. If the hardware connected to the TDO pin does not pull up

ATmega162/V

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the logic level, power consumption will increase. Note that the TDI pin for the next

device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit

in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the

JTAG interface.

ATmega162/V

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System Control and

Reset

Resetting the AVR During Reset, all I/O Registers are set to their initial values, and t he program starts exe-

cution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP

– Absolute Jump – instruction to the reset handling routine. If the program never

enables an interrupt source, the Interrupt Vectors are not used, and regular program

code can be place d at thes e loca tions. This is als o the case if the Re set Vect or is in the

Application section while the Interrupt Vectors are in the Boot section or vice versa. The

circuit diagram in Figure 21 shows the Reset Logic. Table 18 defines the electrical

parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source

goes active. This does not require any clock source to be running.

After all reset source s have gone inactive, a dela y counter is invoked, stretching the

Internal Reset. This allows the power to reach a stable level before normal operation

starts. The Time-out period of the delay counter is defined by the user through the

CKSEL Fuses. The different selections for the delay period are pre sented in “Clock

Sources” on page 36.

Reset Sources The ATmega162 has five sources of reset:

• Power-on Reset. The MCU is reset when the supp ly voltage is below the Power-on

Reset threshold (VPOT).

• External Reset. The MCU is reset when a low le vel is present on the RESET pin for

longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the W atchdog Timer period expires and

the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when th e supply v oltage VCC is below th e

Brown-out Reset threshold (VBOT) and the Brown-out Detector is enable d. The

device is guarante ed to operate at maximum frequency for the VCC voltage down to

VBOT. VBOT must be set to the corresponding minimum voltage of the device (i.e.,

minimum VBOT for ATmega162V is 1.8V).

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset

1149.1 (JTAG) Boundary-scan” on page 206 for details.

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Figure 21. Reset Logic

Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT

(falling)

Power-on Reset A Power-on Reset (POR) pulse is generat ed by an On-chip detection circuit. The detec-

tion level is defined in Table 18. The POR is activated whenever VCC is below the

detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to

detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is Reset from Power-on.

Reaching the Power-on Reset th reshold volt age invokes the dela y counter, which de ter-

mines how long the device is kept in RESET after VCC rise. The RESET signal is

activated again, without any delay, when VCC decreases below the detect ion leve l.

Table 18. Reset Characteristics

Symbol Parameter Condition Min. Typ. Max. Units

VPOT

Po wer-on Reset

Threshold Voltage (rising) TA = -40 - 85°C0.7 1.0 1.4 V

Po wer-on Reset

Threshold Voltage

(falling)(1) TA = -40 - 85°C0.6 0.9 1.3 V

VRST RESET Pin Threshold

Voltage VCC = 3V 0.1 VCC 0.9 VCC V

tRST Minimum pulse width on

RESET Pin VCC = 3V 2.5 µs

MCU Control and Status

BODLEVEL [ 2..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

WDRF

BORF

EXTRF

PORF

DATA B U S

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

JTRF

JTAG Reset

Watchdog

Oscillator

SUT[1:0]

Watchdog

Timer

RESET Reset Circuit

Brown-out

Reset Circuit

Power-on

Reset Circuit

COUNTER RESET

INTERNAL RESET

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Figure 22. MCU Start-up, RESET Tied to VCC.

Figure 23. MCU Start-up, RESET Extended Externally

External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer

than the minimum pulse width (see Table 18) will generate a Reset, even if the clock is

not running. Shorter pulses are not guaranteed to generate a Reset. When the applied

signal reaches the Reset Threshold Voltage – VRST on its positive edge, the delay

counter starts the MCU after the Time-out period tTOUT has expired.

Figure 24. External Reset During Operation

RESET

TIME-OUT

NTERNAL

RESET

TOUT

POT

RST

RESET

TIME-OUT

NTERNAL

RESET

tTOUT

VPOT

VRST

VCC

ATmega162/V

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Brown-out Detection ATmega162 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC

level during operation by comparing it to a fixed trigger level. The trigger level for the

BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to

ensure spike free Brown-out Detection. The hysteresis on the detection level should be

interprete d as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.

Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For

devices where this is the case, the device is tested down to VCC = VBOT during the

production test. This guarantees that a Brown-out Reset will occur before VCC drops

to a voltage where correct operation of the microcontroller is no longer guaranteed.

This test is performed using BODL EVEL = 110 for ATmega162V, BODLEVEL = 101

and BODLEVEL = 100 for ATmega162.

2. For ATmega162V. Otherwise reserved.

When the BOD is enabled and VCC decreases to a value below the trigg er level (VBOT- in

Figure 25), the Brown-out Reset is immediately activated. When VCC increases above

the trigger level (VBOT+ in Figure 25), the delay counter starts the MCU after the Time-

out period tTOUT has expired.

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level

for longer than tBOD given in Table 18.

Table 19. BODLEVEL Fuse Coding

BODLEVEL Fuses [2:0] Min. VBOT(1) Typ. VBOT Max. VBOT Units

111 BOD Disabled

110(2) 1.7 1.8 2.0

101 2.5 2.7 2.9

100 4.1 4.3 4.5

011(2) 2.1 2.3 2.5

010

Reserved001

000

Table 20. Brown-out Hysteresis

Symbol Parameter Min. Typ. Max. Units

VHYST Brown-out Detector hysteresis 50 mV

tBOD Min Pulse Width on Brown-out Reset 2 µs

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Figure 25. Brown-out Reset During Operation

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-

tion. On the falli ng edge of this pulse, the dela y timer star ts counting the Time-out per iod

tTOUT. Refer to page 53 fo r details on operation of the Watchdog Timer.

Figure 26. Watchdog Reset Durin g Operation

MCU Control and Status

caused an MCU Reset.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register

selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or

by writing a logic zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zer o to the flag.

VCC

RESET

TIME-OUT

NTERNAL

RESET

VBOT- VBOT+

tTOUT

Bit 76543210

JTD –SM2 JTRF WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 See Bit Description

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• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zer o to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zer o to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to

the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and

then Reset the MCUCSR as early as possible in the program. If the register is cleared

before another reset occurs, the source of th e Reset can be found by e xamining the

Reset Flags.

Internal Voltage

Reference ATmega162 features an internal bandgap reference. This reference is used for Brown-

out Detection, and it can be used as an input to the Analog Comparator.

Voltage Reference Enable

Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used.

The start-up time is give n in Table 21. To save power, the reference is not a lways turned

on. The refere nce is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL Fuses).

2. When the bandgap reference is connected to t he An alog Comparator (by setting

the ACBG bit in ACSR).

Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always

allow the reference to start up befo re the o utput from t he Analog Co mparator is used. To

reduce power consumption in Power-down mode, the user can avoid the two conditions

above to ensure that t he reference is turned off before entering Power-down mode.

Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at

1 MHz. This is the typical frequency at VCC = 5V. See characterization data for typical

values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog

Reset interval ca n be adjusted as shown in Table 23 on page 55. The WDR – Watchdog

Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when

it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be

selected to determine the reset period. If the reset period expires without another

Watchdog Reset, the ATmega162 resets and executes from the Reset Vector. For tim-

ing details on the Watch do g Reset, re fe r to pa g e 55 .

To prevent unintentional d isabling of the Watchdog or unintentional change of time-out

period, 3 different safety levels are selected by the Fuses M161C and WDTON as

Table 21. Internal Voltage Reference Characteristics

Symbol Parameter Min. Typ. Max. Units

VBG Bandgap reference v oltage 1.05 1.10 1.15 V

tBG Bandgap reference start-up time 40 70 µs

IBG Bandgap reference current

consumption 10 µA

ATmega162/V

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shown in Table 22. Safety leve l 0 correspon ds to the se t ting in ATmeg a16 1. Ther e is no

restriction on enabling the WDT in any of the safety levels. Refer to “Timed Sequences

for Changing the Configuration of the Watchdog Timer” on page 57 for details.

Figure 27. Watchdog Timer

Watchdog Timer Control

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATmega162 and will always read as zero.

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog

will not be disabled. Once written to one, hardware will clear this bit after four clock

cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In

Safety Levels 1 and 2, this bit must a lso be set when changing the presca ler bits. See

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 57.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is e nabled, and if the WDE is

written to logic zero, t he Watch dog Ti mer fun ctio n is disab led. WDE can only be clear ed

Table 22. WDT Configuration as a Function of the Fuse Settings of M161C and

WDTON.

M161C WDTON Safety

Level

WDT

Initial

State How to Disab le

the WDT

How to

Change Time-

out

Unprogrammed Unprogrammed 1 Disabled Timed sequence Timed

sequence

Unprogrammed Programmed 2 Enabled Always enabled Timed

sequence

Programmed Unprogrammed 0 Disabled Timed sequence No restriction

Programmed Programmed 2 Enabled Always enabled Timed

sequence

WATCHDOG

OSCILLATOR

Bit 76543210

– – – WDCE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value00000000

ATmega162/V

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if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-

ing procedur e m ust be fo llowe d :

1. In the same operation, write a logic one to WDCE and WDE. A logic one mu st be

written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the

Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algo-

rithm described ab ove. See “Timed Sequences for Chang ing the Configuration of the

Watchdog Timer” on page 57.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is e nabled. The differen t prescaling values and their corresponding

Timeout Periods are shown in Table 23.

Table 23. Watchdog Timer Prescale Select

WDP2 WDP1 WDP0 Number of WDT

Oscillator Cycles Typical Time-out

at VCC = 3.0V Typical Time-out

at VCC = 5.0V

0 0 0 16K (16,384) 17 ms 16 ms

0 0 1 32K (32,768) 34 ms 33 ms

0 1 0 65K (65,536) 69 ms 65 ms

0 1 1 128K (131,072) 0.14 s 0.13 s

1 0 0 256K (262,144) 0.27 s 0.26 s

1 0 1 512K (524,288) 0.55 s 0.52 s

1 1 0 1,024K (1,048,576) 1.1 s 1.0 s

1 1 1 2,048K (2,097,152) 2.2 s 2.1 s

ATmega162/V

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The following code example shows one assembly and one C function for turning off the

WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts

globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

WDT_off:

; Reset WDT

WDR

; Write logical one to WDCE and WDE

in r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example

void WDT_off(void)

{

/* Reset WDT*/

_WDR()

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

ATmega162/V

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Timed Sequences for

Changing the

Configuration of the

Watchdog Timer

The sequence for ch anging co nf igurat io n diff ers sligh tly betwee n t he three safety levels.

Separate procedu res are described for each level.

Safety Level 0 This mode is compatible with th e Watchdog oper ation found in ATmeg a161. The Watch-

dog Timer is initially disabled, but can be enabled by writing the WDE bit to one without

any restriction. The Time-out period can be changed at any tim e without restriction. To

disable an enabled Watchdog Timer, the procedure described on page 54 (WDE bit

description) must be followed.

Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the

WDE bit to one without any restriction. A timed sequence is needed when changing the

Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an

enabled Watchdog Tim er , and/ or chan ging th e Wat chdo g Tim e-o ut, th e followin g pr oce-

dure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one mu st be

written to WDE regardless of the previous value of the WDE bit.

2. Within the next f our cloc k cycles, in t he same operation, write the WDE and WDP

bits as desired, but with the WDCE bit cleared.

Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read

as one. A timed sequence is needed when changing the Watchdog Time-out period. To

change the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the

WDE always is set, the WDE must be written to one to start the timed sequence.

2. Within the next four clock cycles, in the same operation, write the WDP bits as

desired, but with the WDCE bit cleared. The value written to the WDE bit is

irrelevant.

ATmega162/V

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Interrupts This section describes the specifics of the interrupt handling as performed in

ATmega162. Fo r a general explanat ion of the AVR interrupt ha ndling, refer to “Reset

and Interrupt Handling” on pag e 14. Table 24 shows the interrupt table when th e com-

patibility fuse (M161C) is unprogrammed, while Table 25 shows the interrupt table when

M161C Fuse is programmed. All assembly code examples in this sections are using the

interrupt table when the M161C Fuse is unprogrammed.

Interrupt Vectors in

ATmega162 Table 24. Reset and Interrupt Vectors if M161C is unprogrammed

Vector No. Program

Address(2) Source Interrupt Definition

10x000

(1) RESET External Pin, Power-on Reset, Brown-out

Reset, Watchdog Reset, and JTAG AVR

Reset

2 0x002 INT0 External Interrupt Request 0

3 0x004 INT1 External Interrupt Request 1

4 0x006 INT2 External Interrupt Request 2

5 0x008 PCINT0 Pin Change Interrupt Request 0

6 0x00A PCINT1 Pin Change Interrupt Request 1

7 0x00C TIMER3 CAPT Timer/Counter3 Captur e Event

8 0x00E TIMER3 COMPA Timer/Counter3 Compare Match A

9 0x010 TIMER3 COMPB Timer/Counter3 Compare Match B

10 0x012 TIMER3 OVF Timer/Counter3 Overflow

11 0x014 TIMER2 COMP Timer/Counter2 Compare Match

12 0x016 TIMER2 OVF Timer/Counter2 Overflow

13 0x018 TIMER1 CAPT Timer/Counter1 Capture Event

14 0x01A TIMER1 COMPA Timer/Co unter1 Compare Match A

15 0x01C TIMER1 COMPB Timer/Co unter1 Compare Match B

16 0x01E TIMER1 OVF Timer/Counter1 Overflow

17 0x020 TIMER0 COMP Timer/Counter0 Compare Match

18 0x022 TIMER0 OVF Timer/Counter0 Overflow

19 0x024 SPI, STC Serial Transfer Complete

20 0x026 USART0, RXC USART0, Rx Complete

21 0x028 USART1, RXC USART1, Rx Complete

22 0x02A USART0, UDRE USART0 Data Register Empty

23 0x02C USART1, UDRE USART1 Data Register Empty

24 0x02E USART0, TXC USART0, Tx Complete

25 0x030 USART1, TXC USART1, Tx Complete

26 0x032 EE_RDY EEPROM Ready

27 0x034 ANA_COMP Analog Comparator

28 0x036 SPM_RDY Store Program Memory Ready

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Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader

address at reset, see “Boot Loader Support – Read-While-Write Self-programming”

on page 219.

2. When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of the

Boot Flash section. The addre ss of each Interrupt Vector will then be the addre ss in

this table added to the start address of the Boot Flash section.

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader

address at reset, see “Boot Loader Support – Read-While-Write Self-programming”

on page 219.

2. When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of the

Boot Flash section. The addre ss of each Interrupt Vector will then be the addre ss in

this table added to the start address of the Boot Flash section.

Table 25. Reset and Interrupt Vectors if M161C is programmed

Vector No. Program

Address(2) Source Interrupt Definition

10x000

(1) RESET External Pin, Power-on Reset, Brown-out

Reset, Watchdog Reset, and JTAG AVR

Reset

2 0x002 INT0 External Interrupt Request 0

3 0x004 INT1 External Interrupt Request 1

4 0x006 INT2 External Interrupt Request 2

5 0x008 TIMER2 COMP Timer/Counter2 Compare Match

6 0x00A TIMER2 OVF Timer/Counter2 Overflow

7 0x00C TIMER1 CAPT Timer/Counter1 Captur e Event

8 0x00E TIMER1 COMPA Timer/Counter1 Compare Match A

9 0x010 TIMER1 COMPB Timer/Counter1 Compare Match B

10 0x012 TIMER1 OVF Timer/Counter1 Overflow

11 0x014 TIMER0 COMP Timer/Counter0 Compare Match

12 0x016 TIMER0 OVF Timer/Counter0 Overflow

13 0x018 SPI, STC Serial Transfer Complete

14 0x01A USART0, RXC USART0, Rx Complete

15 0x01C USART1, RXC USART1, Rx Complete

16 0x01E USART0, UDRE USART0 Data Register Empty

17 0x020 USART1, UDRE USART1 Data Register Empty

18 0x022 USART0, TXC USART0, Tx Complete

19 0x024 USART1, TXC USART1, Tx Complete

20 0x026 EE_RDY EEPROM Ready

21 0x028 ANA_COMP Analog Comparator

22 0x02A SPM_RDY Store Program Memory Ready

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Table 26 shows Reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these loca-

tions. This is also the case if the Reset Vector is in the Application section while the

Interrupt Vectors are in the Boot section or vice versa.

Note: 1. The Boot Reset Address is shown in Table 94 o n page 231. For the BOOTRST Fuse

“1” means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector

Addresses in ATmega162 is:

Address Labels Code Comments

0x000 jmp RESET ; Reset Handler

0x002 jmp EXT_INT0 ; IRQ0 Handler

0x004 jmp EXT_INT1 ; IRQ1 Handler

0x006 jmp EXT_INT2 ; IRQ2 Handler

0x008 jmp PCINT0 ; PCINT0 Handler

0x00A jmp PCINT1 ; PCINT1 Handler

0x00C jmp TIM3_CAPT ; Timer3 Capture Handler

0x00E jmp TIM3_COMPA ; Timer3 CompareA Handler

0x010 jmp TIM3_COMPB ; Timer3 CompareB Handler

0x012 jmp TIM3_OVF ; Timer3 Overflow Handler

0x014 jmp TIM2_COMP ; Timer2 Compare Handler

0x016 jmp TIM2_OVF ; Timer2 Overflow Handler

0x018 jmp TIM1_CAPT ; Timer1 Capture Handler

0x01A jmp TIM1_COMPA ; Timer1 CompareA Handler

0x01C jmp TIM1_COMPB ; Timer1 CompareB Handler

0x01E jmp TIM1_OVF ; Timer1 Overflow Handler

0x020 jmp TIM0_COMP ; Timer0 Compare Handler

0x022 jmp TIM0_OVF ; Timer0 Overflow Handler

0x024 jmp SPI_STC ; SPI Transfer Complete Handler

0x026 jmp USART0_RXC ; USART0 RX Complete Handler

0x028 jmp USART1_RXC ; USART1 RX Complete Handler

0x02A jmp USART0_UDRE ; UDR0 Empty Handler

0x02C jmp USART1_UDRE ; UDR1 Empty Handler

0x02E jmp USART0_TXC ; USART0 TX Complete Handler

0x030 jmp USART1_TXC ; USART1 TX Complete Handler

0x032 jmp EE_RDY ; EEPROM Ready Handler

0x034 jmp ANA_COMP ; Analog Comparator Handler

0x036 jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x038 RESET: ldi r16,high(RAMEND) ; Main program start

0x039 out SPH,r16 ; Set Stack Pointer to top of RAM

Table 26. Reset and Interrupt Vectors Placement(1)

BOOTRST IVSEL Reset address Interrupt Vectors Start Address

1 0 0x0000 0x0002

1 1 0x0000 Boot Reset Address + 0x0002

0 0 Boot Reset Address 0x0002

0 1 Boot Reset Address Boot Reset Address + 0x0002

ATmega162/V

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0x03A ldi r16,low(RAMEND)

0x03B out SPL,r16

0x03C sei ; Enable interrupts

0x03D <instr> xxx

... ... ...

When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and

the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most

typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

0x000 RESET: ldi r16,high(RAMEND) ; Main program start

0x001 out SPH,r16 ; Set Stack Pointer to top of RAM

0x002 ldi r16,low(RAMEND)

0x003 out SPL,r16

0x004 sei ; Enable interrupts

0x005 <instr> xxx

;

.org 0x1C02

0x1C02 jmp EXT_INT0 ; IRQ0 Handler

0x1C04 jmp EXT_INT1 ; IRQ1 Handler

... .... .. ;

0x1C36 jmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST Fuse is programme d and the boot sect ion size se t to 2K bytes, t he

most typical and general progr am setup for t he Reset and Inte rrupt Vector Addresses is:

Address Labels Code Comments

.org 0x002

0x002 jmp EXT_INT0 ; IRQ0 Handler

0x004 jmp EXT_INT1 ; IRQ1 Handler

... .... .. ;

0x036 jmp SPM_RDY ; Store Program Memory Ready Handler

;

.org 0x1C00

0x1C00 RESET: ldi r16,high(RAMEND) ; Main program start

0x1C01 out SPH,r16 ; Set Stack Pointer to top of RAM

0x1C02 ldi r16,low(RAMEND)

0x1C03 out SPL,r16

0x1C04 sei ; Enable interrupts

0x1C05 <instr> xxx

ATmega162/V

2513H–AVR–04/06

When the BOOTRST Fuse is p rogrammed, t he boot section size set to 2K bytes and the

IVSEL bit in the GI CR Regist er is set before an y int er rupt s are enable d, the most typ ica l

and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

.org 0x1C00

0x1C00 jmp RESET ; Reset handler

0x1C02 jmp EXT_INT0 ; IRQ0 Handler

0x1C04 jmp EXT_INT1 ; IRQ1 Handler

... .... .. ;

0x1C36 jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x1C38 RESET: ldi r16,high(RAMEND) ; Main program start

0x1C39 out SPH,r16 ; Set Stack Pointer to top of RAM

0x1C3A ldi r16,low(RAMEND)

0x1C3B out SPL,r16

0x1C3C sei ; Enable interrupts

0x1C3D <instr> xxx

Moving Interrupts Between

Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector

table.

General Interrupt Control

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the

Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the begin-

ning of the Boot Loader section of the Flash. The actual address of the start of the Boot

Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader

Support – Read-While-Write Self-programming” on page 219 for details. To avoid unin-

tentional changes of Interrupt Vector tables, a special write procedure must be followed

to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles , write the desired v a lue to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are

disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-

lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four

cycles. The I-bit in the Status Register is unaffected by the automatic disabling.

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-

grammed, interrupts are disabled while executing from the Application section. If

Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro-

gramed, interrupts are disabled while executing from the Boot Loader section. Refer to

the section “Boot Loader Support – Read-While-Write Self-programming” on page 219

for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is

cleared by hardware four cycles after it is written or when IVSEL is written. Setting the

Bit 76543210

INT1 INT0 INT2 PCIE1 PCIE0 – IVSEL IVCE GICR

Read/Write R/W R/W R/W R/W R/W R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

ATmega162/V

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IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code

Example below.

Assembly Code Example

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE)

out GICR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL)

out GICR, r16

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of Interrupt Vectors */

GICR = (1<<IVCE);

/* Move interrupts to Boot Flash section */

GICR = (1<<IVSEL);

}

ATmega162/V

2513H–AVR–04/06

I/O-Ports

Introduction All AVR ports have true Re ad-Modify-Write functionality when used as general digital

I/O ports. T h is m e an s that the dir ec tio n o f one port p in can be chang ed w i th ou t u n int en -

tionally changing the direction of an y other pin with the SBI and CBI instructions. The

same applies when changing drive value (if configured as output) or enabling/disabling

of pull-up resistors (if configured as input). Each output buffer has symmetrical drive

characteristics with both high sink and source capability. The pin driver is strong enough

to drive LED displays directly. All port pins have individually selectable pull-up resistors

with a supply-voltage invariant resistance. All I/O pins have protection diodes to both

VCC and Ground as indicated in Figure 28. Refer to “Electrical Characteristics” on page

266 for a complete list of parameters.

Figure 28. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case

“x” represents the numbering letter for the port, and a lower case “n” represents the bit

number. However, when using the register or bit defines in a program, the precise form

must be used. For example, PORTB3 for bit no. 3 in Por t B, here documented generally

as PORTxn. The physical I/O Registers and bit locations are listed in “Register Descrip-

tion for I/O-Ports” on page 83.

Three I/O memory address locations are allocated for each port, one each for the Data

Port Input Pins I/O location is read only, while the Data Register and the Data Direction

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “ Ports as Ge neral Dig ita l I/ O” on

page 65. Most port pins are multiplexed with alternate functions for the peripheral fea-

tures on the device. How each alte rn ate fu nct ion int er fer es with th e port pin is de scr ibed

in “Alternate Port Functions” on page 69. Refer to the individual module sections for a

full description of the alternate functions.

Note that enabling t he a lt ernat e f unc tio n of som e o f the po rt pin s doe s not af fect th e u se

of the other pin s in the port as general digital I/ O.

Cpin

Logic

Rpu

See figure

"General Digital I/O" f

details

Pxn

ATmega162/V

2513H–AVR–04/06

Ports as General Digital

I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows a

functional descript ion of one I/O-port pin, here generically called Pxn.

Figure 29. General Digital I/O(1)

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same por t. clkI/O,

SLEEP, and PUD are common to all ports.

Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in

“Register Description for I/O-Ports” on page 83, the DDxn bits are accessed at the

DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at

the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written

logic one, Pxn is configure d as an outp ut pin. If DDxn is written logic zero, Pxn is config-

ured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up

resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic

zero or the pin has to be configur ed as an outp ut pin. The port pins ar e tri-stat ed when a

reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pi n is configure d as an output pin, the por t pin is

driven high (one). If PORTxn is written logic zero when the pin is configured as an out-

put pin, the port pin is driven low (zero).

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,

PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =

0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up

clk

RPx

RRx

WRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clkI/O: I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BUS

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

ATmega162/V

2513H–AVR–04/06

enabled state is fully acceptable, as a high -impedant environment will not notice the dif-

ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in

the SFIOR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The

user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state

({DDxn, PORTxn} = 0b11) as an int ermediate step.

Table 27 summarizes the control signals for the pin value.

Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through

the PINxn Register bit. As shown in Figure 29, the PINxn Register bit and the preceding

latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure

30 shows a timing diagram of the synchronization when reading an externally applied

pin value. The maximum and minimum pro pagation dela ys are den oted tpd,max and tpd,min

respectively.

Figure 30. Synchronization when Reading an Externally Applied Pin Value

Table 27. Port Pin Configurations

DDxn PORTxn PUD

(in SFIOR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled

low.

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min

ATmega162/V

2513H–AVR–04/06

Consider the clock period starting shortly after the first falling edge of the system cloc k.

The latch is closed when the clock is low, and goes transparent when the clock is high,

as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is

latched when the syst em clock goes low. I t is clocked into the PINxn Reg ister at the suc-

ceeding positiv e clock edge. As in dicated by the tw o arrows tpd,max and tpd,min, a single

signal transition on the pin will be delayed between ½ and 1½ system clock period

depending upon the time of assertion.

When reading back a soft ware assigned pin va lue, a nop instruction must be inserted as

indicated in Figure 31. The out instruction sets the “SYNC LATCH” signal at the positive

edge of the clock. In this case, the delay tpd through the synchronizer is one system

clock period.

Figure 31. Synchronization when Reading a Software Assigned Pin Value

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

ATmega162/V

2513H–AVR–04/06

The following code e xample shows h ow to set port B pins 0 an d 1 high, 2 and 3 low, and

define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The

resulting pin values are read back again, but as previously discussed, a nop instruction

is included to be able to rea d back the value recently assigned to some of the pins.

Note: 1. For the assembly program, two temporary registers are used to minimize the time

from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,

defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enab le and Sleep

Modes As shown in Figure 29, the digital input signal can be clamped to ground at the input of

the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep

Controller in Power-down mode, Power-save mode, Standby mode, and Extended

Standby mode to avoid hi gh power consumpt ion if some input sign als are le ft flo ating, or

have an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as External Interrupt pins. If the External

Interrupt Request is not enabled, SLEEP is active also for these pins. SLEEP is also

overridden by various other alternate functions as described in “Alternate Port Func-

tions” on page 69.

If a logic high level (“one”) is present on an Asynchronous External Interrupt pin config-

ured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the

external interrupt is not enabled, the corresponding External Interrupt Flag will be set

when resuming from the above mentioned sleep modes, as the clamping in these sleep

modes produces the requested logic change.

Assembly Code Example(1)

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

C Code Example(1)

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

ATmega162/V

2513H–AVR–04/06

Unconnected pins If some pins are unused, it is recommend ed to ensure that these pins have a defined

level. Even though most of the digital inputs are disabled in the deep sleep modes as

described above, floating inputs should be avoided to reduce current consumption in all

other modes where the digital inputs are enable d (Reset, Active mode and Idle mode).

The simplest met hod to ensu re a define d level of an unused p in, is to enabl e the inter nal

pull-up. In this case, the pull-up will be disabled during reset. If low power consumption

during reset is important, it is recomme nded to use an external pull-up or pull-dow n.

Connecting unused pins directly to VCC or GND is not recommended, since this may

cause excessive currents if the pin is accidentally configured as an output.

Alternate Port Functions Mos t port pins have alte rnate functions in addition to being gen eral digital I/Os. Fig ure

32 shows how the port pin control signals from the simplified Figure 29 can be overrid-

den by altern ate function s. The ove rriding sig nals may not be present in all port pins, b ut

the figure serves as a generic description applicable to all port pins in the AVR micro-

controller family.

Figure 32. Alternate Port Functions(1)

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same por t. clkI/O,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

clk

RPx

RRx

WRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

SET

CLR

DIxn

AIOxn

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

UOExn: Pxn PULL-UP OVERRIDE ENABLE

UOVxn: Pxn PULL-UP OVERRIDE VALUE

DOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

VOExn: Pxn PORT VALUE OVERRIDE ENABLE

VOVxn: Pxn PORT VALUE OVERRIDE VALUE

DIxn: DIGITAL INPUT PIN n ON PORTx

AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORT

RESET

CLR

PINxn

PORTxn

DDxn

DATA BUS

DIEOVxn

SLEEP

IEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

IEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

LEEP: SLEEP CONTROL

Pxn

I/O

ATmega162/V

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Table 28 summarizes the function of the overriding signals. The pin and port indexes

from Figure 32 are not shown in the succeeding tables. The overriding signals are gen-

erated intern ally in the modules having the alternate function.

The following subs ections shortly describe the alterna te functions for each port, an d

relate the overriding signals to the alternate function. Refer to the alternate function

description for further details.

Table 28. Generic Desc rip tio n of Ov er rid ing Sign als for Alte rn at e Fu n ctio ns .

Signal Name Full Name Description

PUOE Pull-up Override

Enable If this signal is set, the pull-up enable is controlled by the

PUOV signal. If this signal is cleared, the pull-up is

enabled when {DDxn, PORTxn, PUD} = 0b010.

PUO V Pull-up Override

Value If PUOE is set, the pull-up is enabled/disabled when

PUOV is set/cleared, regardless of the setting of the

DDxn, PORTxn, and PUD Register bits.

DDOE Data Direction

Override Enable If this signal is set, the Output Driver Enable is controlled

by the DDOV signal. If this signal is cleared, the Output

driver is enabled by the DDxn Register bit.

DDOV Data Direction

Override Value If DDOE is set, the Output Driver is enabled/disabled

when DDO V is set/cleared, regardless of the setting of the

DDxn Register bit.

PVOE Port Value

Override Enable If this signal is set and the Output Driver is enabled, the

port value is controlled by the PVOV signal. If PVOE is

cleared, and the Output Driver is enabled, the port V alue is

controlled by the PORTxn Register bit.

PVOV Port Value

Override Value If PVOE is set, the port value is set to PV OV, regardless of

the setting of the PORTxn Register bit.

DIEOE Digital Input

Enable Ov erride

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input

Enable is determined by MCU state (Normal Mode, Sleep

Modes).

DIEOV Digital Input

Enable Ov erride

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state

(Nor mal Mode, Sleep Modes).

DI Digital Input This is the Digital Input to alternate functions. In the figure,

the signal is connected to the output of the schmitt trigger

but before the synchronizer. Unless the Digital Input is

used as a clock source, the module with the alternate

function will use its own synchronizer.

AIO Analog

Input/output This is the Analog Input/output to/from alternate functions.

The signal is connected directly to the pad, and can be

used bi-directionally.

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Special Function IO Register –

SFIOR

• Bit 2 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O po rts are disabled even if the DDxn

and PORTxn Registers ar e configured to enable the pull-u ps ({DDxn, PORTxn} = 0b 01).

See “Configuring the Pin” on page 65 for more details about this feature.

Alternate Functions of Port A Port A has an alternate function as the address low byte and data lines for the External

Memory Interface and as Pin Change Interrupt.

Table 30 and Table 31 rela te the alternate functions of Port A to the overrid ing signals

shown in Figure 32 on page 69.

Bit 7 6 5 4 3 2 1 0

TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 29. Port A Pins Alternate Functions

Port Pin Alternate Function

PA7 AD7 (External memory interface address and data bit 7)

PCINT7 (Pin Change INTerrupt 7)

PA6 AD6 (External memory interface address and data bit 6)

PCINT6 (Pin Change INTerrupt 6)

PA5 AD5 (External memory interface address and data bit 5)

PCINT5 (Pin Change INTerrupt 5)

PA4 AD4 (External memory interface address and data bit 4)

PCINT4 (Pin Change INTerrupt 4)

PA3 AD3 (External memory interface address and data bit 3)

PCINT3 (Pin Change INTerrupt 3)

PA2 AD2 (External memory interface address and data bit 2)

PCINT2 (Pin Change INTerrupt 2)

PA1 AD1 (External memory interface address and data bit 1)

PCINT1 (Pin Change INTerrupt 1)

PA0 AD0 (External memory interface address and data bit 0)

PCINT0 (Pin Change INTerrupt 0)

ATmega162/V

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Notes: 1. ADA is short fo r ADdress Activ e and represents the time when address is output. See

“External Memory Interface” on page 26.

2. PCINTn is Pin Change Interrupt Enable bit n.

3. PCINTn is Pin Change Interrupt input n.

Notes: 1. PCINT is Pin Change Interrupt Enable bit n.

2. PCINT is Pin Change Interrupt input n.

Table 30. Overriding Signals for Alternate Functions in PA7..PA4

Signal

Name PA7/AD7/

PCINT7 PA6/AD6/PCINT6 PA5/AD5/PCINT5 PA4/AD4/PCINT4

PUOE SRE SRE SRE SRE

PUOV ~(WR + ADA(1)) •

PORTA7 ~(WR + ADA) •

PORTA6 ~(WR + ADA) •

PORTA5 ~(WR + ADA) •

PORTA4

DDOE SRE SRE SRE SRE

DDOV WR + ADA WR + ADA WR + ADA WR + ADA

PVOE SRE SRE SRE SRE

PVOV if (ADA) then

else D7 OUTPUT

• WR

if (ADA) then

else D6 OUTPUT

• WR

if (ADA) then

else D5 OUTPUT

• WR

if (ADA) then

else D4 OUTPUT

• WR

DIEOE(2

)PCIE0 • PCINT7 PCIE0 • PCINT6 PCIE0 • PCINT5 PCIE0 • PCINT4

DIEOV1111

DI(3) D7 INPUT/

PCINT7 D6 INPUT/

PCINT6 D5 INPUT/

PCINT5 D4 INPUT/

PCINT4

AIO––––

Table 31. Overriding Signals for Alternate Functions in PA3..PA0

Signal

Name PA3/AD3/

PCINT3 PA2/AD2/

PCINT2 PA1/AD1/

PCINT1 PA0/AD0/

PCINT0

PUOE SRE SRE SRE SRE

PUOV ~(WR + ADA) •

PORTA3 ~(WR + ADA) •

PORTA2 ~(WR + ADA) •

PORTA1 ~(WR + ADA) •

PORTA0

DDOE SRE SRE SRE SRE

DDOV WR + ADA WR + ADA WR + ADA WR + ADA

PVOE SRE SRE SRE SRE

PVOV if (ADA) then

else D3 OUTPUT

• WR

if (ADA) then

else D2 OUTPUT

• WR

if (ADA) then

else D1 OUTPUT

• WR

if (ADA) then

else D0 OUTPUT

• WR

DIEOE(1) PCIE0 • PCINT3 PCIE0 • PCINT2 PCIE0 • PCINT1 PCIE0 • PCINT0

DIEOV 1 1 1 1

DI(2) D3 INPUT

/PCINT3 D2 INPUT

/PCINT2 D1 INPUT

/PCINT1 D0 INPUT

/PCINT0

AIO – – – –

ATmega162/V

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Alternate Functions Of Port B The Port B pins with alternate functions are shown in Table 32.

The alternate pin configuration is as follows:

• SCK – Port B, Bit 7

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is

enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7.

When the SPI is enabled as a Master, the data direction of this pin is controlled by

DDB7. When the pin is forced by the SPI to be an input, the pull-up can still be con-

trolled by the PORTB7 bit.

• MISO – Port B, Bit 6

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is

enabled as a M aster, this pin is configured as an input regardless of the setting of

DDB6. When the SPI is enabled a s a Slave, the data direction of this pin is controlled by

DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be con-

trolled by the PORTB6 bit.

• MOSI – Port B, Bit 5

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is

enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5.

When the SPI is enabled as a Master, the data direction of this pin is controlled by

DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be con-

trolled by the PORTB5 bit.

•SS

/OC3B – Port B, Bit 4

SS: Slave Select inp u t. When the SPI is en ab le d a s a slave, th is p in is co nf igu re d a s a n

input regardless of the setting of DDB4. As a Slave, the SPI is activated when this pin is

driven low. When the SPI is enabled as a Master, the data direction of this pin is con-

trolled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still be

controlled by the PORTB4 bit.

Table 32. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7 SCK (SPI Bus Serial Clock)

PB6 MISO (SPI Bus Master Input/Slave Output)

PB5 MOSI (SPI Bus Master Output/Slave Input)

PB4 SS (SPI Slave Select Input)

OC3B (Timer/Counter3 Output Compare Match Output)

PB3 AIN1 (Analog Comparator Negative Input)

TXD1 (USART1 Output Pin)

PB2 AIN0 (Analog Comparator Positive Input)

RXD1 (USART1 Input Pin)

PB1 T1 (Timer/Counter1 External Counter Input)

OC2 (Timer/Counter2 Output Compare Match Output)

PB0 T0 (Timer/Counter0 External Counter Input)

OC0 (Timer/Counter0 Output Compare Match Output)

clkI/O (Divided System Clock)

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OC3B, Output Compare Match B output: The PB4 pin can serve as an external output

for the Timer/Counter3 Output Compare B. The pin has to be configured as an output

(DDB4 set (one) ) to serv e this func tion. The O C3B pin is also the o utput pin for the PWM

mode timer function.

• AIN1/TXD1 – Port B, Bit 3

AIN1, Analog Comparator Negative input. Configure the port pin as input with the inter-

nal pull-up switched off to avoid t he digi tal por t fun ction from int erfe ring wit h the functi on

of the Analog Comp arator.

TXD1, Transmit Data (Data output pin for USART1). When the USART1 Transmitter is

enabled, this pin is configured as an output regardless of the value of DDB3.

• AIN0/RXD1 – Port B, Bit 2

AIN0, Analog Compar ator Positive Input . Configure the p ort pin as input wit h the internal

pull-up switched off to avoid the digital port function from interfering with the function of

the Analog Comparator.

RXD1, Receive Data (Data input pin for USART1). When the USART1 Receiver is

enabled this p in is configured as an input regard less of the value of DDB2. When the

USART1 forces this pin to be an input, the pull-up can still be controlled by the PORTB2

bit.

• T1/OC2 – Port B, Bit 1

T1, Timer/Counter1 Counter Source.

OC2, Output Compare Match output: The PB1 pin can serve as an external output for

the Timer/Counter2 Compare Match. The PB1 pin has to be configured as an output

(DDB1 set (o ne)) to s erve this funct ion. The OC 2 pin is a lso th e ou tput pin for t he PW M

mode timer function.

• T0/OC0 – Port B, Bit 0

T0, Timer/Counter0 counter source.

OC0, Output Compare Match output: The PB0 pin can serve as an external output for

the Timer/Counter0 Compare Match. The PB0 pin has to be configured as an output

(DDB0 set (o ne)) to s erve this funct ion. The OC 0 pin is a lso th e ou tput pin for t he PW M

mode timer function.

clkI/O, Divided System Clock: The divided system clock can be output on the PB0 pin.

The divided system clock will be output if the CKOUT Fuse is programmed, regardless

of the PORTB0 and DDB0 settings. It will also be output during reset.

Table 33 and Table 34 rela te the alternate functions of Port B to the overrid ing signals

shown in Figure 32 on page 69. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute

the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE

INPUT.

ATmega162/V

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Notes: 1. CKOUT is one if the CKOUT Fuse is programmed.

2. clkI/O is the divided system clock.

Table 33. Overriding Signals for Alternate Functions in PB7..PB4

Signal

Name PB7/SCK PB6/MISO PB5/MOSI PB4/SS/OC3B

PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

PUOV PORTB7 •

PUD POR TB6 • PUD POR TB5 • PUD PORTB4 •

PUD

DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

DDOV 0 0 0 0

PVOE SPE • MSTR SPE • MSTR SPE • MSTR OC3B

ENABLE

PVOV SCK OUTPUT SPI SLAVE

OUTPUT SPI MSTR

OUTPUT OC3B

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI SCK INPUT SPI MSTR INPUT SPI SLAVE INPUT SPI SS

AIO – – – –

Table 34. Overriding Signals for Alternate Functions in PB3..PB0

Signal Name PB3/AIN1/TXD1 PB2/AIN0/RXD1 PB1/T1/OC2 PB0/T0/OC0

PUOE TXEN1 RXEN1 0 0

PUOV 0 PORTB2• PUD 0 0

DDOE TXEN1 RXEN1 0 CKOUT(1)

DDOV 1 0 0 1

PVOE TXEN1 0 OC2 ENABLE CKOUT + OC0

ENABLE

PV OV TXD1 0 OC2 if (CK OUT) then

clkI/O(2)

else OC0

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI – RXD1 T1 INPUT T0 INPUT

AIO AIN1 INPUT AIN0 INPUT – –

ATmega162/V

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Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 35. If the JTAG interface is

enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be acti-

vated even if a reset occurs.

• A15/TDI/PCINT15 – Port C, Bit 7

A15, External memory interface address bit 15.

TDI, JTAG Test Data In: Serial input data to be shifted into the Instruction Register or

Data Register (scan chains). When the JTAG interface is enabled, this pin can not be

used as an I/O pin.

PCINT15: The pin can also serve as a pin change interrupt.

• A14/TDO/PCINT14 – Port C, Bit 6

A14, External memory interface address bit 14.

TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Regis-

ter. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP

states that shift out data, the TD0 pin drives actively. In other states the pin is pulled

high.

PCINT14: The pin can also serve as a pin change interrupt.

Table 35. Port C Pins Alternate Fun ctions

Port Pin A lternate Function

PC7 A15 (External memory interf ace address bit 15)

TDI (JTAG Test Data Input)

PCINT15 (Pin Change INTerrupt 15)

PC6 A14 (External memory interf ace address bit 14)

TDO (JTAG Test Data Output)

PCINT14 (Pin Change INTerrupt 14)

PC5 A13 (External memory interf ace address bit 13)

TMS (JTAG Test Mode Select)

PCINT13 (Pin Change INTerrupt 13)

PC4 A12 (External memory interf ace address bit 12)

TCK (JTAG Test Clock)

PCINT12 (Pin Change INTerrupt 12)

PC3 A11 (External memory interf ace address bit 11)

PCINT11 (Pin Change INTerrupt 11)

PC2 A10 (External memory interf ace address bit 10)

PCINT10 (Pin Change INTerrupt 10)

PC1 A9 (External memory interface address bit 9)

PCINT9 (Pin Change INTerrupt 9)

PC0 A8 (External memory interface address bit 8)

PCINT8 (Pin Change INTerrupt 8)

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• A13/TMS/PCINT13 – Port C, Bit 5

A13, External memory interface address bit 13.

TMS, JTAG Test Mode Select: This pin is used fo r navigating throu gh the TAP-cont roller

state machine. When the JTAG interface is enabled, this pin can not be used as an I/O

pin.

PCINT13: The pin can also serve as a pin change interrupt.

• A12/TCK/PCINT12 – Por t C, Bit 4

A12, External memory interface address bit 12.

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter-

face is enabled, this pin can not be used as an I/O pin.

PCINT12: The pin can also serve as a pin change interrupt.

• A11/PCINT11 – Port C, Bit 3

A11, External memory interface address bit 11.

PCINT11: The pin can also serve as a pin change interrupt.

• A10/PCINT10 – Port C, Bit 2

A10, External memory interface address bit 10.

PCINT11: The pin can also serve as a pin change interrupt.

• A9/PCINT9 – Port C, Bit 1

A9, External mem ory inte r face address bit 9.

PCINT9: The pin can also serve as a pin change interrupt.

• A8/PCINT8 – Port C, Bit 0

A8, External mem ory inte r face address bit 8.

PCINT8: The pin can also serve as a pin change interrupt.

Table 36 and Table 37 relate the alternate functions of Port C to the overriding signals

shown in Figure 32 on page 69.

ATmega162/V

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Notes: 1. PCINTn is Pin Change Interrupt Enable bit n.

2. PCINTn is Pin Change Interrupt input n.

Notes: 1. PCINTn is Pin Change Interrupt Enable bit n.

2. PCINTn is Pin Change Interrupt input n.

Table 36. Overriding Signals for Alternate Functions in PC7..PC4

Signal Name PC7/A15/TDI

/PCINT15 PC6/A14/TDO

/PCINT14 PC5/A13/TMS

/PCINT13 PC4/A12/TCK

/PCINT12

PUOE (XMM < 1) •

SRE + JTAGEN (XMM < 2) •

SRE +JTAGEN (XMM < 3) •

SRE + JTAGEN (XMM < 4) •

SRE + JTAGEN

PUOV JTAGEN JTAGEN JTAGEN JTAGEN

DDOE SRE • (XMM<1)

+ JTAGEN SRE • (XMM<2)

+ JTAGEN SRE • (XMM<3)

+ JTAGEN SRE • (XMM<4)

+ JTAGEN

DDOV JTAGEN JTAGEN +

JTAGEN •

(SHIFT_IR |

SHIFT_DR)

JTAGEN JTAGEN

PVOE SRE • (XMM<1) SRE • (XMM<2)

+ JTAGEN SRE • (XMM<3) SRE • (XMM<4)

PVOV A15 if (JTAGEN) then

TDO

else A14

A13 A12

DIEOE(1) JTAGEN |

PCIE1 •

PCINT15

JT AGEN | PCIE1

• PCINT14 JTAGEN |

PCIE1 •

PCINT13

JTAGEN |

PCIE1 •

PCINT12

DIEOV JTAGEN JTAGEN JTAGEN JTAGEN

DI(2) PCINT15PCINT14PCINT13PCINT12

AIO TDI – TMS TCK

Table 37. Overriding Signals for Alternate Functions in PC3..PC0

Signal Name PC3/A11/

PCINT11 PC2/A10/

PCINT10 PC1/A9/PCINT9 PC0/A8/PCINT8

PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)

PUOV0000

DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)

DDOV 1 1 1 1

PVOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)

PVOV A11 A10 A9 A8

DIEOE(1) PCIE1 •

PCINT11 PCIE1 •

PCINT10 PCIE1 • PCINT9 PCIE1 • PCINT8

DIEOV 1 1 1 1

DI(2) PCINT11 PCINT10 PCINT9 PCINT8

AIO – – – –

ATmega162/V

2513H–AVR–04/06

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 38.

The alternate pin configuration is as follows:

•RD

– Port D, Bit 7

RD is the external data memo ry read control strobe.

•W

R – Port D, Bit 6

WR is the external data memory write control strobe.

• TOSC2/OC1A – Port D, Bit 5

TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asyn-

chronous clocking of Timer/Counter2, pin PD5 is disconnected from the port, and

becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator

is connected to this pin, and the pin can not be used as an I/O pin.

OC1A, Output Compare Match A output: The PD5 pin can serve as an external output

for the Timer/Counter1 Output Compare A. The pin has to be configured as an output

(DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the

PWM mode timer function.

Table 38. Port D Pins Alternate Fun ctions

Port Pin Alternate Function

PD7 RD (Read strobe to external memory)

PD6 WR (Write strobe to external memory)

PD5 TOSC2 (Timer Oscillator Pin 2)

OC1A (Timer/Counter1 Output Compare A Match Output)

PD4 TOSC1 (Timer Oscillator Pin 1)

XCK0 (USART0 Exter nal Clock Input/Output)

OC3A (Timer/Counter3 Output Compare A Match Output)

PD3 INT1 (External Interrupt 1 Input)

ICP3 (Timer/Counter3 Input Capture Pin)

PD2 INT0 (External Interrupt 0 Input)

XCK1 (USART1 Exter nal Clock Input/Output)

PD1 TXD0 (USART0 Output Pin)

PD0 RXD0 (USART0 Input Pin)

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• TOSC1/XCK0/ OC3A – Port D, Bit 4

TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asyn-

chronous clocking of Timer/Counter2, pin PD4 is disconnected from the port, and

becomes the input of the inverting Oscillator Amplifier. In this mode, a crystal Oscillator

is connected to this pin, and the pin can not be used as an I/O pin.

XCK0, USART0 External Clock: The Data Direction Register (DDD4) controls whether

the clock is output (DDD4 set (one)) or input (DDD4 cleared (zero)). The XCK0 pin is

active only when USART0 operates in Synchronous mode.

OC3A, Output Compare Match A output: The PD4 pin can serve as an external output

for the Timer/Counter1 Output Compare A. The pin has to be configured as an output

(DDD4 set (one)) to serve this function. The OC4A pin is also the output pin for the

PWM mode timer function.

• INT1/ICP3 – Port D, Bit 3

INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt

source.

ICP3, Input Capture Pin: The PD3 pin can act as an Input Capture pin for

Timer/Counter3.

• INT0/XCK1 – Port D, Bit 2

INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt

source.

XCK1, USART1 External Clock: The Data Direction Register (DDD2) controls whether

the clock is output (DDD2 set (one)) or input (DDD2 cleared (zero)). The XCK1 pin is

active only when USART1 operates in Synchronous mode.

• TXD0 – Port D, Bit 1

TXD0, Transmit Data (Data output pin for USART0). When the USART0 Transmitter is

enabled, this pin is configured as an output regardless of the value of DDD1.

ATmega162/V

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• RXD0 – Port D, Bit 0

RXD0, Receive Data (Data input pin for USART0). When the USART0 Receiver is

enabled this pin is configured as an input regardless of the value of DDD0. When

USART0 forces this pin to be an input, the pull-up can still be controlled by the PORTD0

bit.

Table 39 and Table 40 relate the alternate functions of Port D to the overriding signals

shown in Figure 32 on page 69.

Table 39. Overriding Signals for Alternate Functions PD7..PD4

Signal Name PD7/RD PD6/WR PD5/TOSC2/OC1A PD4/TOSC1/XCK0/OC3A

PUOE SRE SRE AS2 AS2

PUOV 0 0 0 0

DDOE SRE SRE AS2 AS2

DDOV 1 1 0 0

PVOE SRE SRE OC1A ENABLE XCK0 OUTP UT ENA BLE |

OC3A ENABLE

PVOV RD WR OC1A if (XCK0 OUTPUT

ENABLE) then

XCK0 OUTPUT

elseOC3A

DIEOE 0 0 AS2 AS2

DIEOV 0 0 0 0

DI – – – XCK0 INPUT

AIO – – T/C2 OSC OUTPUT T/C2 OSC INPUT

Table 40. Overriding Signals for Alternate Functions in PD3..PD0

Signal Name PD3/INT1 PD2/INT0/XCK1 PD1/TXD0 PD0/RXD0

PUOE 0 0 TXEN0 RXEN0

PUOV 0 0 0 PORTD0 • PUD

DDOE 0 0 TXEN0 RXEN0

DDOV 0 0 1 0

PVOE 0 XCK1 OUTPUT ENABLE TXEN0 0

PVOV 0 XCK1 TXD0 0

DIEOE INT1 ENABLE INT0 ENABLE 0 0

DIEOV 1 1 0 0

DI INT1 INPUT/

ICP1 INPUT INT0 INPUT/XCK1 INPUT – RXD0

AIO – – – –

ATmega162/V

2513H–AVR–04/06

Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 41.

The alternate pin configuration is as follows:

• OC1B – Port E, Bit 2

OC1B, Output Compare Match B output: The PE2 pin can serve as an external output

for the Timer/Counter1 Output Compare B. The pin has to be configured as an output

(DDE0 set (one) ) to serv e this func tion. The O C1B pin is also the o utput pin for the PWM

mode timer function.

Table 42 rel ate the alterna te function s of Port E to the over riding signals shown in Figure

32 on page 69.

•ALE – Port E, Bit 1

ALE is the external data memory Address Latch Enable signal.

• ICP1/INT2 – Port E, Bit 0

ICP1, Input Capture Pin: The PE0 pin can act as an Input Capture pin for

Timer/Counter1.

INT2, External Interrupt Source 2: The PE0 pin can serve as an external interrupt

source.

Table 41. Port E Pins Alternate Functions

Port Pin Alternate Function

PE2 OC1B (Timer/Counter1 Output CompareB Match Output)

PE1 ALE (Address Latch Enable to external memory)

PE0 ICP1 (Timer/Counter1 Input Capture Pin)

INT2 (External Interrupt 2 Input)

Table 42. Overriding Signals for Alternate Functions PE2..PE0

Signal Name PE2 PE1 PE0

PUOE 0 SRE 0

PUOV 0 0 0

DDOE 0 SRE 0

DDOV 0 1 0

PVOE OC1B ENABLE SRE 0

PVOV OC1B ALE 0

DIEOE 0 0 INT2 ENABLED

DIEOV 0 0 1

DI 0 0 INT2 INPUT/ ICP1 INPUT

AIO – – –

ATmega162/V

2513H–AVR–04/06

I/O-Ports

Port A Data Register – PORTA

P ort A Data Direct ion Register

– DDRA

Port A Input Pins Address –

PINA

Port B Data Register – PORTB

P ort B Data Direct ion Register

– DDRB

Port B Input Pins Address –

PINB

Port C Data Register – PORTC

P ort C Data Direct ion Register

– DDRC

Bit 76543210

PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

ATmega162/V

2513H–AVR–04/06

Port C Input Pins Address –

PINC

Port D Data Register – PORTD

P ort D Data Direct ion Register

– DDRD

Port D Input Pins Address –

PIND

Port E Data Register – PORTE

P ort E Data Direction Register

– DDRE

Port E Input Pins Address –

PINE

Bit 76543210

PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

–––––PORTE2PORTE1PORTE0PORTE

Read/WriteRRRRRR/WR/WR/W

Initial Value00000000

Bit 76543210

–––––DDE2DDE1DDE0DDRE

Read/WriteRRRRRR/WR/WR/W

Initial Value00000000

Bit 76543210

–––––PINE2PINE1PINE0PINE

Read/WriteRRRRRRRR

Initial Value00000N/AN/AN/A

ATmega162/V

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External Interrupts The External Interrupts are triggered by the INT0, INT1, INT2 pin, or any of the

PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2..0

or PCINT15..0 pi ns are configu red as outputs. This feature pr ovides a way of gener ating

a software interrupt. The External Interrupts can be triggered by a falling or rising edge

or a low level (INT 2 is only a n edge t r iggere d int errup t). This is set u p as indi cate d i n t he

specification for the MCU Control Register – MCUCR and Extended MCU Control Reg-

ister – EMCUCR. When the external interrupt is enabled and is configured as level

triggered (only INT0/INT1), the interrupt will trigger as long as the pin is held low. The

pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change

interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK1 and

PCMSK0 Registers control which pins contribute to the pin change interrupts. Note that

recognition of f alling or ri sing edge inter rupts o n INT0 a nd I NT1 requir es the p resence of

an I/O clock, described in “Clock Systems and their Distribution” on page 35. Low level

interrupts on INT0/INT1, the edge interrupt on INT2, and Pin change interrupts on

PCINT15..0 are det ected asynchron ously. This implies that the se interrupts can be used

for waking the part also from sleep modes other than Idle mode. The I/O clock is halted

in all sleep modes except Idle mode.

Note that if a level triggered interr upt is used for wake-up from Power-down mode, the

changed level must be held for some time to wake up the MCU. This makes the MCU

less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator

clock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The

frequency of the Watchdog Oscillator is voltage dependent as shown in “Electrical Char-

acteristics” on page 266. The MCU will wake up if the input has the required level during

this sampling or if it is held until the end of the start-up time. The start-up time is def ined

by the SUT Fuses as described in “System Clock and Clock Options” on page 35. If the

level is sampled twice by the Watchdog Oscillator clock but disappears befo re the end

of the start-up time, the MCU will still wake up, but no interrupt will be generated. The

required level must be held long enough for the MCU to complete the wake up to trigger

the level interrupt.

MCU Control Register –

MCUCR The MCU Control Register contains control bits for interrupt sense control and general

MCU functions.

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the

corresponding interrupt mask in the GICR are set. The level and edges on the external

INT1 pin that activate the interrupt are defined in Table 43. The value on the INT1 pin is

sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last

longer than one clock period will generate an interrupt. Shorter pulses are not guaran-

teed to generat e an in te rr upt. If low level in te rrup t is sele ct ed , th e low level must be held

until the completion of the currently executing instruction to generate an interrupt.

Bit 76543210

SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding int errupt mask are set. The level and edges on the external INT0 pin that

activate the interrupt are defined in Table 44. The value on the INT0 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer

than one clock period will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until

the completion of the currently executing instruction to generate an interrupt.

Extended MCU Control

• Bit 0 – ISC2: Interrupt Sense Control 2

The asynchronous External Interrupt 2 is a ctivated by the external pin INT2 if the SREG

I-bit and the corr esponding interrupt mask in GI CR are set. If ISC2 is cleared (zero) , a

falling edge on INT2 activates the interrupt. If ISC2 is set (one), a rising edge on INT2

activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT2

wider than the minimum pulse width given in Table 45 will generate an interrupt. Shorter

pulses are not gua ranteed to generate an interrupt. Wh en changing the ISC2 bit, an

interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its

Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally,

the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit

(INTF2) in the GIFR Register before the interrupt is re-enabled.

Table 43. Interrupt 1 Sense Control

ISC11 ISC10 Description

0 0 The low level of INT1 generates an interrupt request.

0 1 Any logical change on INT1 generates an interrupt request.

1 0 The falling edge of INT1 generates an interrupt request.

1 1 The rising edge of INT1 generates an interrupt request.

Table 44. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Any logical change on INT0 generates an interrupt request.

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

Bit 76543210

SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 45. Asynchronous External Interrupt Characteristics

Symbol Parameter Condition Min. Typ. Max. Units

tINT Minimum pulse width for

asynchronous e xternal interrupt 50 ns

ATmega162/V

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General Interrupt Control

• Bit 7 – INT1: External Interrupt Request 1 Enab le

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enable d. The Interrupt Sen se Control1 bits 1/0 ( ISC11 and

ISC10) in the MCU general Control Register (MCUCR) define whether the external

interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity

on the pin will cause an interrupt request even if INT1 is configured as an output. The

corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Inter-

rupt Vector.

• Bit 6 – INT0: External Interrupt Request 0 Enab le

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enable d. The Interrupt Sen se Control0 bits 1/0 ( ISC01 and

ISC00) in the MCU general Control Register (MCUCR) define whether the external

interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity

on the pin will cause an interrupt request even if INT0 is configured as an output. The

corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter-

rupt Vector.

• Bit 5 – INT2: External Interrupt Request 2 Enab le

When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control2 bit (ISC2) in the

Extended MCU Control Register (EMCUCR) defines whether the external interrupt is

activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an inter-

rupt request even if INT2 is configured as an output. The corresponding interrupt of

External Interrupt Request 2 is executed from the INT2 Interrupt Vector.

• Bit 4 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will

cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-

cuted from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the

PCMSK1 Register.

• Bit 3 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause

an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed

from the PCI0 Inte rru p t Vec tor. PCINT7..0 pins are enabled individually by the PCMSK0

Bit 76543210

INT1 INT0 INT2 PCIE1 PCIE0 –IVSEL IVCE GICR

Read/Write R/W R/W R/W R/W R/W R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

ATmega162/V

2513H–AVR–04/06

General Interrupt Flag

• Bit 7 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1

becomes set (one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU

will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt

routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

This flag is always cleared when INT1 is configured as a level interrupt.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0

becomes set (one). If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU

will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt

routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

This flag is always cleared when INT0 is configured as a level interrupt.

• Bit 5 – INTF2: External Interrupt Flag 2

When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one).

If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrup t routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. Note that when enter-

ing some sleep mode s with the INT2 interrupt disabled, th e input buffer on this pin will

be disabled. This may cause a logic change in internal signals which will set the INTF2

flag. See “Digital Input Enable and Sleep Modes” on page 68 for more information.

• Bit 4 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1

becomes set (one). If the I-bit in SREG and the PCIE1 bit in GICR are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it.

• Bit 3 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0

becomes set (one). If the I-bit in SREG and the PCIE0 bit in GICR are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it.

Bit 76543210

INTF1 INTF0 INTF2 PCIF1 PCIF0 – – –GIFR

Read/Write R/W R/W R/W R/W R/W R R R

Initial Value 0 0 0 0 0 0 0 0

ATmega162/V

2513H–AVR–04/06

Pin Change Mask Regist er 1 –

PCMSK1

• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8

Each PCINT15..8 bit selects whet her pin chang e interrupt is en abled on the corr espond-

ing I/O pin. If PCINT15..8 is set and the PCIE1 bit in GICR is set, pin change interr upt is

enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on

the corresponding I/O pin is disabled.

Pin Change Mask Regist er 0 –

PCMSK0

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each PCINT7..0 bit selects whether pin change interrupt is enabled on the correspond-

ing I/O pin. If PCINT7..0 is set and the PCIE0 bit in GICR is set, pin change interrupt is

enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on

the corresponding I/O pin is disabled.

The mapping between I/O pins and PCINT bits ca n be found in Figur e 1 on page 2. No te

that the Pin Change Mask Register are located in Extended I/O. Thus, the pin change

interrupts are not supported in ATmega161 compatibility mode.

Bit 76543210

PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT9 PCMSK1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

ATmega162/V

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8-bit Timer/Counter0

with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The

main features are:

•Single Channel Counter

•Clear Timer on Compare Match (A uto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Frequency Generator

•External Event Counter

•10-bit Clock Prescaler

•Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 33. For the

actual placement of I/O pins, refer to “Pinout ATmega162” on pag e 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

page 101.

Figure 33. 8-bit Timer/Counter Block Diagram

Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers.

Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer

Interrupt Flag Register (TIFR). All interrupts are individually m asked with the Timer

Interrupt Mask Register (TIM SK). TIFR and TIMSK are not shown in the figure since

these registe rs ar e sh ar ed by oth e r tim er units .

The Timer/Counter ca n be clocked internally, via the p rescaler, or by an external clock

source on the T0 pin. The Clock Select logic block controls which cloc k source and edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

Timer/Counter

DATA BUS

TCNTn

Waveform

Generation OCn

= 0

Control Logic

0xFF

BOTTOM

count

clear

direction

TOVn

(Int.Req

OCRn

TCCRn

Clock Select

Edge

Detector

( From Prescaler )

clkTn

TOP

OCn

(Int.Req.

)

ATmega162/V

2513H–AVR–04/06

inactive when no clock source is selected. The output from the clock select logic is

referred to as the timer clock (clkT0).

The double buffered Output Compare Register (OCR0) is compared with the

Timer/Counter value at all times. Th e result of the compare can be used by the Wave-

form Generat or to gener ate a PWM or vari able frequency ou tput on t he Output Co mpare

pin (OC0). See “Output Compare Unit” on page 92. for details. The Compare Match

event will also set the Compare Flag (OCF0) which can be used to generate an output

compare interrupt request.

Definitions Many register and bit ref ere nces in this se ct ion ar e wr itt en in g ene ral fo rm . A lo wer case

“n” replaces the Timer/Counter number, in this case 0. However, when using the register

or bit defines in a program, the precise form must be used i.e., TCNT0 for accessing

Timer/Counter0 counter value and so on.

The definitions in Table 46 are also used extensively throughout the document.

Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the Clock Select logic which is controlled by the Clock Select

(CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details o n

clock sources and prescaler, see “Timer/Counter0, Timer/Counter1, and

Timer/Counter3 Prescalers” on page 105.

Table 46. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX The counter reach es its MAXimum when it becom es 0xFF (decimal 255).

TOP The counter reaches the T OP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The

assignment is depen dent on the mode of operation.

ATmega162/V

2513H–AVR–04/06

Counter Unit The main part of the 8-bi t Timer/ Counter is th e progra mmable bi-d irection al counter unit .

Figure 34 shows a block diagram of the count er and its surroundings.

Figure 34. Counter Unit Block Diagr am

Signal description (internal signals):

count Increment or decrement TCNT0 by 1.

direction Select between increment and decrement.

clear Clear TCNT0 (set all bits to zero).

clkTnTimer/Counter clo ck, re fe rr ed to as clk T0 in the following.

top Signalize that TCNT0 has reached maximum value.

bottom Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or dec-

remented at each timer clock (clk T0). clkT0 can be gener ated from an exte rnal or internal

clock source, selected by the clock select bits (CS02:0). When no clock source is

selected (CS02:0 = 0) t he timer is st opped. However, the TCNT0 value ca n be accessed

by the CPU, regardless of whether clkT0 is present or not. A CPU write overr ides (has

priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits

located in the Time r/Counter Control Register (TCCR0). There are close co nnections

between how the counter behaves (counts) and how waveforms are generated on the

output Compare Outpu t OC0. For more details about advanced counting sequences

and waveform gener ation, see “Modes of Operation” on page 95.

The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation

selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register

(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will

set the Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 =

1 and Globa l Inter rupt Fla g in SREG is se t), t he Ou tput Com pare Flag ge nerate s an out-

put compare interrupt. The OCF0 Flag is automatically cleared when the interrupt is

executed. Alternatively, the OCF0 Flag can be cleared by software by writing a logical

one to its I/O bit loca tio n. Th e wavef orm g en erat or uses the mat ch sign al t o gene ra te an

output according to operating mode set by the WGM01:0 bits and Compare Output

mode (COM01:0) bits. The max and bottom sig nals are used by the waveform gener ator

for handling the special cases of the extreme values in some modes of operation (See

“Modes of Operation” on page 95.).

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clkTn

bottom

direction

clear

ATmega162/V

2513H–AVR–04/06

Figure 35 shows a block diagram of the output compare unit.

Figure 35. Output Compare Unit, Block Diagram

The OCR0 Register is double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the Nor mal and Clear Timer on Compare (CTC) mo des of operatio n,

the double bu ffering is disabled. The double buffering synchronizes the upd ate of the

OCR0 Compare Register to either to p or bottom of t he counting se quence. The synchro-

nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby

making the output glitch-free.

The OCR0 Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has access to the OCR0 Buffer Register, and if double

buffering is disabled the CPU will access the OCR0 direc tly.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Outpu t Compare (FOC0) bit. Forcing Co mpare

Match will not set the OCF0 Flag or reload/clear the Timer, but the OC0 pin will be

updated as if a real Compare Match ha d occurred (the COM01:0 bits settings define

whether the OC0 pin is set, cleared or toggled).

Compare Match Bloc king by

TCNT0 Write All CPU write operations to the TCNT0 Register will block any Compare Match that

occur in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR0 to be initialized to the same value as TCNT0 without triggering an interrupt when

the Timer/Counter clock is enabled.

OCFn (Int.Req

= (8-bit Comparator )

OCRn

OCn

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

ottom

ATmega162/V

2513H–AVR–04/06

Using the Output Compare

Unit Since writing TCNT0 in any mode of operation will block all compare matches for one

timer clock cycle, there are risks involved when changing TCNT0 when using the output

compare chann el, independently of whether the Timer/Counter is running or not. If the

value written to TCNT0 equals the OCR0 value, the Compare Match will be missed,

resulting in incorrect waveform genera tion. Similarly, do not write the TCNT0 value

equal to BOTTOM when the counter is down-counting.

The setup of the OC0 shou ld be performed before setting t he Data Direct ion Register for

the port pin to output. The easiest way of setting the OC0 value is to use the Force Out-

put Compare (FOC0) strobe bits in Normal mode. The OC0 Register keeps its value

even when changing between Waveform Generation modes.

Be aware that the COM01:0 bits are not double buffered together with the compare

value. Changing the COM01:0 bits will take effect immediately.

Compare Match Output

Unit The Compare Out put mode (COM 01:0) bits have two funct ions. The Wavef orm Ge nera-

tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next

Compare Match. Also, the COM01:0 bits control the OC0 pin output source. Figure 36

shows a simplified sc hematic of the logic a ffected by the COM01:0 bit setting. The I/O

Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the

general I/O Port Control Registers (DDR and PORT) that are affected by the COM01:0

bits are shown. When referring to the OC0 state, the reference is for the internal OC0

Figure 36. Compare Match Output Unit, Schematics

The general I/O port function is overridden by the Output Compare (OC0) from the

waveform generator if either of the COM01:0 bits are set. However, the OC0 pin direc-

tion (input or output) is still controlled by the Data Direction Register (DDR) for the port

pin. The Data Direction Register bit for the OC0 pin (DDR_OC0) must be set as output

before the OC0 value is visible on the pin. The port override function is independent of

the Waveform Generation mode.

PORT

DDR

OCn

Waveform

Generator

OMn1

OMn0

DATA BUS

OCn

clkI/O

ATmega162/V

2513H–AVR–04/06

The design of the output compare pin lo gic allows initialization of the OC0 state before

the output is enabled. Note that some COM01:0 bit settings are reserved for certain

modes of operation. See “8-bit Timer/Counter Register Description” on page 101.

Compare Output Mode and

Waveform Generation The Waveform Generator uses the COM01:0 bits differently in Normal, CTC, and PWM

modes. For all modes, setting the COM01:0 = 0 tells the Waveform Generator that no

action on the OC0 Register is to be performed on the next Compare Match. For Com-

pare Output actions in the non-PWM modes refer to Table 48 on page 102. For fast

PWM mode, refer to Table 49 on page 102, a nd for phase co rrect PWM refer to T able

50 on page 102.

A change of the COM01:0 bits state will have effect at the first Compare Match after the

bits are written. For non-PWM mod es, the action can be forc ed to have immediate effect

by using the FOC0 strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and

Compare Output mode (COM 01:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM01:0

bits control whether the PWM output genera ted should be inverted or not (inverte d or

non-inverted PWM). For non-PWM modes the COM01:0 bits control whether the output

should be set, cleared, or toggled at a Compare Match (See “Compar e Match Output

Unit” on page 94.).

For detailed timing information refer to Figure 40, Figure 41, Figure 42 and Figure 43 in

“Timer/Counter Timing Diagrams” on page 99.

Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the

counting direction is a lways up (incrementing) , and no counte r clear is performe d. The

counter simply overrun s whe n it passes it s maximum 8-bit va lue (T OP = 0xFF) and t hen

restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag

(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The

TOV0 Flag in this case beha ves like a ninth bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt that automatically clears the TOV0

Flag, the timer resolution can be increase d by software. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The output compare unit can be used to generate interrupts at some given time. Using

the output compare to generate waveforms in Normal mode is not recommended, since

this will occupy too much of the CPU time.

Clear Timer on Compare

Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to

manipulate the coun te r re so luti on . I n CT C mo de t he coun te r is cleared to zero when the

counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the

counter, hence also its resolution. This mode allows greater control of the Compare

Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 37. The counter value

(TCNT0) increase s until a Compare Ma tch occurs b etween T CNT0 and OCR0, and then

counter (TCNT0) is cleared.

ATmega162/V

2513H–AVR–04/06

Figure 37. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by

using the OCF0 Flag. If the interrupt is en abled, the interrupt handler routine can be

used for updatin g the TOP value. However, changing TOP to a value close to BOTTOM

when the counter is running with none or a low prescaler value must be done with care

since the CTC mode d oes not h ave th e double buffer ing feat ure. If the new value wr itten

to OCR0 is lower than the current value of TCNT0, the counter will miss the C ompare

Match. The counter will then have to count to its maximum value (0xFF) and wrap

around star ting at 0x 00 bef or e th e Com p ar e Mat ch can occur.

For generating a wavef orm out pu t in CT C mode, the OC0 output ca n be set to toggle its

logical level on each Comp are Match by set ting th e Compare Out put mode b its to to ggle

bitmode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the

data direction for the pin is set to output. The waveform generated will have a maximum

frequency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x 00). The waveform frequency

is defined by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of oper at ion, t he TOV0 F lag is set in the sam e t imer cloc k cycle

that the counter counts from MAX to 0x00.

Fast PWM Mode The fast Pu lse Width Mo dulat ion or fast PWM mod e (WGM01:0 = 3) prov ides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM

option by its single-slope operation. The counter coun ts from BOTTO M to MAX then

restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare

(OC0) is cleared on the Compare Match between TCNT0 and OCR0, and set at BOT-

TOM. In inverting Compare Output mode, the output is set on Compare Match and

cleared at BOTTOM. Due to the single- slope operation, the operating frequ ency of the

fast PWM mode can be twice as high as the phase correct PWM mode that use dual-

slope operation. This high frequency makes the fast PWM mode well suited for power

regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefor e reduces total system cost.

In fast PWM mode, th e co un ter is increme nt ed unt il the count er value mat c hes the MAX

value. The counter is then cleared at the following timer clock cycle. The timing diagram

for the fast PWM mode is shown in Figure 38. The TCNT0 value is in t he timi ng diag ram

shown as a histogram for illustrating the single-slope operation. The diagram includes

CNTn

(

Toggle)

OCn Interrupt Flag Set

1 4

eriod

2 3

(COMn1:0 = 1)

fOCn fclk_I/O

2N1OCRn+()⋅⋅

-----------------------------------------------=

ATmega162/V

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non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0

slopes represent compare matches between OCR0 and TCNT0.

Figure 38. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If

the interrupt is enabled, the interrupt handler routine can be used for updating the com-

pare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0

pin. Setting the COM01:0 bits to two will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COM01:0 to three (See Table 49 on page

102). The actual OC0 value will only be visible on the port pin if the data direction for the

port pin is set as output. The PWM waveform is generated by setting (or clearing) the

OC0 Register at the Compare Match between OCR0 and TCNT0, and clearing (or set-

ting) the OC0 Register at the timer clock cycle the counter is cleared (changes from

MAX to BOTTOM).

The PWM frequency for th e output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0 Register represents special cases when generating a

PWM waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the

output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal

to MAX will result in a constantly high or low output (depending on the polarity of the out-

put set by the COM01:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OC0 to toggle its logi cal level on each Compare Ma tch (COM01:0 = 1). The

waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0 is

set to zero. This feature is similar to the OC0 toggle in CTC mode, except the doub le

buffer feat ure of the output compare unit is enabled in the fast PWM mode.

TCNTn

OCRn Update ans

TOVn Interrupt Flag Set

Period 2 3

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

4 5 6 7

fOCnPWM fclk_I/O

N256⋅

------------------=

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Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-

slope operation. The counter counts repeatedly from BOTTOM to MAX and then from

MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0)

is cleared on the Compare Match between TCNT0 an d OCR0 while up-counting, and

set on the Compar e Match while do wn-counting . In inver ting Output Comp are mode , the

operation is inverted. The dual-slop e operation ha s lower maxim um operat ion frequency

than single slope operation. However, due to the symmetric feature of the dual-slope

PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase

correct PWM mo de the counter is incr emented until the counte r value matches MAX.

When the counter reaches MAX, it changes the count direction. The TCNT0 value will

be equal to MAX for one timer clock cycle. The timing diagram for the phase correct

PWM mode is shown on Figure 39. The TCNT0 value is in the timing diagram shown as

a histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The sm all horizont al line marks on the TCNT0 slope s r epre-

sent compare matches between OCR0 and TCNT0.

Figure 39. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT-

TOM. The Interrupt Flag can be use d to generate an interrupt each time the counter

reaches the BOTTOM value.

In phase corr ect PWM mode, the compare uni t allows generation of PWM waveforms on

the OC0 pin. Setting the COM01:0 bits to two will produce a non-inverted PWM. An

inverted PWM output can be generated by setting the COM01:0 to three (See Table 50

on page 102). The actual OC0 value will only be visible on the port pin if the data direc-

tion for the port pin is set a s output. The PWM waveform is gen erated by clearing (or

setting) the OC0 Register at the Compare Match between OCR0 and TCNT0 when the

counter increments, and setting (or clearing) the OC0 Register at Compare Match

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

1 2 3

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

ATmega162/V

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between OCR0 and TCNT0 when the counter decrements. The PWM frequency for the

output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0 Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

At the very start of period 2 in Figure 39 OCn has a transition from high to low even

though there is no Compar e Match. The poi nt of th is transit ion is to gu arantee symmetr y

around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR0 changes its value from MAX, lik e in Figure 39. When the OCR0 v alue is MAX

the OCn pin v alue is the same as the re sult of a do wn -counting Comp are Match . To

ensure symmetry around BOTTOM the OCn value at MAX must correspond to the

result of an up-counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0, and for that

reason misses the Compare Match and hence the OCn change that would have

happened on the way up.

Timer/Counter Timing

Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set. Figure 40 contains timing data for basic Timer/Counter

operation. The fig ure shows the count sequence close to th e MAX value in all modes

other than phase correct PWM mode.

Figure 40. Timer/Counter Timing Diagram, no Prescaling

Figure 41 shows the same timing data, but with the prescaler enabled.

fOCnPCPWM fclk_I/O

N510⋅

------------------=

clk

(clkI/O/1)

TOVn

clk

I/O

CNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

100

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Figure 41. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 42 shows the setting of OCF0 in all modes except CTC mode.

Figure 42. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8)

Figure 43 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.

Figure 43. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with

Prescaler (fclk_I/O/8)

TOVn

CNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

OCFn

OCRn

CNTn

OCRn Value

OCRn - 1 OCRn OCRn + 1 OCRn + 2

clk

I/O

clk

(clkI/O/8)

OCFn

OCRn

CNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

101

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8-bit Timer/Counter

Timer/Counter Control

• Bit 7 – FOC0: Force Output Compare

The FOC0 bit is only active when the WGM0 0 bit specifies a no n-PWM m ode. However,

for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is

written when operating in PWM mode. When writing a logical one to the FOC0 bit, an

immediate Compare Match is forced on the Waveform Generation unit. The OC0 output

is changed according t o its COM01:0 bits sett ing. Note that the FO C0 bit is implem ented

as a strobe. Therefore it is the value present in the COM01:0 bits that determines the

effect of the forced compare.

A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode

using OCR0 as TOP.

The FOC0 bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the coun ting sequence of the counter, the source for the maximum

(TOP) counter value , and what type of waveform generation to be use d. Modes of oper-

ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare

match (CTC) mode, a nd two t ypes of Pulse Width Modulatio n (PWM) modes. See Table

47 and “Modes of Oper ation” on page 95.

Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-

initions. However, the functionality and location of these bits are compatible with

previous versions of the timer.

• Bit 5:4 – COM01 :0: Compare Match Output Mode

These bits control the output compare pin (OC0) behavior. If one or both of the

COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O

pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-

sponding to the OC0 pin must be set in order to enable the outpu t driver.

Bit 76543210

FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0

Read/Write W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 47. Waveform Generation Mode Bit Description(1)

Mode WGM01

(CTC0) WGM00

(PWM0) Timer/Counter Mode

of Operation TOP Update of

OCR0 at TOV0 Flag

Set on

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM

2 1 0 CTC OCR0 Immediate MAX

3 1 1 Fast PWM 0xFF TOP MAX

102

ATmega162/V

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When OC0 is connected to the pin, the function of the COM01:0 bits depends on the

WGM01:0 bit setting. Tab le 48 sh ows the COM01:0 bit fun ctionalit y when the WGM01 :0

bits are set to a Normal or CTC mode (non-PWM).

Table 49 shows the COM01:0 bit fun ctionality when the WGM01:0 bits are set to fast

PWM mode.

Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the

Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM

Mode” on page 96 f or more details.

Table 50 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase

correct PWM mode.

Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the

Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct

PWM Mode” on page 98 for more details.

Table 48. Compare Output Mode, non-PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0 disconnected.

0 1 Toggle OC0 on Compare Match.

1 0 Clear OC0 on Compare Match.

1 1 Set OC0 on Compare Match.

Table 49. Compare Output Mode, fast PWM Mode(1)

COM01 COM00 Description

0 0 Normal port operation, OC0 disconnected.

01Reserved

1 0 Clear OC0 on Compare Match, set OC0 at TOP.

1 1 Set OC0 on Compare Match, clear OC0 at TOP.

Table 50. Compare Output Mod e, Phase Correct PWM Mode(1)

COM01 COM00 Description

0 0 Normal port operation, OC0 disconnected.

01Reserved

1 0 Clear OC0 on Compare Match when up-counting. Set OC0 on

Compare Match when down-counting .

1 1 Set OC0 on Compare Match when up-counting. Clear OC0 on

Compare Match when down-counting .

103

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• Bit 2:0 – CS02:0: Clock Se lect

The three Cloc k Select bits select the clock source to be used by the Timer/Counter.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the co unting.

Timer/Counter Register –

TCNT0

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)

the Compare Match on the following timer clock. Modifying the counter (TCNT0) while

the counter is running, introduces a risk of missing a Compare Ma tch between TCNT0

and the OCR0 Register.

Output Compare Register –

OCR0

The Output Compare Register contains an 8-bit value that is continuously compared

with the counter value (TCNT0). A match can be used to generate an output compare

interrupt, or to generate a waveform output on the OC0 pin.

Timer/Counter Interrupt Mask

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 b it is writ te n to o ne, and t he I-bit in the St atus Re giste r is se t ( one), t he

Timer/Counter0 Ov erflow interr upt is enabled . The correspond ing interrupt is executed if

an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the

Timer/Counter Interrupt Flag Register – TIFR.

Table 51. Clock Select Bit Description

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped).

001clkI/O/(No prescaling)

010

clkI/O/8 (From prescaler)

011

clkI/O/64 (From prescaler)

100

clkI/O/256 (From prescaler)

101

clkI/O/1024 (From prescaler)

1 1 0 External clock source on T0 pin. Clock on falling edge.

1 1 1 External clock source on T0 pin. Clock on rising edge.

Bit 76543210

TCNT0[7:0] TCNT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR0[7:0] OCR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

104

ATmega162/V

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• Bit 0 – OCIE0: Timer/Counter0 Out put Compare Match Interrupt Enable

When the OCIE0 bit is writt en to one, and th e I- bit in t he Stat us Registe r is set (o ne), the

Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is

executed if a Compare Ma tch in Timer/Co unter0 occurs, i.e., when the OCF0 bit is set in

the Timer/Counter Interrupt Flag Register – TIFR.

Timer/Counter Interrupt Flag

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0

(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the

Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is

set when Timer/Counter 0 changes counting direction at 0x00.

• Bit 0 – OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0

and the data in OCR0 – Outp ut Compare Regist er0. OCF0 is cleared by har dware when

executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by

writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counte r0 Com-

pare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare

Match Interrupt is executed.

Bit 76543210

TOV1 OCF1A OCF1B OCF2 ICF1 TOV2 TOV0 OCF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

105

ATmega162/V

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Timer/Counter0,

Timer/Counter1, and

Timer/Counter3

Prescalers

Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler mod-

ule, but the Timer /Counters can have different prescaler settings. The description below

applies to Timer/Counter3, Timer/Counter1, and Timer/Counter0.

Internal Clock Source The Timer/Counter can be clocked dire ctly by th e syst em clock (by set t ing the CSn 2:0 =

1). This provides the fastest operation, w ith a maximum Timer/Counter clock frequency

equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the pres-

caler can be used as a clock source. The presca led clock has a frequency of either

fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, o r fCLK_I/O/1024. In addition, Timer/Counter 3 has the

option of choosing fCLK_I/O/16 and fCLK_I/O/32.

Prescaler Reset The prescaler is free running, i.e., op erates inde pende ntly of the clock select logic o f the

Timer/Counter, and it is shared by Timer/Counter3, Timer/Counter1, and

Timer/Counter0. Since the prescaler is not affected by the Timer/Counter’s clock select,

the state of the prescaler will have implications for situations where a prescaled clock is

used. One example of prescaling artifacts occurs when the Timer is enabled and

clocked by th e prescaler (6 > CSn2 :0 > 1). The number of system clock cycles from

when the Timer is enabled to the first count occurs can be from 1 to N+1 system clock

cycles, where N equals the prescaler divisor (8, 64, 256, or 1024, additional selections

for Timer/Counter3: 32 and 64).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program

execution. However, care must be taken if the other Timer/Counter that shares the

same prescaler also uses prescaling. A Presca ler Reset will affect the prescaler period

for all Timer/Counters it is connected to.

External Clock Source An external clock source applied to the Tn/T0 pin can be used as Time r/Counter clock

(clkT1/clkT0) for Timer/Counter1 and Timer/Counter0. The Tn/T0 pin is sampled once

every system clock cycle by the pin synchronization logic. The synchronized (sampled)

signal is then passed through the edge de tector. Figure 44 sho ws a functional equiva-

lent block diagram of the Tn/T0 synchronization and edg e detector logic. The registers

are clocked at the positive edge of the internal system clock (clkI/O). The latch is trans-

parent in the high period of the internal system clock.

The edge det ector gener ates one clkT1/clkT0 pulse for each positive ( CSn2:0 = 7) or neg-

ative (CSn2:0 = 6) edge it detects.

Figure 44. Tn/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system

clock cycles from an edge has been applied to the Tn/T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn/T0 has been stable for

at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock

pulse is generated.

Tn_sync

(To Clock

Select Logic)

Edge DetectorSynchronization

DQDQ

clkI/O

106

ATmega162/V

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Each half period of the external clock applied must be longer than one system clock

cycle to ensure correct sampling. The external clock must be guaranteed to have less

than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since

the edge detector uses sampling, the maximum frequency of an external clock it can

detect is half the samplin g fr eq uency (Nyqu i st sa mpli ng t heo rem). However , due t o va ri-

ation of the system clock frequency and duty cy cle caused by Oscillator source (cry stal,

resonator, and capacit ors) tolerances, it is recomm ended that maximum freq uency of an

external clock source is less than fclk_I/O/2.5.

An external clock source can not be presca le d.

Figure 45. Prescaler for Timer/Counter0, Timer/Counter1, and Timer/Counter3(1)

Note: 1. The synchronization logic on the input pins (Tn/T0) is shown in Figure 44.

Special Function IO Register –

SFIOR

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM b it to one activates the Time r/Counter Synchronization mod e. In this

mode, the value that is written to the PSR2 and PSR310 bits is kept, hence keeping the

corresponding prescaler reset signals asserted. This e nsures that the corresponding

Timer/Counters are halted and can be configured to the same value without the risk of

one of them advancing during configuration. When the TSM bit is written to zero, the

PSR2 and PSR310 bits are cleared by har dware, and the Timer/Coun te rs star t counting

simultaneously.

• Bit 0 – PSR310: Presc aler Reset Timer/Counter3, Timer/Counter1, and

Timer/Counter0

When this bit is one, the Timer/Counter3, Timer/Counter1, and Timer/Counter0 pres-

caler will be reset. This bit is normally cleared immediately by hardware, except if the

TSM bit is set. Note that Timer/Counter3, Timer/Coun ter1, and Timer/Counter0 share

the same prescaler and a reset of this prescaler will affect all three timers.

PSR321

Clear

clk

TIMER/COUNTER1 CLOCK SOURCE

CS10

CS11

CS12

clk

TIMER/COUNTER1 CLOCK SOURCE

CS00

CS01

CS02

clk

TIMER/COUNTER3 CLOCK SOURCE

S30

S31

S32

10-BIT T/C PRESCALER

CK/8

CK/64

CK/256

CK/1024

CK/16

CK/32

Bit 7 6 5 4 3 2 1 0

TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

107

ATmega162/V

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16-bit Timer/Counter

(Timer/Counter1 and

Timer/Counter3)

The 16-bit Timer/Counter unit allows accurate program execution timing (event man-

agement), wave generation, and signal timing measurement. The main features are:

•True 16-bit Desi gn (i.e., allows 16-bit PWM)

•Two Independent Output Compare Units

•Double Buffered Output Compare Registers

•One Input Capture Unit

•Input Capture Noise Canceler

•Clear Timer on Compare Match (A uto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Variable PWM Period

•Frequency Generator

•External Event Counter

•Eight Independent Interrupt Sources (T O V1, OCF1A, OCF1B, ICF1, TO V3, OCF3A, OCF3B,

and ICF3)

Restriction in

ATmega161

Compatibility Mode

Note that in ATmega161 compatibility mode, only one 16-bits Timer/Counter is available

(Timer/Counter1).

Overview Most register and bit references in this section are written in general form. A lower case

“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Com-

pare unit chan nel. However, when using the reg ister or bit defines in a program , the

precise form must be used i.e. , TCNT1 for accessing Timer /Count er 1 counte r valu e and

so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 46. For the

actual placement of I/O pins, refer to “Pinout ATmega162” on pag e 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

on page 129.

108

ATmega162/V

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Figure 46. 16-bit Timer/Counter Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Table 32 on page 73, and Table 38 on page 79 for

Timer/Counter1 pin placement and descrip tion.

Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B), and Input Capture

accessing the 16-bit registers. These procedures are described in the section “Access-

ing 16-bit Registers” on page 110. The Timer/Counter Control Registe rs (TCCRnA/B)

are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated

to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR)

and Extended Timer Interrupt Flag Regist er (ETIFR). All interrupts are individually

masked with the Time r Interrupt Mask Register (TIMSK) and Extended Timer Interrup t

Mask Register (ETIMSK). (E)TIFR and (E)TIMSK are not shown in the figure since

these registers are shared by oth e r Tim e r un its.

The Timer/Counter ca n be clocked internally, via the p rescaler, or by an external clock

source on the T1 pin. The Clock Select logic block controls which cloc k source and edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

inactive when no clock source is selected. The output from the Clock Select logic is

referred to as the Time r Clo ck (clk Tn).

The double buffered Output Compare Registers (OCRnA/B) are compared with the

Timer/Counter value at all time. The result of th e compa re can be used by th e waveform

generator to generate a PWM or variable frequency output on the Output Compare pin

Clock Select

Timer/Counter

DATABUS

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clkTn

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(OCnA/B). See “Output Compare Units” on page 116. The Compare Match event will

also set the Compare Match Flag (OCFnA/B) which can be used to generate an output

compare interrupt request.

The Input Capture Register can capture the Timer/Coun ter value at a given external

(edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Compar-

ator pins (See “Analog Comparator” on page 197.) The Input Capture unit includes a

digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be

defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values.

When using OCRnA as TOP value in a PWM mode, the OCRnA Register can not be

used for generating a PWM output. However, the TOP value will in this case be double

buffered allowing the TOP value to be changed in run time. If a fixed TOP value is

required, the ICRn Register can be used as an alternative, freeing th e OCRnA to be

used as PWM output.

Definitions The following definitions are used extensively throughout the section:

Compatibility The 16-bit Timer/Coun ter has been u pdate d and improved fro m previous versions of the

16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier

version regarding:

• All 16-bit Timer/Counter related I/O Register a ddress locations, including Timer

Interrupt Registers.

• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt

Registers.

• Interrupt Vectors.

The following control bits have changed name, but have same functionality and register

location:

• PWMn0 is changed to WGMn0.

• PWMn1 is changed to WGMn1.

• CTCn is changed to WGMn2.

The following bits are added to the 16-bit Timer/Counter Control Registers:

• FOCnA and FOCnB are added to TCCRnA.

• WGMn3 is added to TCCRnB.

The 16-bit Timer/Counter has improvements that will affect the compatibility in some

special cases.

Table 52. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal

65535).

TOP The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be one

of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in

the OCRnA or ICRn Regist e r. The assignm ent is depen den t of th e mode

of operation .

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Accessing 16-bit

Registers The TCNTn, OCRnA/B, and ICRn are 16-bit registers that can be accessed by the AVR

CPU via the 8-b it data bus. The 16-bit register mu st be byte accessed using two read or

write operations. Each 1 6-bit time r has a sin gle 8-bit register for tem porary stor ing of the

high byte of the 16-b it acces s. The sa me Tem porar y Registe r is shared be twee n all 16-

bit registers within each 1 6-bit timer. Accessing th e low byte triggers the 16-bit read or

write operation. When the low byte of a 16-bit register is written by the CPU, the high

byte stored in the te mporary register, an d the low byte written are bo th copied into the

16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by

the CPU, the high byte of the 16-bit register is copied into the temporary register in the

same clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the

OCRnA/B 16-bit registe rs does not involve using the temporary register.

To do a 16-bit write, the high byte must be writte n be fo re the low byt e . For a 16 -b it r ea d,

the low byte must be read before the high byte.

The following code examples show how to access the 16-bit Timer Registers assuming

that no interru pts updates the temporary register. The same principle can be used

directly for accessing the OCRnA/B and ICRn Registers. Note that when using “C”, the

compiler handles the 16-bit access.

Note: 1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

e xtended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an inter-

rupt occurs between the two instructions accessing the 16-bit register, and the interrupt

code updates the temporary register by accessing the same or any other of the 16-bit

Timer Registers, then the result of the access outside the interrupt will be corrupted.

Assembly Code Examples(1)

...

; Set TCNTn to 0x01FF

ldi r17,0x01

ldi r16,0xFF

out TCNTnH,r17

out TCNTnL,r16

; Read TCNTn into r17:r16

in r16,TCNTnL

in r17,TCNTnH

...

C Code Examples(1)

unsigned int i;

...

/* Set TCNTn to 0x01FF */

TCNTn = 0x1FF;

/* Read TCNTn into i */

i = TCNTn;

...

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Therefore, when both the main code and the interrupt code update the temporary regis-

ter, the main code must disable the interrupts during the 16-bit access.

The following code examples show how to do an atomic read of the TCNTn Register

contents. Reading any of the OCRnA/B or ICRn Registers can be done by using the

same principle .

Note: 1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

e xtended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

Assembly Code Example(1)

TIM16_ReadTCNTn:

; Save Global Interrupt Flag

in r18,SREG

; Disable interrupts

cli

; Read TCNTn into r17:r16

in r16,TCNTnL

in r17,TCNTnH

; Restore Global Interrupt Flag

out SREG,r18

ret

C Code Example(1)

unsigned int TIM16_ReadTCNTn( void )

{

unsigned char sreg;

unsigned int i;

/* Save Global Interrupt Flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNTn into i */

i = TCNTn;

/* Restore Global Interrupt Flag */

SREG = sreg;

return i;

}

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The following code examples show how to do an atomic write of the TCNTn Register

contents. Writing any of the OCRnA/B or ICRn Registers can be done by using the

same principle .

Note: 1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

e xtended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The assembly code example requires that the r17:r16 register pair contains the va lue to

be written to TCNTn.

Reusing the Temporary High

Byte Register If writing to more than one 16-bit reg ister where t he high byte is the same for all regi sters

written, then the high byte only needs to be written o nce. However, note that the same

rule of atomic operation described previously also app lies in this case.

Assembly Code Example(1)

TIM16_WriteTCNTn:

; Save Global Interrupt Flag

in r18,SREG

; Disable interrupts

cli

; Set TCNTn to r17:r16

out TCNTnH,r17

out TCNTnL,r16

; Restore Global Interrupt Flag

out SREG,r18

ret

C Code Example(1)

void TIM16_WriteTCNTn( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save Global Interrupt Flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNTn to i */

TCNTn = i;

/* Restore Global Interrupt Flag */

SREG = sreg;

}

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Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the clock select logic which is controlled by the Clock Select

(CSn2:0) bits located in the Timer/Counter Contr ol Register B (TCCRnB). For details on

clock sources and prescaler, see “Timer/Counter0, Timer/Counter1, and

Timer/Counter3 Prescalers” on page 105.

Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional

counter unit. Figure 47 shows a block diagram of the counter and its surroundings.

Figure 47. Counter Unit Block Diagr am

Signal description (internal signals):

Count Increment or decrement TCNTn by 1.

Direction Select between increment and decrement.

Clear Clear TCNTn (set all bits to zero).

clkTnTimer/Counter clock.

TOP Signalize that TCNTn has reached maximum value.

BOTTOM Signalize that TCNTn ha s reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High

(TCNTnH) containing the uppe r eight bits of the counter, and Counter Low (TCNTnL)

containing the lower eight bits. The TCNTnH Register can only be indirectly accessed

by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU

accesses the high byte temporary register (TEMP). The temporary register is updated

with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the

temporary register value when TCNTnL is written. This allows the CPU to read or write

the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is impor-

tant to notice that there are special cases of writing to the TCNTn Register when the

counter is counting that will give unpredictable results. The special cases are described

in the sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or dec-

remented at each Timer Clock (clkTn). The clkTn can be generated from an externa l or

internal clock source, selected by the Clock Sele ct bits (CSn2:0). When no clock source

is selected (CSn2:0 = 0) the Timer is stopped. However, the TCNTn value can be

accessed by the CPU, inde pendent of whether clk Tn is present or not. A CPU write over-

rides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the Waveform Generation mode

bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and

TCCRnB). There are close connections b etween how the counter behaves (counts) and

TEMP (8-bit)

DATA BUS

(8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit) Control Logic

Count

Clear

Direction

TOVn

(Int.Req.)

Clock Select

TOP BOTTOM

Edge

Detector

( From Prescaler )

clk

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how waveforms are generated on the Output Compare outputs OCnx. For more details

about advanced counting seque nces and waveform generation, se e “Modes of Opera-

tion” on page 119.

The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation

selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events

and give them a time-stamp indicat ing time of occurr ence. The ext ernal signal in dicat ing

an event, or multiple events, can be applied via the ICPn pin or alternatively, via the

Analog Comparator unit. The time-stamps can then be used to calculate frequency,

duty-cycle, and other features of the signa l applied. Alternatively th e time-stamps ca n be

used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 48. The ele-

ments of the block diagram that are not directly a part of the Input Capture unit are gray

shaded. The small “n ” in register and bit names indicates the Timer/Counter number.

Figure 48. Input Capture Unit Block Diagram(1)

Note: 1. The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not

Timer/Counter3.

When a change of the logic level (an event) occurs on the Input Capture pin (ICPn),

alternatively on the Analog Comparator output (ACO), and this chan ge confirms to the

setting of the edge detector, a capture will be triggered. When a capture is triggered, the

16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The

Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied

into ICRn Register. If enabled (TICIEn = 1), the Input Capture Flag generates an Input

Capture interrup t. The ICFn Flag is autom atically cleared when th e interrupt is executed.

Alternatively the ICFn Flag can be cleared by software by writing a logical one to its I/O

bit location.

ICFn (Int.Req

Analog

Comparator

WRITE ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

ICPn

Edge

Detector

TEMP (8-bit)

DATA BUS

(8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

ACIC* ICNC ICES

ACO*

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Reading the 16-bit value in the In put Capture Register (I CRn) is done by first readin g the

low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high

byte is copied into the high byte temporary register (TEMP). When the CPU reads the

ICRnH I/O location it will access the TE MP Regis ter.

The ICRn Register can only be written when using a Waveform Generation mode that

utilizes the ICRn Register for defining the counter’s TOP value. In these cases the

Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be

written to the I CRn Register . When wr itin g the ICRn Reg iste r the high byt e must b e wri t-

ten to the ICRnH I/O location before the low byte is written to ICRnL.

For more information on how to access the 16-bit registers refer to “Accessing 16-bit

Registers” on page 110.

Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICPn).

Timer/Counter1 can alternatively use the Analog Comparator output as trigger source

for the Input Capture unit. The Analog Comparator is selected as trigger source by set-

ting the Analog Comparator Input Capture (ACIC) bit in the Analo g Comp arator C ontrol

and Status Register (ACSR). Be aw are that changing trigger source can trigger a cap-

ture. The Input Capture Flag must th erefore be cleared afte r the change.

Both the Input Capture pin (ICPn) and the Analog Comparator output (ACO) inputs are

sampled using the same technique as for the Tn pin (Figure 44 on page 105). The edge

detector is also identical. However, when the noise canceler is enabled, addition al logic

is inserted before the edge detector, which increases the delay by four system clock

cycles. Note that the input of the noise canceler and edge detector is always enabled

unless the Timer/Counter is set in a Waveform Ge neration mode that uses ICRn to

define TOP.

An Input Capture can be triggered by software by controlling the port of the ICPn pin.

Noise Canceler The Noise Canceler improves noise immunity by using a simple digital filtering scheme.

The Noise Canceler input is monitored over four samples, and all four must be equal for

changing the output that in turn is used by the edge detector.

The Noise Canc eler is ena bled by setting th e Inpu t Capt ure No ise Can celer (ICNCn) bit

in Timer/Counter Control Register B (TCCRnB). When enabled t he noise cancel er in tro-

duces additional f our syst em clock cycle s of de lay from a chang e applie d t o the input , to

the update of the ICRn Register. The no ise canceler uses th e syste m clock and is ther e-

fore not affected by the prescaler.

Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough pr ocessor

capacity for handling the incomin g even ts. The tim e betwee n two events is crit ical. If the

processor has not read the captured value in the ICRn Register before the next event

occurs, the ICRn will be overwritten with a new value. In this case the result of the cap-

ture will be incorrect.

When using the I nput Captur e interrup t, the ICRn Re gister shou ld be read as ear ly in the

interrupt handler routine as possible. Even though the Input Capture interrupt has rela-

tively high priority, the maximum interrupt response time is dependent on the maximum

number of clock cycles it takes t o handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution)

is actively changed during operation, is not recommended.

Measurement of an external signa l’s duty cycle requires that the trigger edge is changed

after each capture. Changing the edge sensing must be done as early as possible after

the ICRn Register has been read. After a change of the edge, the Inpu t Capture Flag

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(ICFn) must be cleared by software (writing a logical one to the I/O bit location). For

measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt

handler is used).

Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compar e Regis-

ter (OCRnx). If TCNT equals OCRnx the compara tor signals a match. A match will set

the Output Com pare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx =

1), the Output Compare Flag gener ates an outpu t compare inter rupt. The OCFnx Fla g is

automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can

be cleared by soft ware by writing a log ical one to its I/O bit location. The Wavef orm Gen-

erator uses the match signal to generate an output according to operating mode set by

the Waveform Generation mode (WGMn3:0) bits and Compare Output mode

(COMnx1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator

for handling the special cases of the extreme values in some modes of operation (See

“Modes of Operation” on page 119.)

A special feature of output compare unit A allows it to define the Timer/Counter TOP

value (i.e., counter resolution). In addition to the counter resolution, the TOP value

defines the period time for waveforms generated by the Waveform Generator.

Figure 49 s hows a block d iagram of the o utput c ompar e unit. T he sma ll “n” in t he reg is-

ter and bit names indicates the device number (n = n fo r Timer/Counter n), and the “x”

indicates output compare unit (A/B). The elements of the block diagram that are not

directly a part of the output compare unit are gray shaded.

Figure 49. Output Compare Unit, Block Diagram

The OCRnx Register is double buffered when using any of the twelve Pulse Width Mod-

ulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of

operation, the double buffering is disabled. The double buffering synchronizes the

update of the OCRnx Compare Register to either TOP or BOTTOM of the counting

OCFnx (Int.Req.)

(16-bit Comparator )

OCRnx Buffer (16-bit Register)

OCRnxH Buf. (8-bit)

OCnx

TEMP (8-bit)

DATA BUS

(8-bit)

OCRnxL Buf. (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

COMnx1:0WGMn3:0

OCRnx (16-bit Register)

OCRnxH (8-bit) OCRnxL (8-bit)

Waveform Generator

TOP

BOTTOM

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sequence. The synchronizati on p revents the occurren ce of odd-le ngth, n on-symmet rical

PWM pulses, thereby making the out put glitch-free.

The OCRnx Register access may seem complex, bu t this is not case . When the d ouble

buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double

buffering is disabled the CPU will access the OCRnx directly. The content of the OCR1x

(Buffer or Compare) Register is only changed by a write operation (the Timer/Counter

does not update t his register automa tically as the TCNT1 a nd ICR1 Regist er). Therefo re

OCR1x is not read via the high byte temporary register (TEMP). However, it is a good

practice to read the low byt e first as when accessing other 16- bit registers. Writing the

OCRnx Registers must be done via the TEMP Register since the compare of all 16 bits

is done continuously. The high byte (OCRnxH) has to be written first. When the high

byte I/O location is written by the CPU, the TEMP Register will be updated by the value

written. Then whe n the low byte (OCRnx L) is written to the lower eight b its, the high byte

will be copied into the upper eight bits of either the OCRnx buffer or OCRnx Compare

For more infor mation of how to access the 16-bit registers refer to “Accessing 16-bit

Registers” on page 110.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing Compare

Match will not set the OCFnx Flag or reload/clear the timer, but the OCnx pin will be

updated as if a real Compare Match ha d occurred (the COMn1:0 bits settings define

whether the OCnx pin is set, cleared or toggled).

Compare Match Bloc king by

TCNTn Write All CPU writes to the TCNTn Register will block any Compare Match that occurs in the

next timer clock cycle, e ven whe n the timer is st opped . T his feat ure a llows OCRnx to be

initialized to the same value as TCNTn without triggering an interrupt when the

Timer/Counter clock is enabled.

Using the Output Compare

Unit Since writing TCNTn in any mode of operation will block all compare matches for one

timer clock cycle, there are risks involved when changing TCNTn when using any of the

output compare channels, independent of whether the Timer/Counter is running or not.

If the value written to TCNTn equals the OCRnx value, the Compare Match will be

missed, resulting in incorrect waveform generation. Do not write the TCNTn equal to

TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be

ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNTn value

equal to BOTTOM when the counter is down-counting.

The setup of the OCnx should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OCnx value is to use the Force

Output Compare (FOCnx) strob e bits in Normal mode. The OCn x Register keeps its

value even when changing between Waveform Generation mod es.

Be aware that the COMnx1:0 bits are not double buffered together with the compare

value. Changing the COMnx1:0 bits will take effect immediately.

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Compare Match Output

Unit The Co mpare Outp ut mode (COMnx1: 0) bit s ha ve tw o func tions. The wavefo rm gener a-

tor uses the COMnx1:0 bits for defining the output compare (OCnx) state at the next

Compare Match. Secondly the COMnx1:0 bits control the OCnx pin output source. Fig-

ure 50 shows a sim plified schematic of the log ic affected by the COM nx1:0 bit setting.

The I/O Regist ers, I/ O bits, and I /O pins in the f igure are shown in bold. Only th e par ts of

the general I/O Port Control Registers (DDR and PORT) that are affected by the

COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the

internal OCnx Registe r, not the OCn x pin. If a Syst em Reset occur, the OCnx Register is

reset to “0”.

Figure 50. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the output compare (OCnx) from the

Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin

direction (input or output) is still controlled by the Data Direction Register (DDR) for the

port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as

output before t he OCnx value is visible on the pin . The port override functi on is generally

independent of the Waveform Generation mode, but there are some exceptions. Re fer

to Table 53, Table 54 and Table 55 for details.

The design of the output compare pin logic allows initialization of the OCnx state before

the output is enabled. Note that some COMnx1:0 bit settings are reserved for certain

modes of operation. See “16-bit Timer/Counter Register Description” on page 129.

The COMnx1:0 bits have no effect on the Input Capture unit.

PORT

DDR

OCnx

Waveform

Generator

OMnx1

OMnx0

DATA BUS

OCnx

clkI/O

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Compare Output Mode and

Waveform Generation The Waveform Ge ner ator u se s t he COMn x1 :0 bi ts d iff e ren tl y in nor mal, CTC, and PWM

modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no

action on the OCnx Register is to be performed on the next Compare Match. For Com-

pare Output actions in the non-PWM modes refer to Table 53 on page 129. For fast

PWM mode refe r to Table 54 on page 13 0, and for phase corr ect and phase and fre -

quency correct PWM refer to Table 55 on page 130.

A change of the COMnx1:0 bits state will have effect at the first Compare Match after

the bits are written. F or non-PWM modes, the action can be forced to have imme diate

effect by using the FOCnx strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, is de fined by th e combina tion of the Waveform Generation mode (WGMn3:0) and

Compare Output mo de (COMnx1:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0

bits control whether the PWM output genera ted should be inverted or not (inverte d or

non-inverted PWM ). For non-PWM modes the COMn x1:0 bits control whether th e out-

put should be set, cleared or to ggle at a Compar e Match (See “Co mpare Mat ch Output

Unit” on page 118.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 127.

Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the

counting direction is a lways up (incrementing) , and no counte r clear is performe d. The

counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and

then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counte r Over-

flow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero.

The TOVn Flag in this case be haves like a 17th bit, excep t that it is only se t, not clea red.

However, combined with the timer overflow interrupt that automatically clears the TOVn

Flag, the timer resolution can be increase d by software. There are no special cases to

consider in the normal mode, a new counter value can be written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maxi-

mum interval bet ween the extern al events must not exceed t he resolution of the count er.

If the interval between events are too long, the timer overflow interrupt or the prescaler

must be used to extend the resolution for the capture unit.

The Output Co mpare units ca n be used to genera te interru pts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

Clear Timer on Compare

Match (CTC) Mode In Cle ar Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn

cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0

= 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the

counter, hence also its resolution. This mode allows greater control of the Compare

Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 51. The counter value

(TCNTn) increa ses until a Compare Match occurs wit h either OCRnA or ICRn, and then

counter (TCNTn) is cleared.

120

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Figure 51. CTC Mode, Timing Diagram

An interrupt can be generated at each time the counter value reaches the TOP value by

either using the OCF nA or ICFn Flag according to the register used to define the TOP

value. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing the TO P to a value close to BOTTOM when the

counter is running with none or a low prescaler value must be done with care since the

CTC mode does not have the double buffering feature. If the new value written to

OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the

Compare Match. The counter will then have to count to its maximum value (0xFFFF)

and wrap around starting at 0x0000 before the Compare Match can occur. In many

cases this feature is not desirable. An alternative will then be to use the fast PWM mode

using OCRnA for defining TOP (WG Mn3:0 = 15) since the OCRnA then will be double

buffered.

For generating a waveform output in CTC mode, the OCnA output can be set to toggle

its logical level on each Compare Match by setting the Compare Output mode bits to

toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless

the data dire ctio n for th e pi n is set to outp ut (DDR_ OCnA = 1). The wavef orm gener ated

will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000).

The waveform frequency is defined by the following equation:

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). For

Timer/Counter3 also pr escaler factors 16 and 32 are available.

As for the Normal mode of oper at ion, t he TOVn F lag is set in the sam e t imer cloc k cycle

that the counter counts from MAX to 0x0000.

CNTn

CnA

(

Toggle)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Se

(Interrupt on TOP)

1 4

eriod

2 3

(COMnA1:0 = 1)

OCnA fclk_I/O

2N1OCRnA+()⋅⋅

-----------------------------------------------

----

121

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Fast PWM Mode The fast Pu lse Width Modulation or fast PWM mode (WGMn3:0 = 5,6,7,14, or 15) pro-

vides a high frequen cy PWM waveform generation option . The fast PWM differs from

the other PWM options by its single-slo pe oper at ion. Th e co unte r coun ts from BOTTOM

to TOP then restar ts from BOTT OM. In non- inverting Compar e Outpu t mode, the Output

Compare (OCnx) is set on the Compare Match between TCNTn and OCRnx, and

cleared at TOP. I n inverting Compare Out put mode output is clea red on Compare Mat ch

and set at TOP. Due to the single-slope operation, the operating frequency of the fast

PWM mode can be twice as high as the phase correct and phase and frequency correct

PWM modes that use dual-slope operation. Th is high frequency makes the fast PWM

mode well suited for power regulation, rectification, and DAC applications. High fre-

quency allows physically small sized external components (coils, capacitors), hence

reduces total system cost.

The PWM resolution for fast PW M can be fixed to 8-, 9-, or 10-bit, or defined by eithe r

ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to

0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM

resolution in bits can be calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches either

one of the fixe d values 0x0 0FF, 0x0 1FF, or 0x03F F (WGMn3: 0 = 5, 6, or 7) , the va lue in

ICRn (WGMn3:0 = 14), o r the value in OCRnA (WGMn3:0 = 15) . The counter is then

cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is

shown in Figure 52. The figure shows fast PWM mode when OCRnA or ICRn is used to

define TOP. The TCNTn value is in the timing diagram shown as a histogram for illus-

trating the single-slop e operation. The diagram includes non- inverted and inverted PWM

outputs. The small horizontal line marks on the TCNTn slopes represent compare

matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a Com-

pare Match occurs.

Figure 52. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In

addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set

when either OCRnA or ICRn is used for defining the TOP value. If one of the interrupts

are enabled, the interrupt handler routine can be used for updating the TOP and com-

pare values.

RFPWM TOP 1+()log 2()log

-------------------------------

----

TCNTn

OCRnx / TOP Update

and TOVn Interrupt Flag

Set and OCnA Interrupt

Flag Set or ICFn

Interrupt Flag Set

(Interrupt on TOP)

1 7

Period 2 3 4 5 6 8

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

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When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the compare registers. If the TOP value is lower

than any of the compare registers, a Compare Match will never occur between the

TCNTn and the OCRnx. Note that when usin g fixed TOP values the unused bits are

masked to zero when an y of th e OCRnx Registers are writ te n.

The procedure for u pdating ICRn differs from upd ating OCRnA when use d for defining

the TOP value. The ICRn Register is not double buffered. This means that if ICRn is

changed to a low value when the counter is running with none or a low prescaler value,

there is a risk that the new ICRn value written is lower than the current value of TCNTn.

The result will then be that the counter will miss the Compare Match at the TOP value.

The counter will then have to count to the MAX value (0xFFFF) and wrap around start-

ing at 0x0000 before the Compare Match can occur. The OCRnA Register however, is

double buffered. This feature allows the OCRnA I/O location to be written anytime.

When the OCRnA I/O location is written the value written will be put into the OCRnA

Buffer Register. The OCRnA Compare Register will then be updated with the value in

the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is

done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By

using ICRn, the OCRnA Register is free to be used for generating a PWM output on

OCnA. However, if the base PWM frequency is actively changed (by changing the TOP

value), using the OCRnA as TOP is clearly a better choice due to its double buffer

feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the

OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an

inverted PWM output can be generate d by setting the COMnx1:0 to three (See Table

on page 130). T he actual OCnx value wil l only be visible on the port pin if the data d irec-

tion for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by

setting (or clearing) the OCnx Register at the Compare Match between OCRnx and

TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter

is cleared (changes from TOP to BOTTOM).

The PWM frequency for th e output can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For

Timer/Counter3 also pr escaler factors 16 and 32 are available.

The extreme values for the OCRnx Register represents special cases when generating

a PWM waveform ou tput in the fast PWM mode. If the OCRnx is set equal to BOTTOM

(0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the

OCRnx equal to TOP will result in a constant high or low output (depending on the polar-

ity of the output set by the COMnx1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OCnA to toggle its logical level on each Compare Match (COMnA1:0 = 1).

This applies only if OCRnA is used to def ine the TOP value (WGMn3:0 = 15). The wave-

form generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set

to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the

double buffer fe at ur e of th e ou tput compare uni t is enable d in th e fast PWM mode.

OCnxPWM fclk_I/O

N1TOP+()⋅

-------------------------------

----

123

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Phase Correct PWM Mode The phase correct Pu lse Width Modulation or phase correct PWM mode (WGMn3:0 = 1,

2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation

option. The phase correct PWM mode is, like the phase and frequency correct PWM

mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output

mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn

and OCRnx while up-counting, and set on the Compare Match while down-counting. In

inverting Outp ut Compare m ode, the operatio n is inverte d. The dua l-slope operat ion has

lower maximum operation frequency than single slope operation. However, due to the

symmetric feature of the dual-slope PWM modes, these modes are preferred for motor

control applications.

The PWM resolution f or the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or

defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or

OCRnA set to 0x0003), and the maxim um resolution is 16-bit (ICRn or OCRnA set to

MAX). The PWM resolution in bits can be calculated by using the following equation:

In phase correct PWM m ode t he coun t er is incre men ted unt il th e cou nter value ma t ches

either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the

value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter

has then reached the TOP and changes the count direction. The TCNTn value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM

mode is shown on Figu re 53 . The fi gure sho ws phase corr ect PWM m ode when OCRnA

or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a

histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The sm all horizont al line marks on the TCNTn slope s r epre-

sent compare matches between OCRnx and TCNTn. The OCnx Interr upt Flag will be

set when a Compare Match occur s.

Figure 53. Phase Correct PWM Mode, Timing Diagram

RPCPWM TOP 1+()log 2()log

-------------------------------

----

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

Period

OCnx

(COMnx1:0 =

124

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The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOT-

TOM. When either OCRnA or ICRn is used for definin g the TOP value, the OCnA or

ICFn Flag is set accordingly at the same timer clock cycle as the OCRnx Registers are

updated with the double buffer value (at TOP). The Interrupt Flags can be used to gen-

erate an interrupt each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the compare registers. If the TOP value is lower

than any of the compare registers, a Compare Match will never occur between the

TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are

masked to zero when any of t he OCRnx Reg isters are writ ten. As the t hird period sho wn

in Figure 53 illustrates, changing the TOP actively while the Timer/Counter is running in

the phase correct mode can result in an unsymmetrical output. The reason for this can

be found in the time of update of the OCRnx Register. Since the OCRnx update occurs

at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall-

ing slope is determined by the pr evious TOP valu e, while th e length of the rising slope is

determined by the new TOP valu e. When these two values differ the two slopes of the

period will differ in length. The difference in length gives the unsymmetrical result on the

output.

It is recommended to use the phase and frequency correct mode instead of the phase

correct mode when changing the TOP value while the Timer/Counter is running. When

using a static TOP value there are practically no differences between the two modes of

operation.

In phase correct PWM mode, the compare uni ts allow generation of PWM waveforms on

the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and

an inverted PWM outp ut can be gener ated by setting the COMn x1:0 to t hree ( See Table

55 on page 130). The actual OCnx value will only be visible on the port pin if the data

direction for the port pin is set as output (DDR_OCnx). The PWM waveform is gener-

ated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx

and TCNTn when the coun ter increme nts, and clear ing (or sett ing) the O Cnx Register at

Compare Match between OCRnx and TCNTn when the counter decrements. The PWM

frequency for the output when using phase correct PWM can be calculated by the fol-

lowing equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For

Timer/Counter3 also pr escaler factors 16 and 32 are available.

The extreme values for the OCRnx Register represent special cases when generating a

PWM waveform output in the pha se correct PWM mode. If the OCRnx is set equal to

BOTTOM the output will be continuously low and if set equal to TOP the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values. If OCRnA is used to define the TOP value (WGMn3:0 = 11)

and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle.

Phase and Frequency Correct

PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency cor-

rect PWM mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency

correct PWM waveform generation option. The phase and frequency correct PWM

mode is, like the phase correct PWM mode, based on a dual-slope operation. The

counter counts repe atedly from BOTTO M (0x0 000) to TOP an d th en fr om TOP to BOT-

TOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared

on the Compare Match between TCNTn and OCRnx while up-counting, and set on the

fOCnxPCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

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ATmega162/V

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Compare Match whi le down-counting. In inverting Compare Output mode, the operation

is inverted. The dual-slope operation gives a lower maximum operation frequency com-

pared to the single-slope operation. However, due to the symmetric feature of the dual-

slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct

PWM mode is the time the OCRnx Register is upda ted by the OCRnx Buffer Register,

(see Figure 53 and Figure 54).

The PWM resolution for the phase and frequency correct PWM mode can be defined by

either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to

0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM

resolution in bits can be calculated using the following equation:

In phase and frequency correct PWM mode the counter is incremented until the counter

value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA

(WGMn3:0 = 9). The counter has then reached the TOP and changes the count direc-

tion. The TCNTn value will be equal to TOP for one timer clock cycle. The timing

diagram for t he ph ase co rr ect and f re que ncy correct PWM mode is shown on Figure 54.

The figure shows phase and frequen cy correct PWM mode when OCRnA or ICRn is

used to define TO P. The TCNTn value is in th e timing d iagram shown as a histogra m for

illustrating the dual-slope operation. The diagram includes n on-inverted and inverted

PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare

matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a Com-

pare Match occurs.

Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOVn) is set at the same tim er clock cycle as the

OCRnx Registers are updated with the double buffer value (at BOTTOM). When either

OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag set when

TCNTn has reached TOP. The I nterrupt Flags can th en be used to genera te an interru pt

each time the counter reaches the TOP or BOTTOM value.

RPFCPWM TOP 1+()log 2()log

-------------------------------

----

OCRnx/TOP Update and

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Se

(Interrupt on TOP)

1 2 3 4

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

126

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When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the compare registers. If the TOP value is lower

than any of the compare registers, a Compare Match will never occur between the

TCNTn and the OCRnx.

As Figure 54 shows the output generated is, in co ntrast to the phase correc t mode, sym-

metrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length

of the rising and the falling slopes will always be equal. This gives symmetrical output

pulses and is therefore frequency correct.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By

using ICRn, the OCRnA Register is free to be used for generating a PWM output on

OCnA. However, if the base PWM frequency is actively changed by changing the TOP

value, using the OCRnA as TOP is clearly a better choice due to its double buffer

feature.

In phase and frequency correct PWM mode, the compare units allow generation of

PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a

non-inverted PWM and an inverted PWM output can be generated by setting the

COMnx1:0 to three (See Table 55 on page 130). The actual OCnx value will only be vis-

ible on the port pin if the data direction for th e port pin is set a s output (DDR_O Cnx). The

PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare

Match between OCRnx and TCNTn when the counter increments, and clearing (or set-

ting) the OCnx Register at Compare Match between OCRnx and TCNTn when the

counter decrements. The PWM frequency for the output when using phase and fre-

quency correct PWM can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For

Timer/Counter3 also pr escaler factors 16 and 32 are available.

The extreme values for the OCRnx Register represents special cases when generating

a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to

BOTTOM the output will be continuously low and if set equal to TOP the output will be

set to high for non-inverted PWM mode. For inverted PWM the output will have the

opposite logic values. If OCRnA is use d to define the TOP value (WGMn3:0 = 9) and

COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle.

fOCnxPFCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

127

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Timer/Counter Timing

Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set, and when the OCRnx Register is updated with the

OCRnx buffer value (only for modes utilizing double buffering). Figure 55 shows a timing

diagram for th e set tin g of OCFnx.

Figure 55. Timer/Count er Timing Diagram, Setting of OCFnx, no Prescaling

Figure 56 shows the same timing data, but with the prescaler enabled.

Figure 56. Timer/Count er Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)

Figure 57 shows the count sequence close to TOP in vari ous modes. When using phase

and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The

timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by

BOTTOM+1 and so on. The same renaming ap plies for modes that set the TOVn Flag

at BOTTOM.

clk

(clkI/O/1)

CFnx

clk

I/O

CRnx

CNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

CFnx

CRnx

CNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(clkI/O/8)

128

ATmega162/V

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Figure 57. Timer/Counter Timing Diagram, no Prescaling

Figure 58 shows the same timing data, but with the prescaler enabled.

Figure 58. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(

PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clkTn

(clkI/O/1)

clkI/O

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(

PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clkI/O

clkTn

(clkI/O/8)

129

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16-bit Timer/Counter

Timer/Counter1 Control

Timer/Counter3 Control

• Bit 7:6 – COMnA1:0: Compare Output Mode for channel A

• Bit 5:4 – COMnB1:0: Compare Output Mode for channel B

The COMnA1:0 and COMnB1:0 control the Output Comp are pins (OCnA and OCnB

respectively) beh avior. If one or bot h of t he COMnA1:0 bi ts are writt en to o ne, the O CnA

output overrides the normal port functionality of the I/O pin it is connected to. If one or

both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port

functionality of the I/O pin it is connected to. However, note that the Data Direction Reg-

ister (DDR) bit corresponding to the O CnA or OCnB pin must be set in order to enable

the output driver.

When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is

dependent of the WGMn3:0 bits setting. Table 53 shows the COMnx1:0 bit functionality

when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).

Bit 76543210

COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 TCCR1A

Read/Write R/W R/W R/W R/W W W R/W R/W

Initial Value00000000

Bit 76543210

COM3A1 COM3A0 COM3B1 COM3B0 FOC3A FOC3B WGM31 WGM30 TCCR3A

Read/Write R/W R/W R/W R/W W W R/W R/W

Initial Value00000000

Table 53. Compare Output Mod e, non-PWM

COMnA1/

COMnB1 COMnA0/

COMnB0 Description

0 0 Normal port ope ration, OC nA/OCnB disconnected.

0 1 Toggle OCnA/OCnB on Compare Match.

1 0 Clear OCnA/OCnB on Compare Match (Set output to low level).

1 1 Set OCnA/OCnB on Compare Match (Set output to high level).

130

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Table 54 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the

fast PWM mode.

Note: 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is

set. In this case the Compare Match is ignored, but the set or clear is done at TOP.

See “Fast PWM Mode” on page 121. for more details.

Table 55 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the

phase correct or the phase and frequency correct, PWM mode.

Note: 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is

set. See “Phase Correct PWM Mode” on page 123. for more details.

• Bit 3 – FOCnA: Force Output Compare for channel A

• Bit 2 – FOCnB: Force Output Compare for channel B

The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM

mode. However, for ensuring compatibility with future devices, these bits must be set to

zero when TCCRnA is written when operating in a PWM mode. When writing a logical

one to the FOCnA/FO CnB bit , an immed iate Comp are Ma tch is f orced o n the Wa veform

Generation unit. The OCnA/OCnB output is changed according to its COMnx1:0 bits

setting. Note that the FOCnA/FOCnB b its are implemented as strobes. Therefore it is

the value present in the COMnx1:0 bits that determine the effect of the forced compare.

A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear

Timer on Compare match (CTC) mode using OCRnA as TOP.

The FOCnA/FOCnB bits are always rea d as zero.

Table 54. Compare Output Mod e, Fast PWM(1)

COMnA1/

COMnB1 COMnA0/

COMnB0 Description

0 0 Normal port operation, OCnA/OCnB disconne cted.

0 1 WGMn3:0 = 15: Toggle OCnA on Compare Match , OCnB

disconnected (normal port operation). For all other WGMn

settings, normal port operation, OCnA/OCnB disconnected.

1 0 Clear OCnA/OCnB on Compare Match, set OCnA/OCnB at TOP.

1 1 Set OCnA/OCnB on Compare Match, clear OCnA/OCnB at TOP.

Table 55. Compare Output Mode, Phase Correct and Phase and Frequency Correct

PWM(1)

COMnA1/

COMnB1 COMnA0

COMnB0 Description

0 0 No rmal port operation, OCnA/OCnB disconnected.

0 1 WGMn3:0 = 9 or 14: Toggle OCnA on Compare Match, OCnB

disconnected (normal port operation). For all other WGMn

settings, normal port operation, OCnA/OCnB disconnected.

1 0 Cle ar OCnA/OCnB on Compare Match when up-counting. Set

OCnA/OCnB on Compare Match when down-counting.

1 1 Set OCn A/OCnB on Compare Match when up-counting. Clear

OCnA/OCnB on Compare Match when down-counting.

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• Bit 1:0 – WGMn1:0: Waveform Generation Mode

Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the

counting sequence of the counter, the sou rce for maximum (TOP) counter value, and

what type of waveform generation to be used, see Table 56. Modes of operation sup-

ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare

match (CTC) mode, and three types of Pu lse Width Modulation (PWM) modes. (See

“Modes of Operation” on page 119.)

Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

Table 56. Waveform Genera tion Mode Bit Description(1)

Mode WGMn3 WGMn2

(CTCn) WGMn1

(PWMn1) WGMn0

(PWMn0) Timer/Counter Mode of Operation TOP Update of

OCRnx at TOVn Flag

Set on

0 0 0 0 0 Normal 0xFFFF Immediate MAX

1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM

2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM

3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM

4 0 1 0 0 CTC OCRnA Immediate MAX

5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP

6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP

7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP

8 1 0 0 0 PWM, Phase an d Frequency Correct ICRn BOTTOM BOTTOM

9 1 0 0 1 PWM, Phase and Frequency Correct OCRnA BOTTOM BOTTOM

10 1 0 1 0 PWM, Phase Corre ct ICRn TOP BOTTOM

11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM

12 1 1 0 0 CTC ICRn Immediate MAX

13 1 1 0 1 Reserved – – –

14 1 1 1 0 Fast PWM ICRn TOP TOP

15 1 1 1 1 Fast PWM OCRnA TOP TOP

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Timer/Counter1 Control

Timer/Counter3 Control

• Bit 7 – ICNCn: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture noise canceler. When the noise can-

celer is activated, the input from the Input Capture pin (ICPn) is filtered. The filter

function requires four successive equal valued samples of the ICPn pin for changing its

output. The Input Capture is therefore delayed by four Oscillator cycles when the noise

canceler is enabled.

• Bit 6 – ICESn: Input Capture Edge Select

This bit selects which edge on the Inpu t Captur e pin (ICPn) tha t is used to tr igger a cap-

ture event. When the ICESn bit is written to zer o, a falling (negative) edge is used as

trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the

capture.

When a capture is triggered according to the ICESn setting, the counter value is copied

into the Input Capture Register (ICRn). The event will also set the Input Capture Flag

(ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is

enabled.

When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in

the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently

the Input Capture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit

must be written to zero when TCCRnB is written.

• Bit 4:3 – WGMn3:2: Waveform Generation Mode

See TCCRnA Register description.

Bit 76543210

ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 2:0 – CSn2:0: Clock Select

The three Cloc k Select bits select the clock source to be used by the Time r/Counter, see

Figure 55 and Figure 56.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the co unting..

Table 57. Clock Select Bit Descrip tio n Tim e r/ Co un te r1

CS12 CS11 CS10 Description

0 0 0 No clock source. (Timer/Counter stopped).

001clk

I/O/1 (No prescaling )

010clk

I/O/8 (From prescaler)

011clk

I/O/64 (From prescaler)

100clk

I/O/256 (From prescaler)

101clk

I/O/1024 (From prescaler)

1 1 0 External clock source on T1 pin. Clock on falling edge.

1 1 1 External clock source on T1 pin. Clock on rising edge.

Table 58. Clock Select Bit Descrip tio n Tim e r/ Co un te r3

CS32 CS31 CS30 Description

0 0 0 No clock source. (Timer/Counter stopped).

001clk

I/O / 1 (No prescaling)

010clk

I/O / 8 (From prescaler).

011clk

I/O / 64 (From prescaler).

100clk

I/O / 256 (From prescaler).

101clk

I/O / 1024 (From prescaler).

110clk

I/O / 16 (From prescaler).

111clk

I/O / 32 (From prescaler).

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Timer/Counter1 – TCNT1H

and TCNT1L

Timer/Counter3 – TCNT3H

and TCNT3L

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give

direct access, both for read and for write operations, to the Timer/Counter unit 16-bit

counter. To ensur e t hat bot h the h i gh an d lo w byte s are r ea d and wr it te n simulta ne ously

when the CPU accesses these registers, the access is performed using an 8-bit tempo-

rary high byte register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 110.

Modifying the counter (TCNTn) while the counter is running introduces a risk of missing

a Compare Match between TCNTn and one of the OCRnx Registers.

Writing to the TCNTn Register blocks (removes) the Compare Match on the following

timer clock for all compare units.

Output Compare Re gister 1 A

– OCR1AH and OCR1AL

Output Compare Re gister 1 B

– OCR1BH and OCR1BL

Output Compare Re gister 3 A

– OCR3AH and OCR3AL

Output Compare Re gister 3 B

– OCR3BH and OCR3BL

Bit 76543210

TCNT1[15:8] TCNT1H

TCNT1[7:0] TCNT1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

TCNT3[15:8] TCNT3H

TCNT3[7:0] TCNT3L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR1A[15:8] OCR1AH

OCR1A[7:0] OCR1AL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR1B[15:8] OCR1BH

OCR1B[7:0] OCR1BL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR3A[15:8] OCR3AH

OCR3A[7:0] OCR3AL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR3B[15:8] OCR3BH

OCR3B[7:0] OCR3BL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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The Output Compare Registers contain a 16-bit value that is continuously com pared

with the counter value (TCNTn). A match can be used to generate an output compare

interrupt, or to generate a waveform output on the OCnx pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low

bytes are written simultaneously when the CPU writes to these registers, the access is

performed using an 8-bit temporary high byte register (TEMP). This temporary register

is shared by all the ot her 16-bit registers. See “Accessin g 16-bit Register s” on page 110.

Input Capture Register 1 –

ICR1H an d ICR1L

Input Capture Register 3 –

ICR3H an d ICR3L

The Input Captu re is updated with the counter (TCNTn) value each time a n event occurs

on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1).

The Input Capture can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes

are read simultaneou sly when the CPU accesses these regist ers, the access is per-

formed using an 8-bit temporary high byte register (TEMP). This temporary register is

shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 110.

Timer/Counter Interrupt Mask

Note: 1. This register contains interrupt control bits for several Timer/Counters, but only

Timer1 bits are described in this section. The remaining bits are described in their

respective Timer sections.

• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the T imer/Counter1 overflow in terrupt is enabled. The corresp onding

Interrupt Vecto r (See “Int errupt s” on pa ge 58.) is ex ecuted wh en th e TOV1 Fla g, located

in TIFR, is set.

• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counte r1 Output Compare A Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 58.) is executed when the

OCF1A Flag, located in TI FR, is set.

Bit 76543210

ICR1[15:8] ICR1H

ICR1[7:0] ICR1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

ICR3[15:8] ICR3H

ICR3[7:0] ICR3L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counte r1 Output Compare B Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 58.) is executed when the

OCF1B Flag, located in TI FR, is set.

• Bit 3 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 58.) is executed when the

ICF1 Flag, located in TIFR, is set.

Extended Timer/Counter

Interrupt Mask Register –

ETIMSK(1)

Note: 1. This register contains interrupt control bits for several Timer/Counters, but only

Timer3 bits are described in this section. The remaining bits are described in their

respective Timer sections.

• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 58.) is executed when the

ICF3 Flag, located in TIFR, is set.

• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counte r3 Output Compare A Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 58.) is executed when the

OCF3A Flag, located in TI FR, is set.

• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counte r3 Output Compare B Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 58.) is executed when the

OCF3B Flag, located in TI FR, is set.

• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the T imer/Counter3 overflow in terrupt is enabled. The corresp onding

Interrupt Vecto r (See “Int errupt s” on pa ge 58.) is ex ecuted wh en th e TOV3 Fla g, located

in TIFR, is set.

Bit 7 6 5 4 3 2 1 0

TICIE3 OCIE3A OCIE3B TOIE3 ––ETIMSK

Read/Write R R R/W R/W R/W R/W R R

Initial Value 0 0 0 0 0 0 0 0

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Timer/Counter Interrupt Flag

Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are

described in this section. The remaining bits are described in their respective Timer

sections.

• Bit 7 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC

modes, the TOV1 Flag is set when the timer overflows. Refer to Table 56 on page 131

for the TOV1 Flag behavior when using another WGMn3:0 bi t setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is

executed. Alte rn at ive ly, TO V1 can be clea re d by writing a logic one to its bit loc at ion .

• Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter ( TCNT1) value match es the Ou t-

put Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is

executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter ( TCNT1) value match es the Ou t-

put Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is

executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 3 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set wh en a capture event occurs on the ICP1 p in. When the Inpu t Capture

set when the counter reaches the TOP value.

ICF1 is automati cally cleared when th e Input Capture Int errupt Vector is execute d. Alter-

natively, ICF1 can be cleared by writing a logic one to its bit location.

Bit 76543210

TOV1 OCF1A OC1FB OCF2 ICF1 TOV2 TOV0 OCF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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Extended Timer/Counter

Interrupt Flag Register –

ETIFR(1)

Note: 1. This register contains flag bits for several Timer/Counters, but only Timer3 bits are

described in this section. The remaining bits are described in their respective Timer

sections.

• Bit 5 – ICF3: Timer/Counter3, Input Capture Flag

This flag is set wh en a capture event occurs on the ICP3 p in. When the Inpu t Capture

set when the counter reaches the TOP value.

ICF3 is automati cally cleared when th e Input Capture Int errupt Vector is execute d. Alter-

natively, ICF3 can be cleared by writing a logic one to its bit location.

• Bit 4 – OCF3A: Timer/Counter3, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter ( TCNT3) value match es the Ou t-

put Compare Register A (OCR3A).

Note that a Forced Output Compare (FOC3A) strobe will not set the OCF3A Flag.

OCF3A is automatically cleared when the Output Compare Match A Interrupt Vector is

executed. Alternatively, OCF3A can be cleared by writing a logic one to its bit location.

• Bit 3 – OCF3B: Timer/Counter3, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter ( TCNT3) value match es the Ou t-

put Compare Register B (OCR3B).

Note that a Forced Output Compare (FOC3B) strobe will not set the OCF3B Flag.

OCF3B is automatically cleared when the Output Compare Match B Interrupt Vector is

executed. Alternatively, OCF3B can be cleared by writing a logic one to its bit location.

• Bit 2 – TOV3: Timer/Counter3, Overflow Flag

The setting of this flag is depend ent of the WGMn3:0 bits setting. In normal an d CTC

modes, the TOV3 Flag is set when the timer overflows. Refer to Table 56 on page 131

for the TOV3 Flag behavior when using another WGMn3:0 bi t setting.

TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is

executed. Alte rn at ive ly, TO V3 can be clea re d by writing a logic one to its bit loc at ion .

Bit 76543210

ICF3 OCF3A OC3FB TOV3 ––ETIFR

Read/Write R R R/W R/W R/W R/W R R

Initial Value00000000

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8-bit Timer/Counter2

with PWM and

Asynchronous

operation

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The

main features are:

•Single Channel Counter

•Clear Timer on Compare Match (A uto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Frequency Generator

•10-bit Clock Prescaler

•Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)

•Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 59. For the

actual placement of I/O pins, refer to “Pinout ATmega162” on pag e 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

page 150.

Figure 59. 8-bit Timer/Counter Block Diagram

Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers.

Interrupt request (shorten as Int.Re q.) signals are all visible in the Timer Interrupt Flag

shared by other timer units.

Timer/Counter

DATABUS

TCNTn

Waveform

Generation OCn

= 0

Control Logic

= 0xFF

TOPBOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCn

(Int.Req.)

Synchronization Unit

OCRn

TCCRn

ASSRn

Status flags

clkI/O

clkASY

Synchronized Status flags

asynchronous mode

select (ASn)

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clkTn

clkI/O

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The Timer/Counter can be clocked internally, via th e prescaler, or asynchronously

clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous

operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select

logic block controls which clock source the Timer/Counter uses to increment (or decre-

ment) its value. The Timer/Counter is inactive when no clock source is selected. The

output from the clock select logic is referred to as the Timer Clock (clkT2).

The double buffered Output Compare Register (OCR2) is compared with the

Timer/Counter value at all times. The result of the compare can be used by the wave-

form genera to r to gene rat e a PWM or var i ab le fr equ ency o ut put o n th e O utpu t Co mpa re

Pin (OC2). See “Output Compare Unit” on page 141. for details. The Compare Ma tch

event will also set the Compare Flag (OCF2) which can be used to generate an output

compare interrupt request.

Definitions Many register and bit references in this document are written in general form. A lower

case “n” replaces the Timer/Counter number, in this case 2. However, when using the

accessing Timer/Counter2 counter value and so on.

The definitions in Table 59 are also used extensively throughout the section.

Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchro-

nous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O.

When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken

from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on

asynchronous operation, see “Asynchronous Status Register – ASSR” on page 154. For

details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 158.

Table 59. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).

MAX The counter reaches its M AXimum when it becomes 0xFF (decimal 255).

TOP The counter reaches the T OP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The

assignment is depen dent on the mode of operation.

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Counter Unit The main part of the 8-bi t Timer/ Counter is th e progra mmable bi-d irection al counter unit .

Figure 60 shows a block diagram of the counter and its surrounding environment.

Figure 60. Counter Unit Block Diagr am

Signal description (internal signals):

count Increment or decrement TCNT2 by 1.

direction Selects between increment and decrement.

clear Clear TCNT2 (set all bits to zero).

clkT2 Timer/Counter clock.

top Signalizes that TCNT2 has reached maximum value.

bottom Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or dec-

remented at each timer clock (clk T2). clkT2 can be gener ated from an exte rnal or internal

clock source, selected by the Clock Select bits (CS22:0). When no clock source is

selected (CS22:0 = 0) t he timer is st opped. However, the TCNT2 value ca n be accessed

by the CPU, regardless of whether clkT2 is present or not. A CPU write overr ides (has

priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits

located in the Time r/Counter Control Register (TCCR2). There are close co nnections

between how the counter behaves (counts) and how waveforms are generated on the

Output Compare outpu t OC2. For more details about advanced counting sequences

and waveform gener ation, see “Modes of Operation” on page 144.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation

selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.

Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will

set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 =

1), the Output Compare Flag generates an output compare interrupt. The OCF2 Flag is

automatically cleared when the interrupt is executed. Alternatively, the OCF2 Flag can

be cleared by software by writing a logical one to its I/O bit location. The waveform gen-

erator uses the match signal to generate an output according to operating mode set by

the WGM21:0 bits and Compar e Output mode ( COM21:0) bit s. The max and b ottom sig-

nals are used by the waveform generator for handling the special cases of the extreme

values in some modes of operation (“Modes of Operation” on page 144).

Figure 61 shows a block diagram of the output compare unit.

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

topbottom

direction

clear

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clkI/O

clk

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Figure 61. Output Compare Unit, Block Diagram

The OCR2 Register is double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,

the double bu ffering is disabled. The double buffering synchronizes the upd ate of the

OCR2 Compare Register to either to p or bottom of t he counting se quence. The synchro-

nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby

making the output glitch-free.

The OCR2 Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double

buffering is disabled the CPU will access the OCR2 direc tly.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Outpu t Compare (FOC2) bit. Forcing Co mpare

Match will not set the OCF2 Flag or reload /clear the timer, but the O C2 pin will be

updated as if a real Compare Match ha d occurred (the COM21:0 bits settings define

whether the OC2 pin is set, cleared or toggled).

Compare Match Bloc king by

TCNT2 Write All CPU write operations to the TCNT2 Register will block any Compare Match that

occurs in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when

the Timer/Counter clock is enabled.

Using the Output Compare

Unit Since writing TCNT2 in any mode of operation will block all compare matches for one

timer clock cycle, there are risks involved when changing TCNT2 when using the output

compare chann el, independently of whether the Timer/Counter is running or not. If the

value written to TCNT2 equals the OCR2 value, the Compare Match will be missed,

OCFn (Int.Req

= (8-bit Comparator )

OCRn

OCxy

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

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resulting in incorrect Waveform Generation . Similarly, do not write the TC NT2 value

equal to BOTTOM when the counter is down-counting.

The Setup of the OC2 should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC2 value is to use the Force

Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value

even when changing between Waveform Generation modes.

Be aware that the COM21:0 bits are not double buffered together with the compare

value. Changing the COM21:0 bits will take effect immediately.

Compare Match Output

Unit The Compare Output mode (COM21:0) bits have two functions. The waveform genera-

tor uses the COM21:0 bits for defining the Output Compare (OC2) state at the next

Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 62

shows a simplified sc hematic of the logic a ffected by the COM21:0 bit setting. The I/O

Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the

general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0

bits are shown. When referring to the OC2 state, the reference is for the internal OC2

Figure 62. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC2) from the

waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direc-

tion (input or output) is still controlled by the Data Direction Register (DDR) for the port

pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output

before the OC2 value is visible on the pin. The port override function is independent of

the Waveform Generation mode.

PORT

DDR

OCn

Waveform

Generator

OMn1

OMn0

DATA BUS

OCn

clkI/O

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The design of the Output Compare pin logic allows initialization of the OC2 state before

the output is enabled. Note that some COM21:0 bit settings are reserved for certain

modes of operation. See “8-bit Timer/Counter Register Description” on page 150.

Compare Output Mode and

Waveform Generation The Waveform Generator uses the COM21:0 bits differently in Normal, CTC, and PWM

modes. For all modes, setting the COM21:0 = 0 tells the Waveform Generator that no

action on the OC2 Register is to b e performed on the next Compare Match. For com-

pare output actions in the non-PWM modes refer to Table 61 on page 152. For fast

PWM mode, refer to Table 62 on page 152, a nd for phase co rrect PWM refer to T able

63 on page 152.

A change of the COM21:0 bits state will have effect at the first Compare Match after the

bits are written. For non-PWM mod es, the action can be forc ed to have immediate effect

by using the FOC2 strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and

Compare Output mode (COM 21:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM21:0

bits control whether the PWM output genera ted should be inverted or not (inverte d or

non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output

should be set, cleared, or toggled at a Compare Match (See “Compar e Match Output

Unit” on page 143.).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 148.

Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the

counting direction is a lways up (incrementing) , and no counte r clear is performe d. The

counter simply overrun s whe n it passes it s maximum 8-bit va lue (T OP = 0xFF) and t hen

restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag

(TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The

TOV2 Flag in this case beha ves like a ninth bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt that automatically clears the TOV2

Flag, the timer resolution can be increase d by software. There are no special cases to

consider in the normal mode, a new counter value can be written anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

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Clear Timer on Compare

Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to

manipulate the coun te r re so luti on . I n CT C mo de t he coun te r is cleared to zero when the

counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the

counter, hence also its resolution. This mode allows greater control of the Compare

Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 63. The counter value

(TCNT2) increase s until a Compare Ma tch occurs b etween T CNT2 and OCR2, and then

counter (TCNT2) is cleared.

Figure 63. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by

using the OCF2 Flag. If the interrupt is en abled, the interrupt handler routine can be

used for updating the TOP value. However, changing the TOP to a value close to BOT-

TOM when the counter is running with none or a low prescaler value must be done with

care since the CTC m ode does not ha ve the double buffer ing feature. If the n ew value

written to OCR2 is lower than the current value of TCNT2, the counter will miss the

Compare Match. The counter will then have to count to its maxim um value (0xFF) and

wrap around starting at 0x00 before the Compare Match can occur.

For generating a wavef orm out pu t in CT C mode, the OC2 output ca n be set to toggle its

logical level on each Comp are Match by set ting th e Compare Out put mode b its to to ggle

mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data

direction for the pin is set to output. The waveform generated will have a maximum fre-

quency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is

defined by the fo llow i ng equation:

The N variable represents the prescale factor (1, 8, 32, 64 , 128, 256, or 1024).

As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle

that the counter counts from MAX to 0x00.

CNTn

(

Toggle)

OCn Interrupt Flag Set

1 4

eriod 2 3

(COMn1:0 = 1)

fOCn fclk_I/O

2N1OCRn+()⋅⋅

-----------------------------------------------=

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Fast PWM Mode The fast Pu lse Width Mo dulat ion or fast PWM mod e (WGM21:0 = 1) prov ides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM

option by its single-slope operation. The counter coun ts from BOTTO M to MAX then

restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare

(OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOT-

TOM. In inverting Compare Output mode, the output is set on Compare Match and

cleared at BOTTOM. Due to the single- slope operation, the operating frequ ency of the

fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-

slope operation. This high frequency makes the fast PWM mode well suited for power

regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefor e reduces total system cost.

In fast PWM mode, th e co un ter is increme nt ed unt il the count er value mat c hes the MAX

value. The counter is then cleared at the following timer clock cycle. The timing diagram

for the fast PWM mode is shown in Figure 64. The TCNT2 value is in t he timi ng diag ram

shown as a histogram for illustrating the single-slope operation. The diagram includes

non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2

slopes represent compare matches between OCR2 and TCNT2.

Figure 64. Fast PWM Mode, Timing Diagram

The Timer/Count er Overflow Flag (TOV2) is set e ach time the counter reaches MAX. If

the interrupt is enabled, the interrupt handler routine can be used for updating the com-

pare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2

pin. Setting the COM21:0 bits to two will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COM21:0 to three (See Table 62 on page

152). The actual OC2 value will only be visible on the port pin if the data direction for the

port pin is set as output. The PWM waveform is generated by setting (or clearing) the

OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or set-

ting) the OC2 Register at the timer clock cycle the counter is cleared (changes from

MAX to BOTTOM).

TCNTn

OCRn Update and

TOVn Interrupt Flag Set

Period

2 3

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

4 5 6 7

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The PWM frequency for th e output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64 , 128, 256, or 1024).

The extreme values for the OCR2 Register represent special cases when generating a

PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the

output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal

to MAX will result in a constantly high or low output (depending on the polarity of the out-

put set by the COM21:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OC2 to toggle its logi cal level on each Compare Ma tch (COM21:0 = 1). The

waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2 is set

to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer

feature of the Output Compare unit is enabled in the fast PWM mode.

Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 3) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-

slope operation. The counter counts repeatedly from BOTTOM to MAX and then from

MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2)

is cleared on the Compare Match between TCNT2 an d OCR2 while up-counting, and

set on the C ompar e Matc h while do wn-cou nting. In invertin g outpu t comp are mod e, the

operation is inverted. The dual-slop e operation ha s lower maxim um operat ion frequency

than single slope operation. However, due to the symmetric feature of the dual-slope

PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase

correct PWM mo de the counter is incr emented until the counte r value matches MAX.

When the counter reaches MAX, it changes the count direction. The TCNT2 value will

be equal to MAX for one timer clock cycle. The timing diagram for the phase correct

PWM mode is shown on Figure 65. The TCNT2 value is in the timing diagram shown as

a histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The sm all horizont al line marks on the TCNT2 slope s r epre-

sent compare matches between OCR2 and TCNT2.

Figure 65. Phase Correct PWM Mode, Timing Diagram

fOCnPWM fclk_I/O

N256⋅

------------------=

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

1 2 3

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

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The Timer/Coun ter Overflow Flag (TOV2) is set each time the counter rea ches BOT-

TOM. The Interrupt Flag can be use d to generate an interrupt each time the counter

reaches the BOTTOM value.

In phase corr ect PWM mode, the compare uni t allows generation of PWM waveforms on

the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM. An

inverted PWM output can be generated by setting the COM21:0 to three (See Table 63

on page 152). The actual OC2 value will only be visible on the port pin if the data direc-

tion for the port pin is set a s output. The PWM waveform is gen erated by clearing (or

setting) the OC2 Register at the Compare Match between OCR2 and TCNT2 when the

counter increments, and setting (or clearing) the OC2 Register at Compare Match

between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the

output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64 , 128, 256, or 1024).

The extreme values for the OCR2 Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

At the very start of period 2 in Figure 65 OCn has a transition from high to low even

though there is no Compar e Match. The poi nt of th is transit ion is to gu arantee symmetr y

around BOTTOM. There are two cases that give a transition without a Compare Match.

• OCR2 changes its value from MAX, lik e in Figure 65. When the OCR2 v alue is MAX

the OCn pin v alue is the same as the re sult of a do wn -counting Comp are Match . To

ensure symmetry around BOTTOM the OCn value at MAX must correspond to the

result of an up-counting Compare Match.

• The timer starts counting from a value higher than the one in OCR2, and for that

reason misses the Compare Match and hence the OCn change that would have

happened on the way up.

Timer/Counter Timing

Diagrams The following figures show t he Timer/ Cou nter in syn chro nou s mo de, a nd t he ti mer clock

(clkT2) is therefore sh own a s a clo ck enab le signa l. I n as yn chro nou s m ode , clk I/O should

be replaced by the Timer/Counter Oscillator clock. The figures include information on

when Interrupt Flags are set. Figure 66 contains timing data for basic Timer/Counter

operation. The fig ure shows the count sequence close to th e MAX value in all modes

other than phase correct PWM mode.

fOCnPCPWM fclk_I/O

N510⋅

------------------=

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Figure 66. Timer/Counter Timing Diagram, no Prescaling

Figure 67 shows the same timing data, but with the prescaler enabled.

Figure 67. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 68 shows the setting of OCF2 in all modes except CTC mode.

Figure 68. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)

Figure 69 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.

clk

(clkI/O/1)

TOVn

clk

I/O

CNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

CNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

OCFn

OCRn

CNTn

OCRn Value

OCRn - 1 OCRn OCRn + 1 OCRn + 2

clk

I/O

clk

(clkI/O/8)

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Figure 69. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with

Prescaler (fclk_I/O/8)

8-bit Timer/Counter

Timer/Counter Control

• Bit 7 – FOC2: Force Output Compare

The FOC2 bit is only active wh en the WGM b its specify a non- PWM mode. Howeve r, for

ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is

written when operating in PWM mode. When writing a logical one to the FOC2 bit, an

immediate Compare Match is forced on the Waveform Generation unit. The OC2 output

is changed according t o its COM21:0 bits sett ing. Note that the FO C2 bit is implem ented

as a strobe. Therefore it is the value present in the COM21:0 bits that determines the

effect of the forced compare.

A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode

using OCR2 as TOP.

The FOC2 bit is always read as zero.

• Bit 6, 3 – WGM21:0: Waveform Generation Mode

These bits control the coun ting sequence of the counter, the source for the maximum

(TOP) counter value , and what type of waveform generation to be use d. Modes of oper-

ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare

OCFn

OCRn

CNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

Bit 76543210

FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 TCCR2

Read/Write W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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match (CTC) mode, a nd two t ypes of Pulse Width Modulatio n (PWM) modes. See Table

60 and “Modes of Oper ation” on page 144.

Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-

initions. However, the functionality and location of these bits are compatible with

previous versions of the timer.

Table 60. Waveform Generation Mode Bit Description(1)

Mode WGM21

(CTC2) WGM20

(PWM2) Timer/Counter Mode

of Operation TOP Update of

OCR2 at TOV2 Flag

Set on

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM

2 1 0 CTC OCR2 Immediate MAX

3 1 1 Fast PWM 0xFF TOP MAX

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• Bit 5:4 – COM21 :0: Compare Match Output Mode

These bits control the Output Compare pin (OC2) behavior. If one or both of the

COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O

pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-

sponding to OC2 pin must be set in order to enable the output driver.

When OC2 is connected to the pin, the function of the COM21:0 bits depends on the

WGM21:0 bit setting. Tab le 61 sh ows the COM21:0 bit fun ctionalit y when the WGM21 :0

bits are set to a normal or CTC mo d e (n on -P WM ).

Table 62 shows the COM21:0 bit fun ctionality when the WGM21:0 bits are set to fast

PWM mode.

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the

Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM

Mode” on page 146 for more details.

Table 63 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase

correct PWM mode.

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the

Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct

PWM Mode” on page 147 for more details.

Table 61. Compare Output Mode, non-PWM Mode

COM21 COM20 Description

0 0 Normal port operation, OC2 disconnected.

0 1 Toggle OC2 on Compare Match.

1 0 Clear OC2 on Compare Match.

1 1 Set OC2 on Compare Match.

Table 62. Compare Output Mode, Fast PWM Mode(1)

COM21 COM20 Description

0 0 Normal port operation, OC2 disconnected.

01Reserved

1 0 Clear OC2 on Compare Match, set OC2 at TOP.

1 1 Set OC2 on Compare Match, clear OC2 at TOP.

Table 63. Compare Output Mod e, Phase Correct PWM Mode(1)

COM21 COM20 Description

0 0 Normal port operation, OC2 disconnected.

01Reserved

1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare

Match when down-counting.

1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare

Match when down-counting.

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• Bit 2:0 – CS22:0: Clock Se lect

The three Cloc k Select bits select the clock source to be used by the Time r/Counter, see

Table 64.

Timer/Counter Register –

TCNT2

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes)

the Compare Match on the following timer clock. Modifying the counter (TCNT2) while

the counter is running, introduces a risk of missing a Compare Ma tch between TCNT2

and the OCR2 Register.

Output Compare Register –

OCR2

The Output Compare Register contains an 8-bit value that is continuously compared

with the counter value (TCNT2). A match can be used to generate an output compare

interrupt, or to generate a waveform output on the OC2 pin.

Table 64. Clock Select Bit Description

CS22 CS21 CS20 Description

0 0 0 No clock source (Timer/Counter stopped).

001clkT2S/(No prescaling)

010clk

T2S/8 (From prescaler)

011clk

T2S/32 (From prescaler)

100clk

T2S/64 (From prescaler)

101clk

T2S/128 (From prescaler)

110clk

T2S/256 (From prescaler)

111clk

T2S/1024 (From prescaler)

Bit 76543210

TCNT2[7:0] TCNT2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR2[7:0] OCR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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Asynchr onous operation

of the Timer/Counter

Asynchronous Status

• Bit 3 – AS2: Asynchronous Timer/Counter2

When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When

AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to

the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of

TCNT2, OCR2, and TCCR2 migh t be corrupted.

• Bit 2 – TCN2UB: Timer/Counter2 Update Busy

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes

set. When TCNT2 has been updated from the temporary storage register, this bit is

cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be

updated with a new value.

• Bit 1 – OCR2UB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes

set. When OCR2 has been updated from the temporary storage register, this bit is

cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be

updated with a new value.

• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy

When Timer/Counte r2 opera te s a synchron ou sly and TCCR2 is written, this bit becomes

set. When TCCR2 has been updated from the temporary storage register, this bit is

cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be

updated with a new value.

If a write is performed to any of the three Timer/Counter2 Registers while its update

Busy Flag is set, the updated value might get corrupted and cause an u nintentional

interrupt to occur.

The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading

TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the

temporary storage register is read.

Bit 76543 2 1 0

–––– AS2 TCN2UB OCR2UB TCR2UB ASSR

Read/WriteRRRRR/WR R R

Initial Value 0 0 0 0 0 0 0 0

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Asynchronous Operation of

Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be

corrupted. A safe procedure for switching clock source is:

1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.

2. Select clock source by setting AS2 as appropriate.

3. Write new values to TCNT2, OCR2, and TCCR2.

4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and

TCR2UB.

5. Clear the Timer/Counter2 Interrupt Flags.

6. Enable interrupts, if needed.

• The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an

external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation.

The CPU main clock frequency must be more than four times the Oscillator

frequency.

• When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is

transferred to a temporary register, and latched after two positiv e edges on TOSC1.

The user should not write a new value before the contents of the temporary register

have been transferred to its dest inatio n. Each of the three mention ed reg isters h a ve

their individual t emporary register , which means t hat e.g., writing to TCNT2 does n ot

disturb an OCR2 write in progress. To detect that a transfer to the destinatio n

implemented.

• When entering Power-save or Extended Standby mode after having written to

TCNT2, OCR2, or TCCR2, the user must wait until the written register has been

updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will

enter sleep mode before the changes are effective. This is particularly important if

the Output Compare2 interrupt is used to wake up the device, since the output

compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is

not finished, and the MCU enters sleep mode before the OCR2UB bit returns to

zero, the device will nev er receive a Compare Match interrupt, and the MCU will not

wake u p.

• If Timer/Counte r2 is used to wake the device up from Power-save or Extended

Standb y mode, precauti ons must be t ak e n if the user w a nts t o re- enter one o f these

modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between

wak e-up and re-entering sleep mode is less than one T OSC1 cycle, the interrupt will

not occur, and the device will fail to wak e up. If the user is in doubt whether the time

bef ore re-entering P o wer-sa ve or Extend ed Standby mode is sufficient, the f ollowing

algorithm can be used to ensure tha t one TOSC1 cycle has elapsed:

1. Write a value to TCCR2, TCNT2, or OCR2.

2. Wait until the corresponding Update Busy Flag in ASSR returns to zero.

3. Enter Power-save or Extended Standby mode.

• When the asynchronous operation is selected, the 32.768 kHz Oscillator for

Timer/Counter2 is alw a ys running, e xcept in Pow er-down and Standb y mod es. Af ter

a Power-up Reset or wake- up from Po wer-down or Standby mode, the user should

be aw are of the fact that this Oscillator might tak e as long as one second to stabilize.

The user is advised to wait for at least one second before using Timer /Counter2

after Power-up or wake-up from Power-down or Standby mode. The contents of all

Timer/Counter2 Registers must be considered lost after a wake-up from Power-

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down or Standby mode due to unstable clock signal upon start-up, no matter

whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

• Description of wake up from Power-save or Extended Standby mode when the

Timer is clocked asynchronously: When th e interrupt condition is met, the wake up

process is started on the following cycle of the timer clock, that is, the Timer is

always advanced by at least one before the processor can read the counter v alue.

After wake-u p, the MCU is halted for four cycles, it exe cutes the interrupt routin e,

and resumes execution from the instruction following SLEEP.

• Reading of the TCNT2 Re gister shortly after wak e-up from Power -save may giv e an

incorrect result. Since TCNT2 is clocke d on t he asynchr onous TOSC clock, reading

TCNT2 must be done through a register synch ronized to the internal I/O clock

domain. Synchronization takes place for e very rising TOSC1 edge. When waking up

from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will

read as the pre vious v alue (b ef ore entering sleep) until the next rising T OSC1 edge .

The phase of the TOSC clock after waking up from Power-save mode is essentially

unpredictab le , as it de pends on the w ak e- up time . The reco mmended pr ocedure for

reading TCNT2 is thus as follows:

1. Write any value to either of the registers OCR2 or TCCR2.

2. Wait for the corresponding Update Busy Fla g to be cleared.

3. Read TCNT2.

• During asynchronous operation, the synchronization of the Interrupt Flags for the

Asynchronous Timer takes three processor cycles plus one timer cycle. The Timer

is theref ore adv anced b y at least one bef ore the processor can read the Timer v alue

causing the settin g of the Interrupt Flag. The output compare pin is changed on the

Timer clock and is not synchronized to the processor clock.

Timer/Counter Interrupt Mask

• Bit 4 – OCIE2: Timer/Counter2 Out put Compare Match Interrupt Enable

When the OCIE2 bit is written to one and the I -bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is

executed if a Compare Ma tch in Timer/Co unter2 occurs, i.e., when the OCF2 bit is set in

the Timer/Counter Interrupt Flag Register – TIFR.

• Bit 2 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Ov erflow interr upt is enabled . The correspond ing interrupt is executed if

an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the

Timer/Counter Interrupt Flag Register – TIFR.

Bit 76543210

TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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Timer/Counter Interrupt Flag

• Bit 4 – OCF2: Output Compare Flag 2

The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2

and the data in OCR2 – Outp ut Compare Regist er2. OCF2 is cleared by har dware when

executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by

writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counte r2 Com-

pare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare

Match Interrupt is executed.

• Bit 2 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2

(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the

Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter2 changes counting direction at 0x00.

Bit 76543210

TOV1 OCF1A OC1FB OCF2 ICF1 TOV2 TOV0 OCF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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Timer/Counter Prescaler Figure 70. Prescaler for Timer/Counter2

The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to

the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asyn-

chronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real

Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from

Port D. A crysta l can th en be connec ted be tween the TOSC 1 and TOSC2 p ins to se rve

as an independent clock source for Timer/Counter2. The Oscillator is optimized for use

with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not

recommended.

For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clk T2S/32, clkT2S/64,

clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be

selected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to

operate with a pred ictable prescaler .

Special Function IO Register –

SFIOR

• Bit 1 – PSR2: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally

cleared immediately by hardware. If this bit is written when Timer/Counter2 is operating

in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit

will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7

– TSM: Timer/Counter Synchronization Mode” on page 106 for a description of the

Timer/Counter Synchronization mode.

10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

clkI/O clkT2S

OSC1

AS2

CS20

CS21

CS22

clkT2S

/64

clkT2S

/128

clkT2S

/1024

clkT2S

/256

clkT2S

/32

PSR2

Clear

clkT2

Bit 7 6 5 4 3 2 1 0

TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Val-

ue 00000000

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Serial Peripheral

Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between the ATmega162 and peripheral devices or between several AVR devices. The

ATmega162 SPI includes the following features:

•Full-duplex, Three-wire Synchronous Data Transfer

•Master or Slave Operation

•LSB First or MSB First Data Transfer

•Seven Programmable Bit Rates

•End of Transmissi on Interru pt Flag

•Write Collision Flag Protection

•Wake-up from Idle Mode

•Double Speed (CK/2) Master SPI Mode

Figure 71. SPI Block Diagram(1)

Note: 1. Refer to Figure 1 on pa ge 2, and Table 32 on page 73 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 72.

The system consists of two Shift Registers, and a Master clock generator. The SPI Mas-

ter initiates the communication cycle when pulling low the Slave Select SS pin of the

desired Slave. Master and Slave prepare the data to be sent in their respective Shift

Registers, and the Master generates the required clock pulses on the SCK line to inter-

change data. Data is always shifted from Master to Slave on the Master Out – Slave In,

MOSI, line, and fr om Slave to Master on th e Master In – Slave Out, M ISO, line. After

each data packet, the Master will synchronize the Slave by pulling high the Slave Select,

SS, line.

SPI2X

DIVIDER

/2/4/8/16/32/64/128

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When configured as a Master, the SPI interface has no automatic control of the SS line.

This must be handled by user software before communication can start. When this is

done, writing a byte to the SPI Data Register starts the SPI clock generator, and the

hardware shifts t he eight bits int o the Slave. Af te r sh ift ing on e byt e, t he SPI clo ck gene r-

ator stops, setting the End of Transmission Flag (SPIF). If the SPI Interrupt Enable bit

(SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue

to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high

the Slave Select, SS line. The last inco ming byte will be kept in the buffer register for

later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated

as long as the SS pin is driven high. In this state, software may u pdate the contents of

the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock

pulses on the SCK pin until the SS pin is driven low. As one b yte has been completely

shifted, the End of Transmission Flag, SPIF is set. If the SPI interrupt enable bit, SPIE,

in the SPCR Register is set, an interrupt is requested. The Slave may continue to place

new data to be sent into SPDR before readin g the incoming da ta. The last incom ing byte

will be kept in the Buffer Register for later use.

Figure 72. SPI Master-slave Interconnection

The system is single buff ered in th e transmit dir ection and doub le buffere d in the re ceive

direction. This means that bytes to be transmitted cannot be written to the SPI Data

received character must be read from the SPI Data Register before th e next character

has been completely shifted in. Otherwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To

ensure correct sampling of the clock signal, the minimum low and high periods should

be:

Low periods: Longer th an 2 CPU clock cycles.

High periods: Longer than 2 CPU clock cycles.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is

overridden according to Table 65. For more details on automatic port overrides, refer to

“Alternate Port Functions” on page 69.

MSB MASTER LSB

8-BIT SHIFT REGISTER

MSB SLAVE LSB

8-BIT SHIFT REGISTER

MISO

MOSI

SPI

CLOCK GENERATOR

SCK

MISO

MOSI

SCK

VCC

SHIFT

ENABLE

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Note: 1. See “Alternate Functions Of Port B” on page 73 for a detailed description of how to

define the direction of the user defined SPI pins.

The following code examples sho w how to init ial ize th e SPI as a Ma st er a nd h ow to pe r-

form a simple transmission. DDR_SPI in the examples must be replaced by the actual

Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO, and DD_SCK

must be replaced by the actual data direction bits for these pins. E.g., if MOSI is placed

on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.

Table 65. SPI Pin Overrides(1)

Pin Direction, Master SPI Direction, Slave SPI

MOSI User Defined Input

MISO Input User Defined

SCK User Defined Input

SS User Defined Input

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Note: 1. The example code assumes that the part specific header file is included.

Assembly Code Example(1)

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

sbis SPSR,SPIF

rjmp Wait_Transmit

ret

C Code Example(1)

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

}

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The following code examples show how to initialize the SPI as a slave and how to per-

form a simple reception.

Note: 1. The example code assumes that the part specific header file is included.

Assembly Code Example(1)

SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in r16,SPDR

ret

C Code Example(1)

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return data register */

return SPDR;

}

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SS Pin Functionality

Slave Mode When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When

SS is held low, the SPI is activated, and MISO becomes an output if configured so by

the user. All other pins are in puts. When SS is driven high, all pins a re inputs, and the

SPI is passive, which means that it will not receive incoming data. Note that the SPI

logic will be reset once the SS pin is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter syn-

chronous with the master clock gener ator. When the SS pin is d riven high, the SPI Slave

will immediately reset the send and receive logic, and drop any partially received data in

the Shift Register.

Master Mode When the SPI is configured as a Master (M STR in SPCR is set), the user can determine

the direction of the SS pin.

If SS is configured as an out p ut, the pin is a ge neral ou tp ut p in wh ich does n ot aff ect t he

SPI system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If

the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master

with the SS pin defined as an input, the SPI system interprets this as another Master

selecting the SPI as a slave And starting to send data to it. To avoid bus contention, the

SPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a

result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF Flag in SPSR is set, and if the SPI inte rrupt is enabled, and the I- bit in

SREG is set, the interrupt routine will be executed.

Thus, when inte rrupt-dr iven SPI t ransmission is used in Master mode, and t here exists a

possibility that SS is driven low, the interrupt should always check that the MSTR bit is

still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to

re-enable SPI Master mode.

SPI Control Register – SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set

and the if the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is ena bled. This bit must be set to enable

any SPI operation s.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

Bit 76543210

SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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• Bit 4 – MSTR: Master/Slave Select

This bit selects Mast er SPI mode when writ ten to one, an d Slave SPI mode when wr itten

logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will

be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to

re-enable SPI Master mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero,

SCK is low when idle . Refer to F igure 73 a nd Figure 74 for an exa mple. The CPO L func-

tionality is summarized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clo ck Phase bit (CPHA) determ ine if data is sam pled on the lead ing

(first) or trailing (last) edge of SCK. Refer to Figure 73 and Figure 74 for an exam ple.

The CPHA functionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and

SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator

Clock frequency fosc is shown in the following table:

Table 66. CPOL Functionality

CPOL Leading Edge Trailing Edge

0 Rising Falling

1 Falling Rising

Table 67. CPHA Functionality

CPHA Leading Edge Trailing Edge

0 Sample Setup

1 Setup Sample

Table 68. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency

000

fosc/4

001

fosc/16

010

fosc/64

011

fosc/128

100

fosc/2

101

fosc/8

110

fosc/32

111

fosc/64

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SPI Status Register – SPSR

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if

SPIE in SPCR is set and global int errupts are en abled. If SS is an input and is driven low

when the SPI is in master mode, this will also set the SPIF Flag. SPIF is cleared by

hardware when executing the corresponding interrupt handlin g vect or. Alt ernative ly, th e

SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then acce ssing

the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.

The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register

with WCOL set, and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATmega162 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when

the SPI is in Master mode (see Table 68). This means that the minimum SCK period will

be two CPU clock periods. When the SPI is conf igured as Slav e, the SPI is only guar a n-

teed to work at fosc/4 or lower.

The SPI interface on the ATmega162 is also used for program memory and EEPROM

downloading or uploading. See page 247 for SPI serial programming and verification.

SPI Data Register – SPDR

The SPI Data Registe r is a re ad /wri te register used fo r da ta transf er between t he Regis-

ter File and the SPI Shift Register. Writing to the register initiates data transmission.

Reading the register causes the Shift Register receive buffer to be read.

Bit 76543210

SPIF WCOL – – – – – SPI2X SPSR

Read/WriteRRRRRRRR/W

Initial Value00000000

Bit 76543210

MSB LSB SPDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value X X X X X X X X Undefined

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Data Modes There are four combinations of SCK phase and polarity with respect to serial data,

which are determined by control bits CPHA and CPOL. The SPI data transfer formats

are shown in Figure 73 and Figure 74. Data bits are shifted out and latched in on oppo-

site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is

clearly seen by summarizing Table 66 and Table 67, as done below:

Figure 73. SPI Transfer Format with CPHA = 0

Figure 74. SPI Transfer Format with CPHA = 1

Table 69. CPOL and CPHA Functionality

Leading Edge Trailing Edge SPI Mode

CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0

CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1

CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2

CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3

Bit 1

Bit 6 LSB

MSB

SCK (CPOL = 0)

mode 0

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 2

MSB

LSB Bit 6

Bit 1 Bit 5

Bit 2 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5

MSB first (DORD = 0)

LSB first (DORD = 1)

SCK (CPOL = 0)

mode 1

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 3

MSB

LSB Bit 6

Bit 1 Bit 5

Bit 2 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6 LSB

MSB

MSB first (DORD = 0)

LSB first (DORD = 1)

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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART) is a highly flexible serial communication device. The main features are:

•Full Duplex Operation (Independent Serial Receive and Transmit Registers)

•Asynchronous or Synchronous Operation

•Master or Slave Clocked Synchronous Operation

•High Resolution Baud Rate Generator

•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

•Odd or Even Parity Gene ration and Parity Check Supported by Hardware

•Data OverRun Detection

•Framing Error Detection

•Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

•Three Separate Interrupts on TX Complete, TX Data Register Empty an d R X Comp le te

•Multi-processor Communication Mode

•Double Speed Asynchronous Communication Mode

Dual USART The ATmega162 has two USARTs, USART0 and USART1. The functionality for both

USARTs is described below.

USART0 and USART1 have diff erent I/O Registers as shown in “Register Summary” on

page 306. Note that in ATmega161 compatibility mode, the double buffering of the

USART Receive Register is disabled. For details, see “AVR USART vs. AVR UART –

Compatibility” on page 170. Note also that the shared UBRRHI Register in ATmega161

has been split into two separate registers, UBRR0H and UBRR1H, in ATmega162.

A simplified block diagram of the USART Tr ansmitter is shown in Figure 75. CPU acces-

sible I/O Registers and I/O pins are shown in bold.

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Figure 75. USART Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Table 34 on page 75, Table 39 on p age 81, and Table

40 on page 81 for USART pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART

(listed from the top): Clock Generator, Transmitter and Receiver. Control registers are

shared by all units. The Clock Generation logic consists of synchronization logic for

external clock input used by synchronous slave operation, and the baud rate generator.

The XCK (Transfer Clock) pin is only used by synchronous transfer mode. The Trans-

mitter consists of a single write buffer, a serial Shift Register, parity generator and

control logic for handling different serial frame formats. The write buffer allows a contin-

uous transfer of data without any delay between frames. The Receiver is the most

complex part of the USART m od u le du e to its clock and data recovery units. The recov-

ery units are used fo r asynchron ous data re ception . In additi on to the r ecovery unit s, the

Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDR). The receiver supports the same frame formats as the Transmitter,

and can detect Frame Error, Data OverRun and Parity Errors.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA UCSRB UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

DATABUS

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

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AVR USART vs. AVR UART –

Compatibility The USART is fully compatible with the AVR UART regarding:

• Bit locations inside all USART Registers

• Baud Rate Generation

• Transmitter Operation

• Transmit Buffer Functionality

• Receiver Operation

However, the receive buffering has two improvements that will affect the compatibility in

some special cases:

• A second Buffer Register has been added. The two buffer registers operate as a

circular FIFO buffer. Therefore the UDR must only be read once for each incoming

data! More important is the fact that the Error Flags (FE and DOR) and the ninth

data bit (RXB8) ar e b uffered with the data in the receive buff e r. Theref ore the status

bits must always be read before the UDR Register is read. Otherwise the error

status will be lost since the bu ffer state is lost.

• The Receiver Shift Register can now act as a third buffer level. This is done by

allowing th e receiv ed data to remain in the serial Shift Register (see Figure 75) if the

Buffer Registers are full, until a new start bit is detected. The USART is therefore

more resistant to Data OverRun (DOR) error conditions.

The following control bits have changed name, but have same functionality and register

location:

• CHR9 is changed to UCSZ2.

• OR is changed to DOR.

Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver.

The USART supports four modes of clock operation: Normal asynchronous, Double

Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL

bit in USART Control and Status Register C (UCSRC) selects between asynchronous

and synchronous operation. Double Speed (asynchronous mode only) is controlled by

the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1),

the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock

source is internal (Master mode) or external (Slave mode). The XCK pin is only active

when using synchronous mode.

Figure 76 shows a block diagram of the clock generation logic.

Figure 76. Clock Generation Logic, Block Diagram

Prescaling

Down-Counter / 2

UBRR

/ 4 / 2

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK rxclk

Edge

Detector

UCPOL

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Signal description:

txclk Transmitter clock. (Internal Signal)

rxclk Receiver base clock. (Internal Signal)

xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.

xcko Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc XTAL pin frequency (System Clock).

Internal Clock Generation –

The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master

modes of operation. The description in this section refers to Figure 76.

The USART Baud Rate Register (UBRR) and the down-counter connected to it function

as a programmable prescaler or baud rat e generato r. The do wn-counter , running at sys-

tem clock (fosc), is loaded with the UBRR value each time the counter has counted

down to zero or when the UBRRL Regist er is wr itten. A clock is generat ed ea ch time t he

counter reaches zero. This clock is the baud rate generator clock output (=

fosc/(UBRR+1)). The Transmitt er divides th e baud rat e gener ator clock outpu t by 2, 8 or

16 depending on m ode. The baud rate gener ator output is used directly by the r eceiver’s

clock and data recovery units. Howeve r, the recovery units use a state machine that

uses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X and

DDR_XCK bits.

Table 70 contains equations for calculating the baud rate (in bits per second) and for

calculating the UBRR value for each mode of op eration using an internally generated

clock source.

Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).

BAUD Baud rate (in bits per second, bps)

fOSC System Oscillator clock frequency

UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)

Some examples of UBRR values for some system clock frequencies are found in Table

78 (see page 193).

Table 70. Equations for Calculat ing Baud Rate Register Setting

Operating Mode Equation for Calculating

Baud Rate(1) Equation for Calculating

UBRR Value

Asynchronous Normal Mode

(U2X = 0)

Asynchronous Double Speed

Mode (U2X = 1)

Synchronous Master Mode

BAUD fOSC

16 UBRR 1+()

-----------------------------------

----

=UBRR fOSC

16BAUD

------------------------

–=

BAUD fOSC

8UBRR 1+()

--------------------------------

---

=UBRR fOSC

8BAUD

--------------------

–=

BAUD fOSC

2UBRR 1+()

--------------------------------

---

=UBRR fOSC

2BAUD

--------------------

–=

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Double Speed Operation

(U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only

has effect for the asynchronous operation. Set this bit to zero when using synchronous

operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively

doubling the transfer rate for asynchronous communication. Note however that the

Receiver will in this case only use half the n umb er of samples ( reduce d f rom 16 t o 8) f or

data sampling and clock recovery, and therefore a more accurate baud rate setting and

system clock are required when this mode is used. For the T ransmitter, there are no

downsides.

External Clock External clocking is used by the synchronous slave modes of opera tio n. The descr ipt ion

in this section refers to Figure 76 for details.

External clock input from the XCK pin is sampled by a synchronization register to mini-

mize the chance of meta-stability. Th e output from the synchronization register must

then pass through an edge detector before it can be used by the Transmitter and

Receiver. This process introduces a two CPU clock perio d dela y and ther ef ore t he max-

imum external XCK clock frequency is limited by the following equation:

Note that fosc depends on the stability of the system clock source. It is therefore recom-

mended to add some margin to avoid possible loss of data due to frequency variations.

Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock

input (Slave) or clock output (Master). The dependency between the clock edges and

data sampling or data change is the same. The basic principle is that data input (on

RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is

changed.

Figure 77. Synchronous Mode XCK Timing.

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and

which is used for data change. As Figure 77 shows, when UCPOL is zero the data will

be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the

data will be changed at falling XCK edge and sampled at rising XCK edge.

XCK fOSC

--------

---

RxD / TxD

XCK

RxD / TxD

XCK

UCPOL = 0

UCPOL = 1

Sample

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Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start

and stop bits), and optiona lly a parity bit for error checking. The USART a ccepts all 30

combinations of the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

A frame starts with th e start bit followed by the least sig nificant data bit. Then the next

data bits, up to a total of nine, are succeeding, ending with the most significant bit. If

enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-

plete frame is transmitted, it can be directly followed by a new frame, or the

communicatio n line can be set to an idle (high) state. Figure 78 illustrates the possible

combinations of the frame f ormats. Bits inside brackets are optional.

Figure 78. Frame Formats

St Start bit, always low.

(n) Data bits (0 to 8).

PParity bit. Can be odd or even.

Sp Stop bit, always high.

IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be

high.

The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in

UCSRB and UCSRC. The Receiver and Transmitter use the same settin g. Note that

changing the setting of any of these bits w ill corrupt all ongoing communication for both

the Receiver and Transmitte r.

The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.

The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selec-

tion between one or two stop bits is done by the USART Stop Bit Select (USBS) bit . The

receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected

in the cases where the first stop bit is zero.

Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is

used, the result of the exclusive or is inverted. The relation between the parity bit and

data bits is as follows::

Peven Parity bit using even parity

Podd Parity bit using odd parity

dnData bit n of the character

10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)

FRAME

Peven dn1–…d3d2d1d00

Podd

⊕⊕⊕⊕⊕⊕

dn1–…d3d2d1d01⊕⊕⊕⊕⊕⊕

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If used, the parity bit is located between the last data bit and first stop bit of a serial

frame.

USART Initialization The USART has to be initia lized before any commun ication can take place. The initial-

ization process normally consists of setting the baud rate, setting frame format and

enabling the Transmitter or the Receiver depending on the usage. For interrupt driven

USART operation, the Global Interrupt Flag should be cleared (and interrupts globally

disabled) when doing the initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that

there are no ongoing transmissions during the period the registers are changed. The

TXC Flag can be used to check that the Transmitte r has complete d all transfer s, and the

RXC Flag can be used to check that there are no unread data in the receive buffe r. Note

that the TXC Flag must be cleared before each transmission (before UDR is written) if it

is used for this purpose.

The following simple USART initialization code examples show one assembly and one

C function that are equal in functionality. The examples assume asynchronous opera-

tion using polling (no interrupts enabled) and a fixed frame format. The baud rate is

given as a function parameter. For the assembly code, the baud rate p arameter is

assumed to be stored in the r17:r16 Registers. When the function writes to the UCSRC

and UCSRC.

Note: 1. The example code assumes that the part specific header file is included.

More advanced initialization rout ines ca n be made that in clude f rame fo rmat as pa rame-

ters, disable interrupts and so on. However, many applications use a fixed setting of the

Assembly Code Example(1)

USART_Init:

; Set baud rate

out UBRRH, r17

out UBRRL, r16

; Enable receiver and transmitter

ldi r16, (1<<RXEN)|(1<<TXEN)

out UCSRB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0)

out UCSRC,r16

ret

C Code Example(1)

void USART_Init( unsigned int baud )

{

/* Set baud rate */

UBRRH = (unsigned char)(baud>>8);

UBRRL = (unsigned char)baud;

/* Enable receiver and transmitter */

UCSRB = (1<<RXEN)|(1<<TXEN);

/* Set frame format: 8data, 2stop bit */

UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0);

}

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Baud and Control Registers, and for these types of applications the initialization code

can be placed directly in the m ain routine, or be combined with initialization code for

other I/O modules.

Data Transmission – The

USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the

UCSRB Register. When the Tra nsmitter is enabled, the normal por t operation of the

TxD pin is overridden by the USART and given the function as the transmitter’s serial

output. The baud rate, mode of operation and frame format must be set up once before

doing any transmissions. If synchronous operation is used, the clock on the XCK pin will

be overridden and used as transmission clock.

Sending Frames with 5 to 8

Data Bit A data transmission is initiated by loading the transm it buffer with the data to be trans-

mitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The

buffered data in the transmit buffer will be moved to the Shift Register when the Shift

in idle state (no ongoing transmission) or immediately after the last stop bit of the previ-

ous frame is transmitted. When the Shift Register is loaded with new data, it will transfer

one complete frame at the rate given by the Baud Register, U2X bit or by XCK depend-

ing on mode of operation.

The following code examples show a simple USART transmit function based on polling

of the Data Register Empty (UDRE) Flag. When using frames with le ss than eight bits,

the most significant bit s writt en to th e UDR are ignore d. The USART has to be initialized

before the f un ctio n can be u sed. Fo r the assemb ly co de, t he dat a to be se nt is assumed

to be stored in Register R16

Note: 1. The example code assumes that the part specific header file is included.

The function simply waits for the transmit buffer to be empty by checking the UDRE

Flag, before loading it with new data to be transmitted. If the Data Register Empty inter-

rupt is utilized, the interrupt routine writes the data into the buffer.

Assembly Code Example(1)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example(1)

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Put data into buffer, sends the data */

UDR = data;

}

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Sending Frames with 9 Data

Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in

UCSRB before the low byte of the character is written to UDR. The following code

examples show a transmit function that handles 9-bit characters. For the assembly

code, the data to be sent is assumed to be stored in Registers R17:R16.

Note: 1. These transmit functions are written to be general functions. They can be optimized if

the contents of the UCSRB is static. For example, only the TXB8 bit of the UCSRB

The ninth bit can be used for indicating an address frame when using multi processor

communication mode or for other protocol handling as for example synchronization.

Transmitter Flags and

Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register

Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating

interrupts.

The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to

receive new data. This bit is set when the transmit buffer is em pty, and cleared when t he

transmit buffer contai ns data to be transmitt ed that has not ye t been moved into t he Shift

the UCSRA Register.

When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one,

the USART Data Register Empty Interrupt will be executed as long as UDRE is set (pro-

vided that global interrupts are enabled). UDRE is cleared by writing UDR. When

interrupt-driven data transmission is used, the Data Reg ister Empty Interrupt routine

must either write new data to UDR in order to clear UDRE or disable the Data Register

Assembly Code Example(1)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB8

cbi UCSRB,TXB8

sbrc r17,0

sbi UCSRB,TXB8

; Put LSB data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example(1)

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Copy 9th bit to TXB8 */

UCSRB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDR = data;

}

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Empty Interrupt, otherwise a new interrupt will occur once the interrupt routine

terminates.

The Transmit Complete (TXC) Flag bit is set one when the entire frame in the Transmit

Shift Register has been shifted out and there are no new data currently present in the

transmit buffer. The TXC Flag bit is automatically cleared when a transmit complete

interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC

Flag is useful in half-duplex communication interfaces (like the RS-485 standard), where

a transmitting application must enter Receive mode and free the communication bus

immediately after completing the transmission.

When the Transmit Com pete Interr upt Enable (TXCIE) bit in UCSRB is set, the USART

Transmit Complete Interrupt will be executed when the TXC Flag becomes set (pro-

vided that global interrupts are enabled). When the transmit complete interrupt is used,

the interrupt handlin g r out ine do es no t have to clear the TXC Flag , this is d on e aut oma t-

ically when the interrupt is executed.

Parity Generator The Parity Generator calculates the parity bit for the serial frame data. When parity bit is

enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last

data bit and the first stop bit of the frame that is sent.

Disabling the Transmitter The disabling of the Transmitter (setting the TXEN to zero) will not become effective

until ongoing and pending transmissions are completed, i.e., when the Transmit Shift

abled, the Transmitter will no longer override the TxD pin.

Data Reception – The

USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the

UCSRB Register to one. When the receiver is enabled, the normal pin operation of the

RxD pin is overridden by the USART and given the function as the receiver’s serial

input. The baud rate, mode of operation and frame format must be set up once before

any serial reception can be done. If synchronou s operation is used , the clock on the

XCK pin will be used as transfer clock.

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Receiving Frames wi th 5 to 8

Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows

the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive

Shift Register until the first stop bit of a frame is received. A second stop bit will be

ignored by the Receiver. When the first stop bit is received, i.e., a complete serial frame

is present in the Receive S hift Register, the contents of the Shift Register will be moved

into the receive buffer. The receive buffer can then be read by reading the UDR I/O

location.

The following cod e example shows a simple USART receive function base d on polling

of the Receive Complete (RXC) Flag. When using frames with less than eight bits the

most significant bits of the data read from the UDR will be masked to z ero. The USART

has to be initialized before the function can be used.

Note: 1. The example code assumes that the part specific header file is included.

The function simply waits for data to be present in the receive buffer by checking the

RXC Flag, before reading the buffer and retu rning the value.

Assembly Code Example(1)

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get and return received data from buffer

in r16, UDR

ret

C Code Example(1)

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get and return received data from buffer */

return UDR;

}

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Receiving Frames with 9 Data

Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in

UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and

UPE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the

UDR I/O location will change the state of the receive buffer FIFO and consequently the

TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both

nine bit characters and the status bits.

Note: 1. The example code assumes that the part specific header file is included.

Assembly Code Example(1)

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in r18, UCSRA

in r17, UCSRB

in r16, UDR

; If error, return -1

andi r18,(1<<FE)|(1<<DOR)|(1<<UPE)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example(1)

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSRA;

resh = UCSRB;

resl = UDR;

/* If error, return -1 */

if ( status & (1<<FE)|(1<<DOR)|(1<<UPE) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

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The receive function example rea ds all the I/O Registers into the Register File before

any computation is done. This gives an optimal receive buffer utilization since the buffer

location read will be free to accept new data as early as possible.

Receive Compete Flag and

Interrupt The USART Receiver has one flag that indicates the receiver state.

The Receive Complete (RXC) Flag indicates if there are unread data present in the

receive buffer. This flag is one when unread data exist in the receive buffer, and zero

when the receive buffer is empty (i. e., does not contain any unre ad data). If the Receiver

is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit

will become zero.

When the Receive Com plete Interrupt Enable (RXCIE) in UCSRB is set, the USART

Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided

that global interrupts are enabled). When interrupt-driven data reception is used, the

receive complete routine must read the received data from UDR in order to clear the

RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.

Receiver Error Flags The USART Receiver has th ree Error Flags: Frame Error (FE), Data OverRun (DO R)

and Parity Error (UPE). All can be accessed by reading UCSRA. Common for the Error

Flags is that they are located in the rece ive buf fer to geth er with the fra me for which th ey

indicate the error status. Due to the buffering of the Error Flags, the UCSRA must be

read before the receive buffer (UDR), since reading the UDR I/O location changes the

buffer read location. Another equality for the Error Flags is that they can not be altered

by software doing a write to the flag location. However, all flags must be set to zero

when the UCSRA is written for upward compatibility of future USART implementations.

None of the Error Flags can generate interrupts.

The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable

frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly

read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This

flag can be used for detecting out-of-sync conditions, detecting break conditions and

protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC

since the receiver ignores all, except for the first, stop bits. For compatibility with future

devices, always set this bit to zero when writing to UCSRA.

The Data O verRun (D OR) Flag in dicates dat a loss due to a receiver buffer full condition.

A Data OverRun occurs when the rece ive buffer is full (two characters), it is a new char-

acter waiting in the Receive Shift Register, and a new start bit is detected. If the DOR

Flag is set there was one or more serial frame lost between the frame last read from

UDR, and the next frame read from UDR. For compatibility with future devices, always

write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the frame

received was successfully moved from the Shift Register to the receive buffer.

The Parity Error (UPE) Fl ag indicates that t he next frame in the r eceive buffer had a Par-

ity Error when received. If parity check is not enabled the UPE bit will always be rea d

zero. For compatibility with future devices, alwa ys set this bit to zero when writing to

UCSRA. For more details see “Parity Bit Calculation” on page 173 and “Parity Checker”

on page 181.

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Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type

of parity check to be performed (odd or even) is selected by the UPM0 bit. When

enabled, the Parit y Checke r calculates the parit y of the data b its in inco ming fram es and

compares the result with the parity bit from the serial frame. The result of the check is

stored in the receive buffer together with the received data and stop bits. The Parity

Error (UPE) Flag can then be read by software to check if the frame had a Parity Error.

The UPE bit is set if the next character that can be read from the receive buffer had a

parity error when received and the parity checking was enabled at that point (UPM1 =

1). This bit is valid until the receive buffer (UDR) is read.

Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from

ongoing receptions will therefore be lost. When disabled (i.e., th e RXEN is set to zero)

the receiver will no longer override the normal function of the RxD port pin. The receiver

buffer FIFO will be flushed when the rece iver is disabled. Remaining data in the buffe r

will be lost

Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer

will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed

during normal operation, due to for instance an error condition, read the UDR I/O loca-

tion until the RXC Flag is cleared. The following code example shows how to flu sh the

receive buffer.

Note: 1. The example code assumes that the part specific header file is included.

Asynchronous Data

Reception The USART includes a clock recove ry and a data recovery unit for handling asynchro-

nous data reception. The clock recovery logic is used for synchronizing the internally

generated baud rate clock to the incoming asynchr onous serial frames at the RxD pin.

The data recovery logic samples and low pass filters each incoming bit, thereby improv-

ing the noise immunity of the receiver. The asynchronous reception operational range

depends on the accuracy of the internal baud rate clock, the rate of the incoming

frames, and the frame size in number of bits.

Asynchronous Clock

Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-

ure 79 illustrates the sampling process of the start bit of an incoming frame. The sample

rate is 16 times the baud rate for Normal mode, and 8 times the baud rate for Double

Speed mode. The horizon tal arrows illustrate the synchronization varia tion due to the

sampling process. Note the larger time variation when using the double speed mode

Assembly Code Example(1)

USART_Flush:

sbis UCSRA, RXC

ret

in r16, UDR

rjmp USART_Flush

C Code Example(1)

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRA & (1<<RXC) ) dummy = UDR;

}

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(U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is

idle (i.e., no communicatio n ac tivit y).

Figure 79. Start Bit Sampling

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD

line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam-

ple as shown in the figure. The clock recovery logic then uses samples 8, 9 and 10 for

Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample

numbers inside boxes on the figure), to decide if a valid start bit is received. If two or

more of these three samples have logical high levels (the majority wins), the start bit is

rejected as a noise spike and th e receiver starts looking for the next high to low-transi-

tion. If however , a va lid start bit is d etected, the clock recovery logic is synchr onized and

the data recovery can begin. The synchronization process is repeated for each start bit.

Asynchronous Data Recovery When the receiv er clock is synchronized to the start bit, the data re covery can begin.

The data recovery unit uses a state machine that has 16 states for each bit in Normal

mode and 8 states fo r e ach b it in Double Spe ed mod e. Figu re 80 sh ows th e samp ling of

the data bits and the parity bit. Each of the samples is given a number that is equal to

the state of the reco very unit.

Figure 80. Sampling of Data and Parity Bit

The decision of the logic level of the received bit is taken by doing a majority voting of

the logic value to the three samples in the center of the received bit. The center samples

are emphasized on the figure by having the sample number inside boxes. The majority

voting process is done as follows: If two or all three samples have high levels, the

received bit is r egistered to be a lo gic 1. If two or all three samples have low levels, the

received bit is registered to be a logic 0. This majority voting process acts as a low pass

filter for the incoming signa l on the RxD pin. The recove ry pro cess is then repeat ed unt il

a complete frame is received . Including t he first stop bit . Note that t he receiver only uses

the first stop bit of a frame.

Figure 81 shows the sampling of the stop bit and the earliest possible beginning of the

start bit of the next fr am e .

12345678 9 10 11 12 13 14 15 16 12

STARTIDLE

BIT 0

1234 5 678120

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

12345678 9 10 11 12 13 14 15 16 1

BIT n

1234 5 6781

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

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Figure 81. Stop Bit Sampling and Next Start Bit Sampling

The same majority voting is done to the stop bit as done for the other bits in the frame. If

the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after

the last of the bits used for majority voting. For Normal Sp eed mode, the first low level

sample can be at point marked (A) in Figure 81. For Double Speed mode the first low

level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-

tion influences the op erational range of the receiver.

Asynchronous Operational

Range The operational range of the receiver is dependent on the mismatch between the

received bit rate and the internally generated baud rate. If the Transmitter is sending

frames at too fast or too slow bit rates, or the internally generated baud rate of the

receiver does not have a similar (see Table 71) base frequency, the receiv er will not be

able to synchronize the frames to the start bit.

The following equations can be used to calculate the ratio of the incoming data rate and

internal receiver baud rate.

DSum of character size and parity size (D = 5 to 10 bit)

SSamples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

SFFirst sample number used for majority voting. SF = 8 for Normal Speed and

SF = 4 for Double Speed mode.

SMMiddle sample number used for majority voting. SM = 9 for Normal Speed and

SM = 5 for Double Speed mode.

Rslow is the ratio o f the slowest inco ming data rat e that can be accepted in relat ion to the

receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be

accepted in relation to the receiver baud rate.

Table 71 and Table 72 list the maximum receiver baud rate error that can be tolerated.

Note that normal speed mode has higher toleration of baud rate variations.

12345678 9 10 0/1 0/1 0/1

STOP 1

1234 5 6 0/1

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

(A) (B) (C)

Rslow D

+()S

S1–DS⋅SF

----------------------------------------

---

=Rfast D

+()S

D1+()SS

--------------------------------

---

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The recommendations of the maximum receiver baud rate error was made under the

assumption that the Receiver and Transmitter equally divide s the maximum total error.

There are two possible sources for the receivers baud rate error. The receiver’s system

clock (XTAL) will always have some minor instability over the supp ly voltage range and

the temperature range. When using a crystal to generate the system clock, this is rarely

a problem, but for a resonato r the system clock may differ more than 2% depending of

the resonat ors tolerance. The second source for the error is mo re controllable. The baud

rate generator can not always do an exact division of the system frequency to get the

baud rate wanted. In this case an UBRR value that gives an acceptable low error can be

used if possible.

Multi-processor

Communication Mode Set ting the Multi- processor Communication mode (MPCM) bit in UCSRA enables a fil-

tering function of incoming frames received by the USART Receiver. Frames that do not

contain address information will be ignored and not put into the receive buffer. This

effectively reduces the number of incoming frames that has to be handled by the CPU,

in a system with multiple MCUs that communicate via the same serial bus. The Trans-

mitter is unaffected by the MPCM setting, but has to be used differently when it is a part

of a system utilizing the Multi-processor Communication mode.

If the receiv er is se t up to rece ive fra mes that cont ain 5 to 8 d ata bits, th en the first s top

bit indicates if th e frame cont ains data or address info rmation. I f the re ceiver is set up for

frames with nine data bits, then the ninth bit (RXB8) is used for identifying address and

data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame

contains an address. When the frame ty pe bit is zero the frame is a data fra me.

Table 71. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2X = 0)

# (Data+Parity Bit) Rslow (%) Rfast (%) Max. Total Error (%) Recommended Max.

Receiver Error (%)

5 93.20 106.67 +6.67/-6.8% ± 3.0

6 94.12 105.79 +5.79/-5.88 ± 2.5

7 94.81 105.11 +5.11/-5.19 ± 2.0

8 95.36 104.58 +4.58/-4.54 ± 2.0

9 95.81 104.14 +4.14/-4.19 ± 1.5

10 96.17 103.78 +3.7 /-3.83 ± 1.5

Table 72. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2X = 1)

# (Data+Parity Bit) Rslow (%) Rfast (%) Max. Total Error (%) Recommended Max.

Receiver Error (%)

5 94.12 105.66 +5.66/-5.88 ± 2.5

6 94.92 104.92 +4.92/-5.08 ± 2.0

7 95.52 104.35 +4.35/-4.48 ± 1.5

8 96.00 103.90 +3.90/-4.00 ± 1.5

9 96.39 103.53 +3.53/-3.61 ± 1.5

10 96.70 103.23 +3.23/-3.30 ± 1.0

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The Multi-processor Communication mode enables several slave MCUs to receive data

from a Master MCU. This is done by first decoding an address frame to find out which

MCU has been addressed. If a particular slave MCU has been addressed, it will receive

the following data frames as normal, while the other slave MCUs will ignore the received

frames until another address frame is received.

Using MPCM For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZ =

7). The nint h bit ( TXB8) must b e set when an a ddress frame (TXB8 = 1) o r cleared when

a data frame (TXB = 0) is being t ransmitted. The slave MCUs must in th is case be set to

use a 9-bit character frame format.

The following procedure should be used to exchange data in Multi-processor Communi-

cation mode:

1. All Slav e MCUs ar e in Mult i-p roces so r Communication mode (MPCM in UCSRA

is set).

2. The Master MCU sends an address frame, and all slaves receive and read this

frame. In the slave MCUs, the RXC Flag in UCSRA will be set as normal.

3. Each Slave MCU reads the UDR Register and determines if it has been

selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next

address byte and keeps the MPCM setting.

4. The addressed MCU will receive all data frames until a new address frame is

received. The other Slave MCUs, which still have the MPCM bit set, will ignore

the data frames.

5. When the last data frame is received by the addressed MCU, the addressed

MCU sets the MPCM bit and waits for a new address frame from master. The

process then repeats from 2.

Using any of the 5- to 8- bit char act er fr ame for mats is possible, but impr act ica l since the

receiver must change betwee n using n and n+1 character frame formats. This makes

full-duplex operation difficult since the Transmitter and Receiver uses the same charac-

ter size setting. If 5 to 8 bit character frames are used, the Transmitter must be set to

use two stop bit (USBS = 1) since the first stop bit is used for indicating the fr ame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit.

The MPCM bit shares the same I/O loca tion as th e TXC Flag and this migh t accidentally

be cleared when using SBI or CBI instructions.

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Accessing UBRRH/

UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore

some special consideration must be taken when accessing this I/O location.

Write Access When doing a write access of this I/O location, the high bit of the value written, the

USART Register Select (URSEL) bit, controls which one of the two registers that w ill be

written. If URSEL is zero during a write operation, the UBRRH value will be updated. If

URSEL is one, the UCSRC setting will be updated.

The following code examples show how to access the two registers.

Note: 1. The example code assumes that the part specific header file is included.

As the code examples illustrate, write accesses of the two registers are relatively unaf-

fected of the sharing of I/O location.

Assembly Code Examples(1)

...

; Set UBRRH to 2

ldi r16,0x02

out UBRRH,r16

...

; Set the USBS and the UCSZ1 bit to one, and

; the remaining bits to zero.

ldi r16,(1<<URSEL)|(1<<USBS)|(1<<UCSZ1)

out UCSRC,r16

...

C Code Examples(1)

...

/* Set UBRRH to 2 */

UBRRH = 0x02;

...

/* Set the USBS and the UCSZ1 bit to one, and */

/* the remaining bits to zero. */

UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1);

...

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Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex opera-

tion. However, in most ap plications, it is rarely necessary to read any of these registers.

The read access is controlled by a timed sequence. Reading the I/O location once

returns the UBRRH Register cont ents. If the register location was read in previous sys-

tem clock cycle, reading the register in the current clock cycle w ill return the UCSRC

contents. Note that the timed sequence for reading the UCSRC is an atomic operation.

Interrupts must therefore be controlled (e.g., by disabling interrupts globally) during the

read operation.

The following code example shows how to read the UCSRC Register contents.

Note: 1. The example code assumes that the part specific header file is included.

The assembly code example returns the UCSRC value in r16.

Reading the UBRRH content s is not an at omic operatio n and ther efor e it can be read as

an ordinary register, as long as the previous instruction did not access the register

location.

Assembly Code Example(1)

USART_ReadUCSRC:

; Read UCSRC

in r16,UBRRH

in r16,UCSRC

ret

C Code Example(1)

unsigned char USART_ReadUCSRC( void )

{

unsigned char ucsrc;

/* Read UCSRC */

ucsrc = UBRRH;

ucsrc = UCSRC;

return ucsrc;

}

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USART Register

Description

USART I/O Data Register –

UDR

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers

share the same I/O address referred to as USART Data Register or UDR. The Transmit

Data Buffer Register (TXB) will be the destination for data written to the UDR Register

location. Reading the UDR Register location will return the contents of the Receive Data

Buffer Register (RXB) .

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter

and set to zero by the Receiver.

The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is

set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART

Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled,

the Transmitter will load the data into the Transmit Shift Register when the Shift Register

is empty. Then the data will be serially transmitted on the TxD pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever

the receive buffer is accessed. Due to this behavior of the receive buffer, do not use

read modify write instructions (SBI and CBI) on this location. Be careful when using bit

test instructions (SBIC and SBIS), since these also will change the state of the FIFO.

USART Control and Status

• Bit 7 – RXC: USART Receive Complete

This flag bi t is set wh en there a re unread data in the r eceive buffer and cleared when the

receive buffer is empty (i.e., does not contain any unread data). If the receiver is dis-

abled, the receive buffer will be flushed and consequently the RXC bit will become zero.

The RXC Flag can be used to gen erate a Receive Complete interrupt (see d escription of

the RXCIE bit).

• Bit 6 – TXC: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted

out and there are no new data currently present in the transmit buffer (UDR). The TXC

Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can

be cleared by writing a one to its bit location. The TXC Flag can generate a Transmit

Complete interr up t (se e description of the TXCIE bit) .

• Bit 5 – UDRE: USART Data Register Empty

The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If

UDRE is one, the buf fer is empt y, and therefor e ready to be writte n. The UDRE Flag can

generate a Data Register Empty interrupt (see description of the UDRIE bit).

Bit 76543210

RXB[7:0] UDR (Read)

TXB[7:0] UDR (Write)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

RXC TXC UDRE FE DOR UPE U2X MPCM UCSRA

Read/Write R R/W R R R R R/W R/W

Initial Value00100000

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UDRE is set after a Reset to indicate that the transmitter is ready.

• Bit 4 – FE: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when

received. I.e., when the first stop bit of the next character in the receive buffer is zero.

This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop

bit of received data is one. Always set this bit to zero when writing to UCSRA.

• Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun condition is detected. A data overrun occurs when the

receive buffer is full (two characters), it is a new character waiting in the reCeive Shift

read. Always set this bit to zero when writing to UCSRA.

• Bit 2 – UPE: Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received

and the Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the

receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

• Bit 1 – U2X: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using

synchronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec-

tively doubling th e tra n sfe r ra te for as yn chr o no us com mu n ica tion .

• Bit 0 – MPCM: Multi- processor Communication Mode

This bit enable s the Multi- processor Communica tion mode. Wh en the MP CM bit is writ-

ten to one, all the incoming frames received by the USART receiver that do not contain

address information will be ignored. The transmitter is unaffected by the MPCM setting.

For more detailed inf ormation see “Multi -proce ssor Commu nication Mode ” on pag e 184.

USART Control and Status

• Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete

interrupt will be generated only if the RXCIE bit is written to one, the Global Interrupt

Flag in SREG is written to one and the RXC bit in UCSRA is set.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete

interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt

Flag in SREG is written to one and the TXC bit in UCSRA is set.

Bit 76543210

RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 UCSRB

Read/Write R/W R/W R/W R/W R/W R/W R R/W

Initial Value00000000

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• Bit 5 – UDRIE: USART Data Register Empty Int errupt Enable

Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty inter-

rupt will be generated only if the UDRIE bit is w ritten to one, the Global Interrupt Flag in

SREG is written to one and the UDRE bit in UCSRA is set.

• Bit 4 – RXEN: Receiver Enable

Writing this bit to one enables the USART Receiver. The Receiver will override normal

port operation for the RxD pin when enabled. Disabling the Receiver will flush the

receive buffer invalidating the FE, DOR and UPE Flags.

• Bit 3 – TXEN: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override nor-

mal port operation for the TxD pin when enabled. The disabling of the Transmitter

(writing TXEN to zero) will not becom e effective until ongoing and pending transmis-

sions are completed, i.e ., when the Tra nsmit Shift Regist er and Tran smit Buffer Register

do not contain data to be transmitted. When disabled, the Transmitter will no longer

override the TxD port.

• Bit 2 – UCSZ2: Character Size

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits

(character size) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8: Receive Data Bit 8

RXB8 is the ninth data bit of the received character when operating with serial frames

with nine data bits. Must be read before reading the low bits from UDR.

• Bit 0 – TXB8: Transmit Data Bit 8

TXB8 is the 9th data bit in the character to be transmitted when operating with serial

frames with 9 data bits. Must be written before writing the low bits to UDR.

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USART Control and Status

Note: 1. The UCSRC Register shares the same I/O lo cation as the UBRRH Reg iste r. See the

“Accessing UBRRH/ UCSRC Registers” on page 186 section which describes how to

access this register.

• Bit 7 – URSEL: Register Select

This bit selects between accessing the UCSRC or the UBRRH Register. It is read as

one when reading UCSRC. The URSEL must be one when writing the UCSRC.

• Bit 6 – UMSEL: USART Mode Select

This bit selects be tween asynchronous and synchronous mode of operation.

• Bit 5:4 – UPM1:0: Pari ty Mode

These bits enable and set type of parity generation and check. If enabled, the transmit-

ter will automatically generate and send the parity of the transmitted data bits within

each frame. The receiver will generate a parity value for the incoming data and compare

it to the UPM0 setting. If a mismatch is detected, the UPE Flag in UCSRA will be set.

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the transmitter. The receiver

ignores this setting.

Bit 76543210

URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value10000110

Table 73. UMSEL Bit Settings

UMSEL Mode

0 Asynchronous Operation

1 Synchronous Operation

Table 74. UPM Bits Settings

UPM1 UPM0 Parity Mode

0 0 Disabled

01Reserved

1 0 Enabled, Even Parity

1 1 Enabled, Odd Parity

Table 75. USBS Bit Settings

USBS Stop Bit(s)

01-bit

12-bit

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• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits

(Character Size) in a fram e th e re ce ive r an d tra n sm itter use.

• Bit 0 – UCPOL: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous

mode is used. The UCPOL bit sets the relationship between data output change and

data input sample, and the synchronous clock (XCK).

USART Baud Rate Registers –

UBRRL and UBRRH(1)

Note: 1. The UBRRH Register shares the same I/O lo cation as the UCSRC Reg iste r. See the

“Accessing UBRRH/ UCSRC Registers” on page 186 section which describes how to

access this register.

• Bit 15 – URSEL: Register Select

This bit selects between accessing the UBRRH or the UCSRC Register. It is read as

zero when reading UBRRH. The URSEL must be zero when writing the UBRRH.

• Bit 14:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit

must be written to zero when UBRRH is written.

Table 76. UCSZ Bits Settings

UCSZ2 UCSZ1 UCSZ0 Character Size

0005-bit

0016-bit

0107-bit

0118-bit

100Reserved

101Reserved

110Reserved

1119-bit

Table 77. UCPOL Bit Settings

UCPOL Transmitted Data Changed

(Output of TxD Pin) Received Data Sampled

(Input on RxD Pin)

0 Rising XCK Edge Falling XCK Edge

1 Falling XCK Edge Rising XCK Edge

Bit 151413121110 9 8

URSEL – – – UBRR[11:8] UBRRH

UBRR[7:0] UBRRL

76543210

Read/Write R/W R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

00000000

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• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the

four most significant bits, and the UBRRL contains the eight least significant bits of the

USART baud rate. Ongoing transmissions by the transmitter and receiver will be cor-

rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of

the baud rate prescaler.

Examples of Baud Rate

Setting For standard crysta l and reso nator fr equen cies, th e most commonly used ba ud rates for

asynchronous operation can be generated by using the UBRR settings in Table 78.

UBRR values which yie ld an actual baud rate differing less than 0.5 % from the target

baud rate, are bold in the table. Higher error ratings are acceptable, but the receiver will

have less noise resistance when the error ratings are high, especially for large serial

frames (see “Asynchrono us O perat ional Rang e” on p age 183) . The e rror valu es are cal-

culated using the following equation:

Error[%] BaudRateClosest Match

BaudRate

-------------------------------------------------------- 1–

⎝⎠

⎛⎞

100%•=

Table 78. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

Baud

Rate

(bps)

fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 250.2%510.2%470.0%950.0%510.2%1030.2%

4800 120.2%250.2%230.0%470.0%250.2%510.2%

9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%

14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1%

19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2%

28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5%

38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0%

57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5%

76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5%

115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5%

230.4k––––––00.0%––––

250k––––––––––00.0%

Max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps

1. UBRR = 0, Error = 0.0%

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Table 79. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%

4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%

9600 230.0%470.0%250.2%510.2%470.0%950.0%

14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%

19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0%

28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%

38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%

57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0%

76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0%

115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0%

230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0%

250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8%

0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8%

1M ––––––––––0-7.8%

Max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 Mbps 460.8 kbps 921.6 kbps

1. UBRR = 0, Error = 0.0%

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Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 8.0000 MHz fosc = 11.0592 MHz fosc = 14.7456 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%

4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%

9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%

14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%

19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0%

28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%

38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0%

57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%

76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0%

115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0%

230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0%

250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%

0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8%

1M – – 0 0.0% – – – – 0 -7.8% 1 -7.8%

Max. (1) 0.5 Mbps 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kbps 1.8432 Mbps

1. UBRR = 0, Error = 0.0%

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Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%

4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%

9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%

14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%

19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%

28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%

38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2%

57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%

76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4%

115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4%

230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4%

250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0%

0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0%

1M 0 0.0% 1 0.0% – – – – – – – –

Max. (1) 1 Mbps 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps

1. UBRR = 0, Error = 0.0%

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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega-

tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on

the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s

output can be set to trigger the Timer/Counter1 Input Capture functio n. In addition, the

comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The

user can select Interrupt triggering on comparator output rise, fall or toggle. A block dia-

gram of the comparator and its surrounding logic is shown in Figure 82.

Figure 82. Analog Comparator Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2 and Table 32 on page 73 for Analog Comparator pin

placement.

Analog Comparator Control

and Status Regi st er – ACSR

• Bit 7 – ACD: Analog Comparator Disable

When this bit is wr itten logic one, the po wer to the Analog Comparator is switch ed off.

This bit can be set at any time to turn off the Analog Comparator. This will reduce power

consumption in Active and Idle mode. When changing the ACD bit, the Analog Compar-

ator Interr upt must be disabl ed by cleari ng t he ACI E bit in ACSR. Ot herwise an int erru pt

can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the

Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the

Analog Comparator. See “Internal Voltage Ref erence” on page 53.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to

ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode

defined by ACIS1 and ACIS0. The An alog Comparator interrupt routine is execu ted if

ACBG

BANDGAP

REFERENCE

Bit 76543210

ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 N/A 0 0 0 0 0

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the ACIE bit is set and t he I-bit in SREG is set. ACI is cl eared by har dware when execut-

ing the corresponding interrupt handling vector. Alternativel y, ACI is cleared by writing a

logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana-

log Comparator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to

be triggered by the Analog Comparator. The comparator output is in this case directly

connected to the Input Capture front-end logic, making the comparator utilize the noise

canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When

written logic zero , no conne ction b etwe en the Analog Com parat or and the I nput Capture

function exists . To make th e comparator trigger the Timer/Counter1 Input Capture inter-

rupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits deter mine which compa rator event s that tr igger th e Analog Com parator in ter-

rupt. The different settings are shown in Table 82.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-

abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt

can occur when the bits are changed.

Table 82. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle.

01Reserved

1 0 Comparator Interrupt on Falling Output Edge.

1 1 Comparator Interrupt on Rising Output Edge.

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JTAG Interface and

On-chip Debug

System

Features •JTAG (IEEE std. 1149.1 Compliant) Interface

•Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard

•Debugger Access to:

– All Internal Peripheral Units

– Internal and External RAM

– The Internal Register File

–Program Counter

– EEPROM and Flash Memories

•Extensive On-chip Debug Support for Break Conditions, Including

– AVR Break Instruction

– Break on Change of Program Memory Flow

– Single Step Break

– Program Memory Breakpoints on Single Address or Address Range

– Data Memory Breakpoints on Single Address or Address Range

•Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•On-chip Debugging Supported by AVR Studio®

Overview The AVR IEEE std. 1149.1 compliant JTAG interface can be used for

• Testing PCBs by using the JTAG Boundary-scan capability.

• Programming the non-volatile memories, Fuses an d Lock bits.

• On-chip debugging.

A brief description is given in the following sections. Detailed descriptions for Program-

ming via the JTAG interface, an d using the Boundary-scan Chain can be found in the

sections “Programming via the JTAG Interface” on page 252 and “IEEE 1149.1 (JTAG)

Boundary-scan” on page 206, respectively. The On-chip Debug support is considered

being private JTAG instructions, and distributed within ATMEL and to selected third

party vendors only.

Figure 83 shows a block diagra m of the JTAG interface and the On-chip Debug system.

The TAP Controller is a state machin e controlled by the T CK and TMS signals. The TAP

Controller selects either the JTAG Instruction Register or one of several Data Registers

as the scan chain (Shift Register) between the TDI – input and TDO – output. The

Instruction Register holds JTAG instructions controlling the behavior of a Data Register.

The ID-Registe r, Bypass Register , and t he Boundary- scan Chain are the Dat a Register s

used for board-level testing. The JTAG Programming Interface (actually consisting of

several physical and virt ual Data Re gisters) is used for serial prog ramming via th e JTAG

interface. The Internal Scan Chain and Break Point Scan Ch ain are used for On-chi p

debugging only.

Test Access Port – TAP The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology,

these pins const itu te the Test Access Port – TAP. These pins are:

• TMS: Test mode select. This pin is used for navigating through the TAP-controller

state machin e.

• TCK: Test Clock. JTAG operation is synchronous to TCK.

• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data

• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.

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The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –

which is not provided.

When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins

and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is

cleared, the TAP input signals are internally pulled high and the JTAG is enabled for

Boundary-scan and programming. In this case, the TAP output pin (TDO) is left floating

in states where the JTAG TAP controller is not shifting data, and must therefore be con-

nected to a pull-up re sist or or othe r ha rd wa re having pull- ups (for inst ance th e TDI- inp ut

of the next device in the scan chain). The device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is

monitored by the debugger to be able to detect External Reset sources. The debugger

can also pull the RESET pin low to reset the whole system, ass uming only open collec-

tors on the reset line are used in the application.

Figure 83. Block Diagram

TAP

CONTROLLER

FLASH

MEMORY

AVR CPU

DIGITAL

PERIPHERAL

UNITS

JTAG / AVR CORE

COMMUNICATION

INTERFACE

BREAKPOINT

UNIT FLOW CONTROL

UNIT

OCD STATUS

AND CONTROL

INTERNAL

SCAN

CHAIN

INSTRUCTION

BYPASS

JTAG PROGRAMMING

INTERFACE

Instruction

Address

Data

BREAKPOINT

SCAN CHAIN

ADDRESS

DECODER

ANALOG

PERIPHERIAL

UNITS

I/O PORT 0

I/O PORT n

BOUNDARY SCAN CHAIN

Analog inputs

Control & Clock line

DEVICE BOUNDARY

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Figure 84. TAP Controller State Diagram

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

011 1

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TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the

Boundary-scan circuitry, JTAG pr ogramming circuitry, or On-chip Debug system. Th e

state transitions depicted in Figure 84 depend on the signal present on TMS (shown

adjacent to each state transition) at the time of the rising edge at T CK. The initial state

after a Power-on Reset is Test-Logic-Reset.

As a definition in this docum e nt , the LSB is shifte d in an d out firs t for all Shift Re gist er s.

Assuming Run-Test /Id le is th e p rese nt st at e, a typical scenario for using the JT AG in ter-

face is:

• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter

the Shift Instruction Register – Shift-IR state. While in this state, shift the four bits of

the JTAG instructions into the JTAG Instruction Register from the TDI input at the

rising edge of TCK. The TMS input must be held low during input of t he 3 LSBs in

order to remain in the Shift-IR state. The MSB of the instruction is shifted in when

this state is left by setting TMS high. While the instruction is shifted in from the TDI

pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction

selects a particula r Data Register as path between TDI and TDO and controls the

circuitry surrounding the selected Data Regist er.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction

is latched onto the parallel output from the Shift Register path in the Update-IR

state . The Exit-IR, Pause-IR, and Exit2-IR states are on ly used for navigating the

state machin e.

• At the TMS inp ut, app ly the se quence 1 , 0, 0 at t he rising edges of TCK to ent er the

Shift Data Register – Shift-DR state. While in this state, upload the selected data

from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state,

the TMS input must be held low during input of all bits except the MSB. The MSB of

the data is shifted in when this state is left by setting TMS high. While the Data

captured in the Capture-DR state is shifted out on the TDO pin.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected

data register has a latched parallel-output, the latching takes place in the Update-

DR state. The Exit-DR, P ause -DR, and Exit2- DR states are only used for navigating

the state machine.

As shown in the state diagram, the Run-Test/Idle state need not be entered between

selecting JTAG instruction and using Data Registers, and some JTAG instructions may

select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an

Idle state.

Note: Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can

always be entered by holding TMS high for five TCK clock periods.

For detailed information on the JTAG specification, refer to the literature listed in “Bibli-

ography” on page 205.

Using the Boundary-

scan Chain A complete description of the Boundary-scan capabilities are given in the section “IEEE

1149.1 (JTAG) Boundary-scan” on page 206.

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Using the On-chip Debug

system As shown in Figure 83, the hardware support for On-chip Debugging consists mainly of

• A scan chain on the int er face between the internal AVR CPU an d the int ernal

peripheral units

• Break Point unit

• Communication interface between the CPU and JTAG system

All read or modify/write operations needed for implementing the Debugger are done by

applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the

result to an I/O memory mapped location which is part of the communication interface

between the CPU and the JTAG system.

The Break Point unit implem ents Bre ak on Ch ange of pr ogram flo w, Single St ep Brea k,

two Program me mory Bre ak Point s, and tw o Combin ed Bre ak Points. T ogeth er , the fo ur

Break Points can be configured as either:

• 4 single Program Memory Break Points

• 3 Single Program Memory Break Point + 1 single Data Memory Break Point

• 2 single Program Memory Break Points + 2 single Data Memory Break Points

• 2 single Progr am Memory Break P oints + 1 Pro gram Memory Break Point with mask

(“range Break Point”)

• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask

(“range Break Point”)

A debugger, like th e AVR St udio®, ma y howe ve r use o ne or mo re of t hese r esources f or

its internal purpose, leaving less flexibility to the end-user.

A list of the On-chip Debug specific JTAG instructions is given in “O n-chip debug spe-

cific JTAG instructions” on page 204.

The JTAGEN Fuse must be p ro gramme d to ena ble the JTAG Test Access Po rt . In ad di-

tion, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-

chip debug system to work. As a securit y f eature, the On-chip debug system is disabled

when either of the LB1 or LB2 Lock bits are set. Otherwise, the On-chip debug system

would have provided a backdoor into a secured device.

The AVR Studio enables the user to fully control execution of programs on an AVR

device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR

Instruction Set Simulator. AVR Studio supports source level execution of Assembly pro-

grams assembled with Atmel Corporation’s AVR Assembler and C progra ms compiled

with third party vendors’ compilers.

AVR Studio runs under Microsoft® Windows® 95/98/2000, Windows NT®, and

Windows XP®.

For a full description of the AVR Studio, please refer to the AVR Studio User Guide.

Only highlights ar e pr es en te d in this doc um e nt .

All necessary execution commands are available in AVR Studio, both on source level

and on disassembly level. The user can execute the program, single step through the

code either by tracing into or stepping over functions, step out of functions, place the

cursor on a statement and execute until the statement is reached, stop the execution,

and reset the execution target. In addition, the user can have an unlimited number of

code Break Points (using the BREAK instruction) and up to two data memory Break

Points, alternatively combined as a mask (range) Break Point.

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On-chip debug specific

JTAG instructions The On-chi p debug support is considered bein g private JTAG instructions, and distrib -

uted within ATMEL and to selected 3rd party vendors only. Instruction opcodes are

listed for reference.

PRIVATE0; 0x8 Private JTAG instruction for accessing On-chip debug system.

PRIVATE1; 0x9 Private JTAG instruction for accessing On-chip debug system.

PRIVATE2; 0xA Private JTAG instruction for accessing On-chip debug system.

PRIVATE3; 0xB Private JTAG instruction for accessing On-chip debug system.

On-chip Debug Related

On-chip Debug Register –

OCDR

The OCDR Register provides a communica tion chann el from the runn ing progr am in t he

microcontroller t o the de bugge r. The CPU can tr an sfer a byt e to th e debu gg er by writing

to this location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is

set to indicate to the debugger that the register has been written. When the CPU reads

the OCDR Register the 7 LSB will be from the OCDR Reg ister, while the MSB is the

IDRD bit. The debugger clears the IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In th is case,

the OCDR Register can only be accessed if the OCDEN Fuse is programmed, and the

debugger enables access to the OCDR Register. In all other cases, the standard I/O

location is accessed.

Refer to the debugger documentation for further information on how to use this register.

Using the JTAG

Programming

Capabilities

Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS,

TDI and TDO. These are the only pins that need to be controlled/observed to perform

JTAG programming (in add ition t o power p ins). It is not r eq uired to apply 12 V ext ernally.

The JTAGEN Fuse must be programmed and the JTD bit in the MCUSR Register must

be cleared to enable the JTAG Test Access Port.

The JTAG programming capability supports:

• Flash programming and verifying.

• EEPROM programming and verifying.

• Fuse programming and verifying.

• Lock bit programming and verifying.

The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or

LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a

chip erase. This is a security feature that ensures no backdoor exists for reading out the

content of a secured device.

The details on programming through the JTAG interface and programming specific

JTAG instructions are given in the section “Programming via the JTAG Interface” on

page 252.

Bit 7 6543210

MSB/IDRD LSB OCDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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Bibliography For more information about general Boundary-scan, the following litera ture can be

consulted:

• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access P ort and Boundary-scan

Architecture, IEEE, 1993

• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-

Wesley, 1992

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IEEE 1149.1 (JTAG)

Boundary-scan

Features •JTAG (IEEE std. 1149.1 Compliant) Interface

•Boundary-scan Capabilities According to the JTAG Standard

•Full Scan of all Port Functions as well as Analog Circuitry Having Off-chip Connections

•Supports the Optional IDCODE Instruction

•Additional Public AVR_RESET Instruction to Reset the AVR

System Overview The Boundary-scan chain has the capability of driving and observing the logic levels on

the digital I/O pins, as well as the boundary between digital and analog logic for analog

circuitry having Off-chip connections. At syst em level, all ICs having JTAG capabilities

are connected serially by the TDI/TDO signals to form a long Shift Register. An external

controller sets up the devices to drive values at their output pins, and observe the input

values received from other devices. The controller compares the received data with the

expected result. In this way, Boundary-scan provides a mechanism for testing intercon-

nections and integrity of components o n Printed Circuits Boards by using the four TAP

signals only.

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAM-

PLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction

AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the

Data Register path will show the ID-code of the device, since IDCODE is the default

JTAG instruction. It may be desirable to have the AVR device in Reset during Test

mode. If not Reset, inputs to the device may be determined by the scan operations, and

the internal software may be in an undetermined state when exiting the test mode.

Entering Reset, the outputs of any Port Pin will instantly enter the high impedance state,

making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be

issued to make the shortest possible scan chain through the device. The device can be

set in the Reset state either by pulling the external RESET pin low, or issuing the

AVR_RESET instruction with appropriate setting of the Reset Data Register.

The EXTEST instruction is used for sampling external pins and loading output pins with

data. The data from the output latch will be driven out on the pins as soon as the

EXTEST instruction is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRE-

LOAD should also be used for setting initial values to the scan ring, to avoid damaging

the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD

can also be used for taking a snapshot of the external pins during normal operation of

the part.

The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCSR

must be cleared to enable the JTAG Test Access Port.

When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency

higher than the internal chip f requency is possible. The chip clock is not required to run.

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Data Registers The data registers relevant for Boundary-scan operat ions are:

• Bypass Register

• Device Identification Register

• Reset Register

• Boundary-scan Chain

Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Regis-

ter is selected as path between TDI and TDO, the registe r is reset to 0 when leaving the

Capture-DR controller state. The Bypass Register can be used to shorten the scan

chain on a system when the other devices are to be tested.

Device Identificat io n Re gi st er Figure 85 shows the structure of the Device Identification Register.

Figure 85. The Format of the Device Identification Register

Version Version is a 4-bit number identi fying the revision of t he compon ent. Th e relevant version

number is shown in Table 83.

Part Number The part number is a 16-bit code identifying the component. The JTAG Part Number for

ATmega162 is listed in Table 84.

Manufacturer ID The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufac-

turer ID for ATMEL is listed in Ta b le 85 .

Reset Register The Reset Registe r is a test data register used to reset the part. Since the AVR tri-st ates

Port Pins when reset, the Reset Register can also replace the function of the unimple-

mented optional JTAG instruction HIGHZ.

A high value in the Reset Register corresponds to pulling the external Reset low. The

part is reset as long as there is a high valu e present in the Reset Register. Depending

MSB LSB

Bit 31 28 27 12 11 1 0

Device ID Version Part Number Manufacturer ID 1

4 bits 16 bits 11 bits 1 bit

Table 83. JTAG Version Numbers

Version JTAG Version number (Hex)

ATmega162 revision A 0x0

ATmega162 revision B 0x1

ATmega162 revision C 0x2

ATmega162 revision D 0x3

Table 84. AVR JTAG Part Number

Part number JTAG Part Num ber (Hex)

ATmega162 0x9404

Table 85. Manufacturer ID

Manufacturer JTAG Man. ID (Hex)

ATMEL 0x01F

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on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out

Period (refer to “Clock Sources” on page 36) after releasing the Reset Register. The

output from this data register is not latched, so the reset will take place immediately, as

shown in Figure 86.

Figure 86. Reset Register

Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on

the digital I/O pins, as well as the boundary between digital and analog logic for analog

circuitry having Off-chip connections.

See “Boundary-scan Chain” on page 210 for a complete description.

Boundary-scan Specific

JTAG Instructions The Instr uction Register is 4-bit wide, supp orting up to 16 inst ructions. Lis ted below are

the JTAG instructions useful for Boun dary-scan op eration . Note that the optio nal HIGHZ

instruction is not implemented, but all outputs with tri-state capability can be set in high-

impedant state by using the AVR_RESET instruction, since the initial state for all port

pins is tri-state.

As a definition in this datasheet, the LSB is shifted in a nd out first for all Shift Register s.

The OPCODE for each instruction is shown behind the instruction name in hex format.

The text describes which Data Register is selected as path between TDI and TDO for

each instruction.

EXTEST; 0x0 Mandatory JTAG instru ct ion for select ing the Bo undar y-scan Cha in as Da ta Re gister f or

testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output

Control, Output Data, and Input Data a re all accessible in the scan cha in. For analo g cir-

cuits having Off-chip connections, the interface between the analog and the digital logic

is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is

driven out as soon as the JTAG IR-Register is loaded with the EXTEST instruction.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Internal Scan Chain is shifted by the TCK input.

• Update-DR: Data from the scan chain is applied to output pins.

From

TDI

ClockDR · AVR_RESET

TDO

From Other Internal and

External Reset Sources

Internal Reset

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IDCODE; 0x1 Optiona l JTAG instruction selecting the 32-bit I D-register as da ta regist er. The I D-Regis-

ter consists of a version nu mber, a device number and the manufacturer code chosen

by JEDEC. This is the default ins truction after Power-up.

The active states are:

• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan

Chain.

• Shift-DR: The IDCODE sca n ch ain is shifte d by the TCK input.

SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for preloading the output latches and taking a snapshot of

the input/output pins without affecting the system operation. However, the output latches

are not connected to the pins. The Boundary-scan Chain is selected as Data Register.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

• Update-DR: Data from the Boundary-scan chain is applied to the output latches.

However, the output latches are not connected to the pins.

AVR_RESET; 0xC The AVR specific public JTAG instruction for forcing the AVR device into the Reset

mode or releasing the JTAG Reset source. The TAP controller is not reset by this

instruction. The one bit Reset Register is selected as data register. Note that the reset

will be active as long as there is a logic 'one' in the Reset Chain. The output from this

chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; 0xF Mandatory JTAG instruction selecting the Bypass Register for data register.

The active states are:

• Capture-DR: Loads a logic “0” into the Bypass Register.

• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan Rela ted

MCU Control and Status

and provides information on which reset source caused an MCU Reset.

• Bit 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.

If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling

or enabling of the JTAG interface, a timed sequence must be followed when changing

this bit: The application software must write this bit to the desired value twice within four

cycles to change its value.

Bit 76543210

JTD –SM2 JTRF WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 See Bit Description

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If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be

set to one. The reason for this is to avoid static current at the TDO pin in the JTAG

interface.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register

selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or

by writing a logic zero to the flag.

Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on

the digital I/O pins, as well as the boundary between digital and analog logic for analog

circuitry having Off-chip connection.

Scanning the Digital Port Pins Figure 87 shows the Boundary-scan Cell for a bi-directional port pin with pull-up func-

tion. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn

– function, and a bi-directional pin cell that combines the three signals Output Control –

OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.

The port and pin indexes are not used in the following description

The Boundary-scan logic is no t included in t he figures in th e datasheet. Figure 88 shows

a simple digital Port Pin as described in the section “I/O-Ports” on page 64. The Bound-

ary-scan details from Figure 87 replaces the dashed box in Figure 88.

When no alternate port function is prese nt, the Input Data – ID – corresponds to the

PINxn Register value (but ID has no synchronizer), Output Data corresponds to the

PORT Register, Output Control corresponds to the Data Direction – DD Register, and

the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 88 to

make the scan chain read the actual pin value. For Analog function, there is a direct

connection from the external pin to the analog circuit, and a scan chain is inserted on

the interface between the digital logic and the analog circuitry.

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Figure 87. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.

DQ DQ

1DQ DQ

Port Pin (PX

VccEXTESTTo Next CellShiftDR

Output Control (OC)

ullup Enable (PUE)

Output Data (OD)

Input Data (ID)

From Last Cell UpdateDRClockDR

FF2 LD2

FF1 LD1

LD0FF0

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Figure 88. General Port Pin Sch ematic Diagram

Scanning the RESET pin The RESET pin accepts 5V active low logic for standard reset oper ation , and 12V acti ve

high logic for high voltage parallel programming. An observe-only cell as shown in Fig-

ure 89 is inserted bot h for the 5V reset sig nal; RST T, and th e 12V rese t signal; RSTHV.

Figure 89. Observe-only Cell

CLK

RPx

RRx

WRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

CLK : I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BUS

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

See Boundary-Scan Description

for Details!

PUExn

OCxn

ODxn

IDxn

PUExn: PULLUP ENABLE for pin Pxn

OCxn: OUTPUT CONTROL for pin Pxn

ODxn: OUTPUT DATA to pin Pxn

IDxn: INPUT DATA from pin Pxn

From

Cell

ClockDR

ShiftDR

Cell

From System Pin To System Logic

FF1

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Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC

Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low Frequency Crystal

Oscillator, and Ceramic Resonator.

Figure 90 shows how each Oscillator with external connection is supported in the scan

chain. The Enable signal is supported with a general Boundary-scan cell, while the

Oscillator/clock output is attached to an observe-only cell. In addition to the main clock,

the Timer Oscillator is scanned in the same way. The output from the internal RC Oscil-

lator is not scanned, as this Oscillator does not have external connections.

Figure 90. Boundary-scan Cells for Oscillators and Clock Options

Table 86 summaries the scan registers for the external clock pin XTAL1, oscillators with

XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.

Notes: 1. Do not enable more than one clock source as main clock at a time.

2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift

between the Internal Oscillator and the JTAG TCK clock. If possible, scanning an

e x t e rnal clock is preferred.

3. The clock configuration is programmed by fuses. As a fuse is not changed run-time,

the clock configuration is considered fixed for a given application. The user is advised

to scan the same clock option as to be used in the final system. The enable signals

are suppor ted in the scan chain because the system logic can disable clock options

in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not

provided. The INTCAP selection is not supported in the scan-chain, so the boundary

scan chain can not make a XTAL Oscillator requiring internal capacitors to run unless

the fuses are correctly programmed.

Table 86. Scan Signals for the Oscillator(1)(2)(3)

Enable Signal Scanned Clock Line Clock Option

Scanned Clock

Line when Not

Used

EXTCLKEN EXTCLK (XTAL1) External Clock 0

OSCON OSCCK External Crystal

Exter nal Ceramic Resonator 0

OSC32EN OSC32CK Low F req. External Crystal 0

TOSKON TOSCK 32 kHz Timer Oscillator 0

From

Cell

ClockDR

ShiftDR

Cell

To System Logic

FF1

DQ DQ

From

Cell

ClockDR UpdateDR

ShiftDR

Cell EXTEST

From Digital Logic

XTAL1/TOSC1 XTAL2/TOSC2

Oscillator

ENABLE OUTPUT

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Scanning the Analog

Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 91. The

Boundary-scan cell from Figure 92 is attached to each of these signals. The signals are

described in Tab le 87.

The Comparator need not be used for pure connectivity testing, since all analog inputs

are shared with a digital port pin as well.

Figure 91. Analog Comparator

Figure 92. General Boundary-scan Cell used for Signals for Comparator

ACBG

BANDGAP

REFERENCE

AC_IDLE

DQ DQ

From

Cell

ClockDR UpdateDR

ShiftDR

Cell EXTEST

To Snalog Circuitry/

To Digital Logic

From Digital Logic/

From Analog Ciruitry

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ATmega162 Boundary-

scan Order Table 88 shows the Scan order between TDI and TDO when the Boundary-scan chain

is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit

scanned out. The scan order follows the pinout order as far as possible. Therefore, the

bits of Port A and Port E is scanned in the opposite bit order of the other ports. Excep-

tions from the rules are the Scan chains for the analog circuits, which constitute the

most significant bits of the scan chain regardless of which physical pin they are con-

nected to. In Figure 87, PXn. Data corresponds to FF0, PXn. Control corresponds to

FF1, and PXn. Pullup_enabl e corresponds to F F2. Bit 4, 5, 6, and 7of Port C is not in the

scan chain, since these pins constitute t he TAP pins when the JTAG is enabled.

Table 87. Boundary-scan Signals for the Analog Comparator

Signal

Name

Direction as

seen from the

Comparator Description

Recommended

Input when Not

in Use

Output Values when

Recommended

Inputs are Used

AC_IDLE input Turns off Analog

comparator

when true

1 Depends upon µC

code being executed

ACO output Analog

Comparator

Output

Will become

input to µC code

being executed

ACBG input Bandgap

Reference

enable

0 Depends upon µC

code being executed

Table 88. ATmega162 Boundary-scan Order

Bit Number Signal Name Module

105 AC_IDLE Comparator

104 ACO

103 ACBG

102 PB0.Data Port B

101 PB0.Control

100 PB0.Pullup_Enable

99 PB1.Data

98 PB1.Control

97 PB1.Pullup_Enable

96 PB2.Data

95 PB2.Control

94 PB2.Pullup_Enable

93 PB3.Data

92 PB3.Control

91 PB3.Pullup_Enable

90 PB4.Data

89 PB4.Control

88 PB4.Pullup_Enable

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87 PB5.Data Port B

86 PB5.Control

85 PB5.Pullup_Enable

84 PB6.Data

83 PB6.Control

82 PB6.Pullup_Enable

81 PB7.Data

80 PB7.Control

79 PB7.Pullup_Enable

78 RSTT Reset Logic

(Observe-only)

77 RSTHV

76 TOSC 32 kHz Timer Oscillator

75 TOSCON

74 PD0.Data Port D

73 PD0.Control

72 PD0.Pullup_Enable

71 PD1.Data

70 PD1.Control

69 PD1.Pullup_Enable

68 PD2.Data

67 PD2.Control

66 PD2.Pullup_Enable

65 PD3.Data

64 PD3.Control

63 PD3.Pullup_Enable

62 PD4.Data

61 PD4.Control

60 PD4.Pullup_Enable

59 PD5.Data Port D

58 PD5.Control

57 PD5.Pullup_Enable

56 PD6.Data

55 PD6.Control

54 PD6.Pullup_Enable

53 PD7.Data

52 PD7.Control

Table 88. ATmega162 Boundary-scan Order (Continued)

Bit Number Signal Name Module

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51 PD7.Pullup_Enable Port D

50 EXTCLKEN Enable signals for main

Clock/Oscillators

49 OSCON

48 OSC32EN

47 EXTCLK (XTAL1) Clock input and Oscillators

for the main clock (Observe-

only)

46 OSCCK

45 OSC32CK

44 PC0.Data Port C

43 PC0.Control

42 PC0.Pullup_Enable

41 PC1.Data

40 PC1.Control

39 PC1.Pullup_Enable

38 PC2.Data

37 PC2.Control

36 PC2.Pullup_Enable

35 PC3.Data

34 PC3.Control

33 PC3.Pullup_Enable

32 PE2.Data Port E

31 PE2.Control

30 PE2.Pullup_Enable

29 PE1.Data

28 PE1.Control

27 PE1.Pullup_Enable

26 PE0.Data

25 PE0.Control

24 PE0.Pullup_Enable

23 PA7.Data Port A

22 PA7.Control

21 PA7.Pullup_Enable

20 PA6.Data

19 PA6.Control

18 PA6.Pullup_Enable

17 PA5.Data

16 PA5.Control

Table 88. ATmega162 Boundary-scan Order (Continued)

Bit Number Signal Name Module

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Note: 1. PRIVATE_SIGNAL1 should always be scanned in as zero.

Boundary-scan

Description Language

Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable

devices in a standard format used by automated test-generation software. The order

and function of bits in the Boundary-scan Data Register are included in this description.

A BSDL file for ATmega162 is available.

15 PA5.Pullup_Enable Port A

14 PA4.Data

13 PA4.Control

12 PA4.Pullup_Enable

11 PA3.Data

10 PA3.Control

9 PA3.Pullup_Enable

8PA2.Data

7 PA2.Control

6 PA2.Pullup_Enable

5PA1.Data

4 PA1.Control

3 PA1.Pullup_Enable

2PA0.Data

1 PA0.Control

0 PA0.Pullup_Enable

Table 88. ATmega162 Boundary-scan Order (Continued)

Bit Number Signal Name Module

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Boot Loader Support

– Read-While-Write

Self-programming

The Boot Loader Support provides a real Read-While-Write Self-programming mecha-

nism for downloading and uploading program code by the MCU itself. This feature

allows flexible application software updates controlled by the MCU using a Flash-resi-

dent Boot Loader program. The Boot Loader program can use any available data

interface and associated protocol to read code and write (program) th at code into the

Flash memory, or read the code from the progra m memory. The program code within

the Boot Loader section has the capability to write into the entire Flash, including the

Boot Loader memory. The Boot Loader can thus even modify itself, and it can also

erase itself from the code if the feature is not needed anymore. The size of the Boot

Loader memory is configurable with Fuses and the Boot Loader has two separate sets

of Boot Lock bits which can be set independently. This gives the user a unique flexibility

to select different levels of protect ion.

Features •Read-While-Write Self-programming

•Flexible Boot Memory Size

•High Securi ty (Separ a t e Boot Lock Bits for a Fle xi ble Protec tion)

•Separate Fuse to Select Reset Vector

•Optimized Page(1) Size

•Code Efficient Algorithm

•Efficient Read-Modify-Write Support

Note: 1. A page is a section in the Flash consisting of several bytes (see Table 106 on page

238) used during programming. The page organization does not affect normal

operation.

Application and Boot

Loader Flash Sections The Flash memory is organized in two main sections, the Application section and the

Boot Loader section (see Figure 94). The size of the different sections is configured by

the BOOTSZ Fuses as shown in Table 94 on page 231 and Figure 94. These two sec-

tions can have different level of protection since they have different sets of Lock bits.

Application Section The Application section is the section of the Flash that is used for storing t he ap plication

code. The protection level for the application section can be selected by the Application

Boot Lock bits (Boot Lock bits 0), see Table 90 on pag e 222. The Application section

can never store any Boot Loader code since the SPM instruction is disabled when exe-

cuted from the Application section.

BLS – Boot Loader Sect ion While the Application section is used for storing the application code, the The Boot

Loader software must be locat ed in the BLS sin ce the SPM instruct ion can initiat e a pro-

gramming when executing from the BLS only. The SPM instruction can access the

entire Flash, including the BLS itse lf. The protection level for the Boot Loader section

can be selected by the Boot Loader Lock bits (Boot Lock bits 1), see Table 91 on page

222.

Read-While-Write and No

Read-While-Write Flash

Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot

Loader software update is depende nt on which address that is being programmed. In

addition to the two sections that are configurable by the BOOTSZ Fuses as described

above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW)

section and the No Read-While-Write (NRWW) section. The limit between the RWW-

and NRWW sections is given in Table 95 on page 231 and Figure 94 on page 221. The

main difference between the two sections is:

• When eras ing or writing a page located in side the R WW section, the NR WW section

can be read during the operation.

• When erasing or writing a page located inside the NR WW section, the CPU is halted

during the entire operation.

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Note that the user software can never read any code that is located inside the RWW

section during a Boot Loader software operation. The syntax “Read-While-Write sec-

tion” refers to which section that is being pro grammed (erased or written), not which

section that actually is being read during a Boot Loader software update.

RWW – Read-While-Write

Section If a Boot Loader software update is pr ogramming a page inside the RWW section, it is

possible to read code from the Flash, but only code that is located in the NRWW sec-

tion. During an ongoing programming, the software must ensure that the RWW section

never is being read. If the user software is trying to read code that is located inside the

RWW section (i.e., by a call/jmp/lpm or an interrupt) during prog ramming, the software

might end up in an unknown st ate. T o av oid this, th e interr upts should eith er be disa bled

or moved to the Boot Loader section. The Boot Loader section is always located in the

NRWW section. The RWW Section Busy bit (RWWSB) in the Store Program Memory

Control Register (SPMCR) will be read as logical one as long as the RWW section is

blocked for reading. After a prog ramming is complet ed, the RWWSB must be clea red by

software before r ead ing code lo ca te d in th e RWW sect ion. Se e “St ore Pr og ram Me mor y

Control Register – SPMCR” on page 223. for details on how to clear RWWSB.

NR WW – No Read-While-Write

Section The code located in the NRWW section can be read when the Boot Loader software is

updating a page in the RWW section. When the Boot Loader code updates the NRWW

section, the CPU is halted during the entire Page Erase or Page Write operation.

Figure 93. Read-While-Write vs. No Read-While-Write

Table 89. Read-While-Write Features

Which Section does the Z-

pointer Address During the

Programming?

Which Section Can be

Read During

Programming? Is the CPU

Halted?

Read-While-

Write

Supported?

R WW section NRWW section No Yes

NRWW section None Yes No

Read-While-Write

(RWW) Section

No Read-While-Write

(NRWW) Section

Z-pointer

Addresses RWW

Section

Z-pointer

Addresses NRWW

Section

CPU is Halted

During the Operation

Code Located in

NRWW Section

Can be Read During

the Operation

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Figure 94. Memory Sections(1)

Note: 1. The parameters are given in Table 94 on page 231.

Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code.

The Boot Loader has two separate set s of Boot Lock bits which can be set indepen -

dently. This gives the user a unique flexibility to select different levels of protection.

The user can select:

• To protect the entire Flash from a software update by the MCU

• To protect only the Boot Loader Fla sh section from a software update by the MCU

• To protect only the Application Flash section from a software update by the MCU

• Allow software update in the entire Flash

See Table 90 and Table 91 for further details. The Boot Lock bits can be set in software

and in Serial or Parallel Programm ing mode, but they can be cleared by a chip erase

command only. The general Write Lock (Lock bit mode 2) does not control the program-

0x0000

Flashend

Program Memory

BOOTSZ = '11'

Application Flash Section

Boot Loader Flash Section

Flashend

Program Memory

BOOTSZ = '10'

0x0000

Program Memory

BOOTSZ = '01'

Program Memory

BOOTSZ = '00'

Application Flash Section

Boot Loader Flash Section

0x0000

Flashend

Application Flash Section

Flashend

End RWW

Start NRWW

Application flash Section

Boot Loader Flash Section

End RWW

Start NRWW

End RWW

Start NRWW

0x0000

End RWW, End Application

Start NRWW, Start Boot Loader

Application Flash SectionApplication Flash Section

Application Flash Section

Read-While-Write SectionNo Read-While-Write Section Read-While-Write SectionNo Read-While-Write Section

Read While Write SectionNo Read While Write SectionRead-While-Write SectionNo Read-While-Write Section

End Application

Start Boot Loader

End Application

Start Boot Loader

End Application

Start Boot Loader

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ming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock

(Lock bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted.

Note: 1. “1” means unprogrammed, “0” means programmed

Table 90. Boot Lock Bit0 Protect ion Mo des (Ap plic at ion Sectio n )(1)

BLB0 Mode BLB02 BLB01 Protection

111

No restrictions for SPM or LPM accessing the Application

section.

2 1 0 SPM is not allowed to write to the Application section.

300

SPM is not allowed to write to the Application section, and

LPM executin g from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

401

LPM executin g from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

Table 91. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)

BLB1 Mode BLB12 BLB11 Protection

111

No restrictions for SPM or LPM accessing the Boot Loader

section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

300

SPM is not allowed to write to the Boot Loader secti on,

and LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrupts

are disabled while executing from the Boot Loader section.

401

LPM executin g from the Application section is not allowed

to read from the Boot Loader section. If Interr upt Ve ctors

are placed in the Application section, interrupts are

disabled while executing from the Boot Loader section.

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Entering the Boot Loader

Program Entering the Boot Loader takes place by a jump or call from the application program.

This may be initiated b y a trigg er su ch as a com mand r eceived via USART, or SPI in te r-

face. Alternatively, the Boot Re set Fuse can be programmed so that the Reset Vector is

pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is

started after a reset. After the application code is loaded, the program can start execut-

ing the application code. Note that the fuses cannot be changed by the MCU itself. This

means that once the Boot Reset Fuse is programmed, the Reset Vector will always

point to the Boot Loader Reset and the fuse can only be changed through the Serial or

Parallel Programming interface.

Note: 1. “1” means unprogrammed, “0” means programmed

Store Program Memory

Control Register – SPMCR The Store Program Memory Control Register contains the control bits needed to control

the Boot Loader operations.

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE b it is written to one, and th e I-bit in the Stat us Register is set (o ne), the

SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long

as the SPMEN bit in the SPMCR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-programming (Page Erase or Page Write) operation to the RWW section is

initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the

RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit

is written to one after a Self-programming operation is completed. Alternatively the

RWWSB bit will automatically be cleared if a page load operation is initiated.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in t he ATmega162 and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section

is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW

section, the user software must wait until the programming is completed (SPMEN will be

cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the

next SPM instruction within four clock cycles re-enables the RWW section. The RWW

section cannot be re-ena bled while t he Fla sh is b usy with a Pag e Eras e or a Pa ge Wr ite

(SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, th e Flash

load operation will abort and the data loaded will be lost.

Table 92. Boot Reset Fuse(1)

BOOTRST Reset Address

1 Reset Vector = Application Reset (address 0x0000).

0 Reset Vector = Boot Loader Reset (see Table 94 on page 231).

Bit 765 4 3210

SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and

the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared

upon completion of the Lock bit set, or if n o SPM instruction is executed within four clock

cycles.

An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR

pointer) into the destina tion register. See “Reading the Fuse and Lock Bits from Soft-

ware” on page 227 fo r details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles executes Page Write, with the data stored in the temporary buffer. The

page addres s is taken from the high pa rt of the Z-pointer. The d ata in R1 and R0 are

ignored. The PGWRT bit will auto–clear upon completion of a Page Write, or if no SPM

instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation if the NRWW section is addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles executes Page Erase. The page ad dr ess is taken from th e h igh part of

the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon

completion of a Page Erase, or if no SPM instruction is executed within four clock

cycles. The CPU is halte d during the entir e Page Write o peration if t he NRWW section is

addressed.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one

together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM

instruction will have a special meaning, see description above. If only SPMEN is written,

the following SPM instruction will store the value in R1:R0 in the temporary page buffer

addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will

auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed

within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains

high until the operation is completed.

Writing any other combin at ion than “ 100 01” , “01 001 ”, “0 010 1” , “ 00011 ” or “00 001” in the

lower five bits will have no effect.

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Addressing the Flash

During Self-

programming

The Z-pointer is used to address the SPM commands.

Since the Flash is organized in pages (see Table 106 on page 238), the Program

Counter can be treated as having two different sections. One section, consisting of the

least significant bits, is addressing the words within a page, while the most significant

bits are addressin g the page s. This is shown in Figure 95. Note that t he Page Erase and

Page Write operatio ns are addre ssed indepen dently. The refor e it is of major import ance

that the Boot Loader software addresses the same page in both the Page Erase and

Page Write operat ion. On ce a progr ammin g oper ation is init iat ed, t he addr ess is latched

and the Z-pointer can be used for other operatio ns.

The only SPM operation tha t does not use the Z-po inter is Setting th e Boot Loa der Lock

bits. The content of the Z-poin ter is ignore d and will have no ef fect on the operatio n. The

LPM instruction does also use the Z-pointer to store the address. Since this instruction

addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Figure 95. Addressing the Flash during SPM(1)

Notes: 1. The different variables used in Figure 95 are listed in Table 96 on page 232.

2. PCPA GE and PCWORD are listed in Table 106 on page 238.

Bit 151413121110 9 8

ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8

ZL (R30) Z7Z6Z5Z4Z3 Z2Z1Z0

76543210

PROGRAM MEMORY

0115

Z - REGISTER

BIT

ZPAGEMSB

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

ZPCMSB

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

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Self-programming the

Flash The program memory is updated in a page by page fashion. Before programming a

page with the data stored in the tempo rary page buffer, the page must be erased. The

temporary page buffer is filled one word at a time using SPM and the buffer can be filled

either before the Page Erase command or between a Page Erase and a Page Write

operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for

example in the temporary page buffer) before the erase, and then be rewritten. When

using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature

which allows the user software to first read the page, do th e necessary changes, and

then write back the modified data. If alternative 2 is used, it is not possible to read the

old data w hile load ing sin ce th e pa ge is a lrea dy er ased . Th e tem por ary p age bu ffer can

be accessed in a random sequence. It is essential that the page address used in both

the Page Erase and Page W rite operation is addressing the s ame page. See “Simple

Assembly Code Example for a Boot Loader” on page 229 for an assembly code

example.

Performing Page Erase by

SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to

SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1

and R0 is ignored. The page address must be written to PCPAGE in the Z-register.

Other bits in the Z-pointer will be ignored during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the Page

Erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

Filling the Temporary Buffer

(Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCR and execute SPM within four clock cycles after writing SPMCR.

The content of PCWORD in the Z-register is used to address the data in the temporary

buffer. The temporary buffer will auto-erase after a Page Write operation or by writing

the RWWSRE bit in SPMCR. It is also erased after a System Reset. Note that it is not

possible to write more than one time to each address without erasing the temporary

buffer.

Note: If the EEPROM is written in the mi ddle of an SPM Page Load operation, all data load ed

will be lost.

Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to

SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1

and R0 is ignored. The page addre ss must be written to PCPAGE. Other bits in the Z-

pointer must be written zero during this operation.

• Page Write to the RWW section: The NRWW section can be read during the Page

Write.

• Page Write to the NRWW section: The CPU is halted during the operation.

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Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt

when the SPMEN bit in SPMCR is cleared. This means that the interrupt can be used

instead of polling th e SPMCR Register in software. When usin g the SPM interrup t, the

Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is

accessing the RWW section when it is blocked for reading. How to move the interrupts

is described in “Interrupts” on page 58.

Consideration while Updating

BLS Special care must be taken if the user allows the Boot Loader section to be updated by

leaving Boot Lock b it11 unpro grammed. An accid ental write to the Boot Loade r itself can

corrupt the entire Boot Loader, and further software updates might be impossible. If it is

not necessary to change the Boot Loader software itself, it is recommended to program

the Boot Lock bit11 to protect the Boot Loader software from any internal software

changes.

Prevent Reading the RWW

Section During Self-

programming

During Self-programming (either Page Erase or Page Write), the RWW section is

always blocked for reading. The user software itself must preve nt that this section is

addressed during the self programming operation. The RWWSB in the SPMCR will be

set as long as the RWW section is busy. During Self-programming the Interrupt Vector

table should be moved to the BLS as described in “Interrupts” on page 58, or the inter-

rupts must be disabled. Before addressing the RWW section after the programming is

completed, the user software must clear the RWWSB by writing the RWWSRE. See

“Simple Assembly Code Example for a Boot Loader” on page 229 for an example.

Setting the Boot Loader Lock

Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to

SPMCR and execute SPM within four clock cycles after writing SPMCR. The only

accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot

Loader section from any software update by the MCU.

See Table 90 and Table 91 for how the different settings of the Boot Loader bits affect

the Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed

if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in

SPMCR. The Z-pointer is don’t care during this operation, but for future compatibility it is

recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock

bits). For future compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1”

when writing the Lock bits. When programming the Lock bits the entire Flash can be

read during the operation.

EEPROM Write Prevents

Writing to SPMCR Note that an EEPROM write operation will block all software programming to Flash.

Reading the Fuses and Lock bits from software will also be prevented during the

EEPROM write operation. It is recommended that the user checks the status bit (EEWE)

in the EECR Register and verifies that the bit is cleared before writing to the SPMCR

Reading the Fuse and Lock

Bits from Software It is possible to read both the Fuse and Lock bits from software. To re ad the Lock bits,

load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCR. When

an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN

bits are set in SPMCR, the value of the Lock bits will be loaded in the destination regis-

ter. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock

bits or if no LPM in struction is ex ecuted within three CPU cycles or no SPM instruction is

Bit 76543210

R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1

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executed within four C PU cycles. When BLBSET and SPMEN are cleared, LPM will

work as described in the Instruction set Manual.

The algorithm for reading the Fuse Low byte is similar to the one described above for

reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and

set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed

within three cycles after the BLBSET and SPMEN bits are set in the SPM CR, the value

of the Fuse Low byte (FLB) will be loaded in the destination register as shown below.

Refer to Table 101 on page 235 for a detailed description and mapping o f the Fuse Low

byte.

Similarly, when reading the Fuse High byte, load 0x000 3 in the Z-p ointer. When an LPM

instruction is executed within three cycles after the BLBSET and SPMEN bits are set in

the SPMCR, the value of the Fuse High byte (FHB) will be loaded in the destination reg-

ister as shown below. Refer to Table 99 on page 234 for detailed description and

mapping of the Fuse High byte.

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM

instruction is executed within three cycles after the BLBSET and SPMEN bits are set in

the SPMCR, the value of the Extended Fuse byte (EFB) will be loaded in the destination

mapping of the Extended Fuse byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that

are unprogrammed, will be read as one.

Preventing Flash Corruption During periods of low V CC, th e Flas h pro gram ca n b e corru pted because th e su pply vol t-

age is too low for t he CPU and the Flash to operat e properly. T hese issues are the same

as for board level systems using the Flash, and the same design solutions should be

applied.

A Flash program cor ruption can b e caused by two situ ations when the voltag e is too low.

First, a regular write sequence to the Flash requires a minimum voltage to operate cor-

rectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage

for executing instructions is too low.

Flash corruption ca n easily be avoide d by following th ese design recomme ndations (one

is sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot

Loader Lock bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This can be done by enabling the inte rnal Brown-out Detector (BOD) if

the operating voltage matches the detection level. If not, an external low VCC

Reset Protection circuit can be u sed. If a Reset occu rs while a write oper at ion is

in progress, the write operation will be completed provided that the po wer supply

v oltage is sufficient.

Bit 76543210

Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1

Bit 76543210

Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Bit 76543210

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

Bit 76543210

Rd – – – EFB4 EFB3 EFB2 EFB1 –

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3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the SPM CR Register and thus the Flash from unintentional

writes.

Programming Time for Flash

When Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 93 shows the typical

programming time for Flash accesses from the CPU.

Simple Assembly Code

Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during self-programming (page erase and page write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not

; words

.org SMALLBOOTSTART

Write_page:

; page erase

ldi spmcrval, (1<<PGERS) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld r0, Y+

ld r1, Y+

ldi spmcrval, (1<<SPMEN)

call Do_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256

brne Wrloop

; execute page write

subi ZL, low(PAGESIZEB) ;restore pointer

sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; read back and check, optional

Table 93. SPM Programming Time

Symbol Min Programming Time Max Programming Time

Flash Write (Page Er ase, P age Write,

and Write Lock bits by SPM) 3.7ms 4.5ms

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ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB) ;restore pointer

sbci YH, high(PAGESIZEB)

Rdloop:

lpm r0, Z+

ld r1, Y+

cpse r0, r1

jmp Error

sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256

brne Rdloop

; return to RWW section

; verify that RWW section is safe to read

Return:

in temp1, SPMCR

sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not

; ready yet

ret

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in temp1, SPMCR

sbrc temp1, SPMEN

rjmp Wait_spm

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEWE

rjmp Wait_ee

; SPM timed sequence

out SPMCR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

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ATmega162 Boot Loader

Parameters In Table 94 through Table 96, the parameters used in the description of the self pro-

gramming are given.

Note: 1. The different BOOTSZ Fuse configurations are shown in Figure 94

Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on

page 220 and “RWW – Read-While-W rite Section” on page 220

Table 94. Boot Size Configuration(1)

BOOTSZ1 BOOTSZ0 Boot

Size Pages

Application

Flash

Section

Boot

Loader

Flash

Section

End

Application

Section

Boot Reset

Address

(Start Boot

Loader

Section)

128

words 20x0000 -

0x1F7F 0x1F80 -

0x1FFF 0x1F7F 0x1F80

256

words 40x0000 -

0x1EFF 0x1F00 -

0x1FFF 0x1EFF 0x1F00

512

words 80x0000 -

0x1DFF 0x1E00 -

0x1FFF 0x1DFF 0x1E00

1024

words 16 0x0000 -

0x1BFF 0x1C00 -

0x1FFF 0x1BFF 0x1C00

Table 95. Read-While-Write Limit

Section Pages Address

Read-While-Write section (RWW) 112 0x0000 - 0x1BFF

No Read-While-Write section (NRWW) 16 0x1C00 - 0x1FFF

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Note: 1. Z15:Z14: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.

See “Addressing the Flash During Self-programming” on page 225 for details about

the use of Z-pointer during Self-programming.

Table 96. Explanation of Different Variables Used in Figure 95 and the Mapping to the

Z-pointer(1)

Variable Corresponding

Z-value Description

PCMSB 12 Most significant bit in the Program Counter.

(The Program Counter is 13 bits PC[12:0])

PAGEMSB 5 Most significant bit which is used to address

the words within one page (64 words in a page

requires 6 bits PC [5:0]).

ZPCMSB Z13 Bit in Z-register that is mapped to PCMSB.

Because Z0 is not used, the ZPCMSB equals

PCMSB + 1.

ZPAGEMSB Z6 Bit in Z-register that is mapped to PCMSB.

Because Z0 is not used, the ZPAGEMSB

equals PAGEMSB + 1.

PCPAGE PC[12:6] Z13:Z7 Program Counter page address: Page select,

for Page Erase and Page Write

PCWORD PC[5:0] Z6:Z1 Program Counter word address: Word select,

f or filling temporary buffer (must be z ero during

Page Write operation)

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Memory

Programming

Program And Data

Memory Lock Bits The ATmega162 provides six Lock bits which can be left unprogrammed (“1”) or can be

programmed (“0”) to obtain the additional features listed in Table 98. The Lock bits can

only be erased to “1 ” with the Chip Erase command.

Note: 1. “1” means unprogrammed, “0” means programmed

Table 97. Lock Bit Byte(1)

Lock Bit Byte Bit no Description Default Value

7 – 1 (unprogrammed)

6 – 1 (unprogrammed)

BLB12 5 Boot Lock bit 1 (unprogrammed)

BLB11 4 Boot Lock bit 1 (unprogrammed)

BLB02 3 Boot Lock bit 1 (unprogrammed)

BLB01 2 Boot Lock bit 1 (unprogrammed)

LB2 1 Lock bit 1 (unprogrammed)

LB1 0 Lock bit 1 (unprogrammed)

Table 98. Lock Bit Protection Modes(1)(2)

Memory Lock Bi ts Protection Type

LB Mode LB2 LB1

1 1 1 No memory lock features enabled.

210

Further programming of the Flash and EEPROM is

disabled in Parallel and SPI/JTAG Serial Programming

mode. The Fuse bits are locked in both Serial and Parallel

Programming mode(1).

300

Further programming and verification of the Flash and

EEPROM is disabled in Parallel and SPI/JTAG Serial

Programming mode. Also the Boot Loc k bits and the Fuse

bits are locked in both Serial and Parallel Programming

mode(1).

BLB0 Mode BLB02 BLB01

111

No restrictions for SPM or LPM accessing the Application

section.

2 1 0 SPM is not allowed to write to the Application section.

300

SPM is not allowed to write to the Application section, and

LPM executin g from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

401

LPM executin g from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

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Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

Fuse Bits The ATmega162 has three Fuse bytes. Table 100 and Table 101 describe briefly the

functionality of all t he fuse s and ho w th ey ar e mappe d in to the F use b ytes. Note t hat t he

fuses are read as logical zero, “0”, if they are programmed.

Notes: 1. See “ATmega161 Compatibility Mode” on page 5 for details.

2. See Table 19 on page 51 for BODLEVEL Fuse decoding.

BLB1 Mode BLB12 BLB11

111

No restrictions for SPM or LPM accessing the Boot Loader

section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

300

SPM is not allowed to write to the Boot Loader secti on,

and LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrupts

are disabled while executing from the Boot Loader section.

401

LPM executin g from the Application section is not allowed

to read from the Boot Loader section. If Interr upt Ve ctors

are placed in the Application section, interrupts are

disabled while executing from the Boot Loader section.

Table 98. Lock Bit Protection Modes(1)(2) (Continued)

Memory Lock Bi ts Protection Type

Table 99. Extended Fuse Byte(1)(2)

Fuse Low Byte Bit no Description Default Value

–7– 1

–6– 1

–5– 1

M161C 4 ATmega161 compatibility

mode 1 (unprogrammed)

BODLEVEL2(2) 3Brown-out Detector

trigger level 1 (unprogrammed)

BODLEVEL1(2) 2Brown-out Detector

trigger level 1 (unprogrammed)

BODLEVEL0(2) 1Brown-out Detector

trigger level 1 (unprogrammed)

–0– 1

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Notes: 1. The SPIEN Fuse is not accessible in SPI Serial Programming mode.

2. The default value of BOOTSZ1:0 results in maximum Boot Size. See Table 94 on

page 231 for details.

3. Never ship a product with the OCDEN Fuse programmed regardless of the setting of

Lock bits and the JTAGEN Fuse. A progr ammed OCDEN Fuse enables some parts of

the clock system to be running in all sleep modes. This may increase the power

consumption.

4. If the JTAG interface is left unconnected , the JTAGEN fuse should if possible be dis-

abled. This to avoid static current at the TDO pin in the JTAG interface.

Notes: 1. The default value of SUT1:0 results in maximum start-up time for the default clock

source. See Table 12 on page 39 for details.

2. The default setting of CKSEL3:0 results in Internal RC Oscillator @ 8 MHz. See

Table 5 on page 36 for details.

3. The CKOUT Fuse allow the system clock to be output on Port B 0. See “Clock output

buffer” on page 40 for details.

4. See “System Clock Prescaler” on page 41 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are

locked if Lock bit1 (LB1) is program med. Program t he Fuse bits before pr ogramming the

Lock bits.

Table 100. Fuse High Byte

Fuse Low Byte Bit no Description Default Value

OCDEN(3) 7 Enable OCD 1 (unprogrammed, OCD

disabled)

JTAGEN(4) 6 Enable JTAG 0 (programmed, JTAG

enabled)

SPIEN(1) 5Enable Serial Program and Data

Downloading 0 (programmed, SPI prog.

enabled)

WDTON 4 Watchdog Timer always on 1 (unprogrammed)

EESAVE 3 EEPROM memory is preserved

through the Chip Erase 1 (unprogramme d,

EEPROM not preserved)

BOOTSZ1 2 Select Boot Size (see Table 94 for

details) 0 (programmed)(2)

BOOTSZ0 1 Select Boot Size (see Table 94 for

details) 0 (programmed)(2)

BOOTRST 0 Select Reset Vector 1 (unprogrammed)

Table 101. Fuse Low Byte

Fuse Low Byte Bit no Description Default value

CKDIV8(4) 7 Divide clock by 8 0 (programmed)

CKOUT(3) 6 Clock Output 1 (unprogrammed)

SUT1 5 Select start-up time 1 (unprogrammed)(1)

SUT0 4 Select start-up time 0 (programmed)(1)

CKSEL3 3 Select Clock source 0 (programmed)(2)

CKSEL2 2 Select Clock source 0 (programmed)(2)

CKSEL1 1 Select Clock source 1 (unprogrammed)(2)

CKSEL0 0 Select Clock source 0 (programmed)(2)

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Latching of Fuses The Fuse values are latched when the device enters Programming mode and changes

of the Fuse values will have no effect until the part leaves Programming mode. This

does not apply to the EESAVE Fuse which will take effect once it is programmed. The

Fuses are also latched on Power-up in Normal mode.

Signature Bytes All At mel mi crocon t rollers ha ve a 3-b yte signat ur e code which ide nt ifi es the device. This

code can be read in both Serial and Parallel mode, also when the device is locked. The

three bytes reside in a sepa rate address space.

For the ATmega162 the signature bytes are:

1. 0x000: 0x1E (indicates manufactured by Atmel).

2. 0x001: 0x94 (indicates 16KB Flash memory).

3. 0x002: 0x04 (indicates ATmega162 device when 0x001 is 0x94).

Calibration Byte The ATmega162 has a one-byte calibration valu e for the internal RC Oscillator. This

byte resides in the high byte of address 0x000 in the signature address space. During

Reset, this byte is automatically written into the OSCCAL Register to ensure correct fre-

quency of the calibrated RC Oscillator.

Parallel Programming

Parameters, Pin

Mapping, and

Commands

This section describes h ow to parallel program and verify Flash Program memory,

EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega162. Pulses

are assumed to be at least 250 ns unless otherwise noted.

Signal Names In this sect ion , some pin s of the ATme ga1 62 ar e re fere nced by sign al n ames de scr ibing

their functionality during parallel programming, see Figure 96 and Table 102. Pins not

described in the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-

tive pulse. The bit coding is shown in Table 104.

When pulsing WR or OE , the com mand loa ded dete rmines t he action e xecut ed. The di f-

ferent Commands are shown in Table 105.

Figure 96. Parallel Programming

VCC

+5V

GND

XTAL1

PD1

PD2

PD3

PD4

PD5

PD6

PB7 - PB0 DAT

RESET

PD7

+12 V

BS1

XA0

XA1

DY/BSY

PAGEL

PA0

BS2

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Table 102. Pin Name Mapping

Signal Name in

Programming Mode Pin Name I/O Function

RDY/BSY PD1 O 0: Device is b usy prog r amming, 1: Device is ready

for new command

OE PD2 I Output Enable (Active low)

WR PD3 I Write Pulse (Active low)

BS1 PD4 I Byte Select 1 (“0” selects low b yte, “1” selects high

byte)

XA0 PD5 I XTAL Action Bit 0

XA1 PD6 I XTAL Action Bit 1

PAGEL PD7 I Program Memory and EEPROM data Page Load

BS2 PA0 I Byte Select 2 (“0” selects low b yte, “1” selects 2’nd

high byte)

DATA PB7 - 0 I/O Bi-directional Data bus (Output when OE is low)

Table 103. Pin Values used to Enter Programming Mode

Pin Symbol Value

PAGEL Prog_enable[3] 0

XA1 Prog_enable[2] 0

XA0 Prog_enable[1] 0

BS1 Prog_enable[0] 0

Table 104. XA1 and XA0 Coding

XA1 X A0 Action when XTAL1 is Pulsed

0 0 Load Flash or EEPROM address (High or low address byte determined by BS1)

0 1 Load Data (High or Low data byte for Flash determined by BS1).

1 0 Load Command

1 1 No Action, Idle

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Parallel Programming

Enter Programming Mode The following algorithm puts the device in Parallel Programming mode:

1. Apply 4.5 - 5.5V between VCC and GND, and wait at least 100 µs .

2. Set RESET to “0” and toggle XTAL1 at least six times.

3. Set the Prog_enable pins listed in Table 103 on page 237 to “0000” and wait at

least 100 ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns

after +12V has been applied to RESET, will cause the device to fail entering Pro-

gramming mode.

Considerations for Efficient

Programming The loaded command and address are retained in the device during programming. For

efficient pr ogramming, the following should be considered.

• The command need s only be loaded on ce when writing or reading multiple memory

locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless

the EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte n eeds only be loaded before programming or reading a new 256-

word windo w in Flash or 256 byte EEPROM. This consideration also applies to

Signature bytes reading.

Table 105. Command Byte Bit Coding

Command Byte Command Executed

1000 0000 Chip Erase

0100 0000 Write Fuse Bits

0010 0000 Write Lock Bits

0001 0000 Write Flash

0001 0001 Write EEPROM

0000 1000 Read Signature Bytes and Calibration byte

0000 0100 Read Fuse and Lock Bits

0000 0010 Read Flash

0000 0011 Read EEPROM

Table 106. No. of Words in a Page and no. of Pages in the Flash

Flash Size P age Size PCWORD No. of Pages PCPAGE PCMSB

8K words (16K bytes) 64 words PC[5:0] 128 PC[12:6] 12

Table 107. No. of Words in a Page and no. of Pages in the EEPROM

EEPROM Size Page Size PCWORD No. of pages PCPAGE EEAMSB

512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8

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Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock

bits are not reset until the program memory has been completely erased. The Fuse bits

are not changed. A Chip Erase must be performed before the Flash or EEPROM are

reprogrammed.

Note: 1. The EEPRPOM memory is preserved during chip erase if the EESAVE Fuse is

programmed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

Programming the Flash The Flash is organized in pages, se e Table 106 on page 23 8. When programm ing the

Flash, the program data is latched into a page buffer. This allows one page of program

data to be programmed simultaneously. The following procedure describes how to pro-

gram the entire Flash memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This se lect s hig h da ta byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This se lect s hig h da ta byte.

2. Give PAGEL a positive pulse. This latches the data bytes (See Figure 98 for sig-

nal waveforms).

F. Repeat B through E until the entire buffer is filled or until all data within the page is

loaded.

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While the lower bits in th e address are mapped to words within the page, the higher bits

address the pages within the FLASH. This is illustrated in Figure 97 on page 240. N ote

that if less than eight bit s are required to address word s in the page (pagesize < 256 ),

the most significant bit(s) in the address low byte are used to address the page when

performing a Page Write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Give WR a negative pulse. This starts programming of the entire page of data.

RDY/BSY goes low.

2. Wait until RDY/BSY goes high. (See Figure 98 f or signal waveforms)

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse . This load s th e comman d, an d t he in te rnal write sig-

nals are reset.

Figure 97. Addressing the Flash which is Organized in Pages(1)

Note: 1. PCPA GE and PCW ORD are listed in Table 106 on page 238.

PROGRAM MEMORY

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

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Figure 98. Programming the Flash Waveforms

Note: “XX” is don’t care. The letters refer to the programming description above.

Programming the EEPROM The EEPROM is organized in pages, see Table 107 on pag e 238. When programming

the EEPROM, the program data is latched into a page buffer. This allows one page of

data to be programmed simultaneously. The programming algorithm for the EEPROM

data memory is as follows (refer to “Programming the Flash” on page 239 for details on

Command, Address and Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

5. E: Latch data (give PAGEL a posit ive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

1. Set BS to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page.

RDY/BSY goes low.

3. Wait until to RDY/BSY goes high before programming the next page

(See Figure 99 for signal waveforms).

RDY/BSY

ESET +12V

PAGEL

BS2

0x10 ADDR. LOW ADDR. HIGH

DATA

DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH

XA1

XA0

BS1

XTAL1

XX XX XX

ABCDEBCDEGH

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Figure 99. Programming the EEPROM Waveforms

Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the

Flash” on page 239 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flas h word lo w b yte can no w be read at DATA.

5. Set BS to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” on page 239 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at

DATA.

5. Set OE to “1”.

Programming the Fuse Low

Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming

the Flash” on pag e 239 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “0” and BS2 to “0”. This selects low data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

RDY/BSY

ESET +12V

PAGEL

BS2

0x11 ADDR. HIGH

DATA ADDR. LOW DATA ADDR. LOW DATA XX

XA1

XA0

BS1

XTAL1

AGBCEBCEL

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Programming the Fuse High

Bits The algorithm for programming the Fuse high bits is as follows (refer to “Programming

the Flash” on pag e 239 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte .

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

Programming the Extended

Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to “Program-

ming the Flash” on page 239 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse

bit.

3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2 to “0”. This selects low data byte.

Figure 100. Programming the FUSES Waveforms

RDY/BSY

RESET +12V

PAGEL

0x40

DATA DATA XX

XA1

XA0

BS1

XTAL1

0x40 DATA XX

Write Fuse Low byte Write Fuse high byte

0x40 DATA XX

Write Extended Fuse byte

BS2

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Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the

Flash” on page 239 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is pro-

grammed (LB1 and LB2 is programmed), it is not possible to program the Boot

Lock Bits by any external Programming mode.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock

Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming

the Flash” on pag e 239 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can

now be read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can

now be read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1” and BS1 to “0”. The status of the Extended Fuse bits

can now be read at DATA (“0” means programmed ).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be

read at DATA (“0” means programmed).

6. Set OE to “1”.

Figure 101. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

Reading the Signature Byte s The algorithm for reading the signature bytes is as follows (refer to “Programming the

Flash” on page 239 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at

DATA.

4. Set OE to “1”.

Lock Bits 0

BS2

Fuse High Byte

BS1

DATA

Fuse Low Byte 0

BS2

Extended Fuse Byte

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Reading the Calibration Byte The algorithm for readin g the calibration byte is as follows (refer to “Program ming the

Flash” on page 239 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

Parallel Programming

Characteristics Figure 102. Parallel Programming Timing, Including some General Timing

Requirements

Figure 103. Parallel Programming Timing, Loading Sequence with Timing

Requirements(1)

Note: 1. The timing requirements shown in Figure 102 (i.e., tDVXH, tXHXL, and tXLDX) also apply

to loading operation.

Data & Contol

(

DATA, XA0/1, BS1, BS2)

XTAL1

tXHXL

tWLWH

tDVXH tXLDX

tPLWL

tWLRH

RDY/BSY

PAGEL

tPHPL

tPLBX

tBVPH

XLWL

tWLBX

tBVWL

WLRL

XTAL1

AGEL

PLXH

XLXH

XLPH

ADDR0 (low byte) DATA (low byte) DATA (high byte) ADDR1 (low byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

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Figure 104. Parallel Programming Timing, Reading Sequence (within the Same Page)

with Timing Requirements(1)

Note: 1. The timing requirements shown in Figure 102 (i.e., tDVXH, tXHXL, and tXLDX) also apply

to reading operation.

Table 108. Parallel Programming Characteristics, VCC = 5 V ± 10%

Symbol Parameter Min Typ Max Units

VPP Programming Enable Voltage 11.5 12.5 V

IPP Programming Enable Current 250 µA

tDVXH Data and Control Va lid before XTAL1 High 67 ns

tXLXH XTAL1 Low to XTAL1 High 200 ns

tXHXL XTAL1 Pulse Width High 150 ns

tXLDX Data and Control Hold after XTAL1 Low 67 ns

tXLWL XTAL1 Low to WR Low 0 ns

tXLPH XTAL1 Low to PAGEL high 0 ns

tPLXH PAGEL low to XTAL1 high 150 ns

tBVPH BS1 Valid before PAGEL High 67 ns

tPHPL PAGEL Pulse Width High 150 ns

tPLBX BS1 Hold after PAGEL Low 67 ns

tWLBX BS2/1 Hold after WR Low 67 ns

tPLWL PAGEL Low to WR Low 67 ns

tBVWL BS1 Valid to WR Low 67 ns

tWLWH WR Pulse Width Low 150 ns

tWLRL WR Low to RDY/BSY Low 0 1 µs

tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms

tWLRH_CE WR Low to RDY/BSY High f or Chip Erase(2) 7.5 9 ms

tXLOL XTAL1 Low to OE Lo w 0 ns

TAL1

ADDR0 (low byte) DATA (low byte) DATA (high byte) ADDR1 (low byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

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Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock

Bits commands.

2. tWLRH_CE is valid for the Chip Erase command.

Serial Downloading

SPI Serial Programming

Pin Mapping

Both the Flash and EEPROM memory arrays can b e programmed using the serial SPI

bus while RESET is pulled to GND. The serial interface co nsists of pins SCK, MOSI

(input) and MISO (output). After RESET is set low, the Programming Enable instruction

needs to be executed first before program/erase operations can be executed. NOTE, in

Table 109 on page 24 7, the p i n mapp ing f o r SPI pr ogr amm ing i s listed. Not all part s use

the SPI pins dedicated for the internal SPI interf ace.

Figure 105. SPI Serial Programming and Verify(1)

Note: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock

source to the XTAL1 pin.

When programming the EEPROM, an auto-erase cy cle is built into the self-timed pro-

gramming operation (in the Serial mode ONLY) and there is no need to first execute the

Chip Erase instruction. The Chip Erase operation turns the content of every m emory

location in both the Program and EEPROM arrays into 0xFF.

tBVDV BS1 Valid to DATA valid 0 250 ns

tOLDV OE Low to DATA Valid 250 ns

tOHDZ OE High to DATA Tri-stated 250 ns

Table 108. Parallel Programming Characteristics, VCC = 5 V ± 10% (Continued)

Symbol Parameter Min Typ Max Units

Table 109. Pin Mapping SPI Seri al Programming

Symbol Pins I/O Description

MOSI PB5 I Serial Data in

MISO PB6 O Serial Data out

SCK PB7 I Serial Clock

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

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Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high

periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

SPI Serial Programming

Algorithm When writing serial data to the ATmega162, data is clocked on the rising edge of SCK.

When reading data from the ATm ega162, data is clocked on the falling edge of SCK.

See Figure 106.

To program and verify the ATmega162 in the SPI Serial Programming mode, the follow-

ing sequence is recommended (See four byte instruction formats in Table 111):

1. Power-up sequence:

Apply pow er between VCC and GND while RESET and SCK are set to “0”. In

some systems, the programmer can not guarantee that SCK is held low during

Power-up. In this case, RESET must be given a positive pulse of at least two

CPU clock cycles duration after SCK has been set to “0”.

2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Pro-

gramming Enable serial instruction to pin MOSI.

3. The SPI Serial Programming instructions will not work if the communication is

out of synchronization. When in sync. the second byte (0x53), will echo back

when issuing the third byte of the Programming Enable instruction. Whether the

echo is correct or not , all four bytes of the ins truction must be transmitt ed. If the

0x53 did not echo back, give RESET a positive pulse and issue a new Program-

ming Enable command.

4. The Flash is programmed one page at a time. The page size is found in Table

106 on page 238. The memory page is loaded one byte at a time by supplying

the 6 LSB of the address and data together with the Load Program Memory

Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program

Memory Page is stored by loading the Wr ite Program Memory Page instruction

with the 8 MSB of the address. If polling is not used, the user must wait at least

tWD_FLASH before issuing the next page. (See Table 110.) Accessing the SPI

serial programming interface before the Flash write operation completes can

result in incorrect programming.

5. The EEPROM array can either be programmed one page at a time or it can be

programmed byte by byte.

For Page Programming, the following algorithm is used:

The EEPROM memory page is loaded one byte at a time by supplying the 2 LSB of

the address and data together with the Load EEPROM Memory Page instruction.

The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page

instruction with th e 8 MSB of the address. If po lling is not used, the use r must wait at

least tWD_EEPROM before issuing the next page. (See Table 100.) Accessing the SPI

Serial Programming interface before the EEPROM write operation completes can

result in incorrect programming.

Alternatively, the EEPROM can be programmed bytewise:

The EEPROM array is programmed one byte at a time by supplying the address

and data together with the Write EEPROM instruction. An EEPROM memory loca-

tion is first automatically erased before new data is written. If polling is not used, the

user must wait at least tWD_EEPROM before issuing the next byte. (See Table 110.) In

a chip erased device, no 0xFFs in the data file(s) need to be programmed.

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6. Any memory location can b e v erified by using the Read instruction which returns

the content at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence

normal operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn VCC power off.

Data Polling Flash When a page is being programmed into the Flash, reading an address location within

the page being programmed will give the value 0xFF. At the time the device is ready for

a new page, the programmed value will read correctly. This is used to determin e when

the next page can be writt en. Note that the en tire page is written simultane ously and any

address within the page can be used for polling. Data pollin g of the Flash will not work

for the value 0xFF, so when programming this value, the user will have to wait for at

least tWD_FLASH before programming the next page. As a chip erased device contains

0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be

skipped. See Table 110 for tWD_FLASH value.

Data Polling EEPROM When a new byte has been wri tten an d is being prog rammed int o EEPROM, re ading the

address location being programmed will give the value 0xFF. At the time the device is

ready for a new byte, the programmed value will read correctly. This is used to deter-

mine when the next byte can be written. This will not work for the va lue 0xFF, but the

user should have the following in mind: As a chip erased device contains 0xFF in all

locations, programming of addresses that are meant to contain 0xFF, can be skipped.

This does not apply if the EEPROM is re-programmed without chip erasing the device.

In this case, data polling cannot be used for the value 0xFF, and the user will have to

wait at least tWD_EEPROM before programming the next byte. See Table 110 for

tWD_EEPROM value.

Figure 106. SPI Serial Programming Waveforms

Table 110. Minimum Wait Delay before Writing the Next Flash or EEPROM Location

Symbol Minimum Wait Delay

tWD_FLASH 4.5 ms

tWD_EEPROM 9.0 ms

tWD_ERASE 9.0 ms

tWD_FUSE 4.5 ms

MSB

LSB

SERIAL CLOCK INPUT

(SCK)

SERIAL DATA INPUT

(MOSI)

(MISO)

SAMPLE

ERIAL DATA OUTPUT

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Table 111. SPI Serial Programming Instruction Set(1)

Instruction Ins truction Format Operation

Byte 1 Byte 2 Byte 3 Byte4

Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming

after RESET goes low.

Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.

Read Program Memory 0010 H000 00aa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from

Program memory at word address

a:b.

Load Program Memory

Page

0100 H000 00xx xxxx xxbb bbbb iiii iiii Write H (high or low) data i to

Program Memory page at word

address b. Data low byte must be

loaded before Data high byte is

applied within the same address.

Write Program Memory

Page 0100 1100 00aa aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at

address a:b.

Read EEPROM Memory 1010 0000 00xx xxaa bbbb bbbb oooo oooo Read data o from EEPROM

memory at address a:b.

Write EEPROM Memory

(byte access) 1100 0000 00xx xxaa bbbb bbbb iiii iiii Write data i to EEPROM memory

at address a:b.

Load EEPROM Memory

Page (page access)

1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory

page buffer. After data is loaded,

program EEPROM page.

Write EEPROM Memory

Page (page access) 1100 0010 00xx xxaa bbbb bb00 xxxx xxxx Write EEPROM page at address

a:b.

Read Lock Bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed,

“1” = unprogrammed. See Table

97 on page 233 for details.

Write Loc k Bi ts 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to

program Lock bits . See Table 97

on page 233 for details.

Read Signatu re Byte 0011 0000 00xx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address

Write Fuse Bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram. See Table 101 on

page 235 for details.

Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram. See Table 100 on

page 235 for details.

Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx xxxx xxii Set bits = “0” to program, “1” to

unprogram. See Table 99 on

page 234 for details.

Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed,

“1” = unprogrammed. See Table

101 on page 235 for details.

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Note: 1. a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data ou t, i = data in, x = don’t care

SPI Serial Programming

Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 270.

Read Fuse High Bits

0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fu se high bits. “0” = pro-

grammed, “1” = unprogrammed.

See Table 100 on page 235 for

details.

Read Extended Fuse Bits

0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” =

pro-grammed, “1” =

unprogrammed. See Table 99 on

page 234 for details.

Read Calibration Byte 0011 1000 00xx xxxx 0000 0000 oooo oooo Read Calibration Byte

Poll RDY/BSY

1111 0000 0000 0000 xxxx xxxx xxxx xxxoIf o = “1”, a programming operation

is still busy. Wait until this bit

retur ns to “0” before applying

another command.

Table 111. SPI Serial Programming Instruction Set(1) (Continued)

Instruction Ins truction Format Operation

Byte 1 Byte 2 Byte 3 Byte4

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Programming via the

JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific

pins: TCK, TMS, TDI, and TDO. Control of the Reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The

device is default shipped with the Fuse programmed. In addition, the JTD bit in

MCUCSR must be cleared. Alternatively, if the JTD bit is set, the External Reset can be

forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins

are available for progra mming. This provide s a means of using t he JTAG p ins as no rmal

port pins in running mode while still allowing In-System Programming via the JTAG

interface. Note that this technique can not be used when using the JTAG pins for

Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for

this purpose.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific JTAG

Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG

instructions useful for Programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format.

The text describes which Data Register is selected as path between TDI and TDO for

each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can

also be used as an idle state between JTAG sequences. T he state machine sequence

for changing the instruction word is shown in Figure 107.

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Figure 107. State machine sequence for changing the instruction word

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

011 1

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AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode

or taking the device out from the Reset mode. The TAP controller is not reset by this

instruction. The one bit Reset Register is selected as data register. Note that the reset

will be active as long as there is a logic “one” in the Reset Chain. The output from this

chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port.

The 16-bit Programming Enable Register is selected as data register. The active states

are the following:

• Shift-DR: The programming enable signature is shifted into the Data Register.

• Update-DR: The programming enable signat ure is compared to the correct value,

and Programming mode is entered if the signature is valid.

PROG_COMMANDS (0x5) Th e AVR specific public JTAG instruction for entering programm ing commands via the

JTAG port. The 15-bit Programming Command Register is sele cted as data register.

The active states are the following:

• Capture-DR: The result of the previous command is loaded into the Data Register.

• Shift-DR: The Dat a Register is shift ed b y the TCK input , shifting out the result of the

previous command and shifting in the new command.

• Update-DR: The pr ogramming co mmand is applied to the Flash inputs.

• Run-Test/Idle: One clock cycle is generated, executing the applied command (not

always required, se e Ta b le 11 2 be low).

PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the

JTAG port. The 1024 bit Virtual Flash Page Load Register is selected as register. This is

a virtual scan chain with length equal to the number of bits in one Flash page. Internally

the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR state is not

used to transfer data from the Shift Register. The data are automatically transferred to

the Flash page buffer byte-by-byte in the Shift-DR state by an internal state ma chine.

This is the only active state:

• Shift-DR: Flash page data are shifted in from TDI by the TCK input, and

automatically loaded into the Flash page one byte at a time.

Note: The JTAG instr uction PROG_PAGELOAD can only be used if the AVR device is the first

device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the

byte-wise programming algorithm must be used.

PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to read one full Flash data page via the JTAG

port. The 1032 bit Vir tual Flash Page Read Register is selected as data register. This is

a virtual scan chain with length equal to the number of bits in one Flash page plus eight.

Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR

state is not used to transfe r data to the Shift Regi ster. The d ata are auto matica lly trans-

ferred from the Flash page buffer byte-by-byte in the Shift-DR state by an internal state

machine. This is the only active state:

• Shift-DR: Flash dat a are automatically read one byte at a time and shifted out on

TDO by the TCK input. The TDI input is ignored.

Note: The JTAG instr uction PROG_PAGEREAD can only be used if the AVR device is the first

device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the

byte-wise programming algorithm must be used.

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Data Registers The Data Registers are selected by the JTAG Instruction Registers described in section

“Programming Spec ific JTAG Instructions” on page 252. The Dat a Registers rele vant for

programming operations are:

• Reset Register

• Programming Enable Register.

• Programming Command Register.

• Virtual Flash Page Load Register.

• Virtual Flash Page Read Register.

Reset Register The Reset Register is a test data register used to reset the part during programming. It

is required to reset the part before entering Programming mode.

A high value in the Reset Register corresponds to pulling the external reset low. The

part is reset as long as there is a high valu e present in the Reset Register. Depending

on the fuse settings for the clock options, the part will remain reset for a Reset Time-out

period (refer to “Clock Sources” on page 3 6) after re leasing the Reset Register. The out-

put from this data register is not latched, so the reset will take place im mediately, as

shown in Figure 86 on page 208.

Programming Enable Register The Programming Enable Register is a 16-b it register. The contents o f this register is

compared to the programming enable signature, binary code 1010_0011_0111_0000.

When the cont ents of the register is equa l to the programming en able signature, pro-

gramming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset,

and should always be reset when leaving Programming mode.

Figure 108. Programming Enable Register

TDI

TDO

ClockDR & PROG_ENABLE

Programming Enable

0xA370

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Programming Command

ally shift in programming commands, and to serially shift out the result of the previous

command, if any. The JTAG Programming Instruction Set is shown in Table 112. The

state sequence when shifting in the programming commands is illustrated in Figure 110.

Figure 109. Programming Command Register

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

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Table 112. JTAG Programming Instruction Set

Instruction TDI sequence TDO sequence Notes

1a. Chip eRase 0100011_10000000

0110001_10000000

0110011_10000000

xxxxxxx_xxxxxxxx

1b. Poll for Chip Erase complete 01100 11_10000000 xxxxxox_xxxxxxxx (2)

2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx

2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx

2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx

2f. Latch Data 0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

2g. Write Flash Page 0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

2h. Poll for Page Write complete 0 110111_00000000 xxxxxox_xxxxxxxx (2)

3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx

3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

3d. Read Data Low and High Byte 0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

xxxxxxx_oooooooo low byte

high byte

4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx

4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx

4e. Latch Data 0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

4f. Wr ite EEPROM Page 0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

(1)

4g. Poll for Page Write complete 0 110011_00000000 xxxxxox_xxxxxxxx (2)

5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx

5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

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5d. Read Data Byte 0110011_bbbbbbbb

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

6a. Enter Fuse Write 0100011_01000000 xxxxxxx_xxxxxxxx

6b. Load Data Low Byte(6) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6c. Write Fuse Extended Byte 0111011_00000000

0111001_00000000

0111011_00000000

xxxxxxx_xxxxxxxx

(1)

6d. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2)

6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6f. Wr ite Fuse High byte 0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

6g. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2)

6h. Load Data Low Byte(8) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6i. Write Fuse Low Byte 0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

(1)

6j. Poll for Fuse Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2)

7a. Enter Lock Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx

7b. Load Data Byte(9) 0010011_11iiiiii xxxxxxx_xxxxxxxx (4)

7c. Write Lock Bits 0110011_0000000 0

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

(1)

7d. Poll for Lock Bit Write complete 0110011_0000000 0 xxxxxox_xxxxxxxx (2)

8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx

8b. Read Fuse Extended Byte(6) 0111010_00000000

0111111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8c. Read Fuse High Byte(7) 0111110_00000000

0111111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8d. Read Fuse Low Byte(8) 0110010_00000000

0110011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8e. Read Lock Bits(9) 0110110_00000000

0110111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_xxoooooo (5)

Table 112. JTAG Programming Instruction Set (Continued)

Instruction TDI sequence TDO sequence Notes

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Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is

nor mally the case).

2. Repeat until o = “1”.

3. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse.

4. Set bits to “0” to program the corresponding lock bit, “1” to leave the Lock bit unchanged.

5. “0” = programmed, “1” = unprogrammed.

6. The bit mapping for Fuses Extended byte is listed in Table 99 on page 234.

7. The bit mapping for Fuses High byte is listed in Table 100 on page 235.

8. The bit mapping for Fuses Low byte is listed in Table 101 on page 235.

9. The bit mapping for Lock Bits byte is listed in Table 97 on page 233.

10.Address bits exceeding PCMSB and EEAMSB (Table 106 and Table 107) are don’t care

Note: a = address high bits

b = address low bits

H = 0 – Low byte, 1 – High Byte

o = data out

i = data in

x = don’t care

8f . Read Fuses and Lock Bits 0111010_00000000

0111110_00000000

0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

(5)

Fuse ext. byte

Fuse high byte

Fuse low byte

Lock bits

9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx

9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

9c. Read Signature Byte 0110010_00000000

0110011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx

10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

10c. Read Calibration Byte 0110110_00000000

0110111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

11a. Load No Operation Command 0 100011_00000000

0110011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_xxxxxxxx

Table 112. JTAG Programming Instruction Set (Continued)

Instruction TDI sequence TDO sequence Notes

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Figure 110. State Machine Sequence for Chang ing/Reading the Data Word

Virtual Flash Page Load

number of bits in one Flash page. Internally the Shift Register is 8-bit, and the data are

automatically transferred to the Flash page buffer byte-by-byte. Shift in all instruction

words in the page, star ting with the LSB of the first instruction in the page and ending

with the MSB of the last instruction in the page . This pro vides an efficient way to load t he

entire Flash page buffer before executing Page Write.

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

011 1

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Figure 111. Virtual Flash Page Load Register

Virtual Flash Page Read

number of bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the

data are automatically transferred from the Flash data page byte-by-byte. The first eight

cycles are us ed to transfer the fir st byte to the internal Shift Register, and the bits that

are shifted out during these right cycles should be ignored. Following this initialization,

data are shifted out star ting with the LSB of the first instruction in the page and ending

with the MSB of the last instruction in the page. This provides an efficient way to read

one full Flash page to verify programming.

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

STROBES

ADDRESS

State

Machine

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Figure 112. Virtual F lash Page Read Register

Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 112.

Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift one in the Reset Register.

2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Pro-

gramming Enable Register.

Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS.

2. Disable all programming instructions by using no oper ation instruction 11a.

3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the Pro-

gramming Enable Register.

4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS.

2. Start Chip Erase using programming ins truction 1a.

3. Poll for Chip Erase complete using programming instruction 1b, or wait for

tWLRH_CE (refer to Table 108 on page 246).

Programming the Flash Before programming the Flash a Chip Erase m ust be perform ed. See “Perfo rming Chip

Erase” on page 262.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load address high byte using programming instruction 2b.

4. Load address low byt e using programming instruction 2c.

5. Load data using programming instructions 2d, 2e and 2f.

6. Repeat steps 4 and 5 for all instruction words in the page.

7. Write the page using programming instruction 2g.

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

STROBES

ADDRESS

State

Machine

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8. Poll for Flash write complete using programming instruction 2h, or wait for

tWLRH_FLASH (refer to Table 108 on page 246).

9. Repeat steps 3 to 7 until all data have been programmed.

A more efficient data transfer can be achieved using the PROG_PAGELOAD

instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load the page address using programming instructions 2b and 2c. PCWORD

(ref er to Table 106 on page 238) is used to add ress within one page an d must be

writte n as 0.

4. Enter JTAG instruction PROG_PAGELOAD.

5. Load the entire page by shifting in all instruction words in the page, starting with

the LSB of the first instruction in the page and ending with the MSB of the last

instruction in the page.

6. Enter JTAG instruction PROG_COMMANDS.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for

tWLRH_FLASH (refer to Table 108 on page 246).

9. Repeat steps 3 to 8 until all data have been programmed.

Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load address using programming instructions 3b and 3c.

4. Read data using programming instruction 3d.

5. Repeat steps 3 and 4 until all data have been re ad .

A more efficient data transfer can be achieved using the PROG_PAGEREAD

instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load the page address using programming instructions 3b and 3c. PCWORD

(ref er to Table 106 on page 238) is used to add ress within one page an d must be

writte n as 0.

4. Enter JTAG instruction PROG_PAGEREAD.

5. Read the entire page by shifting out all instruction words in the page, starting

with the LSB of the first instruction in the page and ending with the MSB of the

last instruction in the page. Remember that the first 8 bits shifted out should be

ignored.

6. Enter JTAG instruction PROG_COMMANDS.

7. Repeat steps 3 to 6 until all data have been read.

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Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed. See “Performing

Chip Erase” on page 262.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM write using programming instruction 4a.

3. Load address high byte using programming instruction 4b.

4. Load address low byt e using programming instruction 4c.

5. Load data using programming instructions 4d and 4e.

6. Repeat steps 4 and 5 for all data bytes in the page.

7. Write the data using programming instruction 4f.

8. Poll for EEPROM write complete using programming instruction 4g, or wait for

tWLRH (refer to Table 108 on page 246).

9. Repeat steps 3 to 8 until all data have been programmed.

Note: The PROG_PAGELOAD instruction can not be used when programming the EEPROM

Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM read using programming instruction 5a.

3. Load address using programming instructions 5b and 5c.

4. Read data using programming instruction 5d.

5. Repeat steps 3 and 4 until all data have been re ad .

Note: The PROG_PAGER EAD instruction ca n no t b e use d when rea d i ng the EEPROM

Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse write using programming instruction 6a.

3. Load data low byte using programming instructions 6b. A bit value of “0” will pro-

gram the corresponding Fuse, a “1” will unprogram the Fuse.

4. Write Fuse extended byte using programming instruction 6c.

5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH

(refer to Table 108 on page 246).

6. Load data low byte using programming instructions 6e. A bit value of “0” will pro-

gram the corresponding Fuse, a “1” will unprogram the Fuse.

7. Write Fuse High by te using programming instruction 6f.

8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH

(refer to Table 108 on page 246).

9. Load data low byte using programming instructions 6h. A “0” will program the

Fuse, a “1” will unprogram the Fuse.

10. Write Fuse Low byte using programming instruction 6i.

11. Poll for Fuse write complete using programming instruction 6j, or wait for tWLRH

(refer to Table 108 on page 246).

Programming the Lock Bits 1. Enter JTAG instruction PR OG_COMMANDS.

2. Enable Lock bit write using progra mming instruction 7a.

3. Load data using programming instructions 7b. A bit value of “0” will program the

corresponding Lock bit, a “1” will leave the Lock bit unchanged.

4. Write Lock bits using progr amming instruction 7c.

5. Poll for Lock bit write complete using programming instruction 7d, or wait for

tWLRH (refer to Table 108 on page 246).

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Reading the Fuses and Lock

Bits 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse/Lock bit read using programming instruction 8a.

3. To read all Fuses and Lock bits, use programming instruction 8f.

To only re ad Fu se Extend ed byte, use programming instruction 8b.

To only read Fuse High byte, use programming instruction 8c.

To only read Fuse Low byte, use programming instruction 8d.

To only read Lock bits, use programming instruction 8e .

Reading the Signature Byte s 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Signature byte read using programming ins truction 9a.

3. Load address 0x00 using programming instruction 9b.

4. Read first signature byte using programming instruction 9c.

5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second

and third signature bytes, respectively.

Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Calibr ation byte read using programming instruction 10a.

3. Load address 0x00 using programming instruction 10b.

4. Read the calibration byte using programming instruction 10c.

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Electrical Characteristics

DC Characteristics

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device . This is a stress r ating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for e xtended periods may aff ect device

reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to VCC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin............................................... 40.0 mA

DC Current VCC and GND Pins.......................200.0 mA PDIP,

400 mA TQFP/MLF

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ. Max. Units

VIL Input Low Voltage , Exce pt XTAL1

and RESETpin VCC = 1.8 - 2.4V

VCC = 2.4 - 5.5V -0.5

-0.5 0.2 VCC(1)

0.3 VCC(1) V

VIH Input High Voltage, Except XTAL1

and RESET pin VCC = 1.8 - 2.4V

VCC = 2.4 - 5.5V 0.7 VCC(2)

0.6 VCC(2) VCC + 0.5

VCC + 0.5 V

VIL1 Input Low Voltage, XTAL1 pin VCC = 1.8 - 5.5V -0.5 0.1 VCC(1) V

VIH1 Input High Voltage, XTAL1 pin VCC = 1.8 - 2.4V

VCC = 2.4 - 5.5V 0.8 VCC(2)

0.7 VCC(2) VCC + 0.5

VCC + 0.5 V

VIL2 Input Low Voltage, RESET pin VCC = 1.8 - 5.5V -0.5 0.2 VCC V

VIH2 Input High Voltage, RESET pin VCC = 1.8 - 5.5V 0.9 VCC(2) VCC + 0.5 V

VOL Output Low Voltage(3), P orts A, B, C ,

D, and E IOL = 20 mA, VCC = 5V

IOL = 10 mA, VCC = 3V 0.7

0.5 V

VOH Output High V oltage(4), P orts A, B, C ,

D, and E IOL = -20 mA, VCC = 5V

IOL = 10mH, VCC = 3V 4.2

2.3 V

IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low

(absolute value) 1µA

IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high

(absolute value) 1µA

RRST Reset Pull-up Resistor 30 60 kΩ

Rpu I/O Pin Pull-up Resistor 20 50 kΩ

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Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest v alue where the pin is guaranteed to be read as high

3. Although each I/O por t can sink more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state

conditions (non-transient), the following must be obser ved:

PDIP Package:

1] The sum of all IOL, for all ports, should not exceed 200 mA.

2] The sum of all IOL, for port B0 - B7, D0 - D7, and XTAL2, should not exceed 100 mA.

3] The sum of all IOL, for ports A0 - A7, E0 - E2, C0 - C7, should not exceed 100 mA.

TQFP and QFN/MLF Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports B0 - B7, D0 - D7, and XTAL2, should not exceed 200 mA.

3] The sum of all IOL, for ports C0 - C7 and E1 - E2, should not exceed 200 mA.

4] The sum of all IOL, for ports A0 - A7 and E0, should not exceed 200 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state

conditions (non-transient), the following must be obser ved:

PDIP Package:

1] The sum of all IOH, for all ports, should not exceed 200 mA.

2] The sum of all IOH, for port B0 - B7, D0 - D7, and XTAL2, should not exceed 100 mA.

3] The sum of all IOH, for ports A0 - A7, E0 - E2, C0 - C7, should not exceed 100 mA.

TQFP and MLF Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports B0 - B7, D0 - D7, and XTAL2, should not exceed 200 mA.

3] The sum of all IOH, for ports C0 - C7 and E1 - E2, should not exceed 200 mA.

4] The sum of all IOH, for ports A0 - A7 and E0, should not exceed 200 mA.

ICC

Power Supply Current

Active 1 MHz, VCC = 2V

(ATmega162V) 0.8 mA

Active 4 MHz, VCC = 3V

(ATmega162/V) 5mA

Active 8 MHz, VCC = 5V

(ATmega162) 16 mA

Idle 1 MHz, VCC = 2V

(ATmega162V) 0.3 mA

Idle 4 MHz, VCC = 3V

(ATmega162/V) 2mA

Idle 8 MHz, VCC = 5V

(ATmega162) 8mA

Power-down mode

WDT Enabled,

VCC = 3.0V < 10 14 µA

WDT Disabled,

VCC = 3.0V < 1.5 2 µA

VACIO Analog Comparator Input Offset

Voltage VCC = 5V

Vin = VCC/2 < 10 40 mV

IACLK Analog Comparator Input Leakage

Current VCC = 5V

Vin = VCC/2 -50 50 nA

tACPD Analog Comparator Propagation

Delay VCC = 2.7V

VCC = 4.0V 750

500 ns

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued)

Symbol Parameter Condition Min. Typ. Max. Units

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If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

Figure 113. Absolute Maximum Frequency as a function of VCC, ATmega162V

Figure 114. Absolute Maximum Frequency as a function of VCC, ATmega162

Frequency

8 MHz

6 MHz

1 MHz

1.8V 2.4V 5.5V2.7V 4.5V

Safe Operating

Area

Frequency

8 MHz

6 MHz

1 MHz

1.8V 2.4V 5.5V2.7V 4.5V

Safe Operating

Area

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External Cloc k Drive

Waveforms Figure 115. External Clock Drive Waveforms

External Cloc k Drive

VIL1

VIH1

Table 113. External Clock Drive

Symbol Parameter

VCC = 1.8 - 5.5V VCC =2.7 - 5.5V VCC = 4.5 - 5.5V

UnitsMin. Max. Min. Max. Min. Max.

1/tCLCL

Oscillator

Frequency 0108016MHz

tCLCL Clock Period 1000 125 62.5 ns

tCHCX High Time 400 50 25 ns

tCLCX Low Time 400 50 25 ns

tCLCH Rise Time 2.0 1.6 0.5 µs

tCHCL Fall Time 2.0 1.6 0.5 µs

∆tCLCL

Change in

period from one

clock cycle to

the next

22 2%

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SPI Timing

Characteristics See Figure 116 and Figure 117 for details.

Note: 1. In SPI Programming mode, the minimum SCK high/low period is:

– 2 tCLCL for fCK < 12 MHz

– 3 tCLCL for fCK > 12 MHz.

Figure 116. SPI Interface Timing Requirements (Master Mode)

Table 114. SPI Timing Parameters

Description Mode Min Typ Max

1 SCK peri od Master See Table 68

2 SCK high/low Master 50% duty cycle

3 Rise/Fall time Ma ster 3.6

4 Setup Master 10

5 Hold Master 10

6 Out to SCK Master 0.5 • tsck

7 SCK to out Master 10

8 SCK to out high Master 10

9 SS low to out Slave 15

10 SCK period Slave 4 • tck

11 SCK high/low(1) Slave 2 • tck

12 Rise/Fall time Slave 1.6 µs

13 Setup Slave 10

14 Hold Slave tck

15 SCK to out Slave 15

16 SCK to SS high Slave 20

17 SS high to tri-state Slave 10

18 SS low to SCK Slave 2 • tck

MOSI

(

Data Output)

SCK

(CPOL = 1)

MISO

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

345

271

ATmega162/V

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Figure 117. SPI Interface Timing Requirements (Slave Mode)

MISO

(Data Output)

SCK

(CPOL = 1)

MOSI

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

11 11

1213 14

272

ATmega162/V

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External Data Memory Timing

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 115. External Data Memory Characteristics, 4.5 - 5.5 Volts, no Wait-s tate

Symbol Parameter

8 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

LHLL ALE Pulse Width 115 1.0tCLCL-10 ns

AVLL Address Valid A to ALE Low 57.5 0.5tCLCL-5(1) ns

3a tLLAX_ST

Address Hold After ALE Low,

write access 55 ns

3b tLLAX_LD

Address Hold after ALE Low,

read access 55 ns

AVLLC Address Valid C to ALE Low 57.5 0.5tCLCL-5(1) ns

AVRL Address Valid to RD Low 115 1.0tCLCL-10 ns

AVWL Address Valid to WR Low 115 1.0tCLCL-10 ns

LLWL ALE Low to WR Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) ns

LLRL ALE Low to RD Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) ns

DVRH Data Setup to RD High 40 40 ns

10 tRLDV Read Low to Data Valid 75 1.0tCLCL-50 ns

11 tRHDX Data Hold After RD High 0 0 ns

12 tRLRH RD Pulse Width 115 1.0tCLCL-10 ns

13 tDVWL Data Setup to WR Low 42.5 0.5tCLCL-20(1) ns

14 tWHDX Data Hold After WR High 115 1.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 125 1.0tCLCL ns

16 tWLWH WR Pulse Wi dth 115 1.0tCLCL-10 ns

Table 116. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state

Symbol Parameter

8 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

10 tRLDV Read Low to Data Valid 200 2.0tCLCL-50 ns

12 tRLRH RD Pulse Width 240 2.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 240 2.0tCLCL ns

16 tWLWH WR Pulse Width 240 2.0tCLCL-10 ns

273

ATmega162/V

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Table 117. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 ns

12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 375 3.0tCLCL ns

16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns

Table 118. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 ns

12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns

14 tWHDX Data Hold After WR High 240 2.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 375 3.0tCLCL ns

16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns

Table 119. External Data Memory Characteristics, 2.7 - 5.5 Volts, no Wait-s tate

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

LHLL ALE Pulse Width 235 tCLCL-15 ns

AVLL Ad dress Valid A to ALE Low 115 0.5tCLCL-10(1) ns

3a tLLAX_ST

Address Hold After ALE Low,

write access 55

3b tLLAX_LD

Address Hold after ALE Low,

read access 55

AVLLC Address Valid C to ALE Low 115 0.5tCLCL-10(1) ns

AVRL Address Valid to RD Low 235 1.0tCLCL-15 ns

AVWL Address Valid to WR Low 235 1.0tCLCL-15 ns

LLWL ALE Low to WR Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns

LLRL ALE Low to RD Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns

DVRH Data Setup to RD High 45 45 ns

10 tRLDV Read Low to Data Valid 190 1.0tCLCL-60 ns

11 tRHDX Data Hold After RD High 0 0 ns

274

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Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

12 tRLRH RD Pulse Width 235 1.0tCLCL-15 ns

13 tDVWL Data Setup to WR Low 105 0.5tCLCL-20(1) ns

14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 250 1.0tCLCL ns

16 tWLWH WR Pulse Width 235 1.0tCLCL-15 ns

Table 119. External Data Memory Characteristics, 2.7 - 5.5 Volts, no Wait-s tate (Continued)

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

Table 120. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

10 tRLDV Read Low to Data Valid 440 2.0tCLCL-60 ns

12 tRLRH RD Pulse Width 485 2.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 500 2.0tCLCL ns

16 tWLWH WR Pulse Width 485 2.0tCLCL-15 ns

Table 121. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

10 tRLDV Read Low to Data Valid 690 3.0tCLCL-60 ns

12 tRLRH RD Pulse Width 735 3.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 750 3.0tCLCL ns

16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns

Table 122. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

10 tRLDV Read Low to Data Valid 690 3.0tCLCL-60 ns

12 tRLRH RD Pulse Width 735 3.0tCLCL-15 ns

14 tWHDX Data Hold After WR High 485 2.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 750 3.0tCLCL ns

16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns

275

ATmega162/V

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Figure 118. External Memory Timing (SRWn1 = 0, SRWn0 = 0

Figure 119. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

System Clock (CLKCPU)

8 12

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address Data

Prev. data XX

DA7:0 (XMBK = 0) DataAddress

System Clock (CLK

CPU

)

8 12

276

ATmega162/V

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Figure 120. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

Figure 121. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)

Note: 1. The ALE pulse in the last period (T4 - T7) is only present if the next instruction

accesses the RAM (inter nal or external).

ALE

T1 T2 T3

Write

Read

A15:8 Address

Prev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) Data

Address

System Clock (CLK

CPU

)

8 12

T4 T5

ALE

T1 T2 T3

Write

Read

A15:8

Address

Prev. addr.

DA7:0

Address DataPrev. data XX

DA7:0 (XMBK = 0)

Data

Address

System Clock (CLK

CPU

)

8 12

T4 T5 T6

277

ATmega162/V

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ATmega162 Typical

Characteristics The following charts show typical behavior. These figures are not tested during manu-

facturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-

to-rail output is used as clock source. The CKSEL Fuses are programmed to select

external clock.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a fu nction of several factors such as: Operating voltage,

operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and

ambient temper ature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as

CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switch-

ing frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaran-

teed to function properly at frequencies hig her than the ordering code indicat es.

The difference between current consumption in Power-down mode with Watchdog

Timer enabled a nd Power-down m ode with Watc hdog Timer disabled repr esents the di f-

ferential curr en t dr aw n by th e Wat c h do g Time r.

Active Supply Current Figure 122. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

0.5

1.5

2.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

ICC (mA)

5.5V

4.5V

4.0V

3.3V

2.7V

1.8V

5.0V

278

ATmega162/V

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Figure 123. Active Sup ply Current vs. Frequency (1 - 20 MHz)

Figure 124. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1- 20 MHz

02468101214161820

Frequency (MHz)

ICC (mA)

5.5V

4.5V

4.0V

3.3V

2.7V

1.8V

5.0V

CT IVE SUPPLY CURRENT vs. VC

INTERNAL RC OSCI LLATOR, 8 MHz

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V

)

ICC (mA

)

85°C

25°C

-40°C

279

ATmega162/V

2513H–AVR–04/06

Figure 125. Active Supply Current vs. VCC (32 kHz External Oscillator)

Idle Supply Current Figure 126. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)

CT IVE SUPPLY CURRENT vs. VC

32kHz EXTERNAL OSCILLATOR

100

150

200

250

300

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V

)

ICC (uA

)

25°C

85°C

DLE S UPPLY CURRENT vs. F REQ UENC

0.1 - 1.0 MHz

0.2

0.4

0.6

0.8

1.2

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz

)

ICC (mA

)

5.5V

4.5V

4.0V

3.3V

2.7V

1.8V

5.0V

280

ATmega162/V

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Figure 127. Idle Supply Curr ent vs. Frequency (1 - 20 MHz)

Figure 128. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)

DLE S UPPLY CURRENT vs. FREQ UENC

1 - 20 MHz

0 2 4 6 8 10 12 14 16 18 20

Frequency (MHz

)

ICC (mA

)

5.5V

4.5V

4.0V

3.3V

2.7V

1.8V

5.0V

IDLE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 8 MHz

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°C

281

ATmega162/V

2513H–AVR–04/06

Figure 129. Idle Supply Current vs. VCC (32 kHz External Oscillator)

Power-down Supply Current Figure 130. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)

IDLE SUPPLY CURRENT vs. VCC

32kHz EXTERNAL OSCILLATOR

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

POWER-DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

-40°C

282

ATmega162/V

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Figure 131. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)

Power-save Supply Current Figure 132. Power-save Supply Current vs. VCC (Watchdo g Tim e r Disa ble d )

POWER-DOWN SUPPLY CURRENT vs. V

WATCHDOG TIMER ENABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

-40°C

POWER-SAVE SUPPLY CURRENT vs. V

WATCHDOG TIMER DISABLED

1.522.533.544.555.5

VCC (V)

ICC (uA)

85°C

25°C

283

ATmega162/V

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Standby Supply Current Figure 133. Stan dby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer

Disabled)

Figure 134. Standby Supply Current vs. VCC (1 MHz Resonator, Watchdog Timer

Disabled)

STANDBY SUPPLY CURRENT vs. VCC

455 kHz RESONATOR, WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. VCC

1 MHz RESONATOR, WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

284

ATmega162/V

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Figure 135. Standby Supply Current vs. VCC (2 MHz Resonator, Watchdog Timer

Disabled)

Figure 136. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. VCC

2 MHz XTAL, WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. VCC

2 MHz XTAL, WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

285

ATmega162/V

2513H–AVR–04/06

Figure 137. Standby Supply Current vs. VCC (4 MHz Resonator, Watchdog Timer

Disabled)

Figure 138. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. VCC

4 MHz RESONATOR, WATCHDOG TIMER DISABLED

100

120

140

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. VCC

4 MHz XTAL, WATCHDOG TIMER DISABLED

100

120

140

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

286

ATmega162/V

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Figure 139. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog Timer

Disabled)

Figure 140. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. VCC

6 MHz RESONATOR, WATCHDOG TIMER DISABLED

100

120

140

160

180

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. VCC

6 MHz XTAL, WATCHDOG TIMER DISABLED

100

120

140

160

180

200

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

287

ATmega162/V

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Pin Pull-up Figure 141. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)

Figure 142. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 5V

100

120

140

160

012345

VIO (V)

IIO (uA)

85°C

25°C

-40°C

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 2.7V

0 0.5 1 1.5 2 2.5 3

VIO (V)

IIO (uA)

85°C 25°C

-40°C

288

ATmega162/V

2513H–AVR–04/06

Figure 143. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)

Figure 144. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOP (V)

IOP (uA)

85°C 25°C

-40°C

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 5V

100

120

012345

VRESET (V)

IRESET (uA)

-40°C

25°C

85°C

289

ATmega162/V

2513H–AVR–04/06

Figure 145. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)

Figure 146. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 2.7V

0 0.5 1 1.5 2 2.5 3

VRESET (V)

IRESET (uA)

-40°C

25°C

85°C

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VRESET (V)

IRESET (uA)

-40°C

25°C

85°C

290

ATmega162/V

2513H–AVR–04/06

Pin Driver Strength Figure 147. I/O Pin Source Curr en t vs. Ou tp ut Voltage (V CC = 5V)

Figure 148. I/O Pin Source Current vs. Outp ut Voltage (V CC = 2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 5V

012345

VOH (V)

IOH (mA)

85°C

25°C

-40°C

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 2.7V

0 0.5 1 1.5 2 2.5 3

VOH (V)

IOH (mA)

85°C

25°C

-40°C

291

ATmega162/V

2513H–AVR–04/06

Figure 149. I/O Pin Source Current vs. Outp ut Voltage (V CC = 1.8V)

Figure 150. I/O Pin Sink Current vs. Output Voltag e (V CC = 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOH (V)

IOH (mA)

85°C

25°C

-40°C

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

Vcc = 5V

0 0.5 1 1.5 2 2.5

VOL (V)

IOL (mA)

85°C

25°C

-40°C

292

ATmega162/V

2513H–AVR–04/06

Figure 151. I/O Pin Sink Current vs. Output Voltag e (V CC = 2.7V)

Figure 152. I/O Pin Sink Current vs. Output Voltag e (V CC = 1.8V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

Vcc = 2.7V

0 0.5 1 1.5 2 2.5

VOL (V)

IOL (mA)

85°C

25°C

-40°C

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOL (V)

IOL (mA)

85°C

25°C

-40°C

293

ATmega162/V

2513H–AVR–04/06

Pin Thresholds and

Hysteresis Figure 153. I/O Pin Input Th re sh o ld V olta g e vs. VCC (VIH, I/O Pin Read as “1”)

Figure 154. I/O Pin Input Threshold V olta g e vs. VCC (VIL, I/O Pin Read as “0”)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIH, I/O PIN READ AS '1'

0.5

1.5

2.5

1.522.533.544.555.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIL, I/O PIN READ AS '0'

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

294

ATmega162/V

2513H–AVR–04/06

Figure 155. I/O Pin Input Hysteresis vs. V CC

Figure 156. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”)

I/O PIN INPUT HYSTERESIS vs. VCC

0.1

0.2

0.3

0.4

0.5

0.6

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

RESET INPUT THRESHOLD VOLTAGE vs. VCC

VIH, RESET PIN READ AS '1'

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

295

ATmega162/V

2513H–AVR–04/06

Figure 157. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”)

Figure 158. Reset Input Pin Hysteresis vs. VCC

RESET INPUT THRESHOLD VOLTAGE vs. VCC

VIL, RESET PIN READ AS '0'

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

RESET INPUT PIN HYSTERESIS vs. VCC

0.1

0.2

0.3

0.4

0.5

0.6

0.7

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

296

ATmega162/V

2513H–AVR–04/06

BOD Thresholds and Analog

Comparator Offset Figure 159. BOD Thresholds vs. Temperature (BOD Level is 4.3V)

Figure 160. BOD Thresholds vs. Temperature (BOD Level is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 4.3V

4.1

4.2

4.3

4.4

4.5

4.6

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (˚C)

Threshold (V)

Rising V

Falling V

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 2.7V

2.4

2.5

2.6

2.7

2.8

2.9

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (˚C)

Threshold (V)

Rising VCC

Falling VCC

297

ATmega162/V

2513H–AVR–04/06

Figure 161. BOD Thresholds vs. Temperature (BOD Level is 2.3V)

Figure 162. BOD Thresholds vs. Temperature (BOD Level is 1.8V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 2.3V

2.1

2.2

2.3

2.4

2.5

2.6

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (˚C)

Threshold (V)

Rising VCC

Falling VCC

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 1.8V

1.5

1.6

1.7

1.8

1.9

2.1

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (˚C)

Threshold (V)

Rising VCC

Falling VCC

298

ATmega162/V

2513H–AVR–04/06

Figure 163. Bandgap Voltage vs. VCC

Figure 164. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V)

BANDGAP VOLTAGE vs. VCC

1.08

1.09

1.1

1.11

1.12

1.13

1.14

1.5 2 2.5 3 3.5 4 4.5 5 5.5

Vcc (V)

Bandgap Voltage (V)

85°C

25°C

-40°C

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

VCC = 5V

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Common Mode Voltage (V)

Comparator Offset Voltage (V)

85°C

25°C

-40°C

299

ATmega162/V

2513H–AVR–04/06

Figure 165. Analog Comparator Offset Voltage vs. Common Mode Voltage

(VCC =2.7V)

Internal Oscillator Speed Figure 166. Watchdog Oscillator Frequency vs. VCC

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

VCC = 2.7V

-0.001

0.001

0.002

0.003

0.004

0.005

0.006

0 0.5 1 1.5 2 2.5 3

Common Mode Voltage (V)

Comparator Offset Voltage (V)

85°C

25°C

-40°C

WATCHDOG OSCILLATOR FREQUENCY vs. V

1000

1050

1100

1150

1200

1250

1300

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

FRC (kHz)

85°C

25°C

-40°C

300

ATmega162/V

2513H–AVR–04/06

Figure 167. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

Figure 168. Calibrated 8 MHz RC Oscillator Frequency vs.VCC

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

7.5

7.6

7.7

7.8

7.9

8.1

8.2

8.3

8.4

-60 -40 -20 0 20 40 60 80 100

Ta (˚C)

FRC (MHz)

4.0V

1.8V

5.5V

2.7V

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC

6.5

7.5

8.5

9.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

FRC (MHz)

°C

-40

°C

301

ATmega162/V

2513H–AVR–04/06

Figure 169. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value

Current Consumption of

Peripheral Units Figure 170. Brownout Detector Current vs. VCC

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

0 163248648096112

OSCCAL VALUE

FRC (MHz)

BROWNOUT DETECTOR CURRENT vs. VCC

-5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

25°C

-40°C

85°C

302

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Figure 171. 32 kHz TOSC Current vs. VCC (Watchdog Timer Disabled)

Figure 172. Watchdog TImer Current vs. VCC

32kHz TOSC CURRENT vs. VCC

WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

WATCHDOG TIMER CURRENT vs. VCC

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

-40°C

303

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Figure 173. Analog Comparator Current vs. VCC

Figure 174. Programming Current vs. VCC

ANALOG COMPARATOR CURRENT vs. VCC

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

-40°C

PROGRAMMING CURRENT vs. Vcc

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°C

304

ATmega162/V

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Current Consumption in

Reset and Reset Pulsewidth Figure 175. Reset Supply Current vs. Frequen cy (0.1 - 1.0 MHz, Excluding Current

Through The Reset Pull-up)

Figure 176. Reset Supply Current vs. Frequency (1 - 20 MHz, Excluding Current

Through The Reset Pull-up)

RESET SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

0.5

1.5

2.5

3.5

4.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

ICC (mA)

5.5V

4.5V

4.0V

3.3V

2.7V

1.8V

5.0V

RESET SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

02468101214161820

Frequency (MHz)

ICC (mA)

5.5V

4.5V

4.0V

3.3V

2.7V

1.8V

5.0V

305

ATmega162/V

2513H–AVR–04/06

Figure 177. Reset Pulse Width vs. VCC

RESET PULSE WIDTH vs. VCC

500

1000

1500

2000

2500

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Pulsewidth (ns)

°C

-40

°C

306

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Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved – – – – – – – –

.. Reserved – – – – – – – –

(0x9E) Reserved – – – – – – – –

(0x9D) Reserved – – – – – – – –

(0x9C) Reserved – – – – – – – –

(0x9B) Reserved – – – – – – – –

(0x9A) Reserved – – – – – – – –

(0x99) Reserved – – – – – – – –

(0x98) Reserved – – – – – – – –

(0x97) Reserved – – – – – – – –

(0x96) Reserved – – – – – – – –

(0x95) Reserved – – – – – – – –

(0x94) Reserved – – – – – – – –

(0x93) Reserved – – – – – – – –

(0x92) Reserved – – – – – – – –

(0x91) Reserved – – – – – – – –

(0x90) Reserved – – – – – – – –

(0x8F) Reserved – – – – – – – –

(0x8E) Reserved – – – – – – – –

(0x8D) Reserved – – – – – – – –

(0x8C) Reserved – – – – – – – –

(0x8B) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 FOC3A FOC3B WGM31 WGM30 132

(0x8A) TCCR3B ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 129

(0x89) TCNT3H Timer/Counter3 – Counter Register High Byte 134

(0x88) TCNT3L Timer/Counter3 – Counter Register Low Byte 134

(0x87) OCR3AH Timer/Counter3 – Output Compare Register A High Byte 134

(0x86) OCR3A L Timer/Counter3 – Output Compare Register A Low Byte 134

(0x85) OCR3BH Timer/Counter3 – Output Compare Register B High Byte 134

(0x84) OCR3B L Timer/Counter3 – Output Compare Register B Low Byte 134

(0x83) Reserved – – – – – – – –

(0x82) Reserved – – – – – – – –

(0x81) ICR3H Timer/Counter3 – Input Capture Register High Byte 135

(0x80) ICR3L Timer/Counter3 – Input Capture Register Low Byte 135

(0x7F) Reserved – – – – – – – –

(0x7E) Reserved – – – – – – – –

(0x7D) ETIMSK –– TICIE3 OCIE3A OCIE3B TOIE3 – – 136

(0x7C) ETIFR –– ICF3 OCF3A OCF3B TOV3 – – 137

(0x7B) Reserved – – – – – – – –

(0x7A) Reserved – – – – – – – –

(0x79) Reserved – – – – – – – –

(0x78) Reserved – – – – – – – –

(0x77) Reserved – – – – – – – –

(0x76) Reserved – – – – – – – –

(0x75) Reserved – – – – – – – –

(0x74) Reserved – – – – – – – –

(0x73) Reserved – – – – – – – –

(0x72) Reserved – – – – – – – –

(0x71) Reserved – – – – – – – –

(0x70) Reserved – – – – – – – –

(0x6F) Reserved – – – – – – – –

(0x6E) Reserved – – – – – – – –

(0x6D) Reserved – – – – – – – –

(0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 89

(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 89

(0x6A) Reserved – – – – – – – –

(0x69) Reserved – – – – – – – –

(0x68) Reserved – – – – – – – –

(0x67) Reserved – – – – – – – –

(0x66) Reserved – – – – – – – –

(0x65) Reserved – – – – – – – –

(0x64) Reserved – – – – – – – –

(0x63) Reserved – – – – – – – –

(0x62) Reserved – – – – – – – –

(0x61) CLKPR CLKPCE ––– CLKPS3 CLKPS2 CLKPS1 CLKPS0 41

307

ATmega162/V

2513H–AVR–04/06

(0x60) Reserved – – – – – – – –

0x3F (0x5F) SREG I T H S V N Z C 10

0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 13

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13

0x3C(2)(0x5C)(2) UBRR1H URSEL1 UBRR1[11:8] 192

UCSR1C URSEL1 UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 191

0x3B (0x5B) GICR INT1 INT0 INT2 PCIE1 PCIE0 – IVSEL IVCE 62, 87

0x3A (0x5A) GIFR INTF1 INTF0 INTF2 PCIF1 PCIF0 – – – 88

0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 103, 135, 156

0x38 (0x58) TIFR TOV1 OCF1A OCF1B OCF2 ICF1 TOV2 TOV0 OCF0 104, 137, 157

0x37 (0x57) SPMCR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 223

0x36 (0x56) EMCUCR SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 30,44,86

0x35 (0x55) MCUCR SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 30,43,85

0x34 (0x54) MCUCSR JTD – SM2 JTRF WDRF BORF EXTRF PORF 43,52,209

0x33 (0x53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 101

0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) 103

0x31 (0x51) OCR0 Timer/Counter0 Output Compare Register 103

0x30 (0x50) SFIOR TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 32,71,106,158

0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 129

0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 132

0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 134

0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 134

0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 134

0x2A (0x4A ) OCR1AL Timer/Counter1 – Output Compare Register A Low B yte 134

0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte 134

0x28 (0x48) OCR1BL Timer/Counter1 – Output Compar e Register B L ow Byte 134

0x27 (0x47) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 150

0x26 (0x46) ASSR –––– AS2 TCN2UB OCR2UB TCR2UB 154

0x25 (0x45) ICR1H Timer/Counter1 – Input Capture Register High Byte 135

0x24 (0x44) ICR1L Timer/Counter1 – Input Capture Register Low Byte 135

0x23 (0x43) TCNT2 Timer/Counter2 (8 Bits) 153

0x22 (0x42) OCR2 Timer/Counter2 Output Compare Regis ter 153

0x21 (0x41) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 54

0x20(2) (0x40)(2) UBRR0H URSEL0 ––– UBRR0[11:8] 192

UCSR0C URSEL0 UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 191

0x1F (0x3F) EEARH – – – – – – –EEAR8 20

0x1E (0x3E) EEARL EEPROM Address Register Low Byte 20

0x1D (0x3D) EEDR EEPROM Data Register 21

0x1C (0x3C) EECR –––– EERIE EEMWE EEWE EERE 21

0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 83

0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 83

0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 83

0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 83

0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 83

0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 83

0x15 (0x35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 83

0x14 (0x34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 83

0x13 (0x33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 84

0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 84

0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 84

0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 84

0x0F (0x2F) SPDR SPI Data Register 166

0x0E (0x2E) SPSR SPIF WCOL – – – – –SPI2X 166

0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 164

0x0C (0x2C) UDR0 USART0 I/O Data Register 188

0x0B (0x2B) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 188

0x0A (0x2A) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 189

0x09 (0x29) UBRR0L USART0 Baud Rate Register Low Byte 192

0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 197

0x07 (0x27) PORTE – – – – – PORTE2 PORTE1 PORTE0 84

0x06 (0x26) DDRE – – – – – DDE2 DDE1 DDE0 84

0x05 (0x25) PINE – – – – – PINE2 PINE1 PINE0 84

0x04(1) (0x24)(1) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 39

OCDR On-chip Debug Register 204

0x03 (0x23) UDR1 USART1 I/O Data Register 188

0x02 (0x22) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 188

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

308

ATmega162/V

2513H–AVR–04/06

Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debug-

ger specific documentation for details on how to use the OCDR Register.

2. Refer to the USART description for details on how to access UBRRH and UCSRC.

3. For comp atibility with future devices, reser ved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O Register, writing a one back into any flag read as se t, thus clearing the flag. The CBI and SBI instructions

work with regi ste r s 0x00 to 0x1F only.

0x01 (0x21) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 189

0x00 (0x20) UBRR1L USART1 Baud Rate Register Low By te 192

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

309

ATmega162/V

2513H–AVR–04/06

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Sub tr act Imme diate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd , Rr Log ical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constan t Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2

FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← kNone3

RCALL k Relative Su broutine Cal l PC ← PC + k + 1 Non e 3

ICALL Indirect Call to (Z) PC ← ZNone3

CALL k Direct Subrout ine Call PC ← kNone4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Regis ter with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s ) = 1) then PC←PC+k + 1 N one 1/2

BRBC s, k Branch if Status Flag Clea red if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Clea red if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/ 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

310

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BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Registe r Word Rd+1:Rd ← Rr+1:R r None 1

LDI Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+ 1 No n e 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc . (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc . (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load P rogram Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Loa d P rogram Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7 ) ←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

Mnemonics Operands Description Operation Flags #Clocks

311

ATmega162/V

2513H–AVR–04/06

CLH Clear Half Carry Flag in SREG H ← 0 H 1

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1

BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

312

ATmega162/V

2513H–AVR–04/06

Ordering Information

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive).Also Halide free and fully Green.

3. See Figure 113 on page 268.

4. See Figure 114 on page 268.

Speed (MHz) Power Supply Ordering Code Package(1) Operation Range

8(3) 1.8 - 5.5V

ATmega162V-8AI

ATmega162V-8PI

ATmega162V-8MI

ATmega162V-8AU(2)

ATmega162V-8PU(2)

ATmega162V-8MU(2)

44A

40P6

44M1

44A

40P6

44M1

Industrial

(-40°C to 85°C)

16(4) 2.7 - 5.5V

ATmega162-16AI

ATmega162-16PI

ATmega162-16MI

ATmega162-16AU(2)

ATmega162-16PU(2)

ATmega162-16MU(2)

44A

40P6

44M1

44A

40P6

44M1

Industrial

(-40°C to 85°C)

Package Type

44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (QFN/MLF)

313

ATmega162/V

2513H–AVR–04/06

Packaging Information

44A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B

44A

10/5/2001

PIN 1 IDENTIFIER

0˚~7˚

PIN 1

A1 A2 A

eE1 E

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 11.75 12.00 12.25

D1 9.90 10.00 10.10 Note 2

E 11.75 12.00 12.25

E1 9.90 10.00 10.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

314

ATmega162/V

2513H–AVR–04/06

40P6

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual

Inline Package (PDIP) B

40P6

09/28/01

REF

SEATING PLANE

0º ~ 15º

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 4.826

A1 0.381 – –

D 52.070 – 52.578 Note 2

E 15.240 – 15.875

E1 13.462 – 13.970 Note 2

B 0.356 – 0.559

B1 1.041 – 1.651

L 3.048 – 3.556

C 0.203 – 0.381

eB 15.494 – 17.526

e 2.540 TYP

Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

315

ATmega162/V

2513H–AVR–04/06

44M1

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm,

44M1

3/18/05

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.80 0.90 1.00

A1 – 0.02 0.05

A3 0.25 REF

b 0.18 0.23 0.30

D 7.00 BSC

D2 5.00 5.20 5.40

E 7.00 BSC

E2 5.00 5.20 5.40

e 0.50 BSC

L 0.59 0.64 0.69

K 0.20 0.26 0.41

Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Marked Pin# 1 ID

Pin #1 Corner

SEATING PLANE

Pin #1

Triangle

Pin #1

Chamfer

(C 0.30)

Option A

Option B

Pin #1

Notch

(0.20 R)

Option C

5.20 mm Exposed Pad, Micro Lead Frame Package (MLF)

316

ATmega162/V

2513H–AVR–04/06

Erratas The revision letter in this section refers to the revision of the ATmega162 device.

ATmega162, all rev. There are no errata for this revision of ATmega16 2. However, a proposal for so lving

problems regarding the JTAG instruction IDCODE is presented below.

IDCODE masks data from TDI input

The public but optional JTAG instruction IDCODE is not implemented correctly

according to IEEE1149.1; a logic one is scanned into the shif t register instead of the

TDI input while shifting the Device ID Register. Hence, captured data from the pre-

ceding devices in the boundary scan chain are lost and replaced by all-ones, and

data to succeedin g de vice s ar e re pla ce d by all-o ne s du rin g Upda te -DR.

If ATmega162 is the only device in the scan chain, the pr oblem is not visible.

Problem Fix/ Workaround

Select the Device ID Register of the ATmega162 (Either by issuin g the IDCODE

instruction or by entering the Test-Logic-Reset state of the TAP controller) to read

out the contents of its Device ID Register and possibly data from succeeding

devices of the scan chain. Note that data to succeeding devices cannot be entered

during this scan, but data to preceding devices can. Issue the BYPASS instruction

to the ATmega162 to select its Bypass Register while reading the Device ID Reg is-

ters of preceding devices of the boundary scan chain. Never read data from

succeeding devic es in the boundary scan chain or uploa d data to the succeeding

devices while the Device ID Register is selected for the ATmega162. Note that the

IDCODE instruction is the default instruction selected by the Test- L og ic-R eset state

of the TAP-controller.

Alternative Problem Fix/ Wo rkaround

If the Device IDs of all devices in the boundary scan chain must be captured simul-

taneously (for instance if blind interrogation is used), the bo undary scan chain can

be connected in such way that the ATmega162 is the fist device in the chain.

Update-DR will still not work for the succeeding devices in the boundary scan chain

as long as IDCODE is present in the JTAG Instruction Register, but the Device ID

registered cannot be uploaded in any case.

317

ATmega162/V

2513H–AVR–04/06

Datasheet Revision

History Please note that the referring page numbers in this section are referred to this docu-

ment. The referring revision in this section are referring to the document revision.

Changes from Rev.

2513G-03/05 to Rev.

2513H-04/06

1. Added “Resources” on page 7.

2. Updated “Ca libra ted Internal RC Oscilla t or” on page 38 .

3. Updated note for Table 19 on page 51.

4. Updated “Serial Peripheral Interface – SPI” on page 159.

Changes from Rev.

2513F-09/03 to Rev.

2513G-03/05

1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame

Package QFN/MLF”.

2. Updated “Electrical Charact eristics” on page 266

3. Updated “Ordering Information” on page 312

Changes from Rev.

2513D-04/03 to Rev.

2513E-09/03

1. Removed “Preliminary” from the datasheet.

2. Added note on Figure 1 on page 2.

3. Renamed and updated “On-chip Debug System” to “JTAG Interface and

On-chip Debug System” on page 46.

4. Up d at e d Ta b l e 18 on pa ge 49 and Tabl e 19 on pa g e 51.

5. Updated “Test Access Port – TAP” on page 199 regarding JTAGEN.

6. Updated description for the JTD bit on page 209.

7. Added note on JTAGEN in Table 100 on page 235.

8. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical

Characteristics” on page 266.

9. Added a proposal for solving problems regarding the JTAG instruction

IDCODE in “Erratas” on page 316.

Changes from Rev.

2513C-09/02 to Rev.

2513D-04/03

1. Updated the “Ordering Information” on page 312 and “Packaging Informa-

tion” on page 313.

2. Updated “Features” on page 1.

3. Added characterization plots under “ATmega162 Typical Characteristics” on

page 277.

4. Added Chip Erase as a first step under “Programming the Flash” on page 262

and “Programming the EEPROM” on page 264.

5. Changed CAL7, the highest bit in the OSCCAL Register, to a reserved bit on

page 39 and in “Register Summary” on page 306.

318

ATmega162/V

2513H–AVR–04/06

6. Changed CPCE to CLKPCE on page 41.

7. Corrected code examples on page 56.

8. Corrected OCn waveforms in Figure 52 on page 121.

9. Various minor Timer1 corrections.

10. Added note under “Filling the Temporary Buffer (Page Loading)” on page 226

about writing to the EEPROM during an SPM Page Load.

11. Added section “EEPROM Write During Power-do wn Sleep Mode” on page 24.

12. Added information about PWM symmetry for Timer0 on page 99 and Timer2

on page 148.

13. Updated Table 18 on page 4 9, Table 20 on pag e 5 1, Table 36 on pag e 7 8, Tab le

83 on page 207, Table 110 on page 249, Table 113 on page 269, and Table 114

on page 270.

14. Added Figures for “Absolute Maximum Frequency as a function of VCC,

ATmega162” on page 268.

15. Updated Figure 29 on page 65, Figure 32 on page 69, and Figure 88 on page

212.

16. Removed Table 114, “External RC Oscillator, Typical Frequencies(1),” on

page 265.

17. Updated “Electrical Characteristics” on page 266.

Changes from Rev.

2513B-09/02 to Rev.

2513C-09/02

1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

Changes from Rev.

2513A-05/02 to Rev.

2513B-09/02

1. Added information for ATmega162U.

Information about ATmega162U included in “Features” on page 1, Table 19,

“BODLEVEL Fuse Coding,” on page 51, and “Ordering Information” on page 312.

ATmega162/V

2513H–AVR–04/06

Table of Contents Features................................................................................................ 1

Pin Configurations............................................................................... 2

Disclaimer.......... ................... .................... ... ................... .................... ... ............... 2

Overview............................................................................................... 3

Block Diagram ... ................... .................... ... ................... .... ................... ............... 3

ATmega161 and ATmega162 Compatibility................ ... .... ... ... ... ... .... ... ... ... .... ... .. 4

Pin Descriptions.................................................................................................... 5

Resources ............................................................................................ 7

About Code Examples......................................................................... 8

AVR CPU Core ..................................................................................... 9

Introductio n........ ... .................... ................... ................... .................................... .. 9

Architectural Overview.......................................................................................... 9

ALU – Arithmetic Logic Unit................................................................................ 10

Status Register..... ... .... ... ... .................... ................... ................................... ....... 10

General Purpose Register File ........................................................................... 12

Stack Pointer ...................................................................................................... 13

Instruction Exe cu tio n Tim in g . .... ................... ... .................... ................... ... .......... 14

Reset and Interrupt Handling.............................................................................. 14

AVR ATmega162 Memories .............................................................. 17

In-System Reprogrammable Flash Program Memory........................................ 17

SRAM Data Memor y.......... ... .... ... ... ................... .................................... ............. 18

EEPROM Data Memory...................................................................................... 20

I/O Memory........ ................... .................... ................... .................................... ... 25

External Memory Interface.................................................................................. 26

XMEM Register Description................................................................................ 30

System Clock and Clock Options .................................................... 35

Clock Systems and their Distribution.................................................................. 35

Clock Sources. ... ... ... .... ... ................... .................... ... ................... .................... ... 36

Default Clock Source.......................................................................................... 36

Crystal Oscillator ... ... .................... ... ... .................... ... ................... ... .... ................ 36

Low-frequency Crystal Oscillator........................................................................ 38

Calibrated Internal RC Oscillator........................................................................ 38

External Clock..................................................................................................... 40

Clock output buffer.............................................................................................. 40

Timer/Counter Oscillator.... ... .... ... ... ... .... ............................................................. 41

System Clock Prescaler...................................................................................... 41

Power Management and Sleep Modes............................................. 43

Idle Mode............................................................................................................ 44

ATmega162/V

2513H–AVR–04/06

Power-down Mode.............................................................................................. 44

Power-save Mod e........... ... ... .... ... ................... ... .................... ................... ... ....... 45

Standby Mod e. ... ... ... .... ................... .................................... ................... ............. 45

Extended Standby Mode .................................................................................... 45

Minimizing Power Consumption ......................................................................... 46

System Control and Reset................................................................ 48

Internal Voltage Reference................................................................................. 53

Watchdog Timer ................................................................................................. 53

Timed Sequences for Chan gin g th e Co nfigu ra tio n of the Wa tchdo g Timer ....... 57

Interrupts............................................................................................ 58

Interrupt Vec to rs in ATme g a162............................ ................... ... .................... ... 58

I/O-Ports.............................................................................................. 64

Introduction......................................................................................................... 64

Ports as General Digital I/O................................................................................ 65

Alternate Port Functions..................................................................................... 69

Register Descrip tio n for I/O -Po r ts.......... ... ... ... ... .... ................... ................... .... ... 83

External Interrupts............................................................................. 85

8-bit Timer/Counter0 with PWM........................................................ 90

Overview............................................................................................................. 90

Timer/Counter Clo ck Sou rc es............ .... ... ... ................... .... ................... ... ... ....... 91

Counter Unit........................................................................................................ 92

Output Compare Unit.......................................................................................... 92

Compare Match Output Unit............................................................................... 94

Modes of Operation............................................................................................ 95

Timer/Counter Timing Diagrams......................................................................... 99

8-bit Timer/Counter Register Description ......................................................... 101

Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers ...

105

16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)....... 107

Restriction in ATmega161 Compatibility Mode................................................. 107

Overview........................................................................................................... 107

Accessing 16-bit Registers............................................................................... 110

Timer/Counter Clo ck Sou rc es............ .... ... ... ................... .... ................... ... ... ..... 113

Counter Unit...................................................................................................... 113

Input Capture Unit............................................................................................. 114

Output Compare Units...................................................................................... 116

Compare Match Output Unit............................................................................. 118

Modes of Operation.......................................................................................... 119

Timer/Counter Timing Diagrams....................................................................... 127

iii

ATmega162/V

2513H–AVR–04/06

16-bit Timer/Counter Register Description ....................................................... 129

8-bit Timer/Counter2 with PWM and Asynchronous operation... 139

Overview........................................................................................................... 139

Timer/Counter Clo ck Sou rc es............ .... ... ... ................... .... ................... ... ... ..... 140

Counter Unit...................................................................................................... 141

Output Compare Unit........................................................................................ 141

Compare Match Output Unit............................................................................. 143

Modes of Operation.......................................................................................... 144

Timer/Counter Timing Diagrams....................................................................... 148

8-bit Timer/Counter Register Description ......................................................... 150

Asynchrono us op e ratio n of the Timer/Coun te r...... ... ... ................... .................. 154

Timer/Counter Pre scaler....... .... ... ... ................... .... ................... ... .................... . 158

Serial Peripheral Interface – SPI..................................................... 159

SS Pin Functionality . .... ... ... .................... ... ................... ................... .... .............. 164

Data Modes ...................................................................................................... 167

USART .............................................................................................. 168

Dual USART..................................................................................................... 168

Clock Generati on..... .... ... ... .................... ................... ... ................... .................. 170

Frame Forma ts......................... ................................... ................... .................. 173

USART Initialization.......................................................................................... 174

Data Transmission – The USART Transmitter................................................. 175

Data Reception – The USART Receiver .......................................................... 177

Asynchronous Data Reception......................................................................... 181

Multi-processor Communication Mode............................................................. 184

Accessing UBRRH/

UCSRC Register s.............. .................... ... ................... ................... .... .............. 186

USART Register Description............................................................................ 188

Examples of Baud Rate Setting........................................................................ 193

Analog Comparator ......................................................................... 197

JTAG Interface and On-chip Debug System ................................. 199

Features............................................................................................................ 199

Overview........................................................................................................... 199

Test Access Port – TAP.................................................................................... 199

TAP Controller.................................................................................................. 202

Using the Boundary-scan Chain....................................................................... 202

Using the On-chip Debug system..................................................................... 203

On-chip debu g spec ific JTAG ins tru ctions...... ... .... ... ................... .................... . 204

On-chip Debug Related Register in I/O Memory.............................................. 204

Using the JTAG Programming Capabilities...................................................... 204

Bibliography...................................................................................................... 205

ATmega162/V

2513H–AVR–04/06

IEEE 1149.1 (JTAG) Boundary-scan .............................................. 206

Features............................................................................................................ 206

System Overvie w............ ... ... .................... ................... ................... .................. 206

Data Registers.................................................................................................. 207

Boundary-scan Specific JTAG Instructions ...................................................... 208

Boundary-s ca n Cha in..... ... ... .... ... ................... .................... .............................. 210

ATmega162 Boundary-scan Order................................................................... 215

Boundary-scan Description Language Files..................................................... 218

Boot Loader Support – Read-While-Write Self-programming..... 219

Features............................................................................................................ 219

Application and Boot Loader Flash Sections.................................................... 219

Read-While-Write and No Read-While-Write Flash Sections........................... 219

Boot Loader Lock Bits....................................................................................... 221

Entering the Boot Lo ad e r P ro gram. ... .... ... ... ... .................... ................... ........... 223

Addressing the Flash During Self-programming............................................... 225

Self-programming the Flash ............................................................................. 226

Memory Programming..................................................................... 233

Program And Data M em o ry Lo ck Bits ............................ .... ... ................... ... ..... 233

Fuse Bits......... ... ... .................... ................... ... .................... ................... ... ........ 234

Signature Bytes ................................................................................................ 236

Calibration Byte ................................................................................................ 236

Parallel Programming Parameters, Pin Mapping, and Commands.................. 236

Parallel Programm in g..... ... ... .... ... ................... ... .................... ................... ... ..... 238

Serial Downloading........................................................................................... 247

SPI Serial Programming Pin Mapping.............................................................. 247

Programming via the JTAG Interface ............................................................... 252

Electrical Characteristics................................................................ 266

Absolute Maximu m Ra ting s*........... ... .... ... ... ................... .................... ... ........... 266

DC Characteristics............................................................................................ 266

External Clock Drive Waveforms...................................................................... 269

External Clock Drive......................................................................................... 269

SPI Timing Characteristics ............................................................................... 270

External Data Memory Timing.......................................................................... 272

ATmega162 Typical Characteristics .............................................. 277

Instruction Set Summary ................................................................ 309

Ordering Information....................................................................... 312

Packaging Information.................................................................... 313

ATmega162/V

2513H–AVR–04/06

44A ................................................................................................................... 313

40P6 ................................................................................................................. 314

44M1................................................................................................................. 315

Erratas .............................................................................................. 316

ATmega162, all rev........................................................................................... 316

Datasheet Revision History ............................................................ 317

Changes from Rev. 2513G-03/05 to Rev. 2513H-04/06................................... 317

Changes from Rev. 2513F-09/03 to Rev. 2513G-03/05................................... 317

Changes from Rev. 2513D-04/03 to Rev. 2513E-09/03................................... 317

Changes from Rev. 2513C-09/02 to Rev. 2513D-04/03................................... 317

Changes from Rev. 2513B-09/02 to Rev. 2513C-09/02................................... 318

Changes from Rev. 2513A-05/02 to Rev. 2513B-09/02................................... 318

Table of Contents ................................................................................. i

ATmega162/V

2513H–AVR–04/06

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