PIC18F4320-E/P - Microchip Technology

PIC18F2220/2320/4220/4320

The PIC18F2220/2320/4220/4320 Rev. C1 parts you

have received conform functionally to the Device Data

Sheet (DS39599G), except for the anomalies

described below. Any Data Sheet Clarification issues

related to the PIC18F2220/2320/4220/4320 will be

reported in a separate D ata Sheet errat a. Please chec k

the Microchip web site for any existing issues.

The following silicon errata apply only to

PIC18F2220/2320/4220/4320 devices with these

Device/Revision IDs:

All of the issues listed here will be addressed in future

revisions of the PIC18F2220/2320/4220/4320 silicon.

1. Module: Core (DAW Instruction)

The DAW instruction may improperly clear the

Carry bit (STATUS<0>) when executed.

Work around

Test the Carry bit state before executing the DAW

instruction. If the Carry bit is set, increment the

next higher byte to be added, using an instruction

such as INCFSZ (this instruction does not affect

any Status flags and will not overflow a BCD

nibble). After the DAW instruction has been

executed, process the Carry bit normally (see

Example 1).

EXAMPLE 1: PROCESSING THE CARRY

BIT DURING BCD AD DITIONS

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F2220 0000 0101 100 0 0110

PIC18F2320 0000 0101 000 0 0110

PIC18F4220 0000 0101 101 0 0110

PIC18F4320 0000 0101 001 0 0110

The Devic e IDs (DEVID1 an d DEVID2 ) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in binary in the

format “DEVID2 DEVID1”.

MOVLW 0x80 ; .80 (BCD)

ADDLW 0x80 ; .80 (BCD)

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

DAW

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

This is repeated for each DAW instruction.

PIC18F2220/2320/4220/4320 Rev. C1 Silicon Errata

PIC18F2220/2320/4220/4320

2. Module: MSSP (All I2C™ and SPI Modes)

The Buf fer Full flag bit (BF) of th e SSPSTAT regi s-

ter (SSPSTAT<0>) may be inadvertently cleared,

even when the SSPBUF register has not been

read. This will occur only when the following two

conditions occur simultaneously:

• The four Least Significant bits of the BSR

and

• Any instruction that contains C9h in its 8 Least

Significant bits (i.e., register file addresses,

literal data, address offsets, etc.) is executed.

Work around

Identified work arounds will involve setting the

contents of BSR<3:0> to some value other than

0Fh.

In addition to those proposed below , other solutions

may exist.

1. When developing or modifying code, keep

these guidelines in mind:

• Assign 12-bit addresses to all variables.

This allows the assembler to know when

Access Bank in g can be use d.

• Do not set the BSR to point to Bank 15

(BSR = 0Fh).

• Allow the assembler to manipulate the

Access bit present in most instructions.

Accessi ng the SFRs in Bank 15 will be do ne

through the Access Bank. Continue to use

the BSR to select all GPR Banks.

2. If accessing a part of Bank 15 is required and

the use of Access Banking is not possible,

consider using indirect addressing.

3. If pointing the BSR to Bank 15 is unavoidable,

review the absolute file listing. Verify that no

instructions contain C9h in the 8 Least Signifi-

cant bits while the BSR points to Bank 15

(BSR = 0Fh).

Date Codes that pertain to this issue:

All engineering and production devices.

3. Module: MSSP (SPI, Slave Mode)

In its current implementation, the SS (Slave

Select) control signal generated by an external

master processor may not be successfully recog-

nized by the PIC® microcontroller operating in

Slave Select mode (SSPM3:SSPM0 = 0100). In

particular, it has been observed that faster transi-

tions (those with shorter fall times) are more likely

to be missed than slower transitions.

Work around

Insert a series resistor between the source of the

SS signal and the corresponding SS input line of

the microcontroller. The value of the resistor is

dependent on both the application system’s

characteristics and process variations between

microcontrollers. Experimentation and thorough

testing is encou rag ed.

This is a recommended solution; others may exist.

Date Codes that pertain to this issue:

All engineering and production devices.

PIC18F2220/2320/4220/4320

4. Module: Oscillator

The 32 kHz internal oscillator, INTRC, will be held

in Reset if either of the following is enabled:

• Pow er-up Timer

• High-Speed Crystal/Resonator with PLL

Enabled (HSPLL) Oscillator mode

Without the INTRC oscillator running, the Po wer-up

Timer and Phase Locked Loop (PLL) timer will not

expire and the PIC18F2220/2320/4220/4320

device will no t exit Reset. This issue does no t affect

the Watchdog Timer or any other mode.

The provided work arounds require only two

modifications to the Configuration Word values.

No add itiona l chan ges to t he appl icati on hardwa re

or software are necessary, except as noted below.

Work around: Power-up Timer

Disable the Power-up Timer by programming

PWRTEN (CONFIG2L< 0> ) to ‘1’. This results in a

shorter time before the microcontroller begins to

exe c ute code after power up or ex iting from Sleep

mode or from Brown-out Reset (if enabled).

If a power-up delay is needed to ensure a stable

VDD, consider using the Brown-out Reset (BOR)

feature. The BOR keeps the device in Reset until

the specified VDD has been achieve d.

This work around is available by programming the

BOR bit to ‘1’ and selecting BOR voltage bits with

BORV<1:0> bits in the CONFIG2L Configuration

Word.

If BOR i s not enabl ed and add itional s tart-up d elay

is needed, consider implementing an external

system supervisor to keep the microcontroller in

Reset until the VDD has stabilized. Alternately,

consid er use of an eq uivalent PIC18 F4321 devic e.

Work around: HSPLL Oscillator Mode

Two work arounds are available through the

Configuration bits. Enabling either of the following

features permits the HSPLL mode to work

successfully:

• Two-Speed Start-up

• Fail-Safe Clock Monitor

Both options permit the microcontroller to start

from the 32 kHz INTRC after power-up, BOR, or

wake-up from Sleep mode. The options also

permit code to execute while PLL is waiting to lo ck.

The PLL lock time typically is 2 ms which results in

approxi mately 16 instru ction execu tions before th e

switch to the HSPLL clock occurs. If typical initial-

iza tion co de is p erfo rmed aft er a Power- on Rese t

or Brown-out Reset, the impact of this work around

should be neg ligible.

If Sleep mode is u sed , b oth work a r oun ds res ul t i n

code execution during PLL lock time. A software

delay may be neede d to av oid exe cuting time -cri t-

ical code after wake-up. The OSTS

(OSCCON<3>) bit will set to indicate when the

HSPLL is ready and time-critical code can be

executed.

The Two-Speed Start-up and Fail-Safe Clock

Monitor work arounds switch the system clock

source from INTRC to HSPLL mode after a PLL

lock occurs. This is handled automatically by the

microcontroller and requires no additional soft-

ware or special monitoring. For more information,

see Section 2.7 “Clock Sources and Oscillator

Switching” in the “PIC18F2220/2320/4220/4320

Data Sheet” (DS39599).

Date Codes that pertain to this issue:

Engineering and production devices with a date

code of 0813 or later may be affected.

PIC18F2220/2320/4220/4320

REVISION HISTORY

Rev A Document (9/2008)

First revision of this document. Includes silicon issues

1 (Core – DAW Instruction), 2 (MSSP – All I2C™ and

SPI modes), 3 (MSSP – SPI, Slave Mode) and

4 (INTRC Oscillator).

Rev B Document (1/2009)

Changed title of silicon issue 4 (Oscillator).

Information contained in this publication regarding device

applications a nd t he lik e is provided only for yo ur conve nience

and may be superseded by updates . It is y our responsibilit y to

ensure that your application meets with your specifications.

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICm icro,

PICSTA RT, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MX LAB ,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Prog ra m ming, IC SP, ICEPIC , Mi n d i , MiW i , MPA SM, MPL AB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCU s and dsPIC® DSCs, KEELOQ® code hopp ing

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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