500 MHz to 1700 MHz Balanced Mixer,
LO Buffer and RF Balun
Data Sheet
ADL5367
Rev. B Document Feedback
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FEATURES
RF frequency range of 500 MHz to 1700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion loss: 7.7 dB
SSB noise figure of 8.3 dB
SSB noise figure with 5 dBm blocker of 21 dB
Input IP3 of 34 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle 5 mm × 5 mm, 20-lead LFCSP
1500 V HBM/500 V FICDM ESD performance
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
GENERAL DESCRIPTION
The ADL5367 uses a highly linear, doubly balanced passive
mixer core along with integrated RF and LO balancing circuitry
to allow for single-ended operation. The ADL5367 incorporates
an RF balun, allowing optimal performance over a 500 MHz to
1700 MHz RF input frequency range. Performance is optimized for
RF frequencies from 500 MHz to 1200 MHz using a high-side LO
and for RF frequencies from 900 MHz to 1700 MHz using a
low-side LO. The balanced passive mixer arrangement provides
good LO to RF leakage, typically better than −35 dBm, and
excellent intermodulation performance. The balanced mixer
core also provides extremely high input linearity, allowing the
device to be used in demanding cellular applications where in-
band blocking signals may otherwise result in the degradation
of dynamic performance. A high linearity IF buffer amplifier
follows the passive mixer core to yield a typical power conversion
loss of 7.7 dB and can be used with a wide range of output
impedances.
FUNCTIONAL BLOCK DIAGRAM
2
3
1
20 19 18 17 16
6 7 8 9 10
4
5
14
13
15
12
BIAS
GENERATOR
VPMX
RFIN
RFCT
COMM
COMM
LOI2
VPSW
VGS1
VGS0
LOI1
VCMI IFOPIFON PWDN COMM
VLO3 LGM3 VLO2 LOSW NC
ADL5367
NC = NO CONNECT
11
08083-001
Figure 1.
The ADL5367 provides two switched LO paths that can be
used in TDD applications where it is desirable to rapidly switch
between two local oscillators. LO current can be externally set
using a resistor to minimize dc current commensurate with the
desired level of performance. For low voltage applications, the
ADL5367 is capable of operation at voltages down to 3.3 V with
substantially reduced current. Under low voltage operation, an
additional logic pin is provided to power down (<200 µA) the
circuit when desired.
The ADL5367 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency (MHz)
Single
Mixer
Single Mixer
and IF Amp
Dual Mixer
and IF Amp
500 to 1700 ADL5367 ADL5357 ADL5358
1200 to 2500
ADL5365
ADL5355
ADL5356
2300 to 2900 ADL5363 ADL5353 ADL5354
ADL5367* PRODUCT PAGE QUICK LINKS
Last Content Update: 11/29/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
•ADL5367 Evaluation Board
DOCUMENTATION
Data Sheet
•ADL5367: 500 MHz to 1700 MHz Balanced Mixer, LO Buffer
and RF Balun Data Sheet
TOOLS AND SIMULATIONS
• ADIsimPLL™
•ADIsimRF
REFERENCE MATERIALS
Product Selection Guide
•RF Source Booklet
•RF, Microwave, and Millimeter Wave IC Selection Guide
2017
Technical Articles
•The Differential-signal Advantage for Communications
System Design
DESIGN RESOURCES
•ADL5367 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
View all ADL5367 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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ADL5367 Data Sheet
Rev. B | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Performance ........................................................................... 4
3.3 V Performance ........................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance ........................................................................... 7
3.3 V Performance ...................................................................... 14
Upconversion .............................................................................. 15
Spur Tables .................................................................................. 16
Circuit Description......................................................................... 17
RF Subsystem .............................................................................. 17
LO Subsystem ............................................................................. 17
Applications Information .............................................................. 19
Basic Connections ...................................................................... 19
IF Port .......................................................................................... 19
Mixer VGS Control DAC .......................................................... 19
Evaluation Board ............................................................................ 20
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
3/16—Rev. B to Rev. C
Added Thermal Resistance Section and Junction to
Board Thermal Impedance Section ............................................... 5
Changes to Figure 2 .......................................................................... 6
Change to Evaluation Board Section and Figure 49 .................. 20
2/15—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 1
Deleted Figure 37 and Figure 39 ................................................... 13
Deleted Bias Resistor Selection Section ....................................... 19
Changes to Figure 49 ...................................................................... 20
Changes to Table 7 .......................................................................... 21
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
10/09—Revision 0: Initial Version
Data Sheet ADL5367
Rev. B | Page 3 of 24
SPECIFICATIONS
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RF INPUT INTERFACE
Return Loss Tunable to >20 dB over a limited bandwidth 14 dB
Input Impedance 50 Ω
RF Frequency Range 500 1700 MHz
OUTPUT INTERFACE
Output Impedance Differential impedance, f = 200 MHz 34||1.9 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V
LO INTERFACE
LO Power −6 0 +10 dBm
Return Loss 12.6 dB
Input Impedance 50 Ω
LO Frequency Range 730 1670 MHz
POWER-DOWN (PWDN) INTERFACE 2
PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of the final level 160 ns
Device disabled, supply current < 5 mA 220 ns
PWDN Input Bias Current Device enabled 0.0 μA
Device disabled 70 μA
1 Apply the supply voltage from the external circuit through the choke inductors.
2 PWDN function is intended for use with VS ≤ 3.6 V only.
ADL5367 Data Sheet
Rev. B | Page 4 of 24
5 V PERFORMANCE
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Loss Including 1:1 IF port transformer and printed circuit board (PCB) loss 6.5 7.7 8.5 dB
Voltage Conversion Loss ZSOURCE = 50 Ω, differential ZLOAD = 50 Ω differential 1.4 dB
SSB Noise Figure 8.3 dB
SSB Noise Figure Under Blocking 5 dBm blocker present ±10 MHz from wanted RF input, LO source
filtered
21 dB
Input Third-Order Intercept (IIP3) fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 1103 MHz, each RF tone
at 0 dBm
28 34 dBm
Input Second-Order Intercept (IIP2) fRF1 = 950 MHz, fRF2 = 900 MHz, fLO = 1103 MHz, each RF tone
at 0 dBm
80 dBm
Input 1 dB Compression Point (IP1dB)1 Exceeding 20 dBm RF power results in damage to the device 25 dBm
LO to IF Leakage Unfiltered IF output −15 dBm
LO to RF Leakage −40 dBm
RF to IF Isolation −47 dBc
IF/2 Spurious 0 dBm input power −75 dBc
IF/3 Spurious 0 dBm input power −72 dBc
POWER SUPPLY
Positive Supply Voltage 4.5 5 5.5 V
Total Quiescent Current VS = 5 V 97 mA
1 Exceeding 20 dBm RF power results in damage to the device.
3.3 V PERFORMANCE
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Loss Including 4:1 IF port transformer and PCB loss 7.3 dB
Voltage Conversion Loss ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential 1 dB
SSB Noise Figure 8.1 dB
Input Third-Order Intercept (IIP3) fRF1 = 1949.5 MHz, fRF2 = 1950.5 MHz, fLO = 1750 MHz,
each RF tone at −10 dBm
28.5 dBm
Input Second-Order Intercept (IIP2) fRF1 = 1950 MHz, fRF2 = 1900 MHz, fLO = 1750 MHz,
each RF tone at −10 dBm
75 dBm
POWER INTERFACE
Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 56 mA
Power-Down Current Device disabled 150 μA
Data Sheet ADL5367
Rev. B | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage, VS 5.5 V
RF Input Level 20 dBm
LO Input Level 13 dBm
IFOP, IFON Bias Voltage 6.0 V
VGS0, VGS1, LOSW, PWDN 5.5 V
Internal Power Dissipation 1.2 W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) 260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is thermal resistance, junction to ambient (°C/W), and θJB is
thermal impedance, junction to board (°C/W).
Table 6. Thermal Resistance
Package Type θJA1 θ
JB1 Unit
20-Lead LFCSP 25 14.74 °C/W
1 See the JEDEC standard, JESD51-2, for information on optimizing thermal
impedance (PCB with 3 × 3 vias).
Junction to Board Thermal Impedance
The junction to board thermal impedance (θJB) is the thermal
impedance from the die to or near the component lead of the
ADL5367. For the ADL5367, θJB is determined experimentally
to 14.74°C/W with the device mounted on a 4-layer circuit
board with two layers as ground planes in a configuration
similar to the ADL5367-EVALZ evaluation board. Board size
and complexity (number of layers) affect θJB; more layers tend to
reduce the thermal impedance slightly.
If the board temperature is known, use the junction to board
thermal impedance to calculate die temperature (also known
as junction temperature) to ensure it does not exceed the specified
limit of 150°C. For example if the board temperature is 85°C,
the die temperature is given by the equation
Tj = TB + (PDISS × θJB)
where Tj is the junction temperature.
TB is the board temperature measured at or near the
component lead.
PDISS is the power dissipated from the device.
The typical worst case power dissipation for the ADL5367 is
605 mW (5.5 V × 110 mA). Therefore Tj is
Tj = 85°C + (0.605 W × 14.74°C/W) = 93.91°C
ESD CAUTION
ADL5367 Data Sheet
Rev. B | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
08083-002
NOTES
1. NC = NO CO NNECT .
2. EXPOSED PAD. MUST BE SOLDERED
TO GROUND.
VPMX
RFIN
RFCT
COMM
COMM
VGS1
VPSW
LOI2
VGS0
LOI1
VLO3
LGM3
VLO2
NC
LOSW IFON
IFOP
VCMI
PWDN
COMM
14
13
12
1
3
4
15
11
2
5
7
6
8
9
10
19
20
18
17
16
ADL5367
TOP VIEW
(Not t o S c ale)
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 VPMX Positive Supply Voltage for IF Amplifier.
2 RFIN RF Input. This pin must be ac-coupled.
3 RFCT RF Balun Center Tap (AC Ground).
4, 5, 16 COMM Device Common (DC Ground).
6, 8 VLO3, VLO2 Positive Supply Voltages for LO Amplifier.
7 LGM3 LO Amplifier Bias Control.
9 LOSW LO Switch. LOI1 selected for 0 V, or LOI2 selected for 3 V.
10 NC No Connect.
11, 15 LOI1, LOI2 LO Inputs. This pin must be ac-coupled.
12, 13 VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting.
14 VPSW Positive Supply Voltage for LO Switch.
17 PWDN Power Down. Connect this pin to ground for normal operation or connect this pin to 3.0 V for disable mode.
18, 19 IFON, IFOP Differential IF Outputs.
20 VCMI No Connect. This pin can be grounded.
EPAD (EP) Exposed pad must be soldered to ground.
Data Sheet ADL5367
Rev. B | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, I S = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
80
85
90
95
100
105
110
700 750 800 850 900 950 1000 1050 1100 1150 1200
SUPPLY CURRENT ( mA)
RF FREQ UE NC Y (MHz)
08083-017
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 3. Supply Current vs. RF Frequency
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
700 750 800 850 900 950 1000 1050 1100 1150 1200
CONVERSION LOSS (dB)
RF FREQ UE NC Y (MHz)
TA = +85°C
TA = –40°C
TA = +25°C
08083-035
Figure 4. Power Conversion Loss vs. RF Frequency
26
28
30
32
34
36
38
40
700 750 800 850 900 950 1000 1050 1100 1150 1200
INPUT I P 3 ( dBm)
RF FREQ UE NC Y (MHz)
08083-028
TA = +85°C
TA = –40°C
TA = +25°C
Figure 5. Input IP3 vs. RF Frequency
40
50
60
70
80
90
100
700 750 800 850 900 950 1000 1050 1100 1150 1200
INPUT I P 2 ( dBm)
RF FREQ UE NC Y (MHz)
08083-023
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 6. Input IP2 vs. RF Frequency
700 750 800 850 900 950 1000 1050 1100 1150 1200
SSB NOISE FIGURE (dB)
RF FREQ UE NCY ( M Hz )
08083-011
5
6
7
8
9
10
11
12
T
A
= +25º C
T
A
= +85º C
T
A
= –40ºC
Figure 7. SSB Noise Figure vs. RF Frequency
ADL5367 Data Sheet
Rev. B | Page 8 of 24
VS = 5 V, I S = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
80
85
90
95
100
105
110
SUPPLY CURRENT ( mA)
TEMPERATURE (°C)
V
POS
= 4.75V
V
POS
= 5V
V
POS
= 5.25V
08083-019
–40 –20 020 40 60 80
Figure 8. Supply Current vs. Temperature
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
–40 –20 020 40 60 80
CONVERSION LOSS (dB)
TEMPERATURE (°C)
08083-038
VPOS = 4.75V
VPOS = 5V
VPOS = 5.25V
Figure 9. Power Conversion Loss vs. Temperature
26
28
30
32
34
36
38
40
–40 –20 020 40 60 80
INPUT I P 3 ( dBm)
TEMPERATURE (°C)
V
POS
= 5.25V
V
POS
= 4.75V
V
POS
= 5V
08083-030
Figure 10. Input IP3 vs. Temperature
70
72
74
76
78
80
82
84
86
–40 –20 020 40 60 80
INPUT I P 2 ( dBm)
TEMPERATURE (°C)
V
POS
= 4.75V
V
POS
= 5V
V
POS
= 5.25V
08083-025
Figure 11. Input IP2 vs. Temperature
12
6
7
8
9
10
11
5
–40 –20 020 40 60 80
SSB NOISE FIGURE (dB)
TEMPERATURE (ºC)
08083-012
V
POS
= 5V
V
POS
= 4.75V
V
POS
= 5.25V
Figure 12. SSB Noise Figure vs. Temperature
Data Sheet ADL5367
Rev. B | Page 9 of 24
VS = 5 V, I S = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
80
85
90
95
100
105
110
30 80 130 180 230 280 330 380 430
SUPPLY CURRENT ( mA)
IF FREQUENCY (MHz)
08083-016
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 13. Supply Current vs. IF Frequency
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
30 80 130 180 230 280 330 380 430
CONVERSION LOSS (dB)
IF FREQUENCY (MHz)
08083-033
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 14. Power Conversion Loss vs. IF Frequency
26
28
30
32
34
36
38
40
30 80 130 180 230 280 330 380 430
INPUT I P 3 ( dBm)
IF FREQUENCY (MHz)
08083-026
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 15. Input IP3 vs. IF Frequency
50
55
60
65
70
75
80
85
30 80 130 180 230 280 330 380 430
INPUT I P 2 ( dBm)
IF FREQUENCY (MHz)
T
A
= +25°C
T
A
= +85°C
T
A
= –40°C
08083-021
Figure 16. Input IP2 vs. IF Frequency
12
6
7
8
9
10
11
530 80 130 180 230 280 330 380 430
SSB NOISE FIGURE (dB)
IF FREQ UENCY (MHz)
08083-010
Figure 17. SSB Noise Figure vs. IF Frequency
ADL5367 Data Sheet
Rev. B | Page 10 of 24
VS = 5 V, I S = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
–6 –4 –2 02 4 6 810
CONVERSION LOSS (dB)
LO POWER (dBm)
TA = +85°C
TA = –40°C
08083-034
TA = +25°C
Figure 18. Power Conversion Loss vs. LO Power
26
28
30
32
34
36
38
40
–6 –4 –2 0246810
INPUT I P 3 ( dBm)
LO POWER (dBm)
08083-027
TA = +85°C
TA = –40°C TA = +25°C
Figure 19. Input IP3 vs. LO Power
50
55
60
65
70
75
80
85
90
–6 –4 –2 024 6 810
INPUT I P 2 ( dBm)
LO POWER (dBm)
TA = +25°C
TA = +85°C
TA = –40°C
08083-022
Figure 20. Input IP2 vs. LO Power
–100
–90
–80
–70
–60
–50
–40
700 750 800 850 900 950 1000 1050 1100 1150
1200
IF /2 SP URIOUS ( dBc)
RF FREQ UE NC Y (MHz)
T
A
= +25°C
T
A
= +85°C
T
A
= –40°C
08083-020
Figure 21. IF/2 Spurious vs. RF Frequency
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
700 750 800 850 900 950 1000 1050 1100 1150 1200
IF /3 SP URIOUS ( dBc)
RF FREQ UE NC Y (MHz)
T
A
= +85°C
T
A
= –40°C
08083-040
T
A
= +25°C
Figure 22. IF/3 Spurious vs. RF Frequency
Data Sheet ADL5367
Rev. B | Page 11 of 24
VS = 5 V, I S = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
100
80
60
40
20
0
PERCENT (%)
7.2 7.8 8.0
7.6
CONVERSION LOSS (dB)
7.4 8.2
08083-068
MEAN: 7.7
STANDARD DE V IAT ION: 0.18
Figure 23. Conversion Loss Distribution
100
80
60
40
20
0
PERCENT (%)
31 37 393533 INPUT I P 3 ( dBm)
08083-067
MEAN: 34.67
STANDARD DE V IAT ION: 0.19
Figure 24. Input IP3 Distribution
08083-063
0
10
20
30
40
50
60
70
80
90
100
7.8 8.0 8.2 8.4
NOISE FIGURE (dB)
8.6 8.8 9.0
PERCENTAG E ( %)
MEAN: 8.3
STANDARD DE V IAT ION: 0.05
Figure 25. SSB Noise Figure Distribution
CAPACITANCE (pF )
RESISTANCE (
Ω)
IF FREQUENCY (MHz)
30 80 130 180 230 280 330 380 430
08083-069
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
36.5
36.0
35.5
35.0
34.5
34.0
33.5
33.0
32.5
32.0
31.5
31.0
30.5
Figure 26. IF Port Return Loss
0
20
15
10
5
25
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF RETURN L OSS ( dB)
RF FREQ UE NCY ( M Hz )
08083-013
Figure 27. RF Port Return Loss, Fixed IF
08083-007
20
18
16
14
12
10
8
6
4
2
0
900 950 1000 1050
1100 1150 1200 1250 1300 1350 1400
LO RETURN LOSS (dB)
LO FREQUENCY (MHz)
SELECTED
UNSELECTED
Figure 28. LO Return Loss, Selected and Unselected
ADL5367 Data Sheet
Rev. B | Page 12 of 24
VS = 5 V, I S = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
08083-059
T
A
= –40°C
40
45
50
55
60
65
70
700 750 800 850 900 950 1000 1050 1100 1150 1200
LO SWITCH ISOLATION (dB)
RF FREQ UE NC Y (MHz)
T
A
= +85°C
T
A
= +25°C
Figure 29. LO Switch Isolation vs. RF Frequency
–60
–58
–56
–54
–52
–50
–48
–46
–44
–42
–40
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
RF-TO-IF ISOLATION (dBc)
RF FREQ UE NC Y (MHz)
08083-039
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 30. RF to IF Isolation vs. RF Frequency
–30
–25
–20
–15
–10
–5
0
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
LO-TO-IF LEAKAGE (dBm)
LO FREQUENCY (MHz)
08083-031
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 31. LO to IF Leakage vs. LO Frequency
–50
–45
–40
–35
–30
–25
–20
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
LO-TO-RF LEAKAGE (dBm)
LO FREQUENCY (MHz)
08083-032
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 32. LO to RF Leakage vs. LO Frequency
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
900 950 1000
1050 1100 1150 1200 1250 1300 1350 1400
2LO LEAKAGE (dBm)
LO FREQUENCY (MHz)
2LO TO RF
2LO TO IF
08083-014
Figure 33. 2LO Leakage vs. LO Frequency
–70
–60
–50
–40
–30
–20
–10
0
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
3LO LEAKAGE (dBm)
LO FREUQENCY (MHz)
3LO TO RF
3LO TO IF
08083-015
Figure 34. 3LO Leakage vs. LO Frequency
Data Sheet ADL5367
Rev. B | Page 13 of 24
VS = 5 V, I S = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
08083-058
NOISE FIGURE
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
700 750 800 850 900 950 1000 1050 1100 1150 1200
SSB NOISE FIGURE (dB)
CONVERSION LOSS (dB)
RF FREQ UE NC Y (MHz)
VGS = 0, 0
VGS = 0, 1
VGS = 1, 0
VGS = 1, 1
CONVERSION LOSS
Figure 35. Power Conversion Loss and SSB Noise Figure vs. RF Frequency
08083-062
20
22
24
26
28
30
32
34
36
38
40
700 750 800 850 900 950 1000 1050 1100 1150 1200
INPUT I P 3 ( dBm)
RF FREQ UE NC Y (MHz)
VGS = 0, 0
VGS = 0, 1
VGS = 1, 0
VGS = 1, 1
Figure 36. Input IP3 vs. RF Frequency
30
5
10
15
20
25
0
–30 –25 –20 –15 –10 –5 0510
NOISE FIGURE (dB)
BLO CKE R P OW E R ( dBm)
08083-003
Figure 37. SSB Noise Figure vs.10 MHz Offset Blocker Level
ADL5367 Data Sheet
Rev. B | Page 14 of 24
3.3 V PERFORMANCE
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
50
52
54
56
58
60
62
64
700 750 800 850 900 950 1000 1050 1100 1150 1200
SUPPLY CURRENT ( mA)
RF FREQ UE NC Y (MHz)
08083-018
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 38. Supply Current vs. RF Frequency at 3.3 V
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
700 750 800 850 900 950 1000 1050 1100 1150 1200
CONVERSION LOSS (dB)
RF FREQ UE NC Y (MHz)
08083-036
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 39. Power Conversion Loss vs. RF Frequency at 3.3 V
20
22
24
26
28
30
32
34
700 750 800 850 900 950 1000 1050 1100 1150 1200
INPUT I P 3 ( dBm)
RF FREQ UE NC Y (MHz)
08083-029
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 40. Input IP3 vs. RF Frequency at 3.3 V
40
45
50
55
60
65
70
75
80
85
700 750 800 850 900 950 1000 1050 1100 1150 1200
INPUT I P 2 ( dBm)
RF FREQ UE NC Y (MHz)
08083-024
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 41. Input IP2 vs. RF Frequency at 3.3 V
08083-064
T
A
= –40°C
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
700 750 800 850 900 950 1000 1050 1100 1150 1200
NOISE FIGURE (dB)
RF FREQ UE NC Y (MHz)
T
A
= +85°C
T
A
= +25°C
Figure 42. SSB Noise Figure vs. RF Frequency at 3.3 V
Data Sheet ADL5367
Rev. B | Page 15 of 24
UPCONVERSION
TA = 25°C, fIF = 153 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted.
08083-065
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
700 750 800 850 900 950 1000 1050 1100 1150 1200
CONVERSION LOSS (dB)
RF FREQ UE NC Y (MHz)
T
A
= +85°C
T
A
= –40°C T
A
= +25°C
Figure 43. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion
08083-060
20
22
24
26
28
30
32
34
700 750 800 850 900 950 1000 1050 1100 1150 1200
INPUT I P 3 ( dBm)
RF FREQ UE NC Y (MHz)
T
A
= +85°C
T
A
= –40°C T
A
= +25°C
Figure 44. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion
08083-066
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
700 750 800 850 900 950 1000 1050 1100 1150 1200
CONVERSION LOSS (dB)
RF FREQ UE NC Y (MHz)
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 45. Power Conversion Loss vs. RF Frequency at 3.3 V, Upconversion
08083-061
20
22
24
26
28
30
32
34
700 750 800 850 900 950 1000 1050 1100 1150 1200
INPUT I P 3 ( dBm)
RF FREQ UE NC Y (MHz)
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
Figure 46. Input IP3 vs. RF Frequency at 3.3 V, Upconversion
ADL5367 Data Sheet
Rev. B | Page 16 of 24
SPUR TABLES
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.
5 V Performance
VS = 5 V, I S = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and
ZO = 50 Ω, unless otherwise noted.
M
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
N
0 −7.8 −24.6 −35.7 −53.0 −47.4
1 −39.7 0.0 −45.0 −27.5 −53.0 −54.4 −71.8
2 −84.6 −68.8 −77.4 −72.8 −80.2 −80.9 −87.8 −96.8
3 <−100 −78.6 −95.5 −75.9 −97.9 −91.7 <−100 <−100
4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
3.3 V Performance
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 =
0 V, and Z O = 50 Ω, unless otherwise noted.
M
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
N
0 −12.6 −28.8 −40.6 −43.0 −59.6
1 −40.5 0.0 −42.7 −27.1 −53.2 −50.7 −71.8
2 −78.6 −59.5 −64.8 −68.0 −65.9 −73.0 −75.4 −89.4
3
−93.9 −66.3 −90.1 −63.0 −90.5 −77.8 −96.4 −95.6
4 <−100 <−100 −95.6 −95.5 −97.0 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 <−100 −98.9 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
12
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
Data Sheet ADL5367
Rev. B | Page 17 of 24
CIRCUIT DESCRIPTION
The ADL5367 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated
into a single die, using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.
The RF subsystem consists of an integrated, low loss RF balun,
passive MOSFET mixer, sum termination network, and IF
amplifier.
The LO subsystem consists of an SPDT terminated FET switch
and a three-stage limiting LO amplifier. The purpose of the LO
subsystem is to provide a large, fixed amplitude, balanced signal
to drive the mixer independent of the level of the LO input.
A block diagram of the device is shown in Figure 47.
2
3
1
20 19 18 17 16
6 7 8 9 10
4
5
14
13
15
12
BIAS
GENERATOR
VPMX
RFIN
RFCT
COMM
COMM
LOI2
VPSW
VGS1
VGS0
LOI1
VCMI IFOPIFON PWDN COMM
VLO3 LGM3 VLO2 LOSW NC
ADL5367
NC = NO CONNECT
11
08083-051
Figure 47. Simplified Schematic
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced to balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the device.
The RF balun can easily support an RF input frequency range
of 500 MHz to 1700 MHz.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the IF
output. This termination is accomplished by the addition of a
sum network between the IF output and the mixer.
Additionally, dc current can be saved by reducing the dc supply
voltage to as low as 3.3 V, further reducing the dissipated power
of the device. (Note that no performance enhancement is obtained
by reducing the value of these resistors and excessive dc power
dissipation may result.)
LO SUBSYSTEM
The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation performance.
The resulting amplifier provides extremely high performance
centered on an operating frequency of 1100 MHz. The best
operation is achieved with either high-side LO injection for RF
signals in the 500 MHz to 1200 MHz range or low-side injection
for RF signals in the 900 MHz to 1700 MHz range. Operation
outside these ranges is permissible, and conversion loss is
extremely wideband, easily spanning 500 MHz to 1700 MHz,
but intermodulation is optimal over the aforementioned ranges.
The ADL5367 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.
ADL5367 Data Sheet
Rev. B | Page 18 of 24
The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the
LO amplifier by raising the value of the external bias control
resistor. For dc current critical applications, the LO chain
can operate with a supply voltage as low as 3.3 V, resulting in
substantial dc power savings.
In addition, when operating with supply voltages below 3.6 V,
the ADL5367 has a power-down mode that permits the dc
current to drop to <200 µA.
All of the logic inputs are designed to work with any logic family
that provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.
Data Sheet ADL5367
Rev. B | Page 19 of 24
APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5367 mixer is designed to upconvert or downconvert
between radio frequencies (RF) from 500 MHz to 1700 MHz and
intermediate frequencies (IF) from dc to 450 MHz. Figure 48
depicts the basic connections of the mixer. It is recommended
to ac-couple the RF and LO input ports to prevent nonzero dc
voltages from damaging the RF balun or LO input circuit. The
RFIN capacitor value of 8 pF is recommended to provide the
optimized RF input return loss for the desired frequency band.
For upconversion, the IF input, Pin 18 (IFON) and Pin 19 (IFOP),
must be driven differentially or using a 1:1 ratio transformer for
single ended operation. An 8 pF capacitor is recommended for
the RF output, Pin 2 (RFIN).
IF PORT
The real part of the output impedance is approximately 50 Ω,
as seen in Figure 26, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion loss that is approximately the same as the power
conversion loss, as shown in Table 3.
MIXER VGS CONTROL DAC
The ADL5367 features two logic control pins, Pin 12 (VGS0) and
Pin 13 (VGS1), that allow programmability for internal gate to
source voltages for optimizing mixer performance over desired
frequency bands. The evaluation board defaults both VGS0 and
VGS1 to ground. Power conversion loss, NF, and IIP3 can be
optimized, as shown in Figure 35 and Figure 36.
2
3
1
19 18 17 16
6 7 8 9 10
14
15
12
11
BIAS
GENERATOR
LO2_IN
RF-IN +5V
+5V
+5V
+5V
LO1_IN
10kΩ
R1
0Ω
C24
560pF
10kΩ
10pF10pF
10pF
8pF
10pF
0.01µF
4.7µF
RBIAS L O
22pF
10pF
22pF
ADL5367
20
13
5
4
08082-052
T1
IF1_OUT
C25
560pF
Figure 48. Typical Application Circuit
ADL5367 Data Sheet
Rev. B | Page 20 of 24
EVALUATION BOARD
An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 49. The evaluation board, ADL5367-E VA L Z , is fabricated
using Rogers® RO3003 material.
Table 8 describes the various configuration options of the
evaluation board. The evaluation board layout is shown in
Figure 50 to Figure 53.
08082-053
C22
1nF
C20
10pF
C2
10µF C21
10pF
C1
8pF
C10
22pF
C12
22pF
VGS1
LO2_IN
LO1_IN
RF-IN
R22
10kΩ
VPOS
PWR_UP
R23
15kΩ
VPOS
VPOS
VPOS
LOSEL
VGS0
C5
0.01µF C4
10pF
C6
10pF
C8
10pF
R9
1.7kΩR4
10kΩ
R21
10kΩ
R14
0ΩL3
0Ω
VPMX
RFIN
RFCT
COMM
COMM
VGS1
VPSW
LOI2
VGS0
LOI1
IFON
IFOP
VCMI
PWDN
COMM
VLO3
LGM3
VLO2
NC
LOSW
ADL5367
R1
0Ω
C24
560pF
T1
IF1_OUT
C25
560pF
Figure 49. Evaluation Board Schematic
Data Sheet ADL5367
Rev. B | Page 21 of 24
Table 8. Evaluation Board Configuration
Components Description Default Conditions
C2, C6, C8,
C20, C21
Power Supply Decoupling. Nominal supply decoupling consists ofa 10 µF
capacitor to ground in parallel with a 10 pF capacitor to ground positioned
as close to the device as possible.
C2 = 10 µF (Size 0603),
C6, C8, C20, C21 = 10 pF (Size 0402)
C1, C4, C5 RF Input Interface. The input channels are ac-coupled through C1.
C4 and C5 provide bypassing for the center taps of the RF input baluns.
C1 = 3 pF (Size 0402), C4 = 10 pF (Size 0402),
C5 = 0.01 µF (Size 0402)
T1, R1, C24, C25 IF Output Interface. T1 is a 1:1 impedance transformer that provides a
single-ended IF output interface. Remove R1 for balanced output
operation. C24 and C25 block the dc bias at the IF ports.
T1 = TC1-1-13M+ (Mini-Circuits),
R1 = 0 Ω (Size 0402),
C24, C25 = 560 pF (Size 0402)
C10, C12, R4 LO Interface. C10 and C12 provide ac coupling for the LO1_IN and
LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input
for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is
enabled when the LOSEL test point is logic low. LO2_IN is enabled when
LOSEL is pulled to logic high.
C10, C12 = 22 pF (Size 0402),
R4 = 10 kΩ (Size 0402)
R21 PWDN Interface. R21 pulls the PWDN logic low and enables the device.
The PWR_UP test point allows the PWDN interface to be exercised using
the an external logic generator. Grounding the PWDN pin for nominal
operation is allowed. Using the PWDN pin when supply voltages exceed
3.3 V is not allowed.
R21 = 10 kΩ (Size 0402)
C22, L3, R9, R14,
R22, R23, VGS0,
VGS1
Bias Control. R22 and R23 form a voltage divider to provide 3 V for logic
control, bypassed to ground through C22. VGS0 and VGS1 jumpers
provide programmability at the VGS0 and VGS1 pins. It is recommended to
pull these two pins to ground for nominal operation. R9 sets the bias
point for the internal LO buffers. R14 sets the bias point for the internal
IF amplifier.
C22 = 1 nF (Size 0402), L3 = 0 Ω (Size 0603),
R9 = 1.7 kΩ (Size 0402), R14 = 0 Ω (Size 0402),
R22 = 10 kΩ (Size 0402), R23 = 15 kΩ (Size 0402),
VGS0 = VGS1 = 3-pin shunt
ADL5367 Data Sheet
Rev. B | Page 22 of 24
08083-054
Figure 50. Evaluation Board Top Layer
08083-055
Figure 51. Evaluation Board Ground Plane, Internal Layer 1
08083-056
Figure 52. Evaluation Board Power Plane, Internal Layer 2
08083-057
Figure 53. Evaluation Board Bottom Layer
Data Sheet ADL5367
Rev. B | Page 23 of 24
OUTLINE DIMENSIONS
COMPLIANT
TO
JEDEC STANDARDS M O-220-WHHC.
111908-A
0.65
BSC
0.70
0.60
0.40
0.35
0.28
0.23
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
SEATING
PLANE
0.80
0.75
0.70 0. 05 MAX
0.02 NO M
0.20 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
1516
5
Figure 54. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-20-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option
Ordering
Quantity
ADL5367ACPZ-R7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7” Tape and Reel CP-20-9 1,500
ADL5367-EVALZ Evaluation Board 1
1 Z = RoHS Compliant Part.
