ICS9DB801 Integrated Circuit Systems, Inc. Eight Output Differential Buffer for PCI Express (50-200MHz) Key Specifications: * Outputs cycle-cycle jitter < 50ps * Outputs skew: 50ps * 50 - 200MHz operation * Extended frequency range in bypass mode: Revision B: up tp 333.33 MHz Revision C: up to 400 MHz Features/Benefits: * Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread. * Supports undriven differential outputs in PD# and SRC_STOP# modes for power management. * Supports polarity inversion to the output enables , SRC_STOP and PD. Polarity Inversion Pin List Table OE_INV Pins 0 1 6 OE_0 OE0# 7 OE_3 OE3# 14 OE_1 OE1# 15 OE_2 OE2# 26 PD# PD 27 SRC_STOP# SRC_STOP 35 OE_5 OE5# 36 OE_6 OE6# 43 OE_4 OE4# 44 OE_7 OE7# SRC_DIV# VDD GND SRC_IN SRC_IN# OE_0 OE_3 DIF_0 DIF_0# GND VDD DIF_1 DIF_1# OE_1 OE_2 DIF_2 DIF_2# GND VDD DIF_3 DIF_3# BYPASS#/PLL SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS9DB801 (Same as ICS9DB108) Output Features: * 8 - 0.7V current-mode differential output pairs * Supports zero delay buffer mode and fanout mode * Bandwidth programming available Pin Configurations 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GNDA IREF LOCK OE_7 OE_4 DIF_7 DIF_7# OE_INV VDD DIF_6 DIF_6# OE_6 OE_5 DIF_5 DIF_5# GND VDD DIF_4 DIF_4# HIGH_BW# SRC_STOP# PD# GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GNDA IREF LOCK OE7# OE4# DIF_7 DIF_7# OE_INV VDD DIF_6 DIF_6# OE6# OE5# DIF_5 DIF_5# GND VDD DIF_4 DIF_4# HIGH_BW# SRC_STOP PD GND OE_INV = 0 SRC_DIV# VDD GND SRC_IN SRC_IN# OE0# OE3# DIF_0 DIF_0# GND VDD DIF_1 DIF_1# OE1# OE2# DIF_2 DIF_2# GND VDD DIF_3 DIF_3# BYPASS#/PLL SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS9DB801 Recommended Application: DB800 Version 2.0 Yellow Cover part with PCI Express suppor with extended bypass mode frequency range. OE_INV = 1 48-pin SSOP & TSSOP 1015B--09/07/06 Integrated Circuit Systems, Inc. ICS9DB801 Pin Desription for OE_INV = 0 PIN PIN # PIN NAME TYPE 1 SRC_DIV# IN 2 3 4 5 VDD GND SRC_IN SRC_IN# 6 OE_0 IN 7 OE_3 IN 8 9 10 11 12 13 DIF_0 DIF_0# GND VDD DIF_1 DIF_1# 14 OE_1 IN 15 OE_2 IN 16 17 18 19 20 21 DIF_2 DIF_2# GND VDD DIF_3 DIF_3# 22 BYPASS#/PLL IN 23 24 SCLK SDATA IN I/O PWR PWR IN IN OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT DESCRIPTION Active low Input for determining SRC output frequency SRC or SRC/2. 0 = SRC/2, 1= SRC Power supply, nominal 3.3V Ground pin. 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. 1015B--09/07/06 2 Integrated Circuit Systems, Inc. ICS9DB801 Pin Desription for OE_INV = 0 PIN PIN # PIN NAME TYPE 25 GND PWR Ground pin. 26 PD# IN 27 SRC_STOP# IN 28 HIGH_BW# IN 29 30 31 32 33 34 DIF_4# DIF_4 VDD GND DIF_5# DIF_5 35 OE_5 IN 36 OE_6 IN 37 38 39 DIF_6# DIF_6 VDD OUT OUT PWR 40 OE_INV IN 41 42 DIF_7# DIF_7 OUT OUT 43 OE_4 IN 44 OE_7 IN 45 LOCK OUT 46 IREF IN 47 48 GNDA VDDA PWR PWR OUT OUT PWR PWR OUT OUT DESCRIPTION Asynchronous active low input pin, with 120Kohm internal pullup resistor, used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. Active low input to stop SRC outputs. 3.3V input for selecting PLL Band Width 0 = High, 1= Low 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V Ground pin. 0.7V differential complement clock outputs 0.7V differential true clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V This latched input selects the polarity of the OE pins. 0 = OE pins active high, 1 = OE pins active low (OE#) 0.7V differential complement clock outputs 0.7V differential true clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 3.3V output indicating PLL Lock Status. This pin goes high when lock is achieved. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 1015B--09/07/06 3 Integrated Circuit Systems, Inc. ICS9DB801 Pin Desription for OE_INV = 1 PIN # PIN NAME PIN TYPE 1 SRC_DIV# IN 2 3 4 5 VDD GND SRC_IN SRC_IN# 6 OE0# IN 7 OE3# IN 8 9 10 11 12 13 DIF_0 DIF_0# GND VDD DIF_1 DIF_1# 14 OE1# IN 15 OE2# IN 16 17 18 19 20 21 DIF_2 DIF_2# GND VDD DIF_3 DIF_3# 22 BYPASS#/PLL IN 23 24 SCLK SDATA IN I/O PWR PWR IN IN OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT DESCRIPTION Active low Input for determining SRC output frequency SRC or SRC/2. 0 = SRC/2, 1= SRC Power supply, nominal 3.3V Ground pin. 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Active low input for enabling DIF pair 0. 1 = tri-state outputs, 0 = enable outputs Active low input for enabling DIF pair 3. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Active low input for enabling DIF pair 1. 1 = tri-state outputs, 0 = enable outputs Active low input for enabling DIF pair 2. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. 1015B--09/07/06 4 Integrated Circuit Systems, Inc. ICS9DB801 Pin Desription for OE_INV = 1 PIN # PIN NAME PIN TYPE 25 GND PWR 26 PD IN 27 SRC_STOP IN 28 HIGH_BW# IN 29 30 31 32 33 34 DIF_4# DIF_4 VDD GND DIF_5# DIF_5 35 OE5# IN 36 OE6# IN 37 38 39 DIF_6# DIF_6 VDD OUT OUT PWR 40 OE_INV IN 41 42 DIF_7# DIF_7 OUT OUT 43 OE4# IN 44 OE7# IN 45 LOCK OUT 46 IREF IN 47 48 GNDA VDDA OUT OUT PWR PWR OUT OUT PWR PWR DESCRIPTION Ground pin. Asynchronous active high input pin used to power down the device. The internal clocks are disabled and the VCO is stopped. Active high input to stop SRC outputs. 3.3V input for selecting PLL Band Width 0 = High, 1= Low 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V Ground pin. 0.7V differential complement clock outputs 0.7V differential true clock outputs Active low input for enabling DIF pair 5. 1 = tri-state outputs, 0 = enable outputs Active low input for enabling DIF pair 6. 1 = tri-state outputs, 0 = enable outputs 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V This latched input selects the polarity of the OE pins. 0 = OE pins active high, 1 = OE pins active low (OE#) 0.7V differential complement clock outputs 0.7V differential true clock outputs Active low input for enabling DIF pair 4 1 = tri-state outputs, 0 = enable outputs Active low input for enabling DIF pair 7. 1 = tri-state outputs, 0 = enable outputs 3.3V output indicating PLL Lock Status. This pin goes high when lock is achieved. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 1015B--09/07/06 5 Integrated Circuit Systems, Inc. ICS9DB801 General Description The ICS9DB801 follows the Intel DB800 Differential Buffer Specification v2.0. This buffer provides eight PCI-Express SRC clocks. The ICS9DB801 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the ICS952601 or ICS954101. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps) requirements. Block Diagram 8 OE_(7:0) SPREAD COMPATIBLE PLL SRC_IN SRC_IN# M U X STOP LOGIC 8 DIF(7:0)) SRC_STOP# HIGH_BW# BYPASS#/PLL PD# CONTROL LOGIC IREF SDATA SCLK LOCK Note: Polarities shown for OE_INV = 0. 1015B--09/07/06 6 Integrated Circuit Systems, Inc. ICS9DB801 Absolute Max Symbol VDD_A VDD_In VIL VIH Parameter 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Ts Tambient Tcase Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model ESD prot Min Max 4.6 4.6 GND-0.5 V DD+0.5V -65 0 150 70 115 2000 Units V V V V C C C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Operating Supply Current IDD3.3PLL IDD3.3ByPass Powerdown Current IDD3.3PD Input Frequency FiPLL Input Frequency FiBypass Input Frequency FiBypass 1 Pin Inductance CONDITIONS MIN TYP 3.3 V +/-5% 2 GND - 0.3 3.3 V +/-5% VIN = VDD -5 VIN = 0 V; Inputs with no pull-up -5 resistors VIN = 0 V; Inputs with pull-up -200 resistors uA uA 175 160 50 1 50 200 175 70 4 200 mA mA mA mA MHz 0 333.33 MHz 0 400 MHz 7 4 4 nH pF pF 1 1 1 3 3.4 MHz 1 1 1.4 MHz 1 0.5 1 ms 1,2 33 kHz 1 15 ns 1,3 300 us 1,3 5 ns 1 5 ns 2 Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated PLL Mode Bypass Mode (Revision B/REV ID = 1H) Bypass Mode (Revision C/REV ID = 2H) Lpin CIN COUT Logic Inputs 1.5 1 Input Capacitance Output pin capacitance PLL Bandwidth when 2.4 PLL_BW=0 PLL Bandwidth BW PLL Bandwidth when 0.7 PLL_BW=1 From VDD Power-Up and after 1,2 TSTAB input clock stabilization or deClk Stabilization assertion of PD# to 1st clock fMOD Triangular Modulation 30 Modulation Frequency DIF output enable after Tdrive_SRC_STOP# SRC_Stop# de-assertion DIF output enable after Tdrive_PD# PD# de-assertion Fall time of PD# and Tfall SRC_STOP# Rise time of PD# and Trise SRC_STOP# 1 Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Time from deassertion until outputs are >200 mV 1015B--09/07/06 7 MAX UNITS NOTES VDD + 0.3 V 0.8 V 5 uA 10 Integrated Circuit Systems, Inc. ICS9DB801 Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo1 VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy Rise Time Fall Time Rise Time Variation Fall Time Variation ppm tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP MAX UNITS NOTES 1 850 1,3 mV -150 150 1150 -300 250 175 175 1,3 550 mV 1 1 1 140 mV 1 0 700 700 125 125 ppm ps ps ps ps 1,2 1 1 1 1 mV Measurement from differential 45 55 % wavefrom VT = 50% tsk3 50 ps Skew PLL mode, 50 ps Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom BYPASS mode as additive jitter 50 ps 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. Duty Cycle dt3 1015B--09/07/06 8 1 1 1 1 Integrated Circuit Systems, Inc. ICS9DB801 SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non -coupled 50 ohm trace. 0.5 max L2 length, Route as non -coupled 50 ohm trace. 0.2 max L3 length, Route as non -coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coup led stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Rout e as coupled stripline 100 ohm differential trace. L1 Unit inch inch inch ohm ohm Figure 2, 3 2, 3 2, 3 2, 3 2, 3 Dimension or Value 2 min to 16 max Unit inch 2 1.8 min to 14.4 max inch 2 Dimension or Value 0.25 to 14 max Unit inch 3 0.225 min to 12.6 max inch 3 Figure L2 L4 Rs L1' L4' L2' Rs Fig.1 Figure Rt HSCL Output Buffer Rt L1 PCI Ex REF_CLK Test Load L3 L3' L2 L4 Rs L1' Fig.2 L4' L2' Rs Rt HSCL Output Buffer L3' L1 Rt PCI Ex Board Down Device REF_CLK Input L3 L2 L4 Rs L4' L1' L2' Rs Fig.3 Rt HSCL Output Buffer L3' 1015B--09/07/06 9 Rt L3 PCI Ex Add In Board REF_CLK Input Integrated Circuit Systems, Inc. ICS9DB801 General SMBus serial interface information for the ICS9DB801 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * * * * * * * * * * * * * * * * Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address DC(H) WRite WR Controller (host) will send start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address DC(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address DD(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 1015B--09/07/06 10 Not acknowledge stoP bit Integrated Circuit Systems, Inc. ICS9DB801 SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD) Byte 0 0 1 PWD Pin # Name Control Function Type Bit 7 PD_Mode PD# drive mode RW driven Hi-Z 0 driven Hi-Z 0 Bit 6 STOP_Mode SRC_Stop# drive mode RW Reserved Bit 5 Reserved Reserved RW X Reserved Bit 4 Reserved Reserved RW X Reserved Bit 3 Reserved Reserved RW X 1 Bit 2 PLL_BW# Select PLL BW RW High BW Low BW Bit 1 BYPASS# BYPASS#/PLL RW fan-out ZDB 1 Bit 0 SRC_DIV# SRC Divide by 2 Select RW x/2 1x 1 SMBus Table: Output Control Register Byte 1 Pin # Name Control Function 42,41 Bit 7 DIF_7 Output Control 38,37 Bit 6 DIF_6 Output Control 34,33 Bit 5 DIF_5 Output Control 30,29 Bit 4 DIF_4 Output Control 20,21 Bit 3 DIF_3 Output Control 16,17 Bit 2 DIF_2 Output Control 12,13 Bit 1 DIF_1 Output Control 8,9 Bit 0 DIF_0 Output Control Type RW RW RW RW RW RW RW RW SMBus Table: Output Control Register Byte 2 Pin # Name Control Function 42,41 Bit 7 DIF_7 Output Control 0 1 PWD Type RW Free-run Stoppable 0 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Bit 6 38,37 DIF_6 Output Control RW Free-run Stoppable 0 Bit 5 34,33 DIF_5 Output Control RW Free-run Stoppable 0 Bit 4 Bit 3 30,29 20,21 DIF_4 DIF_3 Output Control Output Control RW Free-run Stoppable RW Free-run Stoppable 0 0 Bit 2 16,17 DIF_2 Output Control RW Free-run Stoppable 0 Bit 1 12,13 DIF_1 Output Control RW Free-run Stoppable 0 Bit 0 8,9 DIF_0 Output Control RW Free-run Stoppable 0 1015B--09/07/06 11 Integrated Circuit Systems, Inc. ICS9DB801 SMBus Table: Output Control Register Byte 3 Pin # Name Control Function Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Type RW RW RW RW RW RW RW RW 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD X X X X X X X X SMBus Table: Vendor Pin # Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 & Revision ID Register Name Control Function RID3 RID2 REVISION ID RID1 RID0 VID3 VID2 VENDOR ID VID1 VID0 Type R R R R R R R R 0 - 1 - PWD X X X X 0 0 0 1 SMBus Table: DEVICE ID Pin # Name Control Function Byte 5 Device ID 7 (MSB) Bit 7 Device ID 6 Bit 6 Type R R 0 1 Reserved Reserved PWD 1 0 Bit 5 - Device ID 5 R Reserved 0 Bit 4 - Device ID 4 R Reserved 0 Bit 3 - Device ID 3 R Reserved 0 Bit 2 - Device ID 2 R Reserved 0 Bit 1 Bit 0 - Device ID 1 Device ID 0 R R Reserved Reserved 0 1 SMBus Table: Byte Count Register Pin # Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type 0 1 PWD Writing to this register configures how many bytes will be read back. RW RW RW RW RW RW RW RW - - 0 0 0 0 0 1 1 1 1015B--09/07/06 12 Integrated Circuit Systems, Inc. ICS9DB801 Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1. PD#, Power Down The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD# drive mode and Output control bits) before the PLL is shut down. PD# Assertion When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode bit is set to `0', all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is set to `1', both DIF and DIF# are tri-stated. PWRDWN# DIF DIF# PD# De-assertion Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set to `1', all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion. Tstable <1mS PWRDWN# DIF DIF# Tdrive_PwrDwn# <300uS, >200mV 1015B--09/07/06 13 Integrated Circuit Systems, Inc. ICS9DB801 SRC_STOP# The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion. SRC_STOP# - Assertion Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output to stop). When the SRC_STOP# drive bit is `0', the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the SRC_STOP# drive bit is `1', the final state of all DIF output pins is Low. Both DIF and DIF# are not driven. SRC_STOP# - De-assertion (transition from '0' to '1') All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is 2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is `1' (tri-state), all stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion. SRC_STOP_1 (SRC_Stop = Driven, PD = Driven) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) 1015B--09/07/06 14 Integrated Circuit Systems, Inc. ICS9DB801 SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate) 1mS SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) 1015B--09/07/06 15 Integrated Circuit Systems, Inc. ICS9DB801 c N SYMBOL L E1 E INDEX AREA 1 2 h x 45 D A A A1 b c D E E1 e h L N In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8 A1 VARIATIONS D mm. MIN MAX 15.75 16.00 -Ce b SEATING PLANE .10 (.004) C N 48 D (inch) MIN .620 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS9DB801yFLFT Example: ICS XXXX y F LF T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device 1015B--09/07/06 16 MAX .630 Integrated Circuit Systems, Inc. ICS9DB801 c N 48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) L E1 INDEX AREA E 1 2 a D A A2 A1 -C- SYMBOL A A1 A2 b c D E E1 e L N a aaa SEATING PLANE b aaa C In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .011 .0035 .008 SEE VARIATIONS 0.319 BASIC .236 .244 0.020 BASIC .018 .030 SEE VARIATIONS 0 8 -.004 VARIATIONS N e (20 mil) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20 0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10 48 D mm. MIN 12.40 D (inch) MAX 12.60 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 Ordering Information ICS9DB801yGLFT Example: ICS XXXX y G LF T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device 1015B--09/07/06 17 MIN .488 MAX .496 Integrated Circuit Systems, Inc. ICS9DB801 Revision History Rev. Issue Date Description 0.10 4/4/2005 0.20 A 4/8/2005 4/8/2005 B 9/7/2006 Page # 1. Updated Operating Supply Current Spec from Input/Supply/Common Output Parameters table. 2. Updated Ordering Information from "Lead Free" to "Annealed Lead Free". 1. Updated Min/Max BW spec 2. Added 50-200MHz nomenclature to data sheet to indicate B rev limits 3. Released Release to Final 1. Added Polarity Table. 2. Updated Electrical Characteristics. 3. Updated LF Ordering Information from "Annealed Lead Free" to "RoHS Compliant". 1015B--09/07/06 18 7,16-17 1, 7 1, 7, 16-17 Search Entire Site Contact IDT | Investors | Press Document Search | Package Search | Parametric Search | Cross Reference Search | Green & RoHS | Calculators | Thermal Data | Reliability & Quality | Military Add to m yIDT [?] Home > Products > Timing Solutions > PC-Notebook-Server Clocks > PCIe/HCSL Buffers and Generators > 9DB801 9DB801 (PCIe/HCSL Buffers and Generators) Description DB800 Version 2.0 Yellow Cover part with PCI Express suppor with extended bypass mode frequency range. - Eight Output Differential Buffer for PCI Express (50-200MHz) Market Group PC CLOCK Additional Info DB800 Version 2.0 Yellow Cover part with PCI Express suppor with extended bypass mode frequency range. 48-pin SSOP/TSSOP You may also like... Related Orderable Parts 2 1 Attributes 9DB801BFLF 9DB801BFLFT 9DB801BGLF 9DB801BGLFT 9DB801CFLF 9DB801CGLF Voltage 3.3 V (PVG48) 3.3 V (PVG48) 3.3 V (PAG48) 3.3 V (PAG48) 3.3 V (PVG48) 3.3 V (PAG48) Package SSOP 48 SSOP 48 TSSOP 48 TSSOP 48 SSOP 48 TSSOP 48 Speed NA NA NA NA NA NA Temperature C C C C C C Status Active Active Active Active Active Active Sample Yes No Yes No Yes Yes Minimum Order Quantity 180 1000 152 1000 180 152 30 1000 38 1000 30 38 Factory Order Increment 2 1 Related Documents Type Title Size Revision Date Datasheet 9DB801 Datasheet 201 KB 05/21/2007 Model - IBIS 9DB801 IBIS Model 104 KB 03/27/2006 Product Change Notice PCN#: TB-0510-05 New Shipping Tube for TSSOP/TVSOP/TSSOP Exposed 202 KB 12/13/2005 Home | Site Map | About IDT | Press Room | Investor Relations | Trademark | Privacy Policy | Careers | Register | Contact Us Use of this website signifies your agreement to the acceptable use and privacy policy. Copyright 1997-2007 Integrated Device Technology, Inc. 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