Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
Pin ConfigurationsRecommended Application:
DB800 Version 2.0 Yellow Cover part with PCI Express
suppor with extended bypass mode frequency range.
Output Features:
• 8 - 0.7V current-mode differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
Key Specifications:
• Outputs cycle-cycle jitter < 50ps
• Outputs skew: 50ps
• 50 - 200MHz operation
• Extended frequency range in bypass mode:
Revision B: up tp 333.33 MHz
Revision C: up to 400 MHz
Features/Benefits:
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
• Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
• Supports polarity inversion to the output enables ,
SRC_STOP and PD.
Eight Output Differential Buffer for PCI Express (50-200MHz)
48-pin SSOP & TSSOP
SRC_DIV# 1 48 VDDA
VDD 2 47 GNDA
GND 3 46 IREF
SRC_IN 4 45 LOCK
SRC_IN# 5 44 OE_7
OE_0 6 43 OE_4
OE_3 742
DIF_7
DIF_0 841
DIF_7#
DIF_0# 940
OE_INV
GND 10 39 VDD
VDD 11 38 DIF_6
DIF_1 12 37 DIF_6#
DIF_1# 13 36 OE_6
OE_1 14 35 OE_5
OE_2 15 34 DIF_5
DIF_2 16 33 DIF_5#
DIF_2# 17 32 GND
GND 18 31 VDD
VDD 19 30 DIF_4
DIF_3 20 29 DIF_4#
DIF_3# 21 28 HIGH_BW#
BYPASS#/PLL 22 27 SRC_STOP#
SCLK 23 26 PD#
SDATA 24 25 GND
OE_INV = 0
ICS9DB801
(Same as ICS9DB108)
SRC_DIV# 1 48 VDDA
VDD 2 47 GNDA
GND 3 46 IREF
SRC_IN 4 45 LOCK
SRC_IN# 5 44 OE7#
OE0# 643OE4#
OE3# 742
DIF_7
DIF_0 841
DIF_7#
DIF_0# 940
OE_INV
GND 10 39 VDD
VDD 11 38 DIF_6
DIF_1 12 37 DIF_6#
DIF_1# 13 36 OE6#
OE1# 14 35 OE5#
OE2# 15 34 DIF_5
DIF_2 16 33 DIF_5#
DIF_2# 17 32 GND
GND 18 31 VDD
VDD 19 30 DIF_4
DIF_3 20 29 DIF_4#
DIF_3# 21 28 HIGH_BW#
BYPASS#/PLL 22 27 SRC_STOP
SCLK 23 26 PD
SDATA 24 25 GND
OE_INV = 1
ICS9DB801
01
6OE_0 OE0#
7OE_3 OE3#
14 OE_1 OE1#
15 OE_2 OE2#
26 PD# PD
27 SRC_STOP# SRC_STOP
35 OE_5 OE5#
36 OE_6 OE6#
43 OE_4 OE4#
44 OE_7 OE7#
Polarit
y
Inversion Pin List Table
Pins
OE_INV
2
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
PIN # PIN NAME PIN
TYPE DESCRIPTION
1SRC_DIV# IN
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
2 VDD PWR Power supply, nominal 3.3V
3 GND PWR Ground pin.
4 SRC_IN IN 0.7 V Differential SRC TRUE input
5 SRC_IN# IN 0.7 V Differential SRC COMPLEMENTARY input
6OE_0 IN Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
7OE_3 IN Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
8 DIF_0 OUT 0.7V differential true clock outputs
9 DIF_0# OUT 0.7V differential complement clock outputs
10 GND PWR Ground pin.
11 VDD PWR Power supply, nominal 3.3V
12 DIF_1 OUT 0.7V differential true clock outputs
13 DIF_1# OUT 0.7V differential complement clock outputs
14 OE_1 IN Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
15 OE_2 IN Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
16 DIF_2 OUT 0.7V differential true clock outputs
17 DIF_2# OUT 0.7V differential complement clock outputs
18 GND PWR Ground pin.
19 VDD PWR Power suppl
y
, nominal 3.3V
20 DIF_3 OUT 0.7V differential true clock outputs
21 DIF_3# OUT 0.7V differential complement clock outputs
22 BYPASS#/PLL IN Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = B
y
pass mode, 1= PLL mode
23 SCLK IN Clock pin of SMBus circuitr
y
, 5V tolerant.
24 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
Pin Desri
p
tion for OE_INV = 0
3
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
PIN # PIN NAME PIN
TYPE DESCRIPTION
25 GND PWR Ground pin.
26 PD# IN
Asynchronous active low input pin, with 120Kohm internal pull-
up resistor, used to power down the device. The internal clocks
are disabled and the VCO and the crystal are stopped.
27 SRC_STOP# IN Active low input to stop SRC outputs.
28 HIGH_BW# IN 3.3V input for selecting PLL Band Width
0 = High, 1= Low
29 DIF_4# OUT 0.7V differential complement clock outputs
30 DIF_4 OUT 0.7V differential true clock outputs
31 VDD PWR Power supply, nominal 3.3V
32 GND PWR Ground pin.
33 DIF_5# OUT 0.7V differential complement clock outputs
34 DIF_5 OUT 0.7V differential true clock outputs
35 OE_5 IN Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
36 OE_6 IN Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
37 DIF_6# OUT 0.7V differential complement clock outputs
38 DIF_6 OUT 0.7V differential true clock outputs
39 VDD PWR Power supply, nominal 3.3V
40 OE_INV IN This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
41 DIF_7# OUT 0.7V differential complement clock outputs
42 DIF_7 OUT 0.7V differential true clock outputs
43 OE_4 IN Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
44 OE_7 IN Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
45 LOCK OUT 3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
46 IREF IN
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
47 GNDA PWR Ground pin for the PLL core.
48 VDDA PWR 3.3V power for the PLL core.
Pin Desri
p
tion for OE_INV = 0
4
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
PIN # PIN NAME PIN TYPE DESCRIPTION
1 SRC_DIV# IN
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2
,
1= SRC
2 VDD PWR Power su
pp
l
y
, nominal 3.3V
3 GND PWR Ground
p
in.
4 SRC_IN IN 0.7 V Differential SRC TRUE in
p
ut
5 SRC_IN# IN 0.7 V Differential SRC COMPLEMENTARY in
p
ut
6OE0# IN Active low input for enabling DIF pair 0.
1 = tri-state out
p
uts, 0 = enable out
p
uts
7OE3# IN Active low input for enabling DIF pair 3.
1 = tri-state out
p
uts, 0 = enable out
p
uts
8 DIF_0 OUT 0.7V differential true clock out
p
uts
9 DIF_0# OUT 0.7V differential com
p
lement clock out
p
uts
10 GND PWR Ground
p
in.
11 VDD PWR Power su
pp
l
y
, nominal 3.3V
12 DIF_1 OUT 0.7V differential true clock out
p
uts
13 DIF_1# OUT 0.7V differential com
p
lement clock out
p
uts
14 OE1# IN Active low input for enabling DIF pair 1.
1 = tri-state out
p
uts, 0 = enable out
p
uts
15 OE2# IN Active low input for enabling DIF pair 2.
1 = tri-state out
p
uts, 0 = enable out
p
uts
16 DIF_2 OUT 0.7V differential true clock out
p
uts
17 DIF_2# OUT 0.7V differential com
p
lement clock out
p
uts
18 GND PWR Ground
p
in.
19 VDD PWR Power su
pp
l
y
, nominal 3.3V
20 DIF_3 OUT 0.7V differential true clock out
p
uts
21 DIF_3# OUT 0.7V differential com
p
lement clock out
p
uts
22 BYPASS#/PLL IN Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = B
yp
ass mode, 1= PLL mode
23 SCL
K
IN Clock
p
in of SMBus circuitr
y
, 5V tolerant.
24 SDATA I/O Data
p
in for SMBus circuitr
y
, 5V tolerant.
Pin Desription for OE_INV = 1
5
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
PIN # PIN NAME PIN TYPE DESCRIPTION
25 GND PWR Ground
p
in.
26 PD IN Asynchronous active high input pin used to power down the
device. The internal clocks are disabled and the VCO is stopped.
27 SRC_STOP IN Active hi
g
h in
p
ut to sto
p
SRC out
p
uts.
28 HIGH_BW# IN 3.3V input for selecting PLL Band Width
0 = Hi
g
h, 1= Low
29 DIF_4# OUT 0.7V differential com
p
lement clock out
p
uts
30 DIF_4 OUT 0.7V differential true clock out
p
uts
31 VDD PWR Power su
pp
l
y
, nominal 3.3V
32 GND PWR Ground
p
in.
33 DIF_5# OUT 0.7V differential com
p
lement clock out
p
uts
34 DIF_5 OUT 0.7V differential true clock out
p
uts
35 OE5# IN Active low input for enabling DIF pair 5.
1 = tri-state out
p
uts, 0 = enable out
p
uts
36 OE6# IN Active low input for enabling DIF pair 6.
1 = tri-state out
p
uts, 0 = enable out
p
uts
37 DIF_6# OUT 0.7V differential com
p
lement clock out
p
uts
38 DIF_6 OUT 0.7V differential true clock out
p
uts
39 VDD PWR Power su
pp
l
y
, nominal 3.3V
40 OE_INV IN This latched input selects the polarity of the OE pins.
0 = OE
p
ins active hi
g
h, 1 = OE
p
ins active low
(
OE#
)
41 DIF_7# OUT 0.7V differential com
p
lement clock out
p
uts
42 DIF_7 OUT 0.7V differential true clock out
p
uts
43 OE4# IN Active low input for enabling DIF pair 4
1 = tri-state out
p
uts, 0 = enable out
p
uts
44 OE7# IN Active low input for enabling DIF pair 7.
1 = tri-state out
p
uts, 0 = enable out
p
uts
45 LOCK OUT 3.3V output indicating PLL Lock Status. This pin goes high when
lock is achieved.
46 IREF IN
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
47 GNDA PWR Ground
p
in for the PLL core.
48 VDDA PWR 3.3V power for the PLL core.
Pin Desription for OE_INV = 1
6
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
The ICS9DB801 follows the Intel DB800 Differential Buffer Specification v2.0. This buffer provides eight PCI-Express SRC
clocks. The ICS9DB801 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the
ICS952601 or ICS954101. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps)
requirements.
General Description
Block Diagram
STOP
LOGIC
SRC_IN
SRC_IN#
DIF(7:0))
CONTROL
LOGIC
BYPASS#/PLL
S DATA
SCLK
PD#
SPREAD
COMPATIBLE
PLL
8
IREF
OE_(7:0)
8
LOCK
SRC_STOP#
HIGH_BW#
M
U
X
Note: Polarities shown for OE_INV = 0.
7
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
Absolute Max
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage 4.6 V
VDD_In 3.3V Logic Supply Voltage 4.6 V
VIL Input Low Voltage GND-0.5 V
VIH Input High Voltage VD
D
+0.5V V
Ts Storage Temperature -65 150 °C
Tambient Ambient Operating Temp 0 70 °C
Tcase Case Temperature 115 °C
ESD prot
Input ESD protection
human body model 2000 V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V
Input Low Voltage VIL 3.3 V +/-5% GND - 0.3 0.8 V
Input High Current IIH VIN = VDD -5 5 uA
IIL1
VIN = 0 V; Inputs with no pull-up
resistors -5 uA
IIL2
VIN = 0 V; Inputs with pull-up
resistors -200 uA
IDD3.3PLL 175 200 mA
IDD3.3ByPass 160 175 mA
all diff
p
airs driven 50 70 mA
all differential
p
airs tri-stated 1 4 mA
Input Frequency FiPLL PLL Mode 50 200 MHz
Input Frequency FiBypass
Bypass Mode (Revision B/REV
ID = 1H
)
0 333.33 MHz
Input Frequency FiBypass
Bypass Mode (Revision C/REV
ID = 2H
)
0 400 MHz
Pin Inductance1Lpin 7nH1
CIN Logic Inputs 1.5 4 pF 1
COUT Output pin capacitance 4 pF 1
PLL Bandwidth when
PLL_BW=0 2.4 3 3.4 MHz 1
PLL Bandwidth when
PLL_BW=1 0.7 1 1.4 MHz 1
Clk Stabilization1,2 TSTAB
From VDD Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
0.5 1 ms 1,2
Modulation Fre
q
uenc
y
fMOD Trian
g
ular Modulation 30 33 kHz 1
Tdrive_SRC_STOP# DIF output enable after
SRC_Sto
p
# de-assertion 10 15 ns 1,3
Tdrive_PD# DIF output enable after
PD# de-assertion 300 us 1,3
Tfall Fall time of PD# and
SRC_STOP# 5ns1
Trise Rise time of PD# and
SRC_STOP# 5ns2
1Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2See timin
g
dia
g
rams for timin
g
re
q
uirements.
IDD3.3PD
3Time from deassertion until out
p
uts are >200 mV
Input Capacitance1
Input Low Current
Powerdown Current
PLL Bandwidth BW
Full Active, CL = Full load;
Operating Supply Current
8
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2Ω, R
P
=49.9Ω, Ι
REF
= 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Im
p
edance Zo
1
V
O
= V
x
3000 Ω1
Voltage High VHigh 660 850 1,3
Voltage Low VLow -150 150 1,3
Max Volta
g
eVovs 1150 1
Min Volta
g
e Vuds -300 1
Crossin
g
Volta
g
e
(
abs
)
Vcross
(
abs
)
250 550 mV 1
Crossing Voltage (var) d-Vcross Variation of crossin
g
over all
ed
g
es 140 mV 1
Lon
g
Accurac
y
pp
msee T
p
eriod min-max values 0
pp
m1,2
Rise Time t
r
V
OL
= 0.175V, V
OH
= 0.525V 175 700 ps 1
Fall Time t
f
V
OH
= 0.525V V
OL
= 0.175V 175 700 ps 1
Rise Time Variation d-t
r
125 ps 1
Fall Time Variation d-t
f
125 ps 1
Duty Cycle d
t3
Measurement from differential
wavefrom 45 55 % 1
Skew t
sk3
V
T
= 50% 50 ps 1
PLL mode,
Measurement from differential
wavefrom
50 ps 1
BYPASS mode as additive jitter 50 ps 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475Ω (1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
Jitter, Cycle to cycle t
jcyc-cyc
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on sin
g
le ended
signal using absolute value. mV
9
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
SRC Reference Clock
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, Route as non -coupled 50 ohm trace. 0.5 max inch 2, 3
L2 length, Route as non -coupled 50 ohm trace. 0.2 max inch 2, 3
L3 length, Route as non -coupled 50 ohm trace. 0.2 max inch 2, 3
Rs 33 ohm 2, 3
Rt 49.9 ohm 2, 3
Down Device Differential Routing Dimension or Value Unit Figure
L4 length, Route as coupled microstrip 100 ohm
differential trace.
2 min to 16 max
inch 2
L4 length, Route as coup led stripline 100 ohm
differential trace.
1.8 min to 14.4 max
inch 2
Differential Routing to PCI Express Connector Dimension or Value Unit Figure
L4 length, Route as coupled microstrip 100 ohm
differential trace.
0.25 to 14 max
inch 3
L4 length, Rout e as coupled stripline 100 ohm
differential trace.
0.225 min to 12.6
max
inch 3
Fig.1 Rs
Rs
Rt Rt
HSCL Output
Buffer
PCI Ex
REF_CLK
Test Load
L1 L2
L3’
L4
L1’ L2’
L3
L4’
Fig.2 Rs
Rs
Rt Rt
HSCL Output
Buffer
PCI Ex Board
Down Device
REF_CLK Input
L1 L2
L3’
L4
L1’ L2’
L3
L4’
Fig.3 Rs
Rs
Rt Rt
HSCL Output
Buffer
PCI Ex
Add In Board
REF_CLK Input
L1 L2
L3’
L4
L1’ L2’
L3
L4’
10
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
General SMBus serial interface information for the ICS9DB801
How to Write:
•Controller (host) sends a start bit.
• Controller (host) sends the write address DC (H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC (H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD (H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receive r)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
I ndex Bl ock Wri te Operat ion
Slave Address DC(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
ICS (Sla ve /Re ce i ve r)
Controll er (Host)
X Byte
ACK
ACK
Data Byte Count = X
ACK
Slave Address DD(H)
Index Block Read Operation
Slave Address DC(H)
Beginning Byte = N
ACK
ACK
11
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7 PD_Mode PD# drive mode RW driven Hi-Z 0
Bit 6 STOP_Mode SRC_Sto
p
# drive mode RW driven Hi-Z 0
Bit 5 Reserved Reserved RW X
Bit 4 Reserved Reserved RW X
Bit 3 Reserved Reserved RW X
Bit 2 PLL_BW# Select PLL BW RW Hi
g
h BW Low BW 1
Bit 1 BYPASS# BYPASS#/PLL RW fan-out ZDB 1
Bit 0 SRC_DIV# SRC Divide by 2 Select RW x/2 1x 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7 DIF_7 Output Control RW Disable Enable 1
Bit 6 DIF_6 Out
p
ut Control RW Disable Enable 1
Bit 5 DIF_5 Out
p
ut Control RW Disable Enable 1
Bit 4 DIF_4 Output Control RW Disable Enable 1
Bit 3 DIF_3 Output Control RW Disable Enable 1
Bit 2 DIF_2 Out
p
ut Control RW Disable Enable 1
Bit 1 DIF_1 Out
p
ut Control RW Disable Enable 1
Bit 0 DIF_0 Output Control RW Disable Enable 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7 DIF_7 Output Control RW Free-run Stoppable 0
Bit 6 DIF_6 Output Control RW Free-run Stoppable 0
Bit 5 DIF_5 Output Control RW Free-run Stoppable 0
Bit 4 DIF_4 Output Control RW Free-run Stoppable 0
Bit 3 DIF_3 Output Control RW Free-run Stoppable 0
Bit 2 DIF_2 Output Control RW Free-run Stoppable 0
Bit 1 DIF_1 Output Control RW Free-run Stoppable 0
Bit 0 DIF_0 Output Control RW Free-run Stoppable 0
Reserved
12,13
8,9
34,33
30,29
20,21
16,17
8,9
Byte 2
42,41
38,37
30,29
20,21
16,17
12,13
Byte 0
-
-
-
-
-
-
- Reserved
-
Reserved
Byte 1
42,41
38,37
34,33
12
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7 RW X
Bit 6 RW X
Bit 5 RW X
Bit 4 RW X
Bit 3 RW X
Bit 2 RW X
Bit 1 RW X
Bit 0 RW X
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7 RID3 R - - X
Bit 6 RID2 R - - X
Bit 5 RID1 R - - X
Bit 4 RID0 R - - X
Bit 3 VID3 R - - 0
Bit 2 VID2 R - - 0
Bit 1 VID1 R - - 0
Bit 0 VID0 R - - 1
SMBus Table: DEVICE ID
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7 R1
Bit 6 R0
Bit 5 R0
Bit 4 R0
Bit 3 R0
Bit 2 R0
Bit 1 R0
Bit 0 R1
SMBus Table: Byte Count Register
Pin # Name Control
Function Type 0 1 PWD
Bit 7 BC7 RW - - 0
Bit 6 BC6 RW - - 0
Bit 5 BC5 RW - - 0
Bit 4 BC4 RW - - 0
Bit 3 BC3 RW - - 0
Bit 2 BC2 RW - - 1
Bit 1 BC1 RW - - 1
Bit 0 BC0 RW - - 1
Reserved Reserved
B
y
te 3
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
B
y
te 4
-
REVISION ID
-
-
-
-
-
VENDOR ID
-
-
-
-
-
-
-
B
y
te 5
-
-
-
Byte 6
-
Writing to this register
configures how many
bytes will be read back.
-
-
-
-
-
-
-
Device ID 7 (MSB) Reserved
Reserved
Device ID 4 Reserved
Device ID 6 Reserved
Device ID 3 Reserved
Device ID 0 Reserved
Device ID 2 Reserved
Device ID 1 Reserved
Device ID 5
13
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before
shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering
down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending
on the PD# drive mode and Output control bits) before the PLL is shut down.
PD#, Power Down
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PD# Assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
PD# De-assertion
PWRDWN#
DIF
DIF#
PWRDWN#
DIF
DIF#
Tstable
<1mS
Tdrive_PwrDwn#
<300uS, >200mV
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
14
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
SRC_STOP# - Assertion
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP# - De-assertion (transition from '0' to '1')
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP#
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
15
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate)
SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate)
16
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
INDEX
AREA
INDEX
AREA
1 2
N
D
h x 45°
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
b
.10 (.004) C
.10 (.004) C
c
L
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
α0° 8° 0° 8°
MIN MAX MIN MAX
48 15.75 16.00 .620 .630
10-0034
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
Ordering Information
ICS9DB801yFLFT
Example:
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
ICS XXXX y F LF T
17
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
a 0°8°0°8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
48 12.40 12.60 .488 .496
10-0039
Reference Doc.: JEDEC Publication 95, MO-153
In Millimeters In Inches
COMMON DIMENSIONS
0.50 BASIC 0.020 BASIC
8.10 BASIC 0.319 BASIC
ND (inch)
SEE VARIATIONS SEE VARIATIONS
D mm.
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
SYMBOL
SEE VARIATIONS
COMMON DIMENSIONS
SEE VARIATIONS
Ordering Information
ICS9DB801yGLFT
Example:
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
ICS XXXX y G LF T
18
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
Revision History
Rev. Issue Date Description Page #
0.10 4/4/2005
1. Updated Operating Supply Current Spec from Input/Supply/Common
Output Parameters table.
2. Updated Orderin
g
Information from "Lead Free" to "Annealed Lead Free". 7,16-17
0.20 4/8/2005
1. Updated Min/Max BW spec
2. Added 50-200MHz nomenclature to data sheet to indicate B rev limits
3. Released 1, 7
A 4/8/2005 Release to Final
B 9/7/2006
1. Added Polarity Table.
2. Updated Electrical Characteristics.
3. Updated LF Ordering Information from "Annealed Lead Free" to "RoHS
Compliant".
1, 7,
16-17
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9DB801 (PCIe/HCSL Buffers and Generators)
Description
DB800 Version 2.0 Yellow Cover part with PCI Express suppor with extended bypass mode frequency range. - Eight Output Differential Buffer
for PCI Express (50-200MHz)
Market Group
PC CLOCK
Additional Info
DB800 Version 2.0 Yellow Cover part with PCI Express suppor with extended bypass mode frequency range. 48-pin SSOP/TSSOP
Add to m yIDT [?] Home > Products > Timing Solutions > PC-Notebook-Server Clocks > PCIe/HCSL Buffers and Generators > 9DB801
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2
1
Related Orderable Parts
Attributes
9DB801BFLF
9DB801BFLFT
9DB801BGLF
9DB801BGLFT
9DB801CFLF
9DB801CGLF
Voltage
3.3 V (PVG48)
3.3 V (PVG48)
3.3 V (PAG48)
3.3 V (PAG48)
3.3 V (PVG48)
3.3 V (PAG48)
Package
SSOP 48
SSOP 48
TSSOP 48
TSSOP 48
SSOP 48
TSSOP 48
Speed
NA
NA
NA
NA
NA
NA
Temperature
C
C
C
C
C
C
Status
Active
Active
Active
Active
Active
Active
Sample
Yes
No
Yes
No
Yes
Yes
Minimum Order
Quantity
180
1000
152
1000
180
152
Factory Order
Increment
30
1000
38
1000
30
38
2
1
Type
Title
Size
Revision Date
Datasheet
9DB801 Datasheet
201 KB
05/21/2007
Model - IBIS
9DB801 IBIS Model
104 KB
03/27/2006
Product Change Notice
PCN#: TB-0510-05 New Shipping Tube for TSSOP/TVSOP/TSSOP Exposed
202 KB
12/13/2005
Related Documents
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