128Mb: x32 SDRAM Features Synchronous DRAM MT48LC4M32B2 - 1 Meg x 32 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdram Features Table 1: * PC100 functionality * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal banks for hiding row access/precharge * Programmable burst lengths: 1, 2, 4, 8, or full page * Auto precharge, includes concurrent auto precharge, and auto refresh modes * Self refresh mode (not available on AT devices) * Auto refresh - 64ms, 4,096-cycle refresh (15.6s/row) (commercial & industrial) - 16ms, 4,096-cycle refresh (3.9s/row) (automotive) * LVTTL-compatible inputs and outputs * Single +3.3V 0.3V power supply * Supports CAS latency (CL) of 1, 2, and 3 Options Key Timing Parameters CL = CAS (READ) latency Speed Grade Clock Frequency -6 -7 166 MHz 143 MHz Table 2: Access Time Cl = 3 Setup Time Hold Time 5.5ns 5.5ns 1.5ns 2ns 1ns 1ns Configurations 4 Meg x 32 Configuration Refresh count Row addressing Bank addressing Column addressing 1 Meg x 32 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 256 (A0-A7) Marking * Configuration 4M32B2 - 4 Meg x 32 (1 Meg x 32 x 4 banks) * Package - OCPL1 TG - 86-pin TSOP II (400 mil) P - 86-pin TSOP II (400 mil) lead-free F5 - 90-ball VFBGA (8mm x 13mm) B5 - 90-ball VFBGA (8mm x 13mm) lead-free * Timing (cycle time) -6 - 6ns (166 MHz) -7 - 7ns (143 MHz) * Die revision :G * Operating temperature range None - Commercial (0 to +70C) - Industrial (-40 to +85C) IT - Automotive (-40C to +105C) AT2 Table 3: 128Mb (x32) SDRAM Part Numbers Part Number MT48LC4M32B2TG MT48LC4M32B2P MT48LC4M32B2F51 MT48LC4M32B2B51 Architecture 4 Meg x 32 4 Meg x 32 4 Meg x 32 4 Meg x 32 Notes: 1. FBGA Device Decoder: www.micron.com/ decoder. Notes: 1. Off-center parting line. 2. Consult Micron for availability. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_1.fm - Rev. L 1/09 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128Mb: x32 SDRAM Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin/Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 COMMAND INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 AUTO REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 SELF REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 BANK/ROW ACTIVATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Burst READ/Single WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32TOC.fm - Rev. L 1/09 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Functional Block Diagram 4 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Assignment (Top View) 86-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 90-Ball VFBGA Pin Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 CLOCK SUSPEND During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 CLOCK SUSPEND During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Example Temperature Test Point Location, 90-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .44 Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Single READ - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Read - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Read - Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Read - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Write - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Write - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Write - Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Write - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 86-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 90-Ball VFBGA (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32LOF.fm - Rev. L 1/09 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 128Mb (x32) SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Truth Table-Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Truth Table - CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Truth Table - Current State Bank n, Command To Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Truth Table - CURRENT STATE BANK n, COMMAND TO BANK m. . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .46 AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32LOT.fm - Rev. L 1/09 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM General Description General Description The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. Automotive Temperature The automotive temperature (AT) option adheres to the following specifications: * 16ms refresh rate * Self refresh not supported * Ambient and case temperature cannot be less than -40C or greater than +105C PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM General Description Figure 1: Functional Block Diagram 4 Meg x 32 SDRAM CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 BANK0 MODE REGISTER REFRESH 12 COUNTER 12 ROWADDRESS MUX 12 12 BANK0 ROWADDRESS LATCH & DECODER 4096 BANK0 MEMORY ARRAY (4,096 x 256 x 32) 4 DQM0- DQM3 SENSE AMPLIFIERS 32 8192 14 ADDRESS REGISTER 2 DATA OUTPUT REGISTER I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A11, BA0, BA1 4 BANK CONTROL LOGIC 32 32 256 (x32) DQ0- DQ31 DATA INPUT REGISTER COLUMN DECODER 8 PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN COLUMNADDRESS COUNTER/ LATCH 8 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Pin/Ball Assignments and Descriptions Pin/Ball Assignments and Descriptions Figure 2: Pin Assignment (Top View) 86-Pin TSOP VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE# CAS# RAS# CS# A11 BA0 BA1 A10 A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 7 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Pin/Ball Assignments and Descriptions Figure 3: 90-Ball VFBGA Pin Assignment (Top View) 1 2 3 DQ26 DQ24 DQ28 4 5 6 7 8 9 VSS VDD DQ23 DQ21 VDDQ VSSQ VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ VDDQ DQ31 NC NC DQ16 VSSQ VSS DQM3 A3 A2 DQM2 VDD A4 A5 A6 A10 A0 A1 A7 A8 NC NC BA1 A11 CLK CKE A9 BA0 CS# RAS# DQM1 NC NC CAS# WE# DQM0 VDDQ DQ8 VSS VDD DQ7 VSSQ VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 DQ13 DQ15 VSS VDD DQ0 DQ2 A B C D E F G H J K L M N P R Ball and Array PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Pin/Ball Assignments and Descriptions Table 4: Pin Descriptions Pin Numbers Symbol Type Description 68 CLK Input 67 CKE Input 20 CS# Input 17, 18, 19 WE#, CAS#, RAS# DQM0- DQM3 Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue and DQM operation will retain its DQ mask capability while CS# is HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the command being entered. 22, 23 BA0, BA1 Input 25-27, 60-66, 24, 21 A0-A11 Input 2, 4, 5, 7, 8, 10, 11, 13, 74, 76, 77, 79, 80, 82, 83, 85, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56 14, 30, 57, 69, 70, 73 3, 9, 35, 41, 49, 55, 75, 81 6, 12, 32, 38, 46, 52, 78, 84 1, 15, 29, 43 44, 58, 72, 86 DQ0- DQ31 Input/ Output NC - VDDQ Supply No connect: These pins should be left unconnected. Pin 70 is reserved for SSTL reference voltage supply. DQ power supply: Isolated on the die for improved noise immunity. VSSQ Supply DQ ground: Provide isolated ground to DQs for improved noise immunity. VDD VSS Supply Supply Power supply: +3.3V 0.3V. Ground. 16, 71, 28, 59 PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN Input Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) during a READ cycle. DQM0 corresponds to DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16-DQ23 and DQM3 corresponds to DQ24-DQ31. DQM0-DQM3 are considered same state when referenced as DQM. Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A10) and READ/WRITE command (column-address A0-A7 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data I/Os: Data bus. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Pin/Ball Assignments and Descriptions Table 5: Ball Descriptions 90-Ball VFBGA Symbol Type Description J1 CLK Input J2 CKE Input J8 CS# Input J9, K7, K8 Input K9, K1, F8, F2 RAS#, CAS#, WE# DQM0-3 Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue and DQM operation will retain its DQ mask capability while CS# is HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input J7, H8 BA0, BA1 Input G8, G9, F7, F3, G1, G2, G3, H1, H2, J3, G7, H9 A0-A11 Input R8, N7, R9, N8, P9, M8, M7, L8, L2, M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2, D3, E2 E3, E7, H3, H7, K2, K3 B2, B7, C9, D9, E1, L1, M9, N9, P2, P7 B8, B3, C1, D1, E9, L9, M1, N1, P3, P8 A7, F9, L7, R7 A3, F1, L3, R3 DQ0- DQ31 I/O NC - VDDQ Supply No connect: These pins should be left unconnected. H7 is a not connect for this part but may be used as A12 in future designs. DQ power: Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ ground: Provide isolated ground to DQs for improved noise immunity. VDD VSS Supply Supply Power supply: Voltage dependant on option. Ground. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) when during a READ cycle. DQM0 corresponds to DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16-DQ23 and DQM3 corresponds to DQ24-DQ31. DQM0-3 are considered same state when referenced as DQM. Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. Address inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data input/output: Data bus 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Functional Description Functional Description In general, this 128Mb SDRAM (1 Meg x 32 x 4 banks) is a quad-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32-bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands must be applied. Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. If desired, the two AUTO REFRESH commands can be issued after the LMR command. The recommended power-up sequence for SDRAMs: 1. Simultaneously apply power to VDD and VDDQ. 2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTLcompatible. 3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. Wait at least 100s prior to issuing any command other than a COMMAND INHIBIT or NOP. 5. Starting at some point during this 100s period, bring CKE HIGH. Continuing at least through the end of this period, 1 or more COMMAND INHIBIT or NOP commands must be applied. 6. Perform a PRECHARGE ALL command. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition 7. Wait at least tRP time, during this time NOPs or DESELECT commands must be given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 10. Issue an AUTO REFRESH command. 11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register. The mode register is programmed via the MODE REGISTER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not programming the mode register upon initialization will result in default settings which may not be desired. Outputs are guaranteed High-Z after the LMR command is issued. Outputs should be High-Z already before the LMR command is issued. 13. Wait at least tMRD time, during which only NOP or DESELECT commands are allowed. At this point the DRAM is ready for any valid command. Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC loops is achieved. Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL), an operating mode and a write burst mode, as shown in Figure 4 on page 13. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10, M11, BA0, and BA1 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with BL being programmable, as shown in Figure 4 on page 13. The BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary BLs. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to BL is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1- A7 when BL = 2; by A2-A7 when BL = 4; and by A3-A7 when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by BL, the burst type and the starting column address, as shown in Table 6 on page 14. Figure 4: Mode Register Definition A11 A10 11 9 10 Reserved A8 A9 8 A6 A7 7 WB Op Mode 6 A5 A4 5 A3 4 3 CAS Latency BT Program M11, M10, BA0, BA1 = "0" to ensure compatibility with future devices. 0 Programmed Burst Length 1 Single Location Access 1 2 Address Bus A0 0 Mode Register (Ax) Burst Length Burst Length A2 A1 A0 Write Burst Mode M9 A1 A2 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved Reserved Reserved M8 M7 M6-M0 Operating Mode 1 0 1 0 0 Defined Standard Operation 1 1 0 Reserved Reserved - - - All other states reserved 1 1 1 Full Page Reserved PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN M3 Burst Type 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Table 6: Burst Definition Burst Length Starting Column Address 2 A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n = A0-A7 (Location 0-256) 4 8 Full Page (256) Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... Cn - 1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported 1. For a BL = 2, A1-A7 select the block-of-two burst; A0 selects the starting column within the block. 2. For a BL = 4, A2-A7 select the block-of-four burst; A0-A1 select the starting column within the block. 3. For a BL = 8, A3-A7 select the block-of-eight burst; A0-A2 select the starting column within the block. 4. For a full-page burst, the full row is selected and A0-A7 select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a BL = 1, A0-A7 select the unique column to be accessed, and mode register bit M3 is ignored. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 5. Table 7 on page 16 indicates the operating frequencies at which each CL setting can be used. Figure 5: CAS Latency T0 T1 T2 READ NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 1 T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 3 DON'T CARE UNDEFINED Reserved states should not be used as unknown operation or incompatibility with future versions may result. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed BL applies to both read and write bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, BL programmed via M0-M2 applies to both read and write bursts; when M9 = 1, the programmed BL applies to read bursts, but write accesses are single-location (nonburst) accesses. Table 7: CAS Latency Allowable Operating Frequency (MHz) PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN Speed CL = 1 CL = 2 CL = 3 -6 -7 50 50 100 100 166 143 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Commands Table 8 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information. Table 8: Truth Table-Commands and DQM Operation Note 1 applies to the entire table NAME (FUNCTION) CS# COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z Notes: 1. 2. 3. 4. 5. 6. 7. 8. RAS# CAS# WE# DQM ADDR DQs NOTES H L L L L L L L X H L H H H L L X H H L L H H L X H H H L L L H X X X L/H8 L/H8 X X X X X Bank/Row Bank/Col Bank/Col X Code X X X X X Valid Active X X 5 6, 7 L - - L - - L - - L - - X L H Op-Code - - X Active High-Z 2 8 8 3 4 4 CKE is HIGH for all commands shown except SELF REFRESH. A0-A11 define the op-code written to the mode register. A0-A11 provide row address, BA0 and BA1 determine which bank is made active. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from or written to. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0 and BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0-DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; and DQM3 controls DQ24-DQ31. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition LOAD MODE REGISTER The mode register is loaded via inputs A0-A11. See the Mode Register heading in the "Register Definition" section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t MRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQMx signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQMx signal was registered LOW, the corresponding DQs will provide valid data. DQM0 corresponds to DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16-DQ23 and DQM3 corresponds to DQ24-DQ31. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Auto Precharge Auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the "Operation" section of this data sheet. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the "Operation" section. The BURST TERMINATE command does not precharge the row; the row will remain open until a PRECHARGE command is issued. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. Regardless of device width, the 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command every 15.625s (commercial and industrial) or 3.906s (automotive) will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms (commercial and industrial) or 16ms (automotive). SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Upon exiting SELF REFRESH mode, AUTO REFRESH commands must be issued every 15.625s or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Self refresh is not supported on automotive temperature (AT) devices. BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. See Figure 6. After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be issued. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 7 on page 21, which covers any case where 2 < tRCD (MIN)/tCK - 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD. Figure 6: Activating a Specific Row in a Specific Bank CLK CKE HIGH CS# RAS# CAS# WE# A0-A11 BA0, BA1 ROW ADDRESS BANK ADDRESS DONT CARE PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 7: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 T0 T1 T2 T3 CLK tCK tCK COMMAND ACTIVE tCK NOP NOP READ or WRITE tRCD (MIN) tRCD (MIN) +0.5 tCK DON'T CARE Notes: 1. tRCD (MIN) = 20ns, tCK = 8ns tRCD (MIN) x tCK where x = number of clocks for equation to be true. READs READ bursts are initiated with a READ command, as shown in Figure 8. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CL after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 9 on page 22 shows general timing for each possible CL setting. Figure 8: READ Command CLK CKE HIGH CS# RAS# CAS# WE# A0-A7 COLUMN ADDRESS A8, A9, A11 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BA0,1 BANK ADDRESS DON'T CARE PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 10 on page 23 for CAS latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. This 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. Figure 9: CAS Latency T0 T1 T2 READ NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 1 T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 3 DON'T CARE UNDEFINED A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 11 on page 24, or each subsequent READ may be performed to a different bank. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 10: Consecutive READ Bursts T0 T1 T2 T3 T4 T5 CLK COMMAND READ NOP NOP NOP NOP READ X = 0 cycles ADDRESS BANK, COL n BANK, COL b DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 DOUT b CL = 1 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP READ NOP X = 1 cycle BANK, COL b DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 DOUT b CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP READ NOP NOP NOP X = 2 cycles BANK, COL b DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 DOUT b CL = 3 DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. Each READ command may be to either bank. DQM is LOW. 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 11: Random READ Accesses T0 T1 T2 T3 T4 COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m CLK DOUT n DQ NOP DOUT x DOUT a DOUT m CL = 1 T0 T1 T2 T3 T4 COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m T5 CLK DOUT n DQ NOP NOP DOUT x DOUT a DOUT m CL = 2 T0 T1 T2 T3 T4 COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m T5 T6 CLK DOUT n DQ NOP DOUT a NOP DOUT x NOP DOUT m CL = 3 DON'T CARE Notes: 1. Each READ command may be to either bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 12: READ-to-WRITE T0 T1 T2 T3 T4 CLK DQM COMMAND READ ADDRESS BANK, COL n NOP NOP NOP WRITE BANK, COL b tCK tHZ DOUT n DQ DIN b tDS DON'T CARE Notes: 1. CL = 3is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required. The DQM input is used to avoid I/O contention, as shown in Figures 12 and 13. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal; provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was low during T4 in Figure 13, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 12 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 13 shows the case where the additional NOP is needed. Figure 13: READ-to-WRITE with Extra Clock Cycle T0 T1 T2 T3 T4 T5 CLK DQM COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP WRITE BANK, COL b tHZ DOUT n DQ DIN b tDS DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a fullpage burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 14 for each possible CL; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). Figure 14: READ-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 0 cycles ADDRESS BANK (a or all) BANK a, COL n DOUT n DQ DOUT n+2 DOUT n+1 BANK a, ROW DOUT n+3 CL = 1 T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 1 cycle ADDRESS BANK (a or all) BANK a, COL n DOUT n DQ BANK a, ROW DOUT n+2 DOUT n+1 DOUT n+3 CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 2 cycles ADDRESS BANK (a or all) BANK a, COL n DOUT n DQ DOUT n+1 BANK a, ROW DOUT n+2 DOUT n+3 CL = 3 DON'T CARE Notes: 1. DQM is LOW. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvan- PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition tage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 15 for each possible CL; data element n + 3 is the last desired data element of a longer burst. Figure 15: Terminating a READ Burst T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ NOP NOP NOP BURST TERMINATE NOP NOP X = 0 cycles ADDRESS BANK, COL n DOUT n DQ DOUT n+2 DOUT n+1 DOUT n+3 CL = 1 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP X = 1 cycle DOUT n DQ DOUT n+2 DOUT n+1 DOUT n+3 CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP NOP X = 2 cycles DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CL = 3 DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. DQM is LOW. 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 17 on page 29). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Figure 16: WRITE Command CLK CKE HIGH CS# RAS# CAS# WE# A0-A7 COLUMN ADDRESS A8, A9, A11 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BA0,1 BANK ADDRESS VALID ADDRESS DON'T CARE Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 18 on page 29. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. This 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19 on page 29, or each subsequent WRITE may be performed to a different bank. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 17: WRITE Burst T0 T1 T2 T3 COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n CLK DQ DIN n DIN n+1 DON'T CARE Notes: Figure 18: 1. BL = 2. DQM is LOW. WRITE-to-WRITE T0 T1 T2 COMMAND WRITE NOP WRITE ADDRESS BANK, COL n CLK DQ DIN n BANK, COL b DIN n+1 DIN b DON'T CARE Notes: Figure 19: 1. DQM is LOW. Each WRITE command may be to any bank. Random WRITE Cycles T0 T1 T2 T3 COMMAND WRITE WRITE WRITE WRITE ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DIN n DIN a DIN x DIN m CLK DQ DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. Each WRITE command may be to any bank. DQM is LOW. 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 20: WRITE-to-READ T0 T1 T2 COMMAND WRITE NOP READ ADDRESS BANK, COL n T3 T4 T5 NOP NOP NOP DOUT b DOUT b+1 CLK DQ DIN n BANK, COL b DIN n+1 DON'T CARE Notes: 1. The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CL = 2 for illustration. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and writes will not be executed. An example is shown in Figure 20. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The "two-clock" write-back requires at least one clock plus time, regardless of frequency, in auto precharge mode. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 21 on page 31. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The precharge will actually begin coincident with the clock-edge (T2 in Figure 21 on page 31) on a "one-clock" tWR and sometime between the first and second clock on a "two-clock" tWR (between T2 and T3 in Figure 21.) In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 21: WRITE-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 NOP ACTIVE NOP CLK tWR = 1 CLK (tCK > tWR) DQM t RP COMMAND ADDRESS WRITE NOP NOP PRECHARGE BANK (a or all) BANK a, COL n BANK a, ROW t WR DQ DIN n DIN n+1 tWR = 2 CLK (when tWR > tCK) DQM t RP COMMAND ADDRESS WRITE NOP NOP PRECHARGE BANK (a or all) BANK a, COL n NOP NOP ACTIVE BANK a, ROW t WR DQ DIN n DIN n+1 DON'T CARE Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 22, where data n is the last desired data element of a longer burst. Figure 22: Terminating a WRITE Burst T0 T1 T2 COMMAND WRITE BURST TERMINATE ADDRESS BANK, COL n (ADDRESS) DIN n (DATA) CLK DQ NEXT COMMAND DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. DQMs are LOW. 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 23: PRECHARGE Command CLK CKE HIGH CS# RAS# CAS# WE# A0-A9, A11 All Banks A10 Bank Selected BA0,1 BANK ADDRESS VALID ADDRESS DON'T CARE PRECHARGE The PRECHARGE command (Figure 23) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank. When all banks are to be precharged, inputs BA0 and BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Power-Down Power-down occurs if CKE is registered low coincident with a NOP or COMMAND INHIBIT when no accesses are in progress (see Figure 24 on page 33). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (tREF or tREFAT ) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 24: Power-Down (( )) (( )) CLK tCKS CKE > tCKS (( )) COMMAND (( )) (( )) NOP NOP tRCD tRAS All banks idle Input buffers gated off Enter power-down mode. ACTIVE Exit power-down mode. tRC DON'T CARE Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered low. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figure 22 on page 31 and Figure 23 on page 32.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Figure 25: CLOCK SUSPEND During WRITE Burst T0 T1 NOP WRITE T2 T3 T4 T5 NOP NOP DIN n+1 DIN n+2 CLK CKE INTERNAL CLOCK COMMAND ADDRESS DIN BANK, COL n DIN n DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. For this example, BL = 4 or greater, and DM is LOW. 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 26: CLOCK SUSPEND During READ Burst T0 T1 T2 T3 T4 T5 T6 CLK CKE INTERNAL CLOCK COMMAND READ ADDRESS BANK, COL n DQ NOP NOP NOP DOUT n+1 DOUT n NOP DOUT n+2 NOP DOUT n+3 DON'T CARE Notes: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW. Burst READ/Single WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed BL. READ commands access columns according to the programmed BL and sequence, just as in the normal mode of operation (M9 = 0). Concurrent Auto Precharge An access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CL later. The precharge to bank n will begin when the READ to bank m is registered (see Figure 27 on page 35). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n will begin when the WRITE to bank m is registered (see Figure 28 on page 35). PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 27: READ With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP Page Active READ - AP BANK n NOP READ - AP BANK m READ with Burst of 4 NOP NOP NOP Idle Interrupt Burst, Precharge tRP - BANK m t RP - BANK n Page Active BANK m Precharge READ with Burst of 4 BANK n, COL a ADDRESS NOP BANK m, COL d DOUT a+1 DOUT a DQ DOUT d DOUT d+1 CL = 3 (BANK n) CL = 3 (BANK m) DON'T CARE Notes: Figure 28: 1. DQM is LOW. READ With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States READ - AP BANK n Page Active NOP NOP NOP READ with Burst of 4 WRITE - AP BANK m NOP NOP Interrupt Burst, Precharge Idle tRP - BANK n Page Active BANK m ADDRESS NOP Write-Back WRITE with Burst of 4 BANK n, COL a t WR - BANK m BANK m, COL d 1 DQM DOUT a DQ DIN d DIN d+1 DIN d+2 DIN d+3 CL = 3 (BANK n) DON'T CARE Notes: 1. DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN d at T4. WRITE with Auto Precharge 2. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (see Figure 29 on page 36). 3. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 30 on page 36). PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 29: WRITE With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP WRITE - AP BANK n Page Active NOP READ - AP BANK m WRITE with Burst of 4 Precharge tWR - BANK n tRP - BANK n NOP tRP - BANK m BANK m, COL d DIN a DQ NOP READ with Burst of 4 BANK n, COL a ADDRESS NOP Interrupt Burst, Write-Back Page Active BANK m NOP DOUT d+1 DOUT d DIN a+1 CL = 3 (BANK m) DON'T CARE Notes: Figure 30: 1. DQM is LOW. WRITE With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP WRITE - AP BANK n Page Active NOP NOP WRITE with Burst of 4 WRITE - AP BANK m NOP Interrupt Burst, Write-Back tWR - BANK n BANK m ADDRESS DQ Page Active NOP Precharge tRP - BANK n t WR - BANK m Write-Back WRITE with Burst of 4 BANK n, COL a NOP BANK m, COL d DIN a DIN a+1 DIN a+2 DIN d DIN d+1 DIN d+2 DIN d+3 DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. DQM is LOW. 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Table 9: Truth Table - CKE Notes 1-4 apply to the entire table CKEn-1 CKEn Current State COMMANDn ACTIONn Notes L L L H L Maintain power-down Maintain self refresh Maintain clock suspend Exit power-down Exit self refresh Exit clock suspend Power-down entry self refresh entry Clock suspend entry H H X X X COMMAND INHIBIT or NOP COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP AUTO REFRESH WRITE or NOP See Table 10 on page 38 5 6 7 H Power-down Self refresh Clock suspend Power-down Self refresh Clock suspend All banks idle All banks idle Reading or writing Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Table 10: Truth Table - Current State Bank n, Command To Bank n Notes 1-6 apply to the entire table Current State Any Idle Row active Read (auto precharge disabled) Write (auto precharge disabled) CS# RAS# CAS# WE# H L L L L L L L L L L L L L L L L X H L L L L H H L H H L H H H L H X H H L L H L L H L L H H L L H H X H H H L L H L L H L L L H L L L Notes: COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start precharge) BURST TERMINATE READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Truncate WRITE burst, start precharge) BURST TERMINATE Notes 7 7 11 10 10 8 10 10 8 10 10 8 9 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 9 on page 37) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 10, and according to Table 11 on page 40. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/auto Starts with registration of a READ command with auto precharge precharge enabled: enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/auto Starts with registration of a WRITE command with auto precharge precharge enabled: enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the SDRAM will be in the all banks idle state. Accessing mode Starts with registration of a LOAD MODE REGISTER command and register: ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging all: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Table 11: Truth Table - CURRENT STATE BANK n, COMMAND TO BANK m Notes 1-6 apply to the entire table; notes appear below and on next page Current State CS# RAS# CAS# WE# Any H L X L L L L L L L L L L L L L L L L L L L L X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L Idle Row activating, active, or precharging Read (auto precharge disabled) Write (auto precharge disabled) Read (with auto precharge) Write (with auto precharge) Notes: COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE Notes 7 7 7, 10 7, 11 9 7, 12 7, 13 9 7, 8, 14 7, 8, 15 9 7, 8, 16 7, 8, 17 9 1. This table applies when CKEn-1 was HIGH and CKEnis HIGH (see Table 9 on page 37) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Starts with registration of a READ command with auto precharge Precharge Enabled: enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Starts with registration of a WRITE command with auto precharge Precharge Enabled: enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 10 on page 23). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (see Figures 12 and 13 on page 25). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (see Figure 20 on page 30), with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank will interrupt the WRITE on bank n when registered (see Figure 18 on page 29). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n will begin when the READ to bank m is registered (see Figure 27 on page 35). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (see Figure 28 on page 35). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to the READ to bank m (see Figure 29 on page 36). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m (see Figure 30 on page 36). PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Electrical Specifications Stresses greater than those listed Table 12 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 12: Absolute Maximum Ratings Parameter Voltage on VDD, VDDQ supply relative to VSS Voltage on inputs, NC or I/O pins relative to VSS Operating temperature, TA (Commercial) TA (Industrial) TA (Automotive) Storage temperature (plastic) Power dissipation Min Max Units -1 -1 +4.6 +4.6 V V C 0 -40 -40 -55 +70 +85 +105 +150 1 C W Temperature and Thermal Impedance It is imperative that the SDRAM device's temperature specifications, shown in Table 13 on page 43, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device's thermal impedances correctly. The thermal impedances are listed in Table 14 on page 43 for the applicable die revision and packages being made available. These thermal impedance values vary according to the density, package, and particular design used for each device. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, "Thermal Applications" prior to using the thermal impedances listed in Table 14. To ensure the compatibility of current and future designs, contact Micron Applications Engineering to confirm thermal impedance values. The SDRAM device's safe junction temperature range can be maintained when the TC specification is not exceeded. In applications where the device's ambient temperature is too high, use of forced air and/or heat sinks may be required in order to satisfy the case temperature specifications. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Table 13: Temperature Limits Parameter Symbol Table 14: 0 -40 -40 80 90 105 0 -40 -40 85 95 110 0 -40 -40 - 70 85 105 260 TJ TA TPEAK Units Notes C 1, 2, 3, 4 C 3 C 3, 5 C 1. MAX operating case temperature, TC, is measured in the center of the package on the top side of the device, as shown in Figures 31 and 32 on page 44. 2. Device functionality is not guaranteed if the device exceeds maximum TC during operation. 3. All temperature specifications must be satisfied 4. The case temperature should be measured by gluing a thermocouple to the top center of the component. This should be done with a 1mm bead of conductive epoxy, as defined by the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is touching the case. 5. Operating ambient temperature surrounding the package. Thermal Impedance Simulated Values Die Revision G Max TC Operating case temperature: Commercial Industrial Automotive Junction temperature: Commercial Industrial Automotive Ambient temperature: Commercial Industrial Automotive Peak reflow temperature Notes: Min Package Substrate JA (C/W) Airflow = 0m/s 86-pin TSOP 2-layer 4-layer 2-layer 4-layer 82.2 55 64.6 48.2 90-ball VFBGA Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN JA (C/W) Airflow = 1m/s JA (C/W) Airflow = 2m/s JB (C/W) JC (C/W) 65 47.2 50.8 41.1 59.7 45.1 45.3 38.1 49.4 40.6 37.5 32.1 10.3 1.8 1. For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots and the values should be viewed as typical. 3. These are estimates; actual results may vary. 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Figure 31: Example Temperature Test Point Location, 54-Pin TSOP: Top View 22.22mm 11.11mm Test point 10.16mm 5.08mm Figure 32: Example Temperature Test Point Location, 90-Ball VFBGA: Top View 8.00mm 4.00mm Test point 13.00mm 6.50mm PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Table 15: DC Electrical Characteristics and Operating Conditions Notes 1, 6 apply to the entire table; notes appear on page 48; VDD = +3.3V 0.3V, VDDQ = +3.3V 0.3V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Input leakage current: Any input 0V VIN VDD (All other pins not under test = 0V) Output leakage current: DQs are disabled; 0V VOUT VDDQ Output levels: )Output high voltage (IOUT = -4mA) Output low voltage (IOUT = 4mA) Table 16: Symbol Min Max Units Notes VDD, VDDQ VIH Vil II 3 2 -0.3 -5 3.6 VDD + 0.3 0.8 5 V V V A 22 22 IOZ -5 5 A VOH VOL 2.4 - - 0.4 V V IDD Specifications and Conditions Notes 1, 6, 11, 13 apply to the entire table; notes appear on page 48; VDD, VDDQ = +3.3V 0.3V Max Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE; tRC = tRC (MIN); CL = 3 Standby current: Power-Down mode; CKE = LOW; All banks idle Standby current: Active mode; CS# = HIGH; CKE = HIGH; All banks active after tRCD met; No accesses in progress Operating current: Burst mode; Continuous burst; READ or WRITE; All banks active, CL = 3 tRFC = tRFC (MIN) Auto refresh current: CL = 3; CKE, CS# = HIGH Self refresh current: CKE 0.2V Table 17: Symbol -6 -7 Units Notes IDD1 190 165 mA 3, 18, 19, 26 IDD2 2 2 mA IDD3 65 55 mA 19, 26 IDD4 195 175 mA IDD5 320 320 mA IDD6 2 2 mA 3, 18, 19, 26 3, 12, 18, 19, 26 4 Capacitance Note 2 applies to the entire table; notes appear on page 48 Parameter Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 45 Symbol Min Max Units CI1 CI2 CIo 2.5 2.5 4.0 4.0 4.0 6.5 pF pF pF Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Table 18: Electrical Characteristics and Recommended AC Operating Conditions Notes 5, 6, 7, 8, 9, 11 apply to the entire table; notes appear on page 48 -6 AC Characteristics Parameter Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out High-Z time Data-out Low-Z time Data-out hold time ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period AUTO REFRESH period ACTIVE to READ or WRITE delay Refresh period (4,096 rows) Refresh period - Automotive (4,096 rows) PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time Write recovery time Exit self refresh to ACTIVE command PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN Symbol CL = 3 CL = 2 CL = 1 CL = 3 CL = 2 CL = 1 CL = 3 CL = 2 CL = 1 Min t AC (3) (2) t AC (1) t AH tAS t CH tCL t CK (3) tCK (2) tCK (1) tCKH tCKS tCMH tCMS tDH tDS tHZ (3) tHZ (2) tHZ (1) tLZ tOH tRAS tRC tRFC tRCD tREF tREF AT t RP tRRD tT tWR 46 Max Min 5.5 7.5 17 tAC tXSR -7 1 1.5 2.5 2.5 6 10 20 1 1.5 1 1.5 1 1.5 5.5 8 17 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns tCK 120K 5.5 8 17 1 2.5 42 70 70 20 64 16 18 12 0.3 1 CLK+ 6ns 12ns 70 Units 1 2 2.75 2.75 7 10 20 1 2 1 2 1 2 5.5 7.5 17 1 2 42 60 60 18 Max 1.2 120K 64 16 20 14 0.3 1 CLK+ 7ns 14ns 70 1.2 ns ns Notes 23 23 23 10 10 10 25 7 24 27 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Table 19: AC Functional Characteristics Notes 5, 6, 7, 8, 9, 11 apply to the entire table; notes appear on page 48 PARAMETER SYMBOL t READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data High-Z during READs WRITE command to input data delay Data-in to ACTIVE command CL = 3 CL = 2 CL = 1 Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to High-Z from PRECHARGE command CL = 3 CL = 2 CL = 1 PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN CCD CKED t PED t DQD tDQM t DQZ t DWD t DAL (3) t DAL (2) t DAL (1) t DPL tBDL tCDL tRDL tMRD tROH (3) tROH (2) tROH (1) t 47 -6 1 1 1 0 0 2 0 5 4 3 2 1 1 2 2 3 2 1 -7 1 1 1 0 0 2 0 5 4 3 2 1 1 2 2 3 2 1 UNITS NOTES t CK CK t CK t CK tCK t CK t CK t CK t CK t CK t CK tCK tCK tCK tCK tCK tCK tCK t Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Notes Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25C; pin under test biased at 1.4V. AC can range from 0pF to 6pF. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA +70C (commercial), -40C TA +85C (industrial), and -40C TA +105C (automotive) ) is ensured. 6. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA +70C and -40C TA +85C for IT parts) is ensured. 7. An initial pause of 100s is required after power-up, followed by two AUTO Refresh commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO Refresh command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 8. AC characteristics assume tT = 1ns. 9. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10. Outputs measured at 1.5V with equivalent load: Q 30pF 11. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 12. AC timing and IDD tests have VIL = 0.25 and VIH = 2.75, with timing referenced to 1.5V crossover point. 13. Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. 14. IDD specifications are tested after the device is properly initialized. 15. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 17. Timing actually specified by tWR. 18. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 19. The IDD current will decrease as CL is reduced. This is due to the fact that the maximum cycle rate is slower as CL is reduced. 20. Address transitions average one transition every two clocks. 21. CLK must be toggled a minimum of two times during this period. 22. Based on tCK = 143 MHz for -7, 166 MHz for -6. 23. VIH overshoot: VIH (MAX) = VDDQ + 1.2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -1.2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Notes 24. The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 25. Auto precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. tCK = 7ns for -7, 6ns for -6. 28. Check factory for availability of specially screened devices having tWR = 10ns. tWR = 1 t CK for 100 MHz and slower (tCK = 10ns and higher) in manual precharge. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Timing Diagrams Figure 33: Initialize and Load Mode Register T0 CLK (( )) tCK T1 tCKH tCKS Tn + 1 (( )) (( )) tCH (( )) (( )) To + 1 tCL (( )) (( )) (( )) (( )) (( )) (( )) (( )) COMMAND (( )) (( )) DQM 0-3 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) A0-A9, A11 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) A10 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) BA0, BA1 DQ tCMS tCMH ALL BANKS SINGLE BANK (( )) (( )) ALL BANKS High-Z (( )) T = 100s (MIN) AUTO REFRESH (( )) NOP NOP (( )) AUTO REFRESH (( )) NOP NOP (( )) LOAD MODE REGISTER tAS NOP tAH ROW CODE tAS ACTIVE tAH ROW CODE BANK (( )) tRP Power-up: VDD and CK stable Tp + 3 tCMS tCMH (( )) PRECHARGE (( )) NOP Tp + 2 (( )) CKE tCMS tCMH Tp + 1 Precharge all banks tRFC tRFC AUTO REFRESH AUTO REFRESH tMRD Program Mode Register 1, 2 DON'T CARE UNDEFINED Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. 2. Outputs are guaranteed High-Z after command is issued. 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 34: Power-Down Mode T0 T1 tCK CLK T2 (( )) (( )) tCL tCKS tCH CKE tCKS Tn + 2 tCKS (( )) tCKH tCMS tCMH COMMAND Tn + 1 PRECHARGE NOP (( )) (( )) NOP NOP ACTIVE DQM 0-3 (( )) (( )) A0-A9, A11 (( )) (( )) ROW (( )) (( )) ROW (( )) (( )) BANK ALL BANKS A10 SINGLE BANK tAS BA0, BA1 tAH BANK(S) High-Z (( )) DQ Two clock cycles Input buffers gated off while in power-down mode Precharge all active banks All banks idle, enter power-down mode All banks idle Exit power-down mode DON'T CARE UNDEFINED Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. Violating refresh requirements during power-down may result in a loss of data. 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 35: Clock Suspend Mode T0 T1 T2 tCK CLK T3 T4 T5 T6 T7 T8 NOP WRITE T9 tCL tCH tCKS tCKH CKE tCKS tCKH tCMS tCMH COMMAND READ NOP NOP NOP NOP NOP tCMS tCMH DQM0-3 tAS A0-A9, A11 tAH COLUMN m 2 tAS tAH tAS tAH COLUMN e 2 A10 BA0, BA1 BANK BANK tAC tOH tAC DQ tLZ DOUT m tHZ DOUT m + 1 tDS tDH DOUT e DOUT e + 1 DON'T CARE UNDEFINED Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. For this example, BL = 2, CL = 3, and auto precharge is disabled. 2. A8, A9, and A11 = "Don't Care." 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 36: Auto Refresh Mode T0 CLK T1 tCK T2 (( )) (( )) tCH (( )) (( )) (( )) CKE tCKS tCKH tCMS tCMH COMMAND PRECHARGE NOP (( )) ( ( NOP )) AUTO REFRESH NOP A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS BA0, BA1 AUTO REFRESH NOP ACTIVE (( )) (( )) (( )) (( )) (( )) (( )) ROW (( )) (( )) (( )) (( )) ROW (( )) (( )) BANK (( )) (( )) High-Z (( )) tRP tRFC (( )) tRFC Precharge all active banks PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN (( )) ( ( NOP )) tAH BANK(S) Notes: To + 1 (( )) (( )) (( )) DQM 0-3 DQ Tn + 1 tCL DON'T CARE UNDEFINED 1. tRFC must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during tRFC. 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 37: Self Refresh Mode T0 CLK T1 tCK tCL tCH T2 tCKS > tRAS CKE COMMAND tCKS tCKH tCMS tCMH PRECHARGE Tn + 1 (( )) (( )) (( )) (( )) (( )) NOP AUTO REFRESH (( )) (( )) (( )) (( )) (( )) (( )) (( )) A0-A9, A11 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) SINGLE BANK tAS BA0, BA1 DQ tAH BANK(S) High-Z (( )) (( )) tRP Precharge all active banks tXSR Enter self refresh mode Exit self refresh mode (Restart refresh time base) CLK stable prior to exiting self refresh mode Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN AUTO REFRESH )) (( )) (( )) ALL BANKS To + 2 tCKS NOP ( ( DQM0-3 A10 To + 1 DON'T CARE UNDEFINED No maximum time limit for self refresh. tRAS(MAX) applies to non-self refresh mode. requires minimum of two clocks regardless of frequency or timing. As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh mode until all rows have been refreshed by the AUTO REFRESH command at the distributed refresh rate, tREF, or faster. However, the following exceptions are allowed: 3a. The DRAM has been in self refresh mode for a minimum of 64s prior to exiting. 3b. tXSR is not violated. 3c. At least two AUTO REFRESH commands are preformed during each 15.6s interval while the DRAM remains out of the self refresh mode. 4. Self refresh mode not supported on automotive temperature (AT) devices. 1. 2. 3. tXSR 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 38: Single READ - Without Auto Precharge T0 T1 T2 tCK CLK T3 T4 T5 NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP READ tCMS PRECHARGE tCMH DQM / DQML, DQMH tAS A0-A9, A11 COLUMN m2 ROW tAS tAH ROW ALL BANKS ROW A10 tAS BA0, BA1 tAH ROW DISABLE AUTO PRECHARGE tAH BANK SINGLE BANK BANK BANK BANK tAC tOH DOUT m DQ tLZ tRCD tHZ CAS Latency tRP tRAS tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16: A9 and A11 = "Don't Care" x32: A8, A9,and A11 = "Don't Care" See Table 18 on page 46. 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 39: Read - With Auto Precharge T0 T1 tCK CLK tCKS T2 T3 T4 T5 T6 T7 T8 NOP ACTIVE tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS NOP NOP NOP NOP tCMH DQM0-3 tAS A0-A9, A11 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m 2 ROW tAS A10 tAH ROW tAH BANK BANK BANK tAC tOH tAC DOUT m DQ tAC tAC tOH tOH tOH DOUT m + 1 DOUT m + 2 DOUT m + 3 tLZ tRCD tHZ tRP CAS Latency tRAS tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. For this example, BL = 4, and CL = 2. 2. A8, A9, and A11 = "Don't Care." 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 40: Alternating Bank Read Accesses T0 T1 tCK CLK T2 T3 T4 T5 NOP ACTIVE T6 T7 T8 READ NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM 0-3 tAS A0-A9, A11 tAS A10 COLUMN m 2 tAH COLUMN b 2 ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW ROW tAH BANK 0 BANK 0 BANK 4 BANK 4 tAC tOH tAC DQ tLZ tRCD - BANK 0 DOUT m tAC BANK 0 tAC tAC tOH tOH tOH DOUT m + 1 DOUT m + 2 DOUT m + 3 tRP - BANK 0 CAS Latency - BANK 0 tAC tOH DOUT b tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRCD - BANK 4 tRRD CAS Latency - BANK 4 DON'T CARE UNDEFINED Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. For this example, BL = 4, and CL = 2. 2. A8, A9, and A11 = "Don't Care." 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 41: Read - Full-page Burst T0 T1 T2 tCL CLK T3 T4 T5 T6 (( )) (( )) tCK tCH tCKS tCMH ACTIVE NOP READ tCMS NOP NOP NOP tAS tCMH tAS NOP BURST TERM NOP NOP (( )) (( )) COLUMN m 2 tAH (( )) (( )) ROW tAS BA0, BA1 Tn + 4 (( )) (( )) tAH ROW (( )) (( )) NOP DQM 0-3 A10 Tn + 3 (( )) (( )) tCMS A0-A9, A11 Tn + 2 tCKH CKE COMMAND Tn + 1 tAH BANK (( )) (( )) BANK tAC tAC DQ tAC tOH tOH Dout m DOUT m+1 tLZ tRCD CAS Latency tAC ( ( )) tOH (( )) (( )) DOUT m+2 tAC tOH DOUT m-1 Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN DOUT m tOH DOUT m+1 tHZ 256 locations within same row Full page completed Notes: tAC tOH DON'T CARE UNDEFINED 1. For this example, CL = 2. 2. A8, A9, and A11 = "Don't Care." 3. Page left open; no tRP. 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 42: Read - DQM Operation T0 T1 tCK CLK tCKS tCKH tCMS tCMH T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP NOP tCL tCH CKE COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM 0-3 tAS A0-A9, A11 tAS A10 COLUMN m 2 tAH ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW DISABLE AUTO PRECHARGE tAH BANK BANK tAC tOH DQ tAC DOUT m tLZ tRCD tHZ tAC tOH DOUT m + 2 tLZ tOH DOUT m + 3 tHZ CAS Latency DON'T CARE UNDEFINED Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. For this example, CL = 2. 2. A8, A9, and A11 = "Don't Care." 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 43: Single Write T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE NOP PRECHARGE NOP ACTIVE tCMS tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAH tAS A10 COLUMN m 3 ROW ROW tAH ALL BANKS ROW tAS BA0, BA1 ROW DISABLE AUTO PRECHARGE tAH BANK SINGLE BANK BANK tDS BANK BANK tDH DIN m DQ tRCD tRAS t WR 2 tRP tRC DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. 2. 3. For this example, BL = 1, and the WRITE burst is followed by a "manual" PRECHARGE. is required between <DIN m> and the PRECHARGE command, regardless of frequency. A8, A9, and A11 = "Don't Care." tWR 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 44: Write - Without Auto Precharge T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 NOP NOP NOP T7 T8 NOP ACTIVE tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE PRECHARGE tCMS tCMH DQM0-3 tAS A0-A9, A11 ROW tAH ALL BANKs ROW ROW tAS BA0, BA1 COLUMN m 3 ROW tAS A10 tAH tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS tDH DIN m DQ tDS tDH DIN m + 1 tDS tDH DIN m + 2 tDS tDH DIN m + 3 t WR 2 tRCD tRAS BANK tRP tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. 2. 3. 4. For this example, BL = 4, and the WRITE burst is followed by a "manual" PRECHARGE. Faster frequencies require two clocks (when tWR > tCK). A8, A9, and A11 = "Don't Care." tWR of 1 CLK available if running 100 MHz or slower. Check factory for availability. 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 45: Write - With Auto Precharge T0 tCK CLK tCKS tCKH tCMS tCMH T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP NOP NOP ACTIVE tCH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM 0-3 tAS A0-A9, A11 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m 3 ROW tAS A10 tAH ROW tAH BANK BANK tDS tDH DIN m DQ BANK tDS tDH DIN m + 1 tDS tDH DIN m + 2 tDS tDH DIN m + 3 tWR 2 tRCD tRAS tRP tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. For this example, BL = 4. 2. Faster frequencies require two clocks (when tWR > tCK). 3. A8, A9, and A11 = "Don't Care." 62 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 46: Alternating Bank Write Accesses T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP ACTIVE tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS NOP ACTIVE NOP WRITE tCMH DQM0-3 tAS A0-A9, A11 tAH COLUMN b3 ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m3 ROW tAS A10 tAH ROW ROW tAH BANK 0 BANK 0 tDS tDH DIN m DQ BANK 1 tDS tDH DIN m + 1 tDS BANK 1 tDH tDS DIN m + 2 tDH DIN m + 3 tDS tDH DIN b tWR2 - BANK 0 tRCD - BANK 0 BANK 0 tDS tDH DIN b + 1 tDS tDH DIN b + 2 tRP - BANK 0 tDS tDH DIN b + 3 tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRRD tRCD - BANK 1 tWR - BANK 1 DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. For this example, BL = 4. 2. Faster frequencies require two clocks (when tWR > tCK). 3. A8, A9, and A11 = "Don't Care." 63 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 47: Write - Full-page Burst T0 T1 T2 tCL CLK T3 T4 T5 (( )) (( )) tCK tCH tCKS tCKH COMMAND tCMH ACTIVE NOP WRITE NOP NOP NOP tCMS tCMH tAS A10 (( )) (( )) NOP BURST TERM NOP (( )) (( )) COLUMN m 1 tAH (( )) (( )) ROW tAS BA0, BA1 tAH ROW tAS Tn + 3 (( )) (( )) DQM 0-3 A0-A9, A11 Tn + 2 (( )) (( )) CKE tCMS Tn + 1 tAH BANK (( )) (( )) BANK tDS tDH DIN m DQ tDS tDH tDS DIN m + 1 tDH DIN m + 2 tRCD tDS tDH DIN m + 3 (( )) (( )) tDS tDH DIN m - 1 256 locations within same row Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop.2, 3 Full page completed DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. 2. 3. A8, A9, and A11 = "Don't Care." must be satisfied prior to PRECHARGE command. Page left open; no tRP. tWR 64 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 48: Write - DQM Operation T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP NOP T6 T7 NOP NOP tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM 0-3 tAS A0-A9, A11 tAH ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m 2 ROW tAS A10 tAH tAH DISABLE AUTO PRECHARGE BANK BANK tDS tDH tDS DIN m DQ tDH DIN m + 2 tDS tDH DIN m + 3 tRCD DON'T CARE Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 1. For this example, BL = 4. 2. A8, A9, and A11 = "Don't Care." 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Package Dimensions Package Dimensions Figure 49: 86-Pin Plastic TSOP (400 mil) 22.22 0.08 0.61 0.50 TYP SEE DETAIL A 2X 0.10 +0.07 0.20 -0.03 2X 2.80 11.76 0.20 10.16 0.08 2X R 0.75 PIN #1 ID +0.03 0.15 -0.02 2X R 1.00 0.25 GAGE PLANE 0.10 1.20 MAX +0.10 0.10 -0.05 PLATED LEAD FINISH: TG (90% Sn, 10% Pb) OR P (100% Sn) 0.01 0.005 THICK PER SIDE 0.80 TYP PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. Notes: PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 0.50 0.10 DETAIL A 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. "2X" means the notch is present in two locations (both ends of the device). 66 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Package Dimensions Figure 50: 90-Ball VFBGA (8mm x 13mm) 0.65 0.05 SEATING PLANE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3%Ag, 0.5% Cu A 0.10 A 90X O0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PREREFLOW DIAMETER IS 0.42 ON A 0.40 SMD BALL PAD SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC 6.40 0.80 TYP BALL A1 ID BALL A1 ID BALL A1 BALL A9 11.20 0.10 CL 13.00 0.10 5.60 0.05 6.50 0.05 CL 3.20 1.00 MAX 4.00 0.05 8.00 0.10 Notes: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. Recommended pad size for PCB is 0.33mm 0.025mm. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80872800/Source: 09005aef80863355 128MbSDRAMx32_2.fm - Rev. L 1/09 EN 67 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.