MT48LC4M32B2P-6IT:G - Micron Technology

Products and specifications discussed herein are subject to change by Micron without notice.

128Mb: x32 SDRAM

Features

PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Synchronous DRAM

MT48LC4M32B2 – 1 Meg x 32 x 4 banks

For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdram

Features

• PC100 functionality

• Fully synchronous; all signals registere d on positi ve

edge of system clock

• Internal pipe lined operatio n; column addres s can be

changed every clock cycle

• Internal banks for hiding row access/pr echarge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• A uto prechar ge, includes concurr ent auto precharge ,

and auto refresh modes

• Self refresh mode (not available on AT device s)

•Auto refresh

–64ms, 4,096-cycle refresh (15.6µs/row)

(commercial & industrial)

–16ms, 4,096-cycle refresh (3.9µs/row)

(automotive)

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Supports CAS latency (CL) of 1, 2, and 3

Notes: 1. Off-center parting line.

2. Consult Micron for availability.

Options Marking

• Configuration

–4 Me g x 32 (1 Meg x 32 x 4 banks) 4M32B2

•Package – OCPL

–86-pin TSOP II (400 mil) TG

–86-pin TSOP II (400 mil) lead-free P

–90-ball VFBGA (8mm x 13mm) F5

–

90-ball VFBGA (8mm x 13mm) lead-free

• Timing (cycle time)

–6ns (166 MHz) -6

–7ns (143 MHz) -7

•Die revision :G

• Operating temperature range

–Commercial (0° to +70°C) None

–Industrial (-40° to +85°C) IT

–Automotive (–40°C to +105°C) AT2

Notes: 1. FBGA Devi ce Decoder: www.micron.com/

decoder.

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed

Grade Clock

Frequency

Access Time Setup

Time Hold

TimeCl = 3

-6 166 MHz 5.5ns 1.5ns 1ns

-7 143 MHz 5.5ns 2ns 1ns

Table 2: Configurations

4 Meg x 32

Configuration 1 Meg x 32 x 4 banks

Refresh count 4K

Row addressing 4K (A0–A11)

Bank addressing 4 (BA0, BA1)

Column addressing 256 (A0–A7)

Table 3: 128Mb (x32) SDRAM Part Numbers

Part Number Architecture

MT48LC4M32B2TG 4 Meg x 32

MT48LC4M32B2P 4 Meg x 32

MT48LC4M32B2F514 Meg x 32

MT48LC4M32B2B514 Meg x 32

PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

128Mb: x32 SDRAM

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Automotive Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin/Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

COMMAND INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

BURST TERMINATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

AUTO REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

SELF REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

BANK/ROW ACTIVATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

READs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

WRITEs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Burst READ/Single WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Temperature and Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

128Mb: x32 SDRAM

List of Figur es

List of Figures

Figure 1: Functional Block Diagram 4 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 2: Pin Assignment (Top View) 86-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 3: 90-Ball VFBGA Pin Assig nment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 5: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 6: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 7: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 8: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 9: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 10: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 11: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 12: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 13: READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 14: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 15: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 16: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 17: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 18: WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 19: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 20: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 21: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 22: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 23: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 24: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 25: CLOCK SUSPEND During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 26: CLOCK SUSPEND During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 27: READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 28: READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 29: WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 30: WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 31: Example Tem pe r ature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 32: Example Temperature Test Point Location, 90-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 33: Initial ize a nd Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 34: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 35: Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 36: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 37: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 38: Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 39: Read – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 40: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 41: Read – Ful l- pag e Burs t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 42: Read – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 43: Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 44: Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 45: Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 46: Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 47: Write – Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 48: Write – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 49: 86-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 50: 90-Ball VFBGA (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

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128Mb: x32 SDRAM

List of Tables

Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 3: 128Mb (x32) SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 4: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 5: Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 6: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 7: CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 8: Truth Table–Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 9: Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 10: Truth Table – Current State Bank n, Command To Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 11: Truth Table – CURRENT STATE BANK n, COMMAND TO BANK m. . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 12: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 13: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 14: Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 15: DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 16: IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 17: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 18: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .46

Table 19: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

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128Mb: x32 SDRAM

General Description

The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing

134,217,728-bits. It is internally configured as a quad-bank DRAM with a synchronous

interface (all signals are registered on the positive edge of the clock sig nal, CLK). Each of

the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses beg in with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank, A0–A11 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row pr echarge that is initiated at the end of the

burst sequence.

The 128Mb SDRAM uses an internal pipelined ar chi tectur e to achieve high-spe ed opera -

tion. This architectur e is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while accessing one of the other three banks

will hide the precharge cycl es and provide seamless, high-speed, ra ndom-access opera-

tion.

The 128Mb SDRAM is designed to operate in 3.3V, lo w-power memory systems. An auto

refresh mode is provided, along with a power-s aving, power-down mode . All inp uts a nd

outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave be tween internal banks to hide precharge time and

the capability to randomly change column addresses on each clock cycl e during a burst

access.

Automotive Temperature

The automotive temperature (AT) option adheres to the following specifications:

• 16ms refresh rate

• Self refresh not supported

• Ambient and case temperature cannot be less than –40°C or greater than +105°C

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128Mb: x32 SDRAM

General Description

Figure 1: Functional Block Diagram 4 Meg x 32 SDRAM

RAS#

CAS#

CLK

CS#

WE#

CKE

A0–A11,

BA0, BA1

DQM0–

DQM3

256

(x32)

8192

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096 x 256 x 32)

BANK0

ROW-

ADDRESS

LATCH

DECODER

4096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ31

32 DATA

INPUT

DATA

OUTPUT

BANK1

BANK0

BANK2 BANK3

4 4

REFRESH

COUNTER

MODE REGISTER

CONTROL

LOGIC

COMMAND

DECODE

ROW-

ADDRESS

MUX

ADDRESS

COLUMN-

ADDRESS

COUNTER/

LATCH

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128Mb: x32 SDRAM

Pin/Ball Assignments and Descriptions

Figure 2: Pin Assignment (Top View) 86-Pin TSOP

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

DQM0

WE#

CAS#

RAS#

CS#

A11

BA0

BA1

A10

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

DQM1

CLK

CKE

DQM3

VSS

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

VSSQ

DQ24

VSS

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128Mb: x32 SDRAM

Pin/Ball Assignments and Descriptions

Figure 3: 90-Ball VFBGA Pin Assignment (Top View)

1234 67895

DQ26

DQ28

CLK

DQM1

DQ11

DQ13

DQ24

DQ27

DQ29

DQ31

DQM3

CKE

DQ8

DQ10

DQ12

DQ15

DQ25

DQ30

DQ9

DQ14

DQ22

DQ17

A10

BA0

CAS#

DQ6

DQ1

DQ21

DQ19

A11

RAS#

DQM0

DQ4

DQ2

DQ23

DQ20

DQ18

DQ16

DQM2

BA1

CS#

WE#

DQ7

DQ5

DQ3

DQ0

Ball and Array

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128Mb: x32 SDRAM

Pin/Ball Assignments and Descriptions

Table 4: Pin Descriptions

Pin Numbers Symbol Type Description

68 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

67 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides precharge power-down and SELF REFRESH

operation (all ba nks idle), active power-down (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous

except after the device enters power-down and self refresh modes, where CKE

becomes asynchronous until after exiting the same mode. The input buffers,

including CLK, are disabled during power-down and self refresh modes,

providing low standby power. CKE may be tied HIGH.

20 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH, but

READ/WRITE bursts already in progress will continue and DQM operation will

retain its DQ mask capability while CS# is HIGH. CS# prov ides for external bank

selection on systems with mul t iple banks. CS# is considered pa rt of the

command code.

17, 18, 19 WE#,

CAS#,

RAS#

Input Command Inputs: WE#, CAS#, and RAS# (alon g with CS#) define the command

being entered.

16, 71, 28, 59 DQM0–

DQM3 Input Input/Output mask: DQM i s sampled HI GH and is an input mask signal for write

accesses and an output enable signal for read accesses. Input data is maske d

during a WRITE cycle. The output buffers are placed in a High-Z state (two-

clock latency) during a READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1

correspo nds to DQ8–DQ 15 , DQM2 corresponds to DQ16–DQ23 and DQM3

corresponds to DQ24–DQ31. DQM0–DQM3 are considered same state when

referenced as DQM.

22, 23 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE, or PRECHARGE command is being applied.

25–27, 60–66, 24,

21 A0–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command (row-

address A0–A10) and READ/WRITE command (column-address A0–A7 with A10

defining auto precharge) to select one location out of the memory array in the

respective bank. A10 is sampled during a PRECHARGE command to determine

if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0 , BA1

(LOW). The address inputs also provide the op-code during a LOAD MODE

2, 4, 5, 7, 8, 10, 11,

13, 74, 76, 77, 79,

80, 82, 83, 85, 31,

33, 34, 36, 37, 39,

40, 42, 45, 47, 48,

50, 51, 53, 54, 56

DQ0–

DQ31 Input/

Output Data I/Os: Data bus.

14, 30, 57, 69, 70,

73 NC – No connect: These pins should be left unconnected. Pin 70 is reserved for SSTL

reference voltage supply.

3, 9, 35, 41, 49, 55,

75, 81 VDDQ Supply DQ power supply: Isolated on the die for improved noise immunity.

6, 12, 32, 38, 46,

52, 78, 84 VSSQ Supply DQ ground: Prov ide isolated gr ound to DQs for improved noise immunity.

1, 15, 29, 43 VDD Supply Power supply: +3.3V ±0.3V.

44, 58, 72, 86 VSS Supply Ground.

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128Mb: x32 SDRAM

Pin/Ball Assignments and Descriptions

Table 5: Ball Descriptions

90-Ball VFBGA Symbol Type Description

J1 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

J2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides precharge power-down and SELF REFRESH

operation (all ba nks idle), active power-down (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous

except after the device enters power-down and self refresh modes, where CKE

becomes asynchronous until after exiting the same mode. The input buffers,

including CLK, are disabled during power-down and self refresh modes,

providing low standby power. CKE may be tied HIGH.

J8 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH, but

READ/WRITE bursts already in progress will continue and DQM operation will

retain its DQ mask capability while CS# is HIGH. CS# prov ides for external bank

selection on systems with mul t iple banks. CS# is considered pa rt of the

command code.

J9, K7, K8 RAS#,

CAS#,

WE#

Input Command inputs: RAS#, CAS#, and WE# (al ong with CS#) de fine the command

being entered.

K9, K1, F8, F2 DQM0–3 Input Input/Output ma sk: DQM is sa mpled HIGH and is an input mask signal for write

accesses and an output enable signal for read accesses. Input data is maske d

during a WRITE cycle. The output buffers are placed in a High-Z state (two-

clock latency) when during a READ cycle. DQM0 corresponds to DQ0–DQ7,

DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and

DQM3 corresponds to DQ24–DQ31. DQM0–3 are considered same state when

referenced as DQM.

J7, H8 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank th e ACTIVE, READ,

WRITE or PRECHARGE command is being applied. These pins also provide the

op-code during a LOAD MODE REGISTER command.

G8, G9, F7, F3, G1,

G2, G3, H1, H2, J3,

G7, H9

A0–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command (row-

address A0–A11) and READ/WRITE command (column-address A0–A7; with A10

defining auto precharge) to select one location out of the memory array in the

respective bank. A10 is sampled during a PRECHARGE command to determine

if all banks are to be precharged (A10 HI GH) or bank selected by BA 0, BA1

(LOW). The address inputs also provide the op-code during a LOAD MODE

R8, N7, R9, N8, P9,

M8, M7, L8, L2,

M3, M2, P1, N2,

R1, N3, R2, E8, D7,

D8, B9, C8, A9, C7,

A8, A2, C3, A1, C2,

B1, D2, D3, E2

DQ0–

DQ31 I/O Data input/output: Data bus

E3, E7, H3, H7, K2,

K3 NC – No connect: These pins should be left unconnected. H7 is a not connect for this

part but may be used as A12 in future designs.

B2, B7, C9, D9, E1,

L1, M9, N9, P2, P7 VDDQ Supply DQ power: Provide isolated power to DQs for improved noi se immu ni ty.

B8, B3, C1, D1, E9,

L9, M1, N1, P3, P8 VSSQ Supply DQ groun d: Provide isolated ground to DQs for improved noise immunity.

A7, F9, L7, R7 VDD Supply Power supply: Voltage dependant on option.

A3, F1, L3, R3 VSS Supply Ground.

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128Mb: x32 SDRAM

Functional Description

In general, this 128Mb SDRAM (1 Meg x 32 x 4 banks) is a quad-bank DRAM that oper-

ates at 3.3V and includes a synchronous interface (all signals are registered on the posi-

tive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096

rows by 256 columns by 32-bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses beg in with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1

select the bank, A0–A11 select the row). The address bits (A0–A7) registered coincident

with the READ or WRITE command are used to select the starting column location for

the burst access.

Prior to normal ope ration, the SDR AM must be initialized . The fo ll owing sections

provide detailed information covering device initialization, register definition,

command descriptions and device operation.

Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational

procedures other than those specified may result in undefined operation. Once power is

applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is

defined as a signal cycling within timing constraints specified for the clock pin), the

SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND

INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least

through the end of this pe riod, C O MMAND INHIBIT or NOP commands must be

applied.

Once the 100µs delay has been satisfied wi th at least one COMMAND INHIBIT or NOP

command having been applied, a PRECHARGE command should be applied. All banks

must then be pr echarged, thereby placing the device in the all banks idle state.

Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the

AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-

ming. Because the mode register will power up in an unknown state, it must be loaded

prior to applying any operational command. If desired, the two AUTO REFRESH

commands can be issued after the LMR command.

The recommended power-up sequence for SDRAMs:

1. Simultaneously apply power to VDD and VDDQ.

2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-

compatible.

3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing

constraints speci fie d for th e c loc k pin.

4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT

or NOP.

5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least

through the end of this period, 1 or more COMMAND INHIBIT or NOP commands

must be applied.

6. Perform a PRECHARGE ALL command.

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128Mb: x32 SDRAM

7. Wait at least tRP time , duri ng this ti me NOP s or DESELECT commands m ust be giv en.

All banks will complete their precharge, thereby placing the device in the all banks

idle state.

8. Issue an AUTO REFRESH command.

9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

10. Issue an AUTO REFRESH command.

11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

12. The SDRAM is no w ready for mode register programming. Because the mode register

will power up in an unknown state, it should be loaded with desired bit values prior to

applying any operational command. Using the LMR command, program the mode

with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again

or the device loses power. Not programming the mode re gister upon initialization will

result in default settings which may not be desired. Outputs are guaranteed High-Z

after the LMR command is issued. Outputs should be High-Z already before the LMR

command is issued.

13. Wait at least tMRD time, during which only NOP or DESELECT commands are

allowed.

At this point the DRAM is ready for any valid command.

Note: If desired, more than two AUTO REFRESH commands can b e is sue d in the sequence.

After steps 9 and 10 are complete, repeat them until the desired number of AUTO

REFRESH + tRFC loops is achieved.

Mode Register

The mode register is used to define the specific mode of operation of the SDRAM. This

definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL),

an operating mode and a write burst mode, as shown in Figure 4 on page 13. The mode

stor ed information until it is programmed again or the device loses power.

M ode register bits M0–M2 specify the, M3 s pecif ies the type of b urst (sequ entia l or i nte r-

leaved), M4–M6 specify the CL, M7 and M8 spe cify the oper ating mode , M9 specifi es the

write burst mode, and M10, M11, BA0, and BA1 are reserved for future use.

The mode regi ster must be loaded when all banks are idle, and the controller mus t wait

the specified time before initiating the subs equent operation. Violating either of these

requirements will result in unspecified operation.

Burst Length (BL)

Re ad and write access es to the SDRAM ar e bur st oriented, wi th BL being progr ammable,

as shown in Figure 4 on page 13. The BL determines the maximum number of column

locations that can be accessed for a give n READ or WRITE command. Burst lengths of 1,

2, 4, or 8 locations are available for both the sequential and the interleaved burst types,

and a full-page burst is available for the sequential type. The full-page burst is used in

conjunction with the BURST TERMINATE command to generate arbitrary BLs.

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128Mb: x32 SDRAM

Reserved states should not be used, as unknown operation or incompatibility with

future versions may result.

When a READ or WRITE command is issued, a block of columns equal to BL is effectively

selected. All accesses for that burst take place within this block, meaning that the burst

will wrap within the block if a boundary is reached. The block i s uniquely selected b y A1–

A7 when BL = 2; by A2–A7 when BL = 4; and by A3–A7 when BL = 8. The remaining (least

significant) address bit(s) is (are) used to select the starting location within the block.

Full-page bursts wrap within the page if the boundary is reached .

Burst Type

Accesse s within a given b urst may be progr ammed to be eithe r sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by BL, the burst type and the

starting column address, as shown in Table 6 on page 14.

Figure 4: Mode Register Definition

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

–

Defined

–

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Ax)

Address Bus

976543

8210

M6–M0

M8 M7

Op Mode

A10

A11

Reserved WB

Write Burst Mode

Programmed Burst Length

Single Location Access

Program

M11, M10, BA0, BA1 = “0”

to ensure compatibility

with future devices.

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128Mb: x32 SDRAM

Notes: 1. For a BL = 2, A1–A7 select the block-of-two burst; A0 selects the starting column within the

block.

2. For a BL = 4, A2–A7 select the block-of-four burst; A0–A1 select the sta rting column within

the block.

3. For a BL = 8, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within

the block.

4. For a full-page burst, the full row is selected and A0–A7 select the starting column.

5. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

6. For a BL = 1, A0–A7 select the unique column to be accessed, and mode register bit M3 is

ignored.

Table 6: Burst Definition

Burst

Length Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential Ty pe = Interleaved

2A0

00-1 0-1

11-0 1-0

4A1A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

8A2A1A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full Page

(256) n = A0–A7 (Location

0–256) Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

Cn - 1, Cn…

Not supported

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128Mb: x32 SDRAM

CAS Latency (CL)

The CL is the delay, in clock cycles, between the registration of a READ command and

the availability of the first piece of output data. The latency can be set to one, two or

three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data

will be available by clock edge n + m. The DQs will start driving as a result of the clock

edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,

the data will be valid by clock edge n + m. For example, assuming that the clock cycle

time is such that all relevant access times are met, if a read command is registered at T0

and the latency is programmed to two clocks, the DQs will start driving after T1 and the

data will be valid by T2, as shown in Figure 5. Table 7 on page 16 indicates the operating

frequencies at which each CL setting can be use d.

Figure 5: CAS Latency

Reserved states should not be used as unkno wn operation or incompatibility with future

versions may result.

CLK

T2T1 T3T0

CL = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CL = 1

OUT

tOH

COMMAND NOPREAD

tAC

CLK

T2T1 T3T0

CL = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

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128Mb: x32 SDRAM

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combi-

nations of values for M7 and M8 are reserved for future use and/or test modes. The

programmed BL applies to both read and write bursts.

Test modes and reserved states should not be used because unknown operation or

incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, BL programmed via M0–M2 applies to both read and write bursts; when

M9 = 1, the programmed BL applies to read bursts, but write accesses are single-location

(nonburst) accesses.

Table 7: CAS Latency

Speed

Allowable Operating Frequency (MHz)

CL = 1 CL = 2 CL = 3

-6 ≤ 50 ≤ 100≤ 166

-7 ≤ 50 ≤ 100 ≤ 143

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128Mb: x32 SDRAM

Commands

Table 8 provides a quick reference of available commands. This is followed by a written

description of each command. Three additional Truth Tables appear following the Oper-

ation section; these tables provide current state/next state information.

Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0–A11 define the op-code written to the mode register.

3. A0–A11 provide row address, BA0 and BA1 determine which bank is made active.

4. A0–A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersis-

tent), while A10 LOW disables the auto precharge feature; BA0 and BA1 determine which

bank is being read from or written to.

5. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks pre-

charged and BA0 and BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except

for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock

delay). DQM0 controls DQ0–DQ7; DQM1 controls DQ8–DQ15; DQM2 controls DQ16–DQ23;

and DQM3 controls DQ24–DQ31.

COMMAND INHIBIT

The COMMAND INHIBIT function pr ev ents new commands from being executed b y the

SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively des e-

lected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is

selected (CS# is L O W). This prevents unwanted commands fr om being r eg ister ed during

idle or wait states. Operations already in progress are not affected.

Table 8: Truth Table–Commands and DQM Operation

Note 1 applies to the entire table

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES

COMMAND INHIBIT (NOP) HXXXX X X

NO OPERATION (NOP) LHHHX X X

ACTIVE (Select bank and act iva t e ro w) L L H H X Bank/Row X 3

READ (Select bank and column, and start READ burst) L H L H L/H8 Bank/Col X 4

WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid 4

BURST TERMINATE LHHLX X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or SELF REFRESH

(Enter self refresh mode) LLLHX X X 6, 7

LOAD MODE REGISTER L L L L X Op-Code X 2

Write Enable/Output Enable ––––L – Active8

Write Inhibit/Output High-Z ––––H –High-Z8

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128Mb: x32 SDRAM

LOAD MODE REGISTER

The mode register is loaded via inputs A0–A11. See the Mode Register heading in the

“R egister D efinition” section. The LOAD MODE REGISTER command can only be issued

when all banks are idle, and a subsequent executable command cannot be issued until

tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the

addre ss pro vided on inputs A0–A11 selects the r o w. This ro w remains activ e (or open) for

accesses until a pr ec har ge command i s issued to that bank. A precharge command must

be issued befor e opening a different row in the same bank.

READ

The READ command is used to initiate a burst r ead access to an activ e row. The value on

the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0–A7

selects the starting column location. The va lue on input A10 determines whether or not

auto precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the read burst; if auto precharge is not selected, the row will

remai n open for subsequent ac cesses . Read data appears on the DQs s ubject to the logic

level on the DQM inputs two clocks earli er. If a given DQMx signal was regi stered HIGH,

the corres ponding DQs will be H igh-Z two clocks later; if the DQMx signal was r egister ed

LOW, the corresponding DQs w il l provide valid data. DQM0 corresponds to DQ 0–D Q 7,

DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3

corresponds to DQ24–DQ31.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0–A7

selects the starting column location. The value on input A10 determines whether or not

auto precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the writ e burs t; if auto precharge is not selec te d , th e row will

remai n open for subsequent accesses. I nput data appearing on the DQs is written to the

memor y array subject to the DQM input logic le ve l appe aring coincide nt with the data.

If a given DQM signal is registered LOW, the corresponding data will be written to

memory; if the DQM signal is registered HIGH, the corresponding data inputs will be

ignored, and a write will not be executed to that byte/column location.

PRECHARGE

The PRECHAR GE command is used to deactivate the open row in a par ticular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

specifie d time (tRP) after the pr echarge command is issued. Input A10 determines

whether one or all banks ar e to be precharged, and in the case where only one bank is to

be precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated

as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be acti-

vated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge

Auto pr echarge is a feature which performs the same individual-bank precharge func-

tion described above, without r equiring an explicit command. This is accompl ished by

using A10 to enable auto precharge in conjunction with a specifi c REA D or WRITE

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128Mb: x32 SDRAM

command. A precharge of the bank/ row that is addressed with the READ or WRITE

command is automatically performed upon completion of the READ or WRITE burst,

except in the full-page burst mode , wher e auto prechar ge does not apply. A uto pr echarge

is nonpersistent in that it is ei ther enabled or disabled for each individ u al Read or Write

command.

auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. The user must not issue another command to the same bank until the precharge

time (tRP) is completed. This is determined as if an explicit PRECHARGE command was

issued at the earliest possible time, as described for each burst type in the “Operation”

section of this data sheet.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page

bursts. The most recently re gistered READ or WRITE command prior to the BURST

TERMINATE command will be truncated, as shown in the “Operation” section.

The BURST TERMINATE command does not precharge the row; the row will remain

open until a PRECHARGE command is issued.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) refresh in conv entional DRAMs. This command is nonper-

sistent, so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh controller. This makes the address

bits “Don’t Care” during an A UTO REFRESH command. Regardless of device width, the

128Mb SDRAM requires 4,0 96 AUTO REFRESH cycles every 64ms (commercial and

industrial) or 16ms (automotive). Providing a distributed AUT O REFRESH command

every 15.625µs (commercial and industrial) or 3.906µs (automotive) will meet the

refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO

REFRESH commands can be issued in a burst at the minimum cycl e rate ( tRFC), once

every 64ms (commercial and industrial) or 16ms (automotive).

SELF REFRESH

The SELF REFRESH co mm and can be use d to retain data in the SDRAM, even if the rest

of the system is powered down. When in the self r efresh mode, the SDRAM retains data

without external clo ck ing. The SELF REF RESH com m and is initiated like an AU TO

REFRESH command except CKE is disabled (LO W). Once the SELF REFRESH command

is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of

CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides its own internal clocking,

causing it to perform its o wn auto r e fr esh cy cles . The SDRAM must r emain in self r efr esh

mode for a minimum period equal to tRAS and may remain in self refresh mode for an

indefinite period beyond that.

The procedur e for exit ing self r efresh requir es a seque nce of commands. First, CLK must

be stable (stable clock is defined as a signal cycling within timing constraints specified

for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must

have NOP commands issued (a minimum of two clocks ) for tXSR because time is

required for the completion of any internal refresh in progress.

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128Mb: x32 SDRAM

Upon exiting SELF REFRESH mode, AUTO REFRESH commands must be issued every

15.625µs or less as both SELF REFRESH and A UTO REFRESH utilize the row refresh

counter.

Self refresh is not supported on automotive temper ature ( AT) devices.

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row

in that bank must be “opened.” This is accomplished via the ACTIVE command, which

selects both the bank and the row to be activated. See Figure 6.

After opening a ro w (issuing an A CTIVE command), a RE AD or WRITE command may be

issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

issued. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is reflected in Figure 7 on page 21, which covers

any case where 2 < tRCD (MIN)/tCK - 3. (T he same procedure is used to convert other

specificati o n limits from time units to clock cycles.)

A subsequent ACTIVE command to a differ ent row in the same bank can only be issued

after the previous active row has been “closed” (precharged). The minimum time

interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which resul ts in a r eduction of total r o w-access o verhead. The minimum

time interval between successive ACTIVE commands to different banks is defined by

tRRD.

Figure 6: Activating a Specific Row in a Specific Bank

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A11

ROW

ADDRESS

DON´T CARE

HIGH

BA0, BA1

BANK

ADDRESS

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128Mb: x32 SDRAM

Figure 7: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3

Notes: 1. tRCD (MIN) = 20ns, tCK = 8ns

tRCD (MIN) × tCK

where x = number of clocks for equation to be true.

READs

READ bursts are initiated with a READ command, as shown in Figure 8.

The starting column and bank addresses are provided with the READ command, and

auto precharge is either enabled or disabled for that burst access. If auto precharge is

enabled, the row being accessed is precharged at the completion of the burst. For the

generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will

be available following the CL after the READ command. Each subsequent data-out

element will be valid by the next positive clock edge. Figure 9 on page 22 shows general

timing for each possible CL setting.

Figure 8: READ Command

CLK

T2T1 T3T0

COMMAND NOPACTIVE READ or

WRITE

NOP

RCD (MIN)

tRCD (MIN) +0.5 tCK

tCK tCK tCK

DON’T CARE

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A0–A7

A10

BA0,1

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A8, A9, A11

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128Mb: x32 SDRAM

Upon completion of a burst, assuming no other commands have been initiated, the DQs

will go High-Z . A full-page burst will continue until terminated. (At the end of the page , it

will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a subsequent READ com ma nd, and

data from a fixed-length READ burst may be immediately followed by data from a READ

command. In either case, a continuous flow of data can be maintained. The first data

element from the new burst follows either the last element of a completed burst or the

last desired data element of a longer burst that is being truncated. The new READ

command should be issued x cycles before the clock edge at which the last desir ed data

element is valid, where x = CL - 1. This is shown in Figure 10 on page 23 for CAS latencies

of one, two and three; data element n + 3 is either the last of a burst of four or the last

desir ed of a longer burst. This 128Mb SDRAM uses a pipelined architecture and there-

fore does not require the 2n rule associated with a prefetch architecture.

Figure 9: CAS Latency

A READ command can be initiated on any clock cycle following a previous READ

command. Full-speed random read accesses can be performed to t he same bank, as

shown in Figure 11 on page 24, or each subsequent READ may be performed to a

different bank.

CLK

T2T1 T3T0

CL = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CL = 1

OUT

tOH

COMMAND NOPREAD

tAC

CLK

T2T1 T3T0

CL = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

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128Mb: x32 SDRAM

Figure 10: Consecutive READ Bursts

Notes: 1. Each READ command may be to either bank. DQM is LOW.

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

X = 0 cycles

CL = 1

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

X = 1 cycle

CL = 2

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ NOP

X = 2 cycles

CL = 3

DON’T CARE

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128Mb: x32 SDRAM

Figure 11: Random READ Accesses

Notes: 1. Each READ command may be to either bank. DQM is LOW.

Data from any READ burst may be truncated with a subsequent WRITE command, and

data from a fixed-length READ burs t may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations). Th e WRI TE burst may be

initiated on the clock edge immediately following the last (or last desired) data element

from the READ burst, provided that I/O contention can be avoided. In a given system

design, ther e may be a possibility that the device driving the input data will go Low-Z

before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur

between the last read data and the WRITE command.

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,

COL n

DON’T CARE

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CLK

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

OUT

READ READ READ

BANK,

COL aBANK,

COL xBANK,

COL m

CL = 1

CL = 2

CL = 3

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128Mb: x32 SDRAM

Figure 12: READ-to-WRITE

Notes: 1. CL = 3is used for illustration. The READ command may be to any bank, and the WRITE com-

mand may be to any bank. If a burst of one is used, then DQM is not required.

The DQM input is used to avoid I/O contention, as shown in Figures 12 and 13. The

DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command

(DQM latency is two clocks for output buffers) to sup press data-out from the READ.

Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z),

regardless of the state of the DQM signal; provided the DQM was active on the clock just

prior to the WRITE command that truncated the READ command. If not, the second

WRITE will be an invalid WR ITE. For example, if DQM was low during T4 in Figure 13,

then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is

zero clocks for input buffers) to ensure that the written data is not masked. Figure 12

shows the case where the clock frequency allows for bus contention to be avoided

without adding a NOP cycle, and Figure 13 shows the case where the additional NOP is

needed.

Figure 13: READ-to-WRITE with Extra Clock Cycle

Notes: 1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-

mand may be to any bank.

DON’T CARE

READ NOP NOP WRITE

NOP

CLK

T2T1 T4T3T0

DQM

OUT

COMMAND

ADDRESS

BANK,

COL nBANK,

COL b

tHZ

tCK

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

DOUT n

T2T1 T4T3T0

COMMAND

ADDRESS

BANK,

COL n

WRITE

DIN b

BANK,

COL b

tHZ

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128Mb: x32 SDRAM

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE

command to the same bank (provided that auto precharge was not activated), and a full-

page burst may be truncated with a PRECHARGE command to the same bank. The

PRECHAR GE command should be issued x cycles before the clock edge at which the last

desired data element is valid, where x = CL - 1. This is shown in Figure 14 for each

possible CL; data element n + 3 is either the last of a burst of four or the last desired of a

longer burst. Following the PRECHARGE command, a subsequent command to the

same bank cannot be issued until tRP is met. Note that part of the row precharge time is

hidden during the access of the last data element(s).

Figure 14: READ-to-PRECHARGE

Notes: 1. DQM is LOW.

In the case of a fixed-length burst being executed to completion, a PRECHARGE

command issued at the optimum time (as desc ribed abov e) provi des the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE ACTIVE

tRP

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE ACTIVE

tRP

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK a,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE ACTIVE

tRP

BANK a,

ROW

BANK

(a or all)

DON’T CARE

X = 0 cycles

CL = 1

X = 1 cycle

CL = 2

CL = 3

BANK a,

COL nBANK a,

ROW

BANK

(a or all)

BANK a,

COL nBANK a,

ROW

BANK

(a or all)

X = 2 cycles

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128Mb: x32 SDRAM

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHARG E command is that it can be used to truncate fixed-leng th or full-page bursts .

Full-page READ bursts can be truncated with the BURST TERMINATE command, and

fixed-length READ bursts may be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at which the last desired data element is

valid, where x = CL - 1. This is shown in Figure 15 for each possible CL; data element n +

3 is the last desired data element of a longer burst.

Figure 15: Terminating a READ Burst

Notes: 1. DQM is LOW.

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE NOP

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE NOP

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE NOP

X = 0 cycles

CL = 1

X = 1 cycle

CL = 2

CL = 3

X = 2 cycles

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128Mb: x32 SDRAM

WRITEs

WRITE bursts are initiated with a WRITE command, as shown in Figure 16.

The starting column and bank addresses are provided with the WRITE command, and

auto prec harge i s either enabled or disabled for that acc ess . If auto pr e charge is enab led,

the row being accessed is precharged at the completion of the burst. For the generic

WRITE commands us ed in the fol lowing illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident with

the WRITE command. Subsequent data elements will be registered on each successive

positive clock edge. Upon completion of a fixe d-length burst, assuming no other

commands have been initiated, the DQs will remain H ig h-Z and any additional input

data will be ignored (see Figure 17 on page 29). A full-page burst will continue until

terminated. (At the end of the page, it will wrap to column 0 and continue.)

Figure 16: WRITE Command

Data for any WRITE burst may be truncated with a subsequent WRITE command, and

data for a fixed-length WRI TE burst may be immediately followed by data for a WRITE

command. The new WRITE command can b e issued on any c lock follo wi ng the pr evious

WRITE command, and the data provided coincident with the new command applies to

the new command. An example is shown in Fi gur e 18 on page 29. Data n + 1 is either the

last of a burst of two or the last desired of a longer burst. This 128Mb SDRAM uses a

pipelined architecture and therefore does no t require the 2n rule associated with a

prefetch architecture. A WRITE command can be initiated on any clock cycle following a

previous WRITE command. Full-speed random wr it e ac ce ss es within a page can be

performed to the same bank, as shown in Figure 19 on page 29, or each subsequent

WRITE may be performed to a different bank.

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

DON’T CARE

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A0–A7

A10

BA0,1

A8, A9, A11

VALID ADDRESS

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128Mb: x32 SDRAM

Figure 17: WRITE Burst

Notes: 1. BL = 2. DQM is LOW.

Figure 18: WRITE-to-WRITE

Notes: 1. DQM is LOW. Each WRITE command may be to any bank.

Figure 19: Random WRITE Cycles

Notes: 1. Each WRITE command may be to any bank. DQM is LOW.

CLK

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

NOP NOP

DON’T CARE

WRITE

DIN

n + 1

NOP

BANK,

COL n

CLK

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,

COL nBANK,

COL b

n + 1 D

DON’T CARE

CLK

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,

COL n

DIN

aDIN

xDIN

WRITE WRITE WRITE

BANK,

COL aBANK,

COL xBANK,

COL m

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128Mb: x32 SDRAM

Figure 20: WRITE-to-READ

Notes: 1. The WRITE command may be to any bank, and the READ command may be to any bank.

DQM is LOW. CL = 2 for illustration.

Data for any WRITE burst may be truncated with a subsequent READ command, and

data for a fixed -length WRITE burst m ay be imme diately fol lowed by a REA D command.

Once the READ command is registered, the data inputs will be ignored, and writes will

not be executed. An example i s shown in Figure 20. Data n + 1 is either the last of a burst

of two or the last desired of a longer burst.

Data for a fixed-length WRITE burst may be followed by, or truncated with, a

PRECHARGE command to the same bank (provided that auto precharge was not acti-

vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to

the same bank. The PRECHARGE command should be issued tWR after the clock edge at

which the last desired input data element is registered. The “two-clock” write-back

requires at least one clock plus time, r egardless of frequency, in auto prechar ge mode . I n

addition, when truncating a WRITE burst, the DQM signal must be used to mask input

data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE

command. An example is shown in Figure 21 on page 31. Data n + 1 is either the last of a

burst of two or the last desired of a longer burst. Follo wing the PRECHAR GE command, a

subsequent command to the same bank cannot be issued until tRP is met. The

precharge will actually begin coincident with the clock-edge (T2 in Figure 21 on page 31)

on a “one-clock ” tWR and sometime between the first and second clock on a “two-clock”

tWR (between T2 and T3 in Figure 21.)

In the case of a fixed-length burst being executed to completion, a PRECHARGE

command issued at the optimum time (as desc ribed abov e) provi des the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHAR GE command is that it can be used to truncate fixed-length or full-page bursts.

DON’T CARE

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK,

COL n

n + 1 D

OUT

READ NOP NOP

BANK,

COL b

NOP

OUT

b + 1

T4 T5

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Figure 21: WRITE-to-PRECHARGE

Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE

command. When truncating a WRITE burst, the inpu t data applied coincident with the

BURST TERMINATE command will be ignored. The last data written (provided that

DQM is LOW at that time) will be the input data applied one clock previous to the

BURST TERMI NATE command. This is shown in Figure 22, where data n is the last

desir ed data element of a longer burst.

Figure 22: Terminating a WRITE Burst

Notes: 1. DQMs are LOW.

DON’T CARE

DQM

CLK

T2T1 T4T3T0

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n D

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

NOP

WR = 2 CLK (when

WR >

CK)

WR = 1 CLK (

CK >

WR)

DON’T CARE

CLK

T2T1T0

COMMAND

ADDRESS

BANK,

COL n

WRITE BURST

TERMINATE NEXT

COMMAND

DIN

(ADDRESS)

(DATA)

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128Mb: x32 SDRAM

Figure 23: PRECHARGE Command

PRECHARGE

The PRECHARGE command (Figure 23) is used to deactivate the open row in a par tic-

ular bank or the open ro w in all banks . The bank(s) will be avail able for a subsequent ro w

access some specified time (tRP) after the precharge comm a nd is iss u ed . Input A10

determines whether one or all banks are to be prechar ged, and in the case where only

one bank is to be precharged, inputs BA0 and BA1 select the bank. When al l banks are to

be precharged, inputs BA0 and BA1 are treated as “Don’t Car e.” Once a bank has been

precharged, it is in the idle state and must be activated prior to any READ or WRITE

commands being issued to that bank.

Power-Down

Power-down occurs if CKE is registered low coincident with a NOP or COMMAND

INHIBIT when no accesses are in progress (see Figure 24 on page 33). If power-down

occurs when all banks are idle, this mode is referred to as precharge power-do wn; if

power-down occurs when there is a row active in eit h er bank, this mode is referred to as

active power-down. Entering power-down deactivates the input and output buffers,

excluding CKE, for maximum power savings while in standby. The device may not

remain in the power -down state longer than the refr esh period (tREF or tREFAT) since no

refresh operations are performed in this mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE

HIGH at the desired clock edge (meeting tCKS).

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

DON’T CARE

HIGH

All Banks

Bank Selected

A0-A9, A11

BA0,1 BANK

ADDRESS

VALID ADDRESS

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128Mb: x32 SDRAM

Figure 24: Power-Down

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data pr esent on the input pins at the time of a

suspended internal clock edge is ignored; any data present on the DQ pins remains

driven; and burst counters are not incremented, as long as the clock is sus pen ded. (See

examples in Figure 22 on page 31 and Figure 23 on page 32.)

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related

operation will resume on the subsequent positive clock edge.

Figure 25: CLOCK SUSPEND During WRITE Burst

Notes: 1. For this example, BL = 4 or greater, and DM is LOW.

DON’T CARE

tRAS

tRCD

tRC

All banks idle Input buffers gated off

Exit power-down mode.

()()

tCKS > tCKS

COMMAND

NOP ACTIVE

Enter power-down mode.

NOP

CLK

CKE

()()

DON’T CARE

DIN

COMMAND

ADDRESS

WRITE

BANK,

COL n

DIN

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

INTERNAL

CLOCK

NOP

DIN

n + 1 DIN

n + 2

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128Mb: x32 SDRAM

Figure 26: CLOCK SUSPEND During READ Burst

Notes: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

Burst READ/Single WRITE

The burst read/single write mode is entered by progr a mming the write burst mode bit

(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the

access of a single column location (burst of one), regardless of the programmed BL.

READ commands access columns according to the programmed BL and sequence, just

as in the normal mode of operation (M9 = 0).

Concurrent Auto Precharge

An access command to (READ or WRITE) another bank while an access command with

auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM

supports con current auto precharge. Micron SDRAMs support concurrent auto

precharge. Four cases where concurrent auto precharge occurs are defined below.

READ with Auto Precharge

1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-

rupt a READ on bank n, CL la ter. The precharge to bank n will begin when the READ

to bank m is re gistered (see Figur e 27 on page 35).

2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a READ on bank n when register ed. DQM s hould be us ed two clocks prior to

the WRITE command to prevent bus conten tion. The precharge to bank n will begin

when the WRITE to bank m is registered (see Figure 28 on page 35).

DON’T CARE

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

CKE

INTERNAL

CLOCK

NOP

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128Mb: x32 SDRAM

Figure 27: READ With Auto Precharge Interrupted by a READ

Notes: 1. DQM is LOW.

Figure 28: READ With Auto Precharge Interrupted by a WRITE

Notes: 1. DQM is HIGH at T2 to prevent DOUT a + 1 from co ntending with DIN d at T4.

WRITE with Auto Precharge

2. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-

rupt a WRITE on bank n when registered, with the data-out appearing CL later. The

precharge to bank n will begin after tWR is met, where tWR begins when the READ to

bank m is registered. The last valid WRITE to bank n will be data-in registered one

clock prior to the READ to bank m (see Figure 29 on page 36).

3. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a WRITE on bank n when registered. The precharge to bank n will begin

after tWR is met, where tWR begins when the WRITE to bank m is registered. The last

valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank

m (see Figure 30 on page 36).

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

READ - AP

BANK nNOP NOPNOPNOP

OUT

a + 1 D

OUT

d + 1

NOP

BANK n

CL = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4 Precharge

RP - BANK ntRP - BANK m

CL = 3 (BANK n)

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

NOPNOPNOPNOP

d + 1

d + 2 D

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States t

Page

Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active WRITE with Burst of 4 Write-Back

RP -

BANK

ntWR -

BANK

CL = 3 (BANK n)

READ - AP

BANK n

DON’T CARE

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128Mb: x32 SDRAM

Figure 29: WRITE With Auto Precharge Interrupted by a READ

Notes: 1. DQM is LOW.

Figure 30: WRITE With Auto Precharge Interrupted by a WRITE

Notes: 1. DQM is LOW.

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK nNOPNOPNOPNOP

a + 1

NOP NOP

BANK n

BANK m

ADDRESS

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4

ttRP - BANK m

OUT

d + 1

CL = 3 (BANK m)

RP - BANK n

WR - BANK n

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK nNOPNOPNOPNOP

DIN

d + 1

DIN

a + 1 DIN

a + 2

DIN

aDIN

d + 2 DIN

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4 Write-Back

WR - BANK ntRP - BANK ntWR - BANK m

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128Mb: x32 SDRAM

Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous

clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-

MANDn.

4. All state s and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for

clock edge n + 1 (provided that tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is

met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring

during the tXSR period. A minimum of two NOP commands must be provided during tXSR

period.

7. After exiting clock suspend at clock edge n, the device will resume operati on and re cognize

the next command at clock edge n + 1.

Table 9: Truth Table – CKE

Notes 1–4 apply to the entire table

CKEn-1 CKEnCurrent State COMMANDnACTIONnNotes

L L Power-do wn X Maintain power -down

Self refresh X Maintain self refresh

Clock suspend X Maintain clock suspend

L H Power-down COMMAND INHIBIT or NOP Exit power-down 5

Self refresh COMMAND INHIBIT or NOP Exit self refresh 6

Clock suspend X Exit clock suspend 7

H L All banks idle COMMAND INHIBIT or NOP Power-down entry

All banks idle AUTO REFRESH self refresh entry

Reading or writing WRITE or NOP Clock suspend entry

H H See Table 10 on page 38

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128Mb: x32 SDRAM

Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 9 on page 37) and

after tXSR has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank

and the commands shown are those allowed to be issued to that bank when in that state.

Exceptions ar e covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met. No d at a

bursts/accesses and no register accesses are in pr ogress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not

yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not

yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COM-

MAND INHIBIT or NOP commands, or allowable commands to the other bank should be

issued on any clock edge occurring during these states. Allowable commands to the other

bank are determined by its current state and Table 10, and according to Table 11 on

page 40. Precharging: Starts with registration of a PRECHARGE com m and and ends whe n

tRP is met. Once tRP is met, the bank will be in the idle state.

Row activating: Starts with registration of an ACTIVE command and ends when tRCD

is met. Once tRCD is met, the bank will be in the row active state.

Read w/auto

precharge enabled: Starts with registration of a READ command with auto precharge

enabled and ends when tRP has been met. Once tRP is met, the bank

will be in the idle state.

Write w/auto

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled and ends when tRP has been met. Once tRP is met, the bank

will be in the idle state.

Table 10: Truth Table – Current State Bank n, Command To Bank n

Notes 1–6 apply to the entire table

Current

State CS# RAS# CAS# WE# COMMAND (ACTION) Notes

Any HXXX

COMMAND INHIBIT (NOP/Continue previous operation)

LHHH

NO OPERATION (NOP/Continue previous operation)

Idle L L H H ACTIVE (Select and activate row)

LLLH

AUTO REFRESH 7

LLLL

LOAD MODE REGISTER 7

LLHL

PRECHARGE 11

Row activeLHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Deactivate row in bank or banks) 8

Read (auto

precharge

disabled)

LHLH

READ (Select column and start new READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Truncate READ burst, start precharge) 8

LHHL

BURST TERMINAT E

Write (auto

precharge

disabled)

LHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start new WRITE burst) 10

LLHL

PRECHARGE (Truncate WRITE burst, start precharge) 8

LHHL

BURST TERMINAT E 9

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128Mb: x32 SDRAM

5. The following states must not be interrupted by any executable command; COMMA ND

INHIBIT or NOP commands must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends

when tRFC is met. Once tRFC is met, the SDRAM will be in the all

banks idle state.

Accessing mode

ends when tMRD has been met. Once tMRD is met, the SDRAM will

be in the all banks idle state.

Precharging all: Starts with registration of a PRECHARGE ALL command and ends

when tRP is met. Once tRP is met, all banks will be in the idle state.

6. All states and sequences not sh own are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-s pecific; if all banks are to be precharged, all must be in a valid

state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-

less of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

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128Mb: x32 SDRAM

Notes: 1. This table applies when CKEn-1 was HIGH and CKEnis HIGH (see Table 9 on page 37) and

after tXSR has been met (if the previous state was self refresh).

2. This table de scribes alternate bank operation, except where noted; i.e., the current state is

for bank n and the commands shown are those allowed to be issued to bank m (assuming

that bank m is in such a state that the given command is allowable). Exceptions are covered

in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No

data bursts/accesses and no register accesses are in progress.

Read: A READ bu rst has been in itiated , wi th auto precharge dis a bled, and

has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and

has not yet terminated or been terminated.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with auto precharge

enabled, and ends when tRP has been met. Once tRP is met, the

bank will be in the idle state.

Write w/Auto

Precharge Enabled: Starts with registration of a WRITE command with auto precharge

enabled, and ends when tRP has been met. Once tRP is met, the

bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER c ommands may only be issued

when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another ban k ; it applies to the ba nk

represented by the current state only.

Table 11: Truth Table – CURRENT STATE BANK n, COMMAND TO BANK m

Notes 1–6 apply to the entire table; notes appear below and on next page

Current State CS# RAS# CAS# WE# COMMAND (ACTION) Notes

Any HXXX

COMMAND INHIBIT (NOP/Continue previous operation)

LHHH

NO OPERATION (NOP/Continue previous operation)

Idle XXXX

Any Command Otherwise Allowed to Bank m

Row activating,

active, or

precharging

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7

LHLL

WRITE (Select column and start WRITE burst) 7

LLHL

PRECHARGE

Read (auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start new READ burst) 7, 10

LHLL

WRITE (Select column and start WRITE burst) 7, 11

LLHL

PRECHARGE 9

Write (auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7, 12

LHLL

WRITE (Select column and start new WRITE burst) 7, 13

LLHL

PRECHARGE 9

Read (with

auto precharge) LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start new READ burst) 7, 8, 14

LHLL

WRITE (Select column and start WRITE burst) 7, 8, 15

LLHL

PRECHARGE 9

Write (with

auto precharge) LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7, 8, 16

LHLL

WRITE (Select column and start new WRITE burst) 7, 8, 17

LLHL

PRECHARGE 9

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128Mb: x32 SDRAM

6. All state s and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column includ e READs or

WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. Concurrent auto precharge: Bank n will in itiate the auto precharge command when its

burst has been interrupted by bank m’s burst.

9. Burst in bank n conti nues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 10 on

page 23).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-

charge), th e WR ITE to bank m will interrupt th e READ on bank n when registered (see

Figures 12 and 13 on page 25). DQM sh ould be used on e clock prior to the WRITE command

to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered (see

Figure 20 on page 30), with the data-out appearing CL later. The last valid WRITE to bank n

will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or withou t auto pre-

charge), th e WR IT E to bank will interrupt the WRITE on bank n when registered (see

Figure 18 on page 29). The last valid WRITE to bank n will be data-in registered one clock

prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto prec harge),

the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n

will begin when the READ to bank m is registered (see Figure 27 on page 35).

15. For a READ with auto precharge interrupted by a WRITE (with or wit h out auto precharge),

the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be

used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE

to bank n will begin when the WRITE to bank m is registered (see Figure 28 on page 35).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out

appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR

begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in

registered one clock prior to the READ to bank m (see Figure 29 on page 36).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) ,

the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE

to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg-

istered . The la st v al id WRITE to bank n will be data registered one clock to the WRITE to

bank m (see Figure 30 on page 36).

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Electrical Specifications

S tresses greater than those listed Table 12 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the op erational sections of this spec ification is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reli ability.

Table 12: Absolute Maximum Ratings

Parameter Min Max Units

Voltage on VDD, VDDQ supply relative to VSS –1 +4.6 V

Voltage on inputs, NC or I/O pins relative to VSS –1 +4.6 V

Operating temperature,

TA (Commercial)

TA (Industrial)

TA (Automotive)

–40

+70

+85

+105

°C

Storage temperature (plastic) –55 +150 °C

Power dissipation 1 W

Temperature and Thermal Impedance

It is imper ative that the SDRAM device’s temperature specifications, shown in Table 13

on page 43, be maintained in order to ensure the junction temperature is in the proper

operating ra nge to meet data sheet specifications. An important step in maintaining the

proper junction temperature is using the device’s thermal impedances correctly. The

thermal impedances are listed in Table 14 on page 43 for the applicable die revision and

packages being made availa ble. These thermal impedance values vary according to the

density, package, and particular design used for each device.

Incorr ectly using thermal impedances can produce significant errors. Read Mi cron tech-

nical note TN-00-08, “Thermal Applications” prior to using the thermal impedances

listed in Table 14. To ensure the compatibility of current and future designs, contact

Micron Applications Engineering to confirm the rmal impedance values.

The SDRAM device’s safe junction temperature range can be maintained when the TC

specification is not exceede d. I n applications wher e the device's amb ient temperatur e is

too high, use of forced air and/or heat sinks may be required in order to satisfy the case

temperature specifications.

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Electrical Specifications

Notes: 1. MAX operating case temperature, TC, is measured in the center of the package on the top

side of the device, as shown in Figures 31 and 32 on page 44.

2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.

3. All temper ature specifications must be satisfied

4. The case temperature should be measured by gluing a thermocouple to the top center of

the component. This should be done with a 1mm bead of conductive epoxy, as defi ned by

the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is

touching the case.

5. Operating ambient temperature surrounding the package.

Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications

Engineering to confirm thermal impedance values.

2. Thermal resistance data is sampled from multiple lots and the values should be viewed as

typical.

3. These are estimates; actual results may vary.

Table 13: Temperature Limits

Parameter Symbol Min Max Units Notes

Operating case temperature:

Commercial

Industrial

Automotive

TC0

–40

105

°C 1, 2, 3, 4

Junction temperature:

Commercial

Industrial

Automotive

TJ0

–40

110

°C 3

Ambient temperature:

Commercial

Industrial

Automotive

TA0

–40

105

°C 3, 5

Peak reflow temperature TPEAK –260°C

Table 14: Thermal Impedance Simulated Values

Die Revision Package Substrate

θ JA (°C/W)

Airflow =

0m/s

θ JA (°C/W)

Airflow =

1m/s

θ JA (°C/W)

Airflow =

2m/s θ JB (°C/W) θ JC (°C/W)

G86-pin

TSOP 2-layer 82.2 65 59.7 49.4 10.3

4-layer 55 47.2 45.1 40.6

90-ball

VFBGA 2-layer 64.6 50.8 45.3 37.5 1.8

4-layer 48.2 41.1 38.1 32.1

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Electrical Specifications

Figure 31: Example Temperature Test Point Location, 54-Pin TSOP: Top View

Figure 32: Example Temperature Test Point Location, 90-Ball VFBGA: Top View

22.22mm

11.11mm

Test point

10.16mm

5.08mm

Test point

6.50mm

13.00mm

4.00mm

8.00mm

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Electrical Specifications

Table 15: DC Electrical Characteristics and Operating Conditions

Notes 1, 6 apply to the entire table; notes appear on page 48; VDD = +3.3V ±0.3V, VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD, VDDQ3 3.6 V

Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22

Input low voltage: Logic 0; All inputs Vil –0.3 0.8 V 22

Input leakage current:

Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) II–5 5 µA

Output leakage current:

DQs are disabled; 0V ≤ VOUT ≤ VDDQIOZ –5 5 µA

Output levels:

)Output high vol tage (IOUT = –4mA)

Output low voltage (IOUT = 4mA)

VOH 2.4 – V

VOL –0.4V

Table 16: IDD Specifications and Conditions

Notes 1, 6, 11, 13 apply to the entire table; notes appear on page 48; VDD, VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol

Max

Units Notes-6 -7

Operating current: Active mode;

Burst = 2; READ or WRITE; tRC = tRC (MIN); CL = 3 IDD1 190 165 mA 3, 18, 19,

Standby current: Power-Down mode;

CKE = LOW; All banks idle IDD222mA

Standby current: Active mode; CS# = HIGH;

CKE = HIGH; All banks active after tRCD met;

No accesses in progress

IDD3 65 55 mA 19, 26

Operating current: Burst mode; Continuous burst;

READ or WRITE; All banks active, CL = 3 IDD4 195 175 mA 3, 18, 19,

Auto refresh current:

CL = 3; CKE, CS# = HIGH

tRFC = tRFC (MIN) IDD5 320 320 mA 3, 12, 18,

19, 26

Self refresh current: CKE ≤ 0.2V IDD622mA4

Table 17: Capacitance

Note 2 applies to the entire table; notes appear on page 48

Parameter Symbol Min Max Units

Input Capacitance: CLK CI12.54.0pF

Input Capacitance: All other input-only pin s CI22.54.0pF

Input/Output Capacitance: DQs CIo4.06.5pF

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Electrical Specifications

Table 18: Electrical Characteristics and Recommended AC Operating Conditions

Notes 5, 6, 7, 8, 9, 11 apply to the entire table; notes appear on page 48

AC Characteristics

Parameter Symbol

-6 -7

Units NotesMin Max Min Max

Access time from CLK (pos. edge) CL = 3 tAC (3) 5.5 5.5 ns

CL = 2 tAC (2) 7.5 8 ns

CL = 1 tAC (1) 17 17 ns

Address hold time tAH 1 1 ns

Address setup time tAS 1.5 2 ns

CLK high-level width tCH 2.5 2.75 ns

CLK low-level width tCL 2.5 2.75 ns

Clock cycle time CL = 3 tCK (3) 6 7 ns 23

CL = 2 tCK (2) 10 10 ns 23

CL = 1 tCK (1) 20 20 ns 23

CKE hold time tCKH 1 1 ns

CKE setup time tCKS 1.5 2 ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 2 ns

Data-in hold time tDH 1 1 ns

Data-in setup time tDS 1.5 2 ns

Data-out High-Z time CL = 3 tHZ (3) 5.5 5.5 ns 10

CL = 2 tHZ (2) 7.5 8 ns 10

CL = 1 tHZ (1) 17 17 ns 10

Data-out Low-Z time tLZ 1 1 ns

Data-out hold time tOH 2 2.5 ns

ACTIVE to PRECHARGE command tRAS 42120K42120Kns

ACTIVE to ACTIVE command period tRC 60 70 ns

AUTO REFRESH period tRFC 60 70 ns

ACTIVE to READ or WRITE delay tRCD 18 20 ns

Refresh period (4,096 rows) tREF 64 64 ms

Refresh period - Automotive (4,096 rows) tREFAT 16 16 ms

PRECHARGE command period tRP 18 20 ns

ACTIVE bank a to ACTIVE ban k b command tRRD 12 14 ns 25

Transition time tT 0.3 1.2 0.3 1.2 ns 7

Write recovery time tWR 1 CLK+

6ns 1 CLK+

7ns

tCK 24

12ns 14ns ns 27

Exit self refresh to ACTIVE command tXSR 70 70 ns 20

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Electrical Specifications

Table 19: AC Functional Characteristics

Notes 5, 6, 7, 8, 9, 11 apply to the entire table; notes appear on page 48

PARAMETER SYMBOL -6 -7 UNITS NOTES

READ/WRITE command to READ/WRITE command tCCD 1 1 tCK

CKE to clock disable or power-down entry mode tCKED 1 1 tCK

CKE to clock enable or power-down exit setup mode tPED 1 1 tCK

DQM to input data delay tDQD 0 0 tCK

DQM to data mask during WRITEs tDQM 0 0 tCK

DQM to data High-Z during READs tDQZ 2 2 tCK

WRITE command to input data delay tDWD 0 0 tCK

Data-in to ACTIVE command CL = 3 tDAL (3) 5 5 tCK

CL = 2 tDAL (2) 4 4 tCK

CL = 1 tDAL (1) 3 3 tCK

Data-in to PRECHARGE command tDPL 2 2 tCK

Last data-in to burst STOP command tBDL 1 1 tCK

Last data-in to new READ/WRITE command tCDL 1 1 tCK

Last data-in to PRECHARGE command tRDL 2 2 tCK

LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK

Data-out to High-Z from PRECHARGE command CL = 3 tROH (3) 3 3 tCK

CL = 2 tRO H (2) 2 2 tCK

CL = 1 tRO H (1) 1 1 tCK

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Notes

Notes 1. All v o ltages referenced to VSS.

2. This param eter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test

biased at 1.4V. AC can range from 0pF to 6pF.

3. IDD is dependent on output loading and cy cle rates. Specified value s are obtained

with minimum cycle time and the outputs open.

4. Enables on-chip re fresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper

operation o v er the full temper ature range (0°C ≤ T A ≤ +70°C (commerc ial), –40°C ≤ TA ≤

+85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive) ) is ensured.

6. The minimum specifications are used only to indicate cycle time at which proper

operation o ve r the full temper atur e r ange (0°C ≤ T A ≤ +70°C and –40°C ≤ T A ≤ +85°C for

IT parts) is ensured.

7. An initial pause of 100µs is requi red after power-up, followed by two AUTO Refresh

commands, before prope r devi ce operation is ensured. (VDD and VDDQ must be pow-

ered up simultaneously. VSS and VSSQ must be at same potential.) Th e tw o AUTO

Refresh command wake-ups should be repeated any time the tREF refresh require-

ment is exceeded.

8. AC characteristics assume tT = 1ns.

9. In addition to meeting the transition rate specification, the clock and CKE must tran-

sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

10. Outputs measured at 1.5V with equivalent load:

Q30pF

11. tHZ defines the time at which the output achieves the open circuit condition; it is not

a reference to VOH or VOL. The last valid data elemen t will meet tOH before going

High-Z.

12. AC timing and IDD tests have VIL = 0.25 and VIH = 2.75, with timing referenced to 1.5V

crossover point.

13. Other input signals are allowed to transition no more than once in any two-clock

period and are otherwise at valid VIH or VIL levels.

14. IDD specifications are tested after the device is properly initialized.

15. Timing actually specified by tCKS; clock(s) sp ec ifi ed as a reference only at minimum

cycle rate.

16. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at

minimum cycle rate.

17. Timing actually specified by tWR.

18. Required clocks are specified by JEDEC functionality and are not dependent on any

timing parameter.

19. The IDD current will decrease as CL is reduced. This is due to the fact that the maxi-

mum cycle rate is slower as CL is reduced.

20. Addre ss transitions average one transition every two clocks.

21. CLK must be toggled a minimum of two times during this period.

22. Based on tCK = 143 MHz for -7, 166 MHz for -6.

23. VIH overshoot: VIH (MA X ) = VDDQ + 1.2V for a pulse width ≤ 3ns, and the pulse width

cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = –1.2V

for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the

cycle rate.

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Notes

24. The clock frequency must remain constant during access or precharge states (READ,

WRITE, including tWR, and PRECHAR GE commands). CKE may be used to r educe the

data rate.

25. Auto precharge mode only.

26. JEDEC and PC100 specify three clocks.

27. tCK = 7ns for -7, 6ns for -6.

28. Check factory for availability of specially screened devices having tWR = 10ns. tWR = 1

tCK for 100 MHz and slower (tCK = 10ns and higher) in manual precharge.

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Timing Diagrams

Figure 33: Initialize and Load Mode Register

Notes: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.

2. Outputs are guaranteed High-Z after comma nd is issued.

tCH

tCL

tCK

CKE

CLK

COMMAND

BA0, BA1

BANK

tRFC tMRD

tRFC

AUTO REFRESH AUTO REFRESH Program Mode Register

1, 2

tCMH

tCMS

Precharge

all banks

()()

tRP

()()

tCKS

Power-up:

and

CK stable

T = 100µs

(MIN)

PRECHARGE NOP AUTO

REFRESH NOP

LOAD MODE

()()

AUTO

REFRESH

ALL

BANKS

()()

High-Z

tCKH

()()

DQM 0-3

()()

()()()()

()()

NOP

()()

tCMH

tCMS tCMH

tCMS

A0-A9, A11

ROW

tAH

tAS

CODE

()()

A10

ROW

tAH

tAS

CODE

()()

ALL BANKS

SINGLE BANK

()()

DON’T CARE

UNDEFINED

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

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Timing Diagrams

Figure 34: Power-Down Mode

Notes: 1. Violating refresh requirements during power-down may result in a loss of data.

tCH

tCL

tCK

Two clock cycles

CKE

CLK

All banks idle, enter

power-down mode

Precharge all

active banks

Input buffers gated off while in

power-down mode

Exit power-down mode

()()

tCKS tCKS

COMMAND

tCMH

tCMS

PRECHARGE NOP NOP ACTIVENOP

()()

All banks idle

BA0, BA1 BANK

BANK(S)

()()

High-Z

tAH

tAS

tCKH

tCKS

DQM 0-3

()()

A0-A9, A11 ROW

()()

ALL BANKS

SINGLE BANK

A10 ROW

()()

T0 T1 T2 Tn + 1 Tn + 2

DON’T CARE

UNDEFINED

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Timing Diagrams

Figure 35: Clock Suspend Mode

Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

2. A8, A9, and A11 = “Don’t Care.”

tCH

tCL

tCK

tAC

tLZ

DQM0-3

CLK

A10

tOH

OUT

tAH

tAS

tAH

tAS

tAH

tAS

BANK

tDH

OUT

tAC tHZ

OUT

m + 1

COMMAND

tCMH

tCMS

NOPNOP NOP NOPNOPREAD WRITE

DON’T CARE

UNDEFINED

CKE

tCKS tCKH

BANK

COLUMN m

tDS

OUT

e + 1

NOP

tCKH

tCKS

tCMH

tCMS

COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

BA0, BA1

A0-A9, A11

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Timing Diagrams

Figure 36: Auto Refresh Mode

Notes: 1. tRFC must not be interrupted by any executable command; COMMAND INHIBIT or NOP

commands must be applied on each po sitive clock edge du ring tRFC.

UNDEFINEDDON’T CARE

tCH

tCL

tCK

CKE

CLK

tRFC

()()

tRP

()()

COMMAND

tCMH

tCMS

NOPNOP

()()

BANK

ACTIVE

AUTO

REFRESH

()()

NOPNOPPRECHARGE

Precharge all

active banks

AUTO

REFRESH

tRFC

High-Z

BANK(S)

()()

tAH

tAS

tCKH

tCKS

()()

NOP

()()

ROW

()()

ALL BANKS

SINGLE BANK

A10 ROW

()()

T0 T1 T2 Tn + 1 To + 1

BA0, BA1

A0–A9, A11

DQM 0-3

()()()()

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Timing Diagrams

Figure 37: Self Refresh Mode

Notes: 1. No maximum time limit for self refresh. tRAS(MAX) applies to non-self refres h mode.

2. tXSR requires minimum of two clocks regardless of frequency or timing.

3. As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh

mode until all rows have been refreshed by the AUTO REFRESH command at the distributed

refresh rate, tREF, or faster. However, the following exceptions are allowed:

3a. The DRAM has been in self refresh mode for a minimum of 64µs prior to exiting.

3b. tXSR is not violated.

3c. At least two AUTO REFRESH commands are preformed during each 15.6µs interval while

the DRAM remains out of the self refresh mode.

4. Self refresh mode not supported on automotive temperature (AT) devices.

tCH

tCL

tCK

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

()()()()

()()

DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

AUTO

REFRESH

PRECHARGE NOP NOP

BANK(S)

High-Z

tCKS

AUTO

REFRESH

> tRAS

tCKH

tCKS

ALL BANKS

SINGLE BANK

A10

T0 T1 T2 Tn + 1 To + 1 To + 2

BA0, BA1

DQM0–3

A0–A9, A11

()()

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Timing Diagrams

Figure 38: Single READ – Without Auto Precharge

Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

See Table 18 on page 46.

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tHZ

COMMAND

tCMH

tCMS

PRECHARGEACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5

DON’T CARE

UNDEFINED

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Timing Diagrams

Figure 39: Read – With Auto Precharge

Notes: 1. For this example, BL = 4, and CL = 2.

2. A8, A9, and A11 = “Don’t Care.”

DON’T CARE

UNDEFINED

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ tRP

tRAS

tRCD CAS Latency

tRC

CKE

CLK

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tHZ

tOH

OUT

+ 3

tAC tOH

tAC

OUT

+ 2D

OUT

+ 1

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM0–3

A0–A9, A11

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Timing Diagrams

Figure 40: Alternating Bank Read Accesses

Notes: 1. For this example, BL = 4, and CL = 2.

2. A8, A9, and A11 = “Don’t Care.”

DON’T CARE

UNDEFINED

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

CLK

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

tOH

OUT

+ 3

tAC tOH

tAC

OUT

+ 2D

OUT

+ 1

COMMAND

tCMH

tCMS

NOP NOPACTIVE NOP READ NOP ACTIVE

tOH

OUT

tAC tAC

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0 BANK 0 BANK 4 BANK 4 BANK 0

CKE

tCKH

tCKS

COLUMN

T0 T1 T2 T4T3 T5 T6 T7 T8

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 tRCD - BANK 0

CAS Latency - BANK 0

tRCD - BANK 4 CAS Latency - BANK 4

tRC - BANK 0

RRD

BA0, BA1

DQM 0–3

A0–A9, A11

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Timing Diagrams

Figure 41: Read – Full-page Burst

Notes: 1. For this example, CL = 2.

2. A8, A9, and A11 = “Don’t Care.”

3. Page left open; no tRP.

tCH

tCL tCK

tAC

tLZ

tRCD CAS Latency

CKE

CLK

A10

tOH

Dout

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC tOH

OUT

ROW

tHZ

tAC tOH

OUT

tAC tOH

OUT

tAC tOH

OUT

-1

tAC tOH

OUT

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

()()

Full page completed

256 locations within same row

DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

()()

NOP

()()

tAH

tAS

BANK

()()

BANK

tCKH

tCKS

()()

COLUMN

T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

BA0, BA1

DQM 0–3

A0–A9, A11

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128Mb: x32 SDRAM

Timing Diagrams

Figure 42: Read – DQM Operation

Notes: 1. For this example, CL = 2.

2. A8, A9, and A11 = “Don’t Care.”

tCH

tCL

tCK

tRCD CAS Latency

CKE

CLK

A10

tCMS

ROW

BANK

ROW

BANK

DON’T CARE

UNDEFINED

tAC

OUT

tOH

OUT

+ 3D

OUT

+ 2

ttHZ LZ

tCMH

COMMAND NOPNOP NOPACTIVE NOP READ NOPNOP NOP

tHZ

tAC tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM 0-3

A0-A9, A11

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128Mb: x32 SDRAM

Timing Diagrams

Figure 43: Single Write

Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. tWR is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. A8, A9, and A11 = “Don’t Care.”

DON’T CARE

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tWR

tDH

tDS

COMMAND

tCMH

tCMS

ACTIVE NOP WRITE NOP PRECHARGE ACTIVE

tAH

tAS

tAH

tAS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6

NOP

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128Mb: x32 SDRAM

Timing Diagrams

Figure 44: Write – Without Auto Precharge

Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. Faster frequenc ies require two clocks (when tWR > tCK).

3. A8, A9, and A11 = “Don’t Care.”

4. tWR of 1 CLK available if running 100 MHz or slower. Check fac tory for availability.

DISABLE AUTO PRECHARGE

ALL BANKs

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tWR

DON’T CARE

UNDEFINED

tDH

tDS

+ 1 D

+ 2 D

+ 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE NOPPRECHARGE ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN

T0 T1 T2 T4T3 T5 T6 T7 T8

DQM0–3

BA0, BA1

A0–A9, A11

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128Mb: x32 SDRAM

Timing Diagrams

Figure 45: Write – With Auto Precharge

Notes: 1. For this example, BL = 4.

2. Faster frequenc ies require two clocks (when tWR > tCK).

3. A8, A9, and A11 = “Don’t Care.”

DON’T CARE

UNDEFINED

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR

tDH

tDS

+ 1 D

+ 2 D

+ 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE NOP ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

tCKH

tCKS

NOP NOP

COLUMN

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

BA0, BA1

DQM 0-3

A0-A9, A11

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128Mb: x32 SDRAM

Timing Diagrams

Figure 46: Alternating Bank Write Accesses

Notes: 1. For this example, BL = 4.

2. Faster frequenc ies require two clocks (when tWR > tCK).

3. A8, A9, and A11 = “Don’t Care.”

DON’T CARE

tCH

tCL

tCK

CLK

DQ D

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

NOP NOP

tCMS

ACTIVE NOP WRITE NOP NOP ACTIVE

tDH

tDS tDH

tDS

ACTIVE WRITE

tDH

tDS

b + 1 D

b + 3

tDH

tDS tDH

tDS

ENABLE AUTO PRECHARGE

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0 BANK 0 BANK 1

CKE

tCKH

tCKS

b + 2

tDH

tDS

COLUMN b3

COLUMN m3

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 t

RCD - BANK 0

tWR

- BANK 0

WR - BANK 1

tRCD - BANK 1

tRC - BANK 0

RRD

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

BA0, BA1

DQM0–3

A0–A9, A11

BANK 0

BANK 1

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128Mb: x32 SDRAM

Timing Diagrams

Figure 47: Write – Full-page Burst

Notes: 1. A8, A9, and A11 = “Don’t Care.”

2. tWR must be sati sf ied prior to PRECHARGE command.

3. Page left open; no tRP.

tCH

tCL tCK

tRCD

CKE

CLK

A10

tCMS

tAH

tAS

tAH

tAS

ROW

Full-page burst does

not self-terminate. Can

use BURST TERMINATE

command to stop.2, 3

()()

Full page completed

DON’T CARE

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

()()

DIN

tDH

tDS

DIN

+ 1 DIN

+ 2 DIN

+ 3

tDH

tDS tDH

tDS

DIN

- 1

tDH

tDS

tAH

tAS

BANK

()()

BANK

tCMH

tCKH

tCKS

()()

256 locations within same row

COLUMN

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

BA0, BA1

DQM 0-3

A0-A9, A11

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128Mb: x32 SDRAM

Timing Diagrams

Figure 48: Write – DQM Operation

Notes: 1. For this example, BL = 4.

2. A8, A9, and A11 = “Don’t Care.”

DON’T CARE

tCH

tCL

tCK

tRCD

CKE

CLK

A10

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

ENABLE AUTO PRECHARGE

+ 3

tDH

tDS

+ 2

tCMH

COMMAND

NOPNOP NOPACTIVE NOP WRITE NOPNOP

tCMS tCMH

tDH

tDS

tDH

tDS

tAH

tAS

tAH

tAS

DISABLE AUTO PRECHARGE

tCKH

tCKS

COLUMN

T0 T1 T2 T3 T4 T5 T6 T7

BA0, BA1

DQM 0-3

A0-A9, A11

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128Mb: x32 SDRAM

Package Dimensions

Figure 49: 86-Pin Plastic TSOP (400 mil)

Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mol d protru sio n is

0.25mm per side.

3. “2X” means the notch is present in two locations (both ends of the device).

SEE DETAIL A

2X R 1.00

2X R 0.75

0.50

TYP

0.61

10.16 ±0.08

0.50 ±0.10

11.76 ±0.20

PIN #1 ID

DETAIL A

22.22 ±0.08

0.20 +0.07

-0.03

0.15 +0.03

-0.02

0.10 +0.10

-0.05

1.20 MAX 0.10

0.25

GAGE

PLANE

0.80

TYP

2X 0.10

2X 2.80

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC

PLATED LEAD FINISH:

TG (90% Sn, 10% Pb) OR P (100% Sn) 0.01 ±0.005 THICK PER SIDE

PACKAGE WIDTH AND LENGTH DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE PROTRUSION

IS 0.25 PER SIDE.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology , Inc. All other trademarks ar e the property of

their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

for production devices. Although considered final, these specifications are subject to change, as further product

development and data characterization sometimes occur.

128Mb: x32 SDRAM

Package Dimensions

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Figure 50: 90-Ball VFBGA (8mm x 13mm)

Notes: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mol d protru sio n is

0.25mm per side.

3. Recommended pa d size for PCB is 0.33mm ±0.025mm.

BALL A1 ID

1.00 MAX

MOLD COMPOUND:

EPOXY NOVOLAC

SUBSTRATE MATERIAL:

PLASTIC LAMINATE

SOLDER BALL MATERIAL:

62% Sn, 36% Pb, 2% Ag OR

96.5% Sn, 3%Ag, 0.5% Cu

13.00 ±0.10

BALL A1

BALL A9 BALL A1 ID

0.80 TYP

6.50 ±0.05

8.00 ±0.10

4.00 ±0.053.20

5.60 ±0.05

0.65 ±0.05

SEATING PLANE

11.20 ±0.10

6.40

0.10 A

90X Ø0.45

DIMENSIONS APPLY

TO SOLDER BALLS POST

REFLOW. THE PRE-

REFLOW DIAMETER IS

0.42 ON A 0.40 SMD

BALL PAD