Features * * * * * * * * * * * * * * * * * * * * * * * 8-bit Resolution ADC Gain Adjust 1.5 GHz Full Power Input Bandwidth (-3 dB) 1 GSPS (min) Sampling Rate SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc, at FS = 1 GSPS, FIN = 20 MHz SINAD = 42.9 dB (7.0 Effective Bits), SFDR = 52 dBc, at FS = 1 GSPS, FIN = 500 MHz SINAD = 40.3 dB (6.8 Effective Bits), SFDR = 50 dBc, at FS = 1 GSPS, FIN = 1000 MHz (-3 dB FS) 2-tone IMD: -52 dBc (489 MHz, 490 MHz) at 1 GSPS DNL = 0.3 lsb, INL = 0.7 lsb Low Bit Error Rate (10-13) at 1 GSPS Very Low Input Capacitance: 3 pF 500 mVpp Differential or Single-ended Analog Inputs Differential or Single-ended 50 ECL Compatible Clock Inputs ECL or LVDS/HSTL Output Compatibility Data Ready Output with Asynchronous Reset Gray or Binary Selectable Output Data; NRZ Output Mode Power Consumption: 3.4W at Tj = 70C Typical Radiation Tolerance Oriented Design (150 Krad (Si) measured) Two Package Versions ESA/SCC Detailed Specification Available on Request Enhanced CQFP68 Packaged Device: TS8388BFS Evaluation board: TSEV8388BF Demultiplexer: TS81102G0: Companion Device Available ADC 8-bit 1 GSPS TS8388BF Applications * Digital Sampling Oscilloscopes * Satellite Receiver * Electronic Countermeasures/Electronic Warfare * Direct RF Down-conversion Screening * Atmel Standard Screening Level * Mil-PRF-38535, QML Level Q for Package Version, DSCC 5962-0050401QYC * Temperature Range: up to -55C < Tc; Tj < +125C Description The TS8388BF is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 1 GSPS. The TS8388BF uses an innovative architecture, including an on-chip Sample and Hold (S/H), and is fabricated with an advanced high speed bipolar process. The on-chip S/H has a 1.5 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF digitizing). F Suffix: CQFP 68 Ceramic Quad Flat Pack Rev. 2144A-BDC-04/02 1 Functional Description Block Diagram The following figure shows the simplified block diagram. Figure 1. Simplified Block Diagram GAIN MASTER/SLAVE TRACK & HOLD AMPLIFIER VIN, VINB G=2 T/H G=1 T/H G=1 RESISTOR CHAIN ANALOG ENCODING BLOCK 4 INTERPOLATION STAGES 5 4 REGENERATION LATCHES 5 4 ERROR CORRECTION & DECODE LOGIC CLK, CLKB CLOCK BUFFER 8 OUTPUT LATCHES & BUFFERS 8 GORB DRRB DR, DRB Functional Description DATA, DATAB OR, ORB The TS8388BF is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 GHz. The TS8388BF includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry. Successive banks of latches regenerate the analog residues into logical data before entering an error correction circuitry and a resynchronization stage followed by 75 differential output buffers. The TS8388BF works in fully differential mode from analog inputs up to digital outputs. The TS8388BF features a full-power input bandwidth of 1.5 GHz. A control pin GORB is provided to select either Gray or Binary data output format. A gain control pin is provided in order to adjust the ADC gain. A Data Ready output asynchronous reset (DRRB) is available on TS8388BF. The TS8388BF uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation tolerance (no performance drift measured at 150 kRad total dose). 2 TS8388BF 2144A-BDC-04/02 TS8388BF Specifications Absolute Maximum Ratings Table 1. Absolute Maximum Ratings Parameter Symbol Positive supply voltage VCC Digital negative supply voltage DVEE Digital positive supply voltage VPLUSD Negative supply voltage VEE Maximum difference between negative supply voltage DVEE to VEE Analog input voltages Value Unit GND to 6 V GND to -5.7 V GND -0.3 to 2.8 V GND to -6 V 0.3 V VIN or VINB -1 to +1 V Maximum difference between VIN and VINB VIN - VINB -2 to +2 V Digital input voltage VD GORB -0.3 to VCC +0.3 V Digital input voltage VD DRRB VEE -0.3 to +0.9 V Digital output voltage VO VPLUSD -3 to VPLUSD -0.5 V Clock input voltage VCLK or VCLKB -3 to +1.5 V Maximum difference between VCLK and VCLKB VCLK - VCLKB -2 to +2 V Maximum junction temperature Tj +135 C Storage temperature Tstg -65 to +150 C Lead temperature (soldering 10s) Tleads +300 C Note: Comments Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandatory. See "The board set comes fully assembled and tested, with the TS8388BF in CQFP68 package installed." on page 37. Recommended Operating Conditions Table 2. Recommended Operating Conditions Recommended Value Parameter Symbol Comments Positive supply voltage VCC Positive digital supply voltage VPLUSD ECL output compatibility Positive digital supply voltage VPLUSD LVDS output compatibility Negative supply voltage VEE, DVEE Min Typ Max Unit 4.5 +5 5.25 V - GND - V +1.4 +2.4 +2.6 V -5.25 -5 -4.75 V 3 2144A-BDC-04/02 Table 2. Recommended Operating Conditions (Continued) Recommended Value Parameter Symbol Comments Min Typ Max Unit Differential analog input voltage (Full Scale) VIN, VINB VIN - VINB 50 differential or single-ended 113 450 125 500 137 550 mV mVpp Clock input power level PCLK, PCLKB 50 single-ended clock input 3 4 10 dBm Operating temperature range TJ Commercial grade: "C" Industrial grade: "V" Military grade: "M" Electrical Operating Characteristics C 0 < Tc; Tj < 90 -40 < Tc; Tj < 110 -55 < Tc; Tj < +125 VEE = DVEE = -5V; VCC = +5V; VIN -VINB = 500 mVpp Full Scale differential input; Digital outputs 75 or 50 differentially terminated; Tj (typical) = 70C. Full Temperature Range: up to -55C < Tc; Tj < +125C. Table 3. Electrical Specifications Value Symbol Test Level Min Typ Max Unit VCC VPLUSD VPLUSD 1, 2, 6 4 4 4.7 - 1.4 5 0 2.4 5.3 - 2.6 V V V Analog ICC Digital IPLUSD 1, 2 6 1, 2 6 - - - - 385 395 115 120 445 445 145 145 mA mA mA mA VEE 1, 2, 6 -5.3 -5 -4.7 V Analog AIEE Digital DIEE 1, 2 6 1, 2 6 - - - - 165 170 135 145 200 200 180 180 mA mA mA mA PD 1, 2 6 - - 3.4 3.6 4.1 4.3 W W PSRR 4 - 0.5 2 mW - - - 8 - bits Parameter Note Power Requirements Positive supply voltage Analog Digital (ECL) Digital (LVDS) Positive supply current Negative supply voltage Negative supply current Nominal power dissipation Power supply rejection ratio Resolution 4 (2) TS8388BF 2144A-BDC-04/02 TS8388BF Table 3. Electrical Specifications (Continued) Value Symbol Test Level Min Typ Max Unit Full Scale Input Voltage range (differential mode) (0V common mode voltage) VIN VINB 4 - -125 -125 - - 125 125 mV mV Full Scale Input Voltage range (single-ended input option) (See Application Notes) VIN VINB 4 - -250 - - 0 250 - mV mV Analog input capacitance CIN 4 - 3 3.5 pF Input bias current IIN 4 - 10 20 A Input Resistance RIN 4 0.5 1 - M Full Power input Bandwidth FPBW 4 1.3 1.5 - GHz Small signal input Bandwidth (10% full scale) SSBW 4 1.5 1.7 - GHz Logic compatibility for clock inputs (See Application Notes) - - ECL or specified clock input power level in dBm ECL Clock inputs voltages (VCLK or VCLKB): - 4 - - - - Logic "0" voltage VIL - - - -1.5 V Logic "1" voltage VIH - -1.1 - - V Logic "0" current IIL - - 5 50 A Logic "1" current IIH - - 5 50 A Clock input power level into 50 termination - - Clock input power level - 4 -2 4 10 dBm Clock input capacitance CCLK 4 - 3 3.5 pF Parameter Note Analog Inputs Clock Inputs dBm into 50 - - Digital Outputs Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format, Tj (typical) = 70C. (1)(6) Logic compatibility for digital outputs (Depending on the value of VPLUSD) (See Application Notes) - - Differential output voltage swings (assuming VPLUSD = 0V): - 4 - - - - 75 open transmission lines (ECL levels) - - 1.5 1.620 - V 75 differentially terminated - - 0.70 0.825 - V 50 differentially terminated - - 0.54 0.660 - V - 4 - - - - Logic "0" voltage VOL - - -1.62 -1.54 V Logic "1" voltage VOH - -0.88 -0.8 - V Output levels (assuming VPLUSD = 0V) 75 open transmission lines: (10) ECL or LVDS - (6) 5 2144A-BDC-04/02 Table 3. Electrical Specifications (Continued) Value Symbol Test Level Min Typ Max Unit Note - 4 - - - - (6) Logic "0" voltage VOL - - -1.41 -1.34 V Logic "1" voltage VOH - -1.07 -1 - V - - - - - - Logic "0" voltage VOL 1, 2 6 - - -1.40 -1.40 -1.32 -1.25 V V Logic "1" voltage VOH 1, 2 6 -1.16 -1.25 -1.10 -1.10 - - V V Differential Output Swing DOS 4 270 300 - mV - 4 - - 1.6 mV/C Parameter Output levels (assuming VPLUSD = 0V) 75 differentially terminated: Output levels (assuming VPLUSD = 0V) 50 differentially terminated: Output level drift with temperature (6) DC Accuracy Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format Tj (typical) = 70C. Differential non linearity Differential non linearity Integral non linearity Integral non linearity No missing code Gain error Input offset voltage Gain error drift Offset error drift DNL- 1, 2 6 -0.5 -0.6 -0.25 -0.35 - - lsb lsb DNL+ 1, 2 6 - - 0.3 0.4 0.6 0.7 lsb lsb INL- 1, 2 6 -1.0 -1.2 0.7 0.9 - - lsb lsb INL+ 1, 2 6 - - 0.7 0.9 1.0 1.2 lsb lsb - Guaranteed over specified temperature range (2)(3) (2)(3) (3) - 1, 2 6 -10 -11 -2 -2 10 11 % FS % FS - 1, 2 6 -26 -30 -5 -5 26 30 mV mV - - 4 4 100 40 125 50 150 60 ppm/C ppm/C BER 4 - - 1E-12 Error/ sample (2)(4) TS 4 - 0.5 1 ns (2) TOR 4 - 0.5 1 ns (2) Transient Performance Bit Error Rate FS = 1 GSPS FIN = 62.5 MHz ADC settling time VIN -VINB = 400 mVpp Overvoltage recovery time 6 TS8388BF 2144A-BDC-04/02 TS8388BF Table 3. Electrical Specifications (Continued) Parameter Symbol Test Level Value Min Typ Max Unit Note (2) AC Performance Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), Binary output data format, Tj = 70C, unless otherwise specified. Signal to Noise and Distortion ratio - - - - - FS = 1 GSPS, FIN = 20 MHz 4 42 44 - dB 4 41 43 - dB 4 38 40 - dB 1, 2, 6 40 44 - dB - - - - - 4 7.0 7.2 - Bits 4 6.6 6.8 - Bits 4 6.2 6.4 - Bits 1, 2, 6 7.0 7.2 - Bits - - - - - 4 42 45 - dB 4 41 44 - dB 4 41 44 - dB 1, 2, 6 44 45 - dB - - - - - 4 50 54 - dB 4 46 50 - dB 4 42 46 - dB 1, 2, 6 46 45 - dB Spurious Free Dynamic Range - - - - - FS = 1 GSPS, FIN = 20 MHz 4 52 57 - dBc 4 47 52 - dBc FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) 4 42 47 - dBc FS = 1 GSPS, FIN = 1000 MHz (-3 dBFs) 4 45 50 - dBc FS = 50 MSPS, FIN = 25 MHz 1, 2, 6 40 54 - dBc Two-tone Inter-modulation Distortion 4 - - - - - -47 -52 - dBc FS = 1 GSPS, FIN = 500 MHz SINAD FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) FS = 50 MSPS, FIN = 25 MHz Effective Number Of Bits FS = 1 GSPS, FIN = 20 MHz FS = 1 GSPS, FIN = 500 MHz ENOB FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) FS = 50 MSPS, FIN = 25 MHz Signal to Noise Ratio FS = 1 GSPS, FIN = 20 MHz FS = 1 GSPS, FIN = 500 MHz SNR FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) FS = 50 MSPS, FIN = 25 MHz Total Harmonic Distortion FS = 1 GSPS, FIN = 20 MHz FS = 1 GSPS, FIN = 500 MHz THD FS = 1 GSPS, FIN = 1000 MHz (-1 dBFs) FS = 50 MSPS, FIN = 25 MHz FS = 1 GSPS, FIN = 500 MHz FIN1 = 489 MHz at FS = 1 GSPS, FIN2 = 490 MHz at FS = 1 GSPS (2) (2) (2) SFDR (2) IMD Switching Performance and Charcteristics - See Figure 2 and Figure 3 on page 9 Maximum clock frequency FS - 1 - 1.4 GSPS (14) Minimum clock frequency FS 4 10 - 50 MSPS (15) TC1 4 0.280 0.500 50 ns Minimum Clock pulse width (high) 7 2144A-BDC-04/02 Table 3. Electrical Specifications (Continued) Value Symbol Test Level Min Typ Max Unit TC2 4 0.350 0.500 50 ns Ta 4 100 +250 400 ps (2) Jitter 4 - 0.4 0.6 ps (rms) (2)(5) TDO 4 1150 1360 1660 ps (11)(12) Output rise/fall time for DATA (20% - 80%) TR/TF 4 250 350 550 ps (11) Output rise/fall time for DATA READY (20% - 80%) TR/TF 4 250 350 550 ps (11) TDR 4 1110 1320 1620 ps (11)(12) TRDR 4 - 720 1000 ps TOD-TDR 4 0 40 80 ps (14) TD1 4 420 460 500 ps (2)(15) TPD 4 Parameter Minimum Clock pulse width (low) Aperture delay Aperture uncertainty Data output delay Data ready output delay Data ready reset delay Data to data ready - Clock low pulse width (See "Timing Diagrams" on page 9.) Data to data ready output delay (50% duty cycle) at 1 GSPS (See "Timing Diagrams" on page 9.) Data pipeline delay Notes: 8 Note (2)(10) (2)(10) (9)(13) 4 clock cycles 1. 2. 3. 4. 5. Differential output buffers are internally loaded by 75 resistors. Buffer bias current = 11 mA. See "Definition of Terms" on page 41. Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS. Output error amplitude < 4 lsb around correct code (including gain and offset error). Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board): 200 fs. (500 fs expected on TS8388BG) 6. Digital output back termination options depicted in Application Notes. 7. With a typical value of TD = 465 ps, at 1 GSPS, the timing safety margin for the data storing using the ECLinPS 10E452 output registers from Motorola(R) is of 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR, DRB). 8. The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level into the 50 termination resistor of the inphase clock input. (4 dBm into 50 clock input correspond to 10 dBm power level for the clock generator.) 9. At 1 GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate. 10. Specifiedloadingconditionsfordigitaloutputs: -50 or 75 controlled impedance traces properly 50/75 terminated, or unterminated 75 controlled impedance traces. - Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input parasitic capacitance of 1.5 pF including package and ESD protections.) 11. Terminationloadparasiticcapacitancederatingvalues: -50 or 75 controlled impedance traces properly 50/75 terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load. - Unterminated (source terminated) 75 controlled impedance lines: 100 ps/pF or 150 ps per additionnal ECLinPS termination load. 12. Apply proper 50/75 impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8388BF Evaluation Board. 13. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100C temperature variation). Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about "TOD-TDR Variation Over Temperature" on page 23). 14. Min value guarantees performance. Max value guarantees functionality. 15. Min value guarantees functionality. Max value guarantees performance. TS8388BF 2144A-BDC-04/02 TS8388BF Timing Diagrams Figure 2. TS8388BF Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at LOW Level TA = 250 ps TBC X (VIN, VINB) X X N+1 N N-1 X N+2 X N+3 X N+5 X N+4 TC = 1000 ps TC1 TC2 (CLK, CLKB) DIGITAL OUTPUTS TOD = 1360 ps TPD: 4.0 Clock periods 1360 ps DATA N-5 1000 ps DATA N-4 DATA N-3 DATA N-2 DATA N-1 N+1 TD1 = TC1+TDR-TOD = TC1-40 ps = 460 ps TDR = 1320 ps TDR = 1320 ps DATA N Data Ready (DR, DRB) TD2 = TC2+TOD-TDR = TC2+40 ps = 540 ps TRDR = 720 ps DRRB 1 ns (min) Figure 3. TS8388BF Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at HIGH Level TA = 250 ps TBC X (VIN, VINB) N XN-1 N+1 X X X X X N+4 N+2 N+5 TC = 1000 ps TC1 TC2 (CLK, CLKB) DIGITAL OUTPUTS TOD = 1360 ps TPD: 4.0 Clock periods 1360 ps DATA N-5 1000 ps DATA N-4 TDR = 1320 ps TDR = 1320 ps DATA N-3 DATA N-2 DATA N-1 DATA N DATA N+1 TD1 = TC1+TDR-TOD = TC1-40 ps = 460 ps Data Ready (DR, DRB) TRDR = 720 ps TD2 = TC2+TOD-TDR = TC2+40 ps = 540 ps DRRB 1 ns (min) 9 2144A-BDC-04/02 Explanation of Test Levels Table 4. Explanation of Test Levels Num Characteristics 1 100% production tested at +25C(1) (for "C" Temperature range(2)). 2 100% production tested at +25C(1), and sample tested at specified temperatures (for "V" and "M" Temperature range(2)). 3 Sample tested only at specified temperatures. 4 Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature). 5 Parameter is a typical value only. 6 100% production tested over specified temperature range (for "B/Q" Temperature range(2)). Notes: 1. Unless otherwise specified, all tests are pulsed tests: therefore Tj = Tc = Ta, where Tj, Tc and Ta are junction, case and ambient temperature respectively. 2. Refer to "Ordering Information" on page 43. 3. Only MIN and MAX values are guaranteed (typical values are issuing from characterization results). Functions Description Table 5. Functions Description Name Function VCC Positive power supply VEE Analog negative power supply VPLUSD Digital positive power supply GND Ground VIN, VINB Differential analog inputs CLK, CLKB Differential clock inputs <D0:D7> <D0B:D7B> Differential output data port DR, DRB Differential data ready outputs OR, ORB Out of range outputs GAIN ADC gain adjust GORB Gray or Binary digital output select DIOD/DRRB Die junction temperature measurement/ asynchronous data ready reset VCC = +5V VPLUSD = +0V (ECL) VPLUSD = +2.4V (LVDS) VIN OR VINB ORB CLK CLKB TS8388BF 16 GAIN 10 D0 D0B D7 D7B DR GORG DRB DIOD/ DRRB DVEE = -5V VEE = -5V GND TS8388BF 2144A-BDC-04/02 TS8388BF Digital Output Coding NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity voltage errors. Table 6. Digital Output Coding Digital Output Voltage Level Binary GORB = VCC or Floating Gray GORB = GND Out of Range > +251 mV > Positive full scale + 1/2 lsb 11111111 10000000 1 +251 mV +249 mV Positive full scale + 1/2 lsb Positive full scale - 1/2 lsb 11111111 11111110 10000000 10000001 0 0 +126 mV +124 mV Positive 1/2 scale + 1/2 lsb Positive 1/2 scale - 1/2 lsb 11000000 10111111 10100000 11100000 0 0 +1 mV -1 mV Bipolar zero + 1/2 lsb Bipolar zero - 1/2 lsb 10000000 01111111 11000000 01000000 0 0 -124 mV -126 mV Negative 1/2 scale + 1/2 lsb Negative 1/2 scale - 1/2 lsb 01000000 00111111 01100000 00100000 0 0 -249 mV -251 mV Negative full scale + 1/2 lsb Negative full scale - 1/2 lsb 00000001 00000000 00000001 00000000 0 0 < -251 mV < Negative full scale - 1/2 lsb 00000000 00000000 1 Differential Analog Input 11 2144A-BDC-04/02 Package Description Pin Description Table 7. TS8388BF Pin Description Symbol Pin number Function GND 5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51, 52, 53, 58, 59 Ground pins. To be connected to external ground plane. VPLUSD 1, 2, 16, 17, 18, 68 Digital positive supply (0V for ECL compatibility, 2.4V for LVDS compatibility).(2) VCC 26, 29, 32, 33, 46, 47, 61 +5V positive supply. VEE 30, 31, 44, 45, 48 -5V analog negative supply. DVEE 8, 9, 10 -5V digital negative supply. (1) VIN 54 , 55 In phase (+) analog input signal of the Sample and Hold differential preamplifier. VINB 56, 57(1) Inverted phase (-) of analog input signal (VIN). (1) CLK 37 , 38 In phase (+) ECL clock input signal. The analog input is sampled and held on the rising edge of the CLK signal. CLKB 39, 40(1) Inverted phase (-) of ECL clock input signal (CLK). D0, D1, D2, D3, D4, D5, D6, D7 23, 21, 19, 14, 6, 3, 66, 64 In phase (+) digital outputs. B0 is the LSB. B7 is the MSB. D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B 24, 22, 20, 15, 7, 4, 67, 65 Inverted phase (-) digital outputs. B0B is the inverted LSB. B7B is the inverted MSB. OR 62 In phase (+) Out of Range Bit. Out of Range is high on the leading edge of code 0 and code 256. ORB 63 Inverted phase (+) Out of Range Bit (OR). DR 11 In phase (+) output of Data Ready Signal. DRB 12 Inverted phase (-) output of Data Ready Signal (DR). GORB 25 Gray or Binary select output format control pin. - Binary output format if GORB is floating or VCC. - Gray output format if GORB is connected at ground (0V). GAIN 60 ADC gain adjust pin. DIOD/DRRB 49 This pin has a double function (can be left open or grounded if not used): - DIOD: die junction temperature monitoring pin. - DRRB: asynchronous data ready reset function. Notes: 12 1. Following pin numbers 37 (CLK), 40 (CLKB), 54 (VIN) and 57 (VINB) have to be connected to GND through a 50 resistor as close as possible to the package (50 termination preferred option). 2. The common mode level of the output buffers is 1.2V below the positive digital supply. For ECL compatibility the positive digital supply must be set at 0V (ground). For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V. If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply level in the same proportion in order to spare power dissipation. TS8388BF 2144A-BDC-04/02 TS8388BF TS8388BF Pinout Figure 4. TS8388BF Pinout 9 8 7 6 5 4 3 2 1 DVEE D4B D4 GND D5B D5 VPLUSD VPLUSD DVEE DR DRB GND D3 VPLUSD D3B VPLUSD 17 16 15 14 13 12 11 10 DVEE TOP VIEW Pin 1 index 18 VPLUSD VPLUSD 68 19 D2 D6B 67 20 D2B D6 66 21 D1 D7B 65 22 D1B D7 64 23 D0 ORB 63 24 D0B OR 62 25 GORB VCC 61 Gain 60 TS8388BF 56 31 VEE VIN 55 32 VCC VIN 54 33 VCC GND 53 34 GND GND 52 GND VINb GND VEE Diode 30 VEE 57 VCC VINb VCC VCC VEE 29 VEE 58 GND GND GND GND GND 28 CLKb 59 CLKb GND CLK GND CLK 27 GND VCC GND 26 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 13 2144A-BDC-04/02 Typical Characterization Results Static Linearity FS = 50 MSPS/FIN = 10 MHz Figure 5. Integral Non Linearity Note: Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz; Positive peak: 0.78 lsb; Negative peak: -0.73 lsb Figure 6. Differential Non Linearity Note: 14 Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz; Positive peak: 0.3 lsb; Negative peak: -0.39 lsb TS8388BF 2144A-BDC-04/02 TS8388BF Figure 7. Effective Number of Bits = f (VEEA); FS = 500 MSPS; FIN = 100 MHz 8 7 6 ENOB (bits) Effective Number of Bits Versus Power Supplies Variation 5 4 3 2 1 0 -7 -6.5 -6 -5.5 -5 -4.5 -4 VEEA (V) Figure 8. Effective Number of Bits = f (VCC); FS = 500 MSPS; FIN = 100 MHz 8 7 ENOB (bits) 6 5 4 3 2 1 0 3 3.5 4 4.5 5 5.5 6 6.5 7 VCC (V) Figure 9. Effective Number of Bits = f (VEED); FS = 500 MSPS; FIN = 100 MHz 8 7 ENOB (bits) 6 5 4 3 2 1 0 -6 -5.5 -5 -4.5 -4 -3.5 -3 VEED (V) 15 2144A-BDC-04/02 Typical FFT Results Figure 10. FS = 1 GSPS; FIN = 20 MHz Figure 11. FS = 1 GSPS; FIN = 495 MHz Figure 12. FS = 1 GSPS; FIN = 995 MHz (-3 dB Full Scale Input) 16 TS8388BF 2144A-BDC-04/02 TS8388BF Spurious Free Dynamic Range Versus Input Amplitude Figure 13. Sampling Frequency: FS = 1 GSPS; Input Frequency FIN = 995 MHz; Full Scale; ENOB = 6.4; SINAD = 40 dB; SNR = 44 dB; THD = -46 dBc; SFDR = -47 dBc; Gray or Binary Output Coding Figure 14. Sampling Frequency: FS = 1 GSPS; Input Frequency FIN = 995 MHz; -3 dB Full Scale; ENOB = 6.6; SINAD = 40.8 dB; SNR = 44 dB; THD = -48 dBc; SFDR = -50 dBc; Gray or Binary Output Coding 17 2144A-BDC-04/02 Dynamic Performance Versus Analog Input Frequency FS = 1 GSPS, FIN = 0 up to 1600 MHz, Full Scale input (FS), FS -3 dB Clock duty cycle 50/50, Binary/Gray output coding, fully differential or single-ended analog and clock inputs. Figure 15. ENOB (dB) 8 ENOB (dB) 7 -3 dB FS 6 5 FS 4 3 0 200 400 600 800 1000 1200 1400 1600 1800 Input frequency (MHz) Figure 16. SNR (dB) 50 48 46 SNR (dB) 44 FS 42 40 -3 dB FS 38 36 34 32 30 0 200 400 600 800 1000 Input frequency (MHz) 1200 1400 1600 1800 Figure 17. SFDR (dBc) -20 -25 SFDR (dBc) -30 FS -35 -40 -3 dB FS -45 -50 -55 -60 0 200 400 600 800 1000 1200 1400 1600 1800 Input frequency (MHz) 18 TS8388BF 2144A-BDC-04/02 TS8388BF Effective Number of Bits (ENOB) Versus Sampling Frequency Analog Input Frequency: FIN = 495 MHz and Nyquist conditions (FIN = FS/2) Clock duty cycle 50/50, Binary output coding Figure 18. ENOB (dB) 8 FIN = FS/2 7 FIN = 500 MHz ENOB (dB) 6 5 4 3 2 0 200 400 600 800 1000 1200 1400 1600 Sampling frequency (MSPS) SFDR Versus Sampling Frequency Analog Input Frequency: FIN = 495 MHz and Nyquist conditions (FIN = FS/2) Clock duty cycle 50/50, Binary output coding Figure 19. SFDR (dBc) -20 -25 -30 SFDR (dBc) -35 -40 -45 FIN = FS/2 -50 FIN = 500 MHz -55 -60 0 200 400 600 800 1000 1200 1400 1600 Sampling frequency (MSPS) 19 2144A-BDC-04/02 TS8388BF ADC Performances Versus Junction Temperature Figure 20. Effective Number of Bits Versus Junction Temperature FS = 1 GSPS; FIN = 500 MHz; Duty Cycle = 50% 8 ENOB (bits) 7 6 5 4 3 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 160 Figure 21. Signal to Noise Ratio Versus Junction Temperature FS = 1 GSPS; FIN = 507 MHz; Differential Clock; Single-ended Analog Input (VIN = -1 dBFs) 46 SNR (dB) 45 44 43 42 -60 -40 -20 0 20 40 Temperature (C) 60 80 100 120 100 120 Figure 22. Total Harmonic Distorsion Versus Junction Temperature FS = 1 GSPS; FIN = 507 MHz; Differential Clock; Single-ended Analog Input (VIN = -1 dBFs) 53 THD (dB) 51 49 47 45 43 -60 20 -40 -20 0 20 40 Temperature (C) 60 80 TS8388BF 2144A-BDC-04/02 TS8388BF Figure 23. Power Consumption Versus Junction Temperature FS = 1 GSPS; FIN = 500 MHz; Duty Cycle = 50% 5 Power consumption (W) 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (C) Typical Full Power Input Bandwidth Figure 24. 1.5 GHz at -3 dB (-2 dBm Full Power Input) Frequency (MHz) 100 300 500 700 900 1100 1300 1500 1700 0 -1 Magnitude (dB) -2 -3 -4 -5 -6 21 2144A-BDC-04/02 ADC Step Response Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps. Note: This step response was obtained with the TSEV8388B chip on-board (device in die form). Figure 25. Test Pulse Digitized with 20 GHz DSO Vpp ~ 260 mV Tr ~ 240 ps 50 mV/div 500 ps/div 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (ns) Figure 26. Same Test Pulse Digitized with TS8388BF ADC 200 ADC code 150 Tr ~ 280 ps 50 codes/div (Vpp ~ 260 mV) 100 500 ps/div ADC calculated rise time: between 150 and 200 ps 50 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (ns) Note: 22 Ripples are due to the test setup (they are present on both measurements). TS8388BF 2144A-BDC-04/02 TS8388BF TS8388BF Main Features Timing Information Timing Value for TS8388BF Timing values as defined in Table 3 on page 4 are advanced data, issued from electric simulations and first characterizations results fitted with measurements. Timing values are given at CQFP68 package inputs/outputs, taking into account package internal controlled impedance traces propagation delays, gullwing pin model, and specified termination loads. Propagation delays in 50/75 impedance traces are NOT taken into account for TOD and TDR. Apply proper derating values corresponding to termination topology. The min/max timing values are valid over the full temperature range in the following conditions: Propagation Time Considerations * Specified Termination Load (Differential output Data and Data Ready): 50 resistor in parallel with 1 standard ECLinPS register from Motorola (i.e.: 10E452) Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protections). If addressing an output Dmux, take care if some Digital outputs do not have the same termination load and apply corresponding derating value given below. * Output Termination Load derating values for TOD and TDR: ~ 35 ps/pF or 50 ps per additional ECLinPS load. * Propagation time delay derating values have also to be applied for TOD and TDR: ~ 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board. Apply proper time delay derating value if a different dielectric layer is used. TOD and TDR Timing values are given from pin to pin and DO NOT include the additional propagation times between device pins and input/output termination loads. For the TSEV8388B Evaluation Board, the propagation time delay is 6 ps/mm (155 ps/inch) corresponding to 3.4 (at 10 GHz) dielectric constant of the RO4003 used for the Board. If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time values. TD does NOT depend on propagation times because it is a differential data (TD is the time difference between Data Ready output delay and digital Data output delay). TD is also the most straightforward data to measure, again because it is differential: TD can be measured directly onto termination loads, with matched Oscilloscopes probes. TOD-TDR Variation Over Temperature Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per 100C temperature variation). Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TODs and TDR effect can be considered as negligible. 23 2144A-BDC-04/02 Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. In other terms : - If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR). - If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR). However, external TOD-TDR values may be dictated by total digital datas skews between every TODs (each digital data) and TDR: MCM Board, bonding wires and output lines lengths differences, and output termination impedance mismatches. The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maximum values for TOD-TDR. Principle of Operation The Analog input is sampled on the rising edge of external clock input (CLK, CLKB) after TA (aperture delay) of typically 250 ps. The digitized data is available after 4 clock periods latency (pipeline delay (TPD)), on clock rising edge, after 1360 ps typical propagation delay TOD. The Data Ready differential output signal frequency (DR, DRB) is half the external clock frequency, that is it switches at the same rate as the digital outputs. The Data Ready output signal (DR, DRB) switches on external clock falling edge after a propagation delay TDR of typically 1320 ps. A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is available for initializing the differential Data Ready output signal (DR, DRB). This feature is mandatory in certain applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Actually, without Data Ready signal initialization, it is impossible to store the output digital datas in a defined order. Principle of Data Ready Signal Control by DRRB Input Command Data Ready Output Signal Reset The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level (-1.8V). DRRB may also be tied to VEE = -5V for Data Ready output signal Master Reset. So long DRRB remains at logical low level, (or tied to VEE = -5V), the Data Ready output remains at logical zero and is independant of the external free running encoding clock. The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 920 ps typical. TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero crossing point of the differential Data Ready output signal (DR, DRB). The Data Ready Reset command may be a pulse of 1 ns minimum time width. 24 TS8388BF 2144A-BDC-04/02 TS8388BF Data Ready Output Signal Restart The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V). DRRB may also be Grounded, or is allowed to float, for normal free running Data Ready output signal. The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at DRRB rising edge instant: * The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is LOW: The Data Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already defined hereabove. * The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is HIGH: The Data Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320 ps. Consequently, as the analog input is sampled on clock rising edge, the first digitized data corresponding to the first acquisition (N) after Data Ready signal restart (rising edge) is always strobed by the third rising edge of the data ready signal. The time delay (TD1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR, DRB) (zero crossing point). For normal initialization of Data Ready output signal, the external encoding clock signal frequency and level must be controlled. It is reminded that the minimum encoding clock sampling rate for the ADC is 10 MSPS and consequently the clock cannot be stopped. One single pin is used for both DRRB input command and die junction temperature monitoring. Pin denomination will be DRRB/DIOD. On the former version denomination was DIOD. Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. Analog Inputs (VIN) (VINB) The analog input Full Scale range is 0.5V peak to peak (Vpp), or -2 dBm into the 50 termination resistor. In differential mode input configuration, that means 0.25V on each input, or 125 mV around 0V. The input common mode is GROUND. The typical input capacitance is 3 pF for TS8388B in CQFP package. The input capacitance is mainly due to the package. The ESD protections are not connected (but present) on the inputs. Differential Inputs Voltage Span Figure 27. Differiential Inputs Voltage Span [mV] VIN 125 500 mV Full Scale analog input 250 mV VINB -250 mV -125 0V t (VIN, VINB) = 250 mV = 500 mV diff 25 2144A-BDC-04/02 Differential Versus Single-ended Analog Input Operation The TS8388BF can operate at full speed in either differential or single-ended configuration. This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceeding the Sample and hold stage), which has been designed in order to be entered either in differential mode or single-ended mode. This is true so long as the out-of-phase analog input pin VINB is 50 terminated very closely to one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground reference for the inphase analog input pin (VIN). Thus the differential analog input preamplifier will fully reject the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. In typical single-ended configuration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through the 50 termination resistor. In single-ended input configuration, the in-phase input amplitude is 0.5V peak to peak, centered on 0V (or -2 dBm into 50). The inverted phase input is at ground potential through the 50 termination resistor. However, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential mode. Typical Single-ended Analog Input Configuration Figure 28. Typical Single-ended Analog Input Configuration [mV] VIN or VINB double pad (pins 54, 55 or 56, 57) VIN 250 500 mV Full Scale analog input VIN or VINB 500 mV VINB = 0V VINB -250 1 M 3 pF t VIN = 250 mV = 500 mV diff Clock Inputs (CLK) (CLKB) 50 (external) 50 reverse termination The TS8388BF can be clocked at full speed without noticeable performance degradation in either differential or single-ended configuration. This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed in order to be entered either in differential or single-ended mode. Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor spectral density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock signal. Single-ended Clock Input (Ground Common Mode) Although the clock inputs were intended to be driven differentially with nominal -0.8V/-1.8V ECL levels, the TS8388BF clock buffer can manage a single-ended sinewave clock signal centered around 0V. This is the most convenient clock input configuration as it does not require the use of a power splitter. No performance degradation (i.e.: due to timing jitter) is observed in this particular singleended configuration up to 1.2 GSPS Nyquist conditions (FIN = 600 MHz). 26 TS8388BF 2144A-BDC-04/02 TS8388BF This is true so long as the inverted phase clock input pin is 50 terminated very closely to one of the neighboring shield ground pins, which constitutes the local Ground reference for the inphase clock input. Thus the TS8388BF differential clock input buffer will fully reject the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance. The typical inphase clock input amplitude is 1V peak to peak, centered on 0V (ground) common mode. This corresponds to a typical clock input power level of 4 dBm into the 50 termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors. The inverted phase clock input is grounded through the 50 termination resistor. Figure 29. Single-ended Clock Input (Ground common mode): VCLK Common Mode = 0V; VCLKB = 0V; 4 dBm Typical Clock Input Power Level (into 50 termination resistor) CLK or CLKB double pad (pins 37, 38 or 39, 40) [V] VCLK +0.5V CLK or CLKB VCLK = 0V 1 M 50 (external) 0.4 pF VCLK -0.5V t Note: Differential ECL Clock Input 50 reverse termination Do not exceed 10 dBm into the 50 termination resistor for single clock input power level. The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels. In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL levels. Note: As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals to be 180 degrees out of phase especially at fast clock rates in the GSPS range. Figure 30. Differential Clock Inputs (ECL Levels) [mV] -0.8V CLK or CLKB double pad (pins 37, 38 or 39, 40) VCLK VCLKB CLK or CLKB Common mode = -1.3V 1 M 50 (external) 0.4 pF -2V -1.8V t 50 reverse termination 27 2144A-BDC-04/02 Single-ended ECL Clock Input In single-ended configuration enter on CLK (resp. CLKB) pin, with the inverted phase Clock input pin CLKB (respectively CLK) connected to -1.3V through the 50 termination resistor. The inphase input amplitude is 1V peak to peak, centered on -1.3V common mode. Figure 31. Single-ended Clocl Input (ECL): VCLK Common Mode = -1.3V; VCLKB = -1.3V [V] -0.8V VCLK VCLKB = -1.3V -1.8V Noise Immunity Information t Circuit noise immunity performance begins at design level. Efforts have been made on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from the circuit itself or induced by external circuitry (Cascode stages isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors). Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode noise rejection. Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifiers. Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs. The analog inputs and clock inputs of the TS8388BF device have been surrounded by ground pins, which must be directly connected to the external ground plane. Digital Outputs The TS8388BF differential output buffers are internally 75 loaded. The 75 resistors are connected to the digital ground pins through a -0.8V level shift diode (see Figure 32, Figure 33, Figure 34 on page 30). The TS8388BF output buffers are designed for driving 75 (default) or 50 properly terminated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of the 75 resistors when switching ensures a 0.825V voltage drop across the resistor (unterminated outputs). The VPLUSD positive supply voltage allows the adjustment of the output common mode level from -1.2V (VPLUSD = 0V for ECL output compatibility) to +1.2V (VPLUSD = 2.4V for LVDS output compatibility). Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V, (outputs unterminated), around -1.2V common mode voltage. 28 TS8388BF 2144A-BDC-04/02 TS8388BF Three possible line driving and back-termination scenarios are proposed (assuming VPLUSD = 0V): 1. 75 impedance transmission lines, 75 differentially terminated (Figure 32): Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to 0.41V = 0.825V in differential, around -1.21V (respectively +1.21V) common mode for VPLUSD = 0V (respectively 2.4V). 2. 50 impedance transmission lines, 50 differentially termination (Figure 33): Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V), leading to 0.33V = 660 mV in differential, around -1.18V (respectively +1.21V) common mode for VPLUSD = 0V (respectively 2.4V). 3. 75 impedance open transmission lines (Figure 34): Each output voltage varies between -1.6V and -0.8V (respectively +0.8V and +1.6V), which are true ECL levels, leading to 0.8V = 1.6V in differential, around -1.2V (respectively +1.2V) common mode for VPLUSD = 0V (respectively 2.4V). Therefore, it is possible to drive directly high input impedance storing registers, without terminating the 75 transmission lines. In time domain, that means that the incident wave will reflect at the 75 transmission line output and travel back to the generator (i.e.: the 75 data output buffer). As the buffer output impedance is 75, no back reflection will occur. Note: This is no longer true if a 50 transmission line is used, as the latter is not matching the buffer 75 output impedance. Each differential output termination length must be kept identical. It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in case of slight mismatch in the differential output line lengths. Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor leading to switching ground noise. The differential output voltage levels (75 or 50 termination) are not ECL standard voltage levels, however it is possible to drive standard logic ECL circuitry like the ECLinPS logic line from Motorola(R). At sampling rates exceeding 1 GSPS, it may be difficult to trigger the HP16500 or any other Acquisition System with digital outputs. It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers, in order to be able to test the TS8388BF at its optimum performance conditions. 29 2144A-BDC-04/02 Differential Output Loading Configurations (Levels for ECL Compatibility) Figure 32. Differential Output: 75 Terminated VPLUSD = 0V -0.8V -1V/-1.41V Out 75 75 75 Differential output: +0.41V = 0.825V 75 + - 75 impedance 10 nF Common mode level: -1.2V (-1.2V below VPLUSD level) 75 OutB -1.41V/-1V Out -1.02V/-1.35V 11 mA DVEE Figure 33. Differential Output: 50 Terminated VPLUSD = 0V -0.8V 75 50 75 Differential output: +0.33V = 0.660V 50 + - 50 impedance 10 nF Common mode level: -1.2V (-1.2V below VPLUSD level) 50 OutB -1.35V/-1.02V Out -0.8V/-1.6V 11 mA DVEE Figure 34. Differential Output: Open Loaded VPLUSD = 0V -0.8V 75 75 75 + - 75 impedance Differential output: +0.8V = 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level) OutB -1.6V/-0.8V 11 mA DVEE 30 TS8388BF 2144A-BDC-04/02 TS8388BF Differential Output Loading Configurations (Levels for LVDS Compatibility) Figure 35. Differential Output: 75 Terminated VPLUSD = 2.4V 1.6V 1.4V/0.99V Out 75 75 75 Differential output: +0.41V = 0.825V 75 + - 75 impedance 10 nF Common mode level: -1.2V (-1.2V below VPLUSD level) 75 OutB 0.99V/1.4V Out 1.38V/1.05V 11 mA DVEE Figure 36. Differential Output: 50 Terminated VPLUSD = 2.4V 1.6V 75 50 75 Differential output: +0.33V = 0.660V 50 + - 50 impedance 10 nF Common mode level: -1.2V (-1.2V below VPLUSD level) 50 OutB 1.05V/1.38V Out 1.6V/0.8V 11 mA DVEE Figure 37. Differential Output: Open Loaded VPLUSD = 2.4V 1.6V 75 75 75 + - 75 impedance Differential output: +0.8V = 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level) OutB 0.8V/1.6V 11 mA DVEE 31 2144A-BDC-04/02 Out of Range Bit An Out of Range (OR, ORB) bit is provided that goes to logical high state when the input exceeds the positive full scale or falls below the negative full scale. When the analog input exceeds the positive full scale, the digital output datas remain at high logical state, with (OR, ORB) at logical one. When the analog input falls below the negative full scale, the digital outputs remain at logical low state, with (OR, ORB) at logical one again. Gray or Binary Output Data Format Select The TS8388BF internal regeneration latches indecision (for inputs very close to latches threshold) may produce errors in the logic encoding circuitry and leading to large amplitude output errors. This is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (Av) within a given positive amount of time (t): Av = exp((t)/), with the positive feedback regeneration time constant. The TS8388BF has been designed for reducing the probability of occurrence of such errors to approximately 10-13 (targeted for the TS8388BF at 1 GSPS). A standard technique for reducing the amplitude of such errors down to 1 lsb consists of outputting the digital datas in Gray code format. Though the TS8388BF has been designed for featuring a Bit Error Rate of 10-13 with a binary output format, it is possible for the user to select between the Binary or Gray output data format, in order to reduce the amplitude of such errors when occurring, by storing Gray output codes. Digital Datas format selection: Diode Pin 49 * BINARY output format if GORB is floating or VCC. * GRAY output format if GORB is connected to ground (0V). One single pin is used for both DRRB input command and die junction monitoring. The pin denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. (See "Principle of Data Ready Signal Control by DRRB Input Command" on page 24 for Data Ready Reset input command). The operating die junction temperature must be kept below 145C, therefore an adequate cooling system has to be set up. The diode mounted transistor measured Vbe value versus junction temperature is given below. Figure 38. Diode Pin 49 1000 960 920 VBE (mV) 880 840 800 760 720 680 640 600 -55 32 -35 -15 5 25 45 65 Junction temperature (C) 85 105 125 TS8388BF 2144A-BDC-04/02 TS8388BF ADC Gain Control Pin 60 The ADC gain is adjustable by the means of the pin 60 (input impedance is 1 M in parallel with 2 pF). The gain adjust transfer function is given below. Figure 39. ADC Gain Control Pin 60 1.20 1.15 ADC Gain 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -500 -400 -300 -200 -100 0 100 200 300 400 500 Vgain (command voltage) (mV) Note: For more information, please refer to the document "DEMUX and ADCs Application Notes". 33 2144A-BDC-04/02 Equivalent Input/Output Schematics Figure 40. Equivalent Analog Input Circuit and ESD Protections VCC = +5V VCC VCLAMP = +2.4V -0.8V -0.8V GND GND = 0V -5.8V -5.8V +1.65V 50 50 E21V E21V VEE VEE 200 200 VIN VINB Pad capacitance 340 fF Pad capacitance 340 fF 5.8V 5.8V -1.55V 0.8V 0.8V E21G Note: E21G VEE = -5V The ESD protection equivalent capacitance is 150 fF. Figure 41. Equivalent Analog Clock Input Circuit and ESD Protections VCC VCC = +5V +0.8V -5.8V -0.8V -5.8V -5.8V GND = 0V -5.8V -5.8V VEE E31V E31V 150 VEE 150 CLK CLKB Pad capacitance 340 fF 5.8V Pad capacitance 340 fF 5.8V 380 A 0.8V 0.8V E21G Note: 34 VEE = -5V E21G The ESD protection equivalent capacitance is 150 fF. TS8388BF 2144A-BDC-04/02 TS8388BF Figure 42. Equivalent Data Output Buffer Circuit and ESD Protections VPLUSD = 0V to 2.4V -5.8V VEE -5.8V E01V E01V VEE OUT OUTB 5.8V 5.8V Pad capacitance 180 fF Pad capacitance 180 fF 0.8V 0.8V 0.8V DVEE = -5V E21GA VEE = -5V Note: 0.8V VEE = -5V The ESD protection equivalent capacitance is 150 fF. Figure 43. ADC Gain Adjust Equivalent Analog Input Circuit and ESD Protections VCC = +5V GND -0.8V +0.8V NP1032C2 -5.8V E22V 1 k GA Pad capacitance 180 fF 0.8V 2 pF 0.8V GND 5.8V VEE Note: E22GA 500 A 500 A VEE = -5V The ESD protection equivalent capacitance is 150 fF. 35 2144A-BDC-04/02 Figure 44. GORB Equivalent Input Schematic and ESD Protections GORB: Gray or Binary Select Input; Floating or Tied to VCC -> Binary VCC = +5V -0.8V 1 k 1 k -0.8V 1 k -5.8V VEE E21VA 5 k GORB Pad capacitance 180 fF 5.8V 5.8V 250 A 250 A 5.8V E31G VEE = -5V Note: GND = 0V The ESD protection equivalent capacitance is 150 fF. Figure 45. DRRB Equivalent Input Schematic and ESD Protections Actual Protection Range: 6.6V above VEE, in fact stress above GND are clipped by the CB diode used for Tj monitoring VCC = +5V GND=0V NP1032C2 10 k 200 DRRB -1.3V Pad capacitance 180 fF -2.6V 5.8V 0.8V VEE Note: 36 E21G VEE = -5V The ESD protection equivalent capacitance is 150 fF. TS8388BF 2144A-BDC-04/02 TS8388BF TSEV8388BF: Device Evaluation Board For complete specification, see separate TSEV8388B document. General Description The TSEV8388BF Evaluation Board (EB) is a board which has been designed in order to facilitate the evaluation and the characterization of the TS8388BF device up to its 1.5 GHz full power bandwidth at up to 1 GSPS in the military temperature range. The high speed of the TS8388BF requires careful attention to circuit design and layout to achieve optimal performance. This four metal layer board with internal ground plane has the adequate functions in order to allow a quick and simple evaluation of the TS8388BF ADC performances over the temperature range. The TSEV8388BF Evaluation Board is very straightforward as it only implements the TS8388BF ADC, SMA connectors for input/output accesses and a 2.54 mm pitch connector compatible with HP16500C high frequency probes. The board also implements a de-embedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip lines, and a die junction temperature measurement setting. The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and enhanced thermal characteristics for operation in the high frequency domain and extended temperature range. The board dimensions are 130 mm x 130 mm. The board set comes fully assembled and tested, with the TS8388BF in CQFP68 package installed. 37 2144A-BDC-04/02 Nominal CQFP68 Thermal Characteristics Although the power dissipation is low for this performance, the use of a heat sink is mandatory. Thermal Resistance from Junction to Ambient: RTHJA The following table lists the converter thermal performance parameters, with or without heatsink. The user will find some advice on this topics below. For the following measurements, a 50 x 50 x 16 mm heatsink has been used (see Figure 47 on page 39). Table 8. Thermal Resitance ja Thermal Resistance (C/W) CQFP68 on Board Air Flow (m/s) Estimated - Without Heatsink Targeted - With Heatsink(1) 0 50 10 0.5 40 8.9 1 35 7.9 1.5 32 7.3 2 30 6.8 2.5 28 6.5 3 26 6.2 4 24 5.8 5 23.5 5.6 Note: 1. Heatsink is glued to backside of package or screwed and pressed with thermal grease. Figure 46. Thermal Resistance from Junction to Ambient: Rthja 60 RTHJA (C/W) 50 40 30 Without heatsink 20 10 With heatsink 0 0 1 2 3 4 5 Air flow (m/s) 38 TS8388BF 2144A-BDC-04/02 TS8388BF Thermal Resistance from Junction to Case: RTHJC Typical value for Rthjc is given to 4.75C/W. CQFP68 Board Assembly Figure 47. CQFP68 Board Assembly with a 50 x 50 x 16 mm External Heatsink 28.96 24.13 Printed circuit Aluminum heatsink 1.4 15.0 Interface: Af-filled epoxy or thermal conductive grease - 100 m max. 4.0 2.5 16.0 1.3 3.2 50.0 39 2144A-BDC-04/02 Enhanced CQFP68 Thermal Characteristics Enhanced CQFP68 Thermal Resistance from Junction to Case: RTHJC The CQFP68 has been modified, in order to improve the thermal characteristics: * A CuW heatspreader has been added at the bottom of the package. * The die has been electrically isolated with the ALN substrate. Typical value for Rthjc is given to 1.56C/W. This value does not include thermal contact resistance between package and external component (heatsink or PCBoard). As an example, 2.0C/W can be taken for 50 m of thermal grease. Heatsink It is recommended to use an external heatsink, or PCBoard special design. The stand off has been calculated to permit the simultaneous soldering of the leads and of the heatspreader with the solder paste. Figure 48. Enhanced CQFP68 Suggested Assembly 28.78 24.13 Printed circuit board CuW heatspreader Thermal via Solid ground plane Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated in the device. 40 TS8388BF 2144A-BDC-04/02 TS8388BF Definitions Definition of Terms (BER) Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that differs by more than 4 lsb from the correct code. (FPBW) Full Power Input Bandwidth Analog input frequency at which the fundamental component in the digitally reconstructed output has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at Full Scale. (SINAD) Signal to Noise and Distortion Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all other spectral components, including the harmonics except DC. (SNR) Signal to Noise Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all other spectral components excluding the five first harmonics. (THD) Total Harmonic Distorsion Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value of the measured fundamental spectral component. (SFDR) Spurious Free Dynamic Range Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below Full Scale, to the RMS value of the next highest spectral component (peak spurious spectral component). SFDR is the key parameter for selecting a converter to be used in a frequency domain application (Radar systems, digital receiver, network analyzer, etc.). It may be reported in dBc (i.e.: degrades as signal levels is lowered), or in dBFS (i.e.: always related back to converter full scale). (ENOB) Effective Number Of Bits ENOB = SINAD - 1.76 + 20 log (A/V/2) 6.02 Where A is the actual input amplitude and V is the full scale range of the ADC under test. (DNL) Differential Non Linearity The Differential Non Linearity for an output code i is the difference between the measured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than 1 lsb guarantees that there are no missing output codes and that the transfer function is monotonic. (INL) Integral Non Linearity The Integral Non Linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|. (DG) Differential Gain The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full Scale peak to peak amplitude. FIN = 5 MHz (TBC). (DP) Differential Phase Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full Scale peak to peak amplitude. FIN = 5 MHz (TBC). (TA) Aperture Delay Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing point), and the time at which (VIN, VINB) is sampled. 41 2144A-BDC-04/02 (JITTER) Aperture Uncertainty Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the signal at the sampling point. (TS) Settling Time Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step function is applied to the differential analog input. (ORT) Overvoltage Recovery Time Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input is reduced to midscale. (TOD) Digital Data Output Delay Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. (TD1) Time Delay from Data to Data Ready Time delay from Data transition to Data ready. (TD2) Time Delay from Data Ready to Data General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period. (TC) Encoding Clock Period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2 (TPD) Pipeline Delay Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). For the TS8388BF the TPD is 4 clock periods. (TRDR) Data Ready Reset Delay Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB) and the reset to digital zero transition of the Data Ready output signal (DR). (TR) Rise Time Time delay for the output DATA signals to rize from 20% to 80% of delta between low level and high level. (TF) Fall Time Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and high level. (PSRR) Power Supply Rejection Ratio Ratio of input offset variation to a change in power supply voltage. (NRZ) Non Return to Zero When the input signal is larger than the upper bound of the ADC input range, the output code is identical to the maximum code and the Out of Range bit is set to logic one. When the input signal is smaller than the lower bound of the ADC input range, the output code is identical to the minimum code, and the Out of range bit is set to logic one. (It is assumed that the input signal amplitude remains within the absolute maximum ratings). (IMD) InterModulation Distortion The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the worst third order intermodulation products. The input tones levels are at -7 dB Full Scale. (NPR) Noise Power Ratio The NPR is measured to characterize the ADC performance in response to broad bandwidth signals. When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test. 42 TC2 = Minimum clock pulse width (low) TS8388BF 2144A-BDC-04/02 TS8388BF Ordering Information Package Device TS 8388B M F B/Q Manufacturer prefix Screening Level __: Standard B/Q: Mil-PRF-38535, QML level Q Space: according to ESA/scc 9000 Device or family Package: F: CQFP68 gullwing FS: Enhanced CQFP68 with heatspreader Temperature Range: M: -55C < Tc; Tj < 125C V: -40C < Tc < 110C C: 0C < Tc < 90C Evaluation Board TS EV 8388B F ZA2 ZA2: with MC100EL16 digital recivers __: No receivers Evaluation board prefix CQFP68 package The evaluation board is delivered with an ADC and includes the heat sink. 43 2144A-BDC-04/02 Outline Dimensions Figure 49. Package Dimension - 68-lead Ceramic Quad Flat Pack (CQFP) TOP VIEW M 0.005 Y X Z CQFP 68 28.78 - 29.13 1.133 - 1.147 0.050 BCS 1.27 BSC Pin N 1 index 24.13 0.152 0.950 0.006 0.58 0.05 0.023 0.002 0.8 BCS 20.32 BSC 0.950 0.006 24.13 0.152 0.027 - 0.037 0.70 - 0.95 0 - 8 0.46 - 0.88 0.018 - 0.035 0.004 1.9 0.20 0.075 0.008 3.43 Max 0.135 Max 1.133 - 1.147 28.78 - 29.13 44 0.005 - 0.010 0.13 - 0.25 TS8388BF 2144A-BDC-04/02 TS8388BF Figure 50. Package Dimension - 68-lead Enhanced CQFP with Heatspreder 0.8 BCS 20.32 BSC Y X Z CQFP 68 28.78 - 29.13 1.133 - 1.147 24.13 0.152 0.950 0.006 0.050 BCS 1.27 BSC Pin N 1 index M 0.005 0.58 0.05 0.023 0.002 TOP VIEW 0.950 0.006 24.13 0.152 0.51 0.13 0.020 0.005 0.787 0.0310 0.978 0.0385 0.18 0.13 0.007 0.005 1.133 - 1.147 28.78 - 29.13 0 - 8 0.027 - 0.037 0.70 - 0.95 0.005 - 0.010 0.13 - 0.25 45 2144A-BDC-04/02 Datasheet Status Description Table 9. Datasheet Status Datasheet Status Validity Objective specification This datasheet contains target and goal specifications for discussion with customer and application validation. Before design phase Target specification This datasheet contains target or goal specifications for product development. Valid during the design phase Preliminary specification -site This datasheet contains preliminary data. Additional data may be published later; could include simulation results. Valid before characterization phase Preliminary specification -site This datasheet contains also characterization results. Valid before the industrialization phase Product specification This datasheet contains final product specification. Valid for production purposes Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification. Life Support Applications 46 These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Motorola (R) is the registered trademark of Motorola Company. Other terms and product names may be the trademark of others. Printed on recycled paper. 2144A-BDC-04/02